JP2017044671A - Inspection system and inspection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inspection system capable of improving the throughput of inspection.SOLUTION: The inspection system comprises: a stage 12 for holding a wafer 15; a storage 42 that stores a piece of layout information 45 of a plurality of chips formed on the wafer 15; an inspection unit 44 that inspects for any defect on the wafer 15 held on the stage 12 while moving the stage 12 on the basis of the layout information 45 without performing alignment for comparing the alignment pattern on the wafer 15 to a reference alignment pattern.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an inspection apparatus and an inspection method.

  In a semiconductor device such as an integrated circuit, a wafer defect inspection is performed in a manufacturing process. Since semiconductor devices are highly integrated, a method for inspecting a wafer having a line width of 100 nm or less has been proposed (for example, Patent Document 1).

  In the photolithography process, the wafer pattern and the reticle pattern are aligned. For this reason, an alignment method that realizes highly accurate alignment and an alignment method that improves the throughput without lowering the alignment accuracy have been proposed (for example, Patent Documents 2 and 3).

JP 2012-119694 A JP-A-8-330394 JP 2000-156336 A

  In performing a defect inspection of a wafer, the wafer is aligned. However, if an attempt is made to align the wafer with high accuracy, the inspection throughput will decrease.

  The inspection apparatus and the inspection method are intended to improve inspection throughput.

  The inspection apparatus described in the present specification compares a stage that holds a wafer, a storage unit that stores layout information of a plurality of chips formed on the wafer, and an alignment pattern on the wafer with a reference alignment pattern. An inspection apparatus comprising: an inspection unit that inspects defects of the wafer held on the stage by moving the stage based on the layout information without performing alignment.

  In the inspection method described in this specification, a layout of a plurality of chips formed on the wafer is performed without performing a step of placing the wafer on a stage and an alignment for comparing the alignment pattern on the wafer with a reference alignment pattern. Moving the stage based on the information to inspect for defects in the wafer held on the stage.

  According to the inspection apparatus and the inspection method described in this specification, inspection throughput can be improved.

FIG. 1 is a diagram illustrating the inspection apparatus according to the first embodiment. FIG. 2 is a flowchart illustrating control by the control unit of the inspection apparatus according to the first embodiment. 3A is a diagram for explaining step S12 in FIG. 2, FIG. 3B is a diagram for explaining step S16 in FIG. 2, and FIG. 3C is a diagram for explaining step S18 in FIG. It is. FIG. 4 is a diagram illustrating an inspection apparatus according to Comparative Example 1. FIG. 5 is a flowchart showing control by the control unit of the inspection apparatus according to Comparative Example 1. 6A is a diagram for explaining steps S56 and S58 in FIG. 5, and FIG. 6B is a diagram for explaining step S60 in FIG. FIG. 7 is a diagram illustrating an inspection apparatus according to Modification 1 of Comparative Example 1. FIG. 8 is a diagram illustrating an inspection apparatus according to the second comparative example. 9A is a diagram for explaining step S56 in FIG. 5, FIG. 9B is a diagram for explaining step S58 in FIG. 5, and FIG. 9C is a diagram for explaining step S60 in FIG. It is. FIG. 10 is a diagram for explaining the effect of the inspection apparatus according to the first embodiment. FIG. 11 is a diagram illustrating the inspection apparatus according to the second embodiment. FIG. 12 is a flowchart illustrating the control by the control unit of the inspection apparatus according to the second embodiment. FIG. 13 is a diagram for explaining step S36 in FIG.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram illustrating an inspection apparatus 100 according to the first embodiment. As illustrated in FIG. 1, the inspection apparatus 100 according to the first embodiment includes an inspection room 10, a storage room 30, and a processing unit 40. A substage 11, a stage 12, a light source 13, and an imaging unit 14 are provided in the examination room 10. The substage 11 holds the wafer 15 in order to perform pre-alignment before placing the wafer 15 on the stage 12. The stage 12 holds the wafer 15 in order to inspect defects on the surface of the wafer 15. The stage 12 can be rotated by the driving unit 16 and can be moved in the surface direction of the surface of the wafer 15.

  The light source 13 is, for example, an LED (Light Emitting Diode). The light source 13 irradiates the surface of the wafer 15 with illumination light such as visible light or ultraviolet light. The light source 13 can irradiate the wafer 15 with light having a plurality of wavelengths. The imaging unit 14 is, for example, a CCD (Charge Coupled Device) camera, and captures an image of the surface of the wafer 15. The imaging unit 14 is installed, for example, at a distance where the entire view of the wafer 15 can be imaged, and a part of the wafer 15 can be zoomed in for imaging.

  A FOUP (Front Open Unified Pod) 31 that holds a plurality of wafers 15 is set in the storage chamber 30. For example, 25 wafers 15 can be stored in the FOUP 31. The wafer 15 held on the FOUP 31 is transferred onto the substage 11 in the inspection chamber 10 by a handler (not shown).

  The processing unit 40 includes a control unit 41 including a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory). Further, the processing unit 40 includes a storage unit 42 that stores data and a display unit 43 that displays data. The control unit 41 implements various functions by executing a defect inspection program stored in the storage unit 42. Although described in detail later, the control unit 41 has a function as, for example, the inspection unit 44.

  The storage unit 42 stores layout information 45 of a plurality of chips formed on the wafer 15 and position information 46 of a base chip among the plurality of chips. The layout information 45 and the base chip position information 46 are stored for each type of semiconductor device. The layout information 45 and the base chip position information 46 may be stored in the storage unit 42 using design information of a mask used for manufacturing a semiconductor device. The layout information 45 is arrangement information of a plurality of chips formed on the wafer 15 and includes, for example, the position coordinates of each chip with the center of the wafer 15 as the origin and the size of each chip. The base chip position information 46 is the position information of one chip selected from a plurality of chips formed on the wafer 15. For example, the position coordinates of the chip with the center of the wafer 15 as the origin are used. Is included.

  In addition, the storage unit 42 stores inspection conditions for defect inspection (for example, the wavelength, output, and focus position of light emitted from the light source 13, sensitivity of the imaging unit 14 (for example, CCD sensitivity), number of inspections, etc.). ing. For example, the storage unit 42 does not detect defects in the pattern formed on a plurality of chips on the wafer 15, but stores inspection conditions for detecting foreign matters larger than the chip pattern and uneven color of the wafer 15. Yes. For example, the storage unit 42 stores inspection conditions in which foreign matters smaller than 100 μm are hard to be detected, and foreign matters having a size of 100 μm or more and color unevenness are easily detected. Note that the inspection conditions stored in the storage unit 42 may be changed according to a film to be inspected (for example, copper, aluminum, resist, or the like).

  Note that the storage unit 42 stores image information and position information of a reference alignment pattern that performs alignment by comparison with alignment patterns formed on the wafer 15 as in Comparative Examples 1 and 2 described later. Not.

  The control unit 41 uses the driving unit 16 to move the stage 12 based on the layout information 45 and the base chip position information 46 stored in the storage unit 42, and uses the light source 13 and the imaging unit 14 to detect defects in the wafer 15. It functions as an inspection unit 44 for inspecting.

  The display unit 43 is a liquid crystal display, for example, and displays a result of a defect inspection performed on the wafer 15 under the instruction of the control unit 41.

  FIG. 2 is a flowchart illustrating the control by the control unit 41 of the inspection apparatus 100 according to the first embodiment. 3A is a diagram for explaining step S12 in FIG. 2, FIG. 3B is a diagram for explaining step S16 in FIG. 2, and FIG. 3C is a diagram for explaining step S18 in FIG. It is. As shown in FIG. 2, the controller 41 uses a handler (not shown) to transfer the wafer 15 from the FOUP 31 in the storage chamber 30 to the substage 11 and places the wafer 15 on the substage 11 (step S10). . Thereafter, as shown in FIG. 3A, the control unit 41 performs pre-alignment of the wafer 15 by irradiating the wafer 15 placed on the substage 11 with light and detecting the notch 19 (step). S12). After the pre-alignment is completed, the control unit 41 uses a handler (not shown) to transport the wafer 15 on the substage 11 to the stage 12 and place the wafer 15 on the stage 12 (step S14).

  Next, the control unit 41 (inspection unit 44) uses the drive unit 16 to move the stage 12 based on the position information 46 of the base point chip of the type specified by the operator and stored in the storage unit 42 (step S16). ). That is, the control unit 41 (inspection unit 44) moves the stage 12 based on the position information 46 of the base chip 17a among the plurality of chips 17 formed on the wafer 15, as shown in FIG. Let As a result, the base chip 17a is illuminated by the light source 13 and enters the range imaged by the imaging unit 14. Here, the description will be made assuming that the region 18a including all the chips formed side by side with the base chip 17a is within the range illuminated by the light source 13 and imaged by the imaging unit 14. The first direction is a lateral direction with respect to the notch 19, and the second direction is a direction that intersects the first direction and extends from the notch 19 toward the end of the wafer 15 opposite to the notch 19. .

  Next, the control unit 41 (inspection unit 44) uses the drive unit 16 to store the imaging unit 14 while moving the stage 12 based on the layout information 45 of the product that is stored in the storage unit 42 and specified by the operator. Using this, the surface of the wafer 15 is imaged. The control unit 41 (inspection unit 44) inspects the defect of the wafer 15 using the image captured by the imaging unit 14 (step S18). That is, as shown in FIG. 3C, the control unit 41 (inspection unit 44) images the region 18a of the wafer 15 using the imaging unit 14, and then sends the chip in the second direction based on the layout information 45. The stage 12 is moved as described. As a result, the region 18 b falls within the range illuminated by the light source 13 and imaged by the imaging unit 14. The control unit 41 (inspection unit 44) images the region 18b of the wafer 15 using the imaging unit 14. The control unit 41 (inspection unit 44) inspects the defect of the wafer 15 by comparing the captured image in the region 18a and the captured image in the region 18b and taking a difference. Such defect inspection is repeatedly performed up to the region 18 n of the wafer 15. At this time, the control unit 41 (inspection unit 44) performs defect inspection under an inspection condition in which a defect of the pattern formed on the chip 17 is not detected, and foreign matter or color unevenness larger than the pattern is detected. For example, the control unit 41 (inspection unit 44) performs defect inspection under inspection conditions in which foreign matters smaller than 100 μm are not easily detected, and foreign matters having a size of 100 μm or more and color unevenness are easily detected.

  After the defect inspection is completed, the control unit 41 displays the inspection result on the display unit 43 (step S20). For example, the control unit 41 displays the number of defects detected by the defect inspection on the display unit 43.

  Next, the control unit 41 stores the wafer 15 on the stage 12 in the FOUP 31 in the storage chamber 30 using a handler (not shown) (step S22). Thereafter, the control unit 41 determines whether or not it is the last wafer to be subjected to the defect inspection based on the number of inspections in the inspection condition stored in the storage unit 42 (step S24). If not the last wafer but a wafer to be inspected remains, the process returns to step S10. If it is the last wafer and no wafer to be inspected remains, the inspection is terminated. Note that the control unit 41 may determine whether it is the last wafer based on whether all the wafers in the FOUP 31 have been inspected.

  Here, in describing the effects of the inspection apparatus 100 of the first embodiment, the inspection apparatuses of the comparative example 1 and the comparative example 2 will be described. FIG. 4 is a diagram illustrating an inspection apparatus 500 according to the first comparative example. As shown in FIG. 4, the inspection apparatus 500 of Comparative Example 1 includes an inspection room 50, a storage room 70, and a processing unit 80. In the examination room 50, a substage 51, a stage 52, a light source 53, an imaging unit 54, and an autofocus unit 55 are provided. The imaging unit 54 includes a color camera 56 and an image sensor 57. The stage 52 can be rotated by the drive unit 59 and can be moved in the surface direction of the surface of the wafer 58.

  The light source 53 is, for example, a mercury xenon lamp. The light source 53 irradiates the surface of the wafer 58 with, for example, visible light or ultraviolet light. The imaging unit 54 captures an image of the surface of the wafer 58. The autofocus unit 55 is provided to check the focus of the light emitted from the light source 53. The focus can be adjusted by the position of the lens through which the light emitted from the light source 53 passes. A FOUP 71 holding a plurality of wafers 58 is set in the storage chamber 70.

  The processing unit 80 includes a control unit 81, a storage unit 82, and a display unit 83. The storage unit 82 includes layout information 86 of a plurality of chips formed on the wafer 58, image information 87 and position information 88 of a reference alignment pattern used for low-precision and high-precision alignment, and inspection area information 89. , Is stored. Layout information 86, reference alignment pattern image information 87 and position information 88, and inspection area information 89 are stored for each type of semiconductor device. The layout information 86 is arrangement information of a plurality of chips formed on the wafer 58 as in the first embodiment, and includes the position coordinates of each chip with the center of the wafer 58 as the origin, the size of each chip, and the like. . The reference alignment pattern image information 87 includes information indicating an image of a pattern used for low-precision and high-precision alignment. The reference alignment pattern position information 88 includes position coordinates with the origin of the center of the wafer 58 of the pattern used for low-precision and high-precision alignment. The inspection area information 89 includes position coordinates and size with the center of the wafer 58 defining the inspection area as the origin. In addition, the storage unit 82 stores inspection conditions for defect inspection.

  The control unit 81 functions as an alignment unit 84 that performs alignment of the wafer 58 and an inspection unit 85 that inspects defects of the wafer 58. The display unit 83 displays the result of defect inspection under the instruction of the control unit 81.

  FIG. 5 is a flowchart illustrating control by the control unit 81 of the inspection apparatus 500 according to the first comparative example. 6A is a diagram for explaining steps S56 and S58 in FIG. 5, and FIG. 6B is a diagram for explaining step S60 in FIG. As shown in FIG. 5, the controller 81 first performs steps S50 to S54. Steps S50 to S54 are the same as steps S10 to S14 of FIG.

  After step S54, the control unit 81 (alignment unit 84) moves the stage 52 based on the position information 88 of the reference alignment pattern stored in the storage unit 82 and used for the low-precision alignment of the product specified by the operator. . As a result, an alignment pattern used for low-precision alignment enters the field of view of an optical microscope (not shown). The control unit 81 (alignment unit 84) confirms that the alignment pattern detected by the optical microscope matches the image information 87 of the reference alignment pattern used for the low-precision alignment stored in the storage unit 82. Thereafter, the control unit 81 (alignment unit 84) compares the position coordinates of the alignment pattern detected by the optical microscope with the position information 88 of the reference alignment pattern for low-precision alignment stored in the storage unit 82, and the amount of deviation. Is calculated. The controller 81 (alignment unit 84) performs this operation at a plurality of locations (for example, three locations 1 to 3) of the wafer 58 as shown in FIG. Thereafter, the control unit 81 (alignment unit 84) converts the coordinates of the stage 52 into correction coordinates based on the result of this low-precision alignment (step S56).

  Next, the control unit 81 (alignment unit 84) is stored in the storage unit 82, and is based on the position information 88 of the reference alignment pattern used for high-precision alignment of the type specified by the operator and the correction coordinates. The stage 52 is moved. As a result, an alignment pattern used for high-precision alignment enters the field of view of a scanning electron microscope (not shown). The control unit 81 (alignment unit 84) confirms that the alignment pattern detected by the scanning electron microscope matches the image information 87 of the reference alignment pattern used for high-precision alignment stored in the storage unit 82. Thereafter, the control unit 81 (alignment unit 84) compares the position coordinates of the alignment pattern detected by the scanning electron microscope with the position information 88 of the reference alignment pattern for high-precision alignment stored in the storage unit 82. The amount of deviation is calculated. The controller 81 (alignment unit 84) performs this operation at a plurality of locations (for example, three locations 1 to 3) of the wafer 58 as shown in FIG. Thereafter, the control unit 81 (alignment unit 84) corrects the correction coordinates based on the result of the high-precision alignment (step S58).

  Next, the control unit 81 (inspection unit 85) moves the stage 52 based on the layout information 86 of the type that is stored in the storage unit 82 and specified by the operator and the corrected correction coordinates. The controller 81 (inspection unit 85) images the surface of the wafer 58 by the imaging unit 54 while moving the stage 52, and inspects the defect of the wafer 58 by comparing the captured images (step S60). For example, as shown in FIG. 6B, the control unit 81 (inspection unit 85) performs chip feeding sequentially as indicated by an arrow 61 based on the layout information 86 and the corrected correction coordinates. An image of the chip 60 is taken. In this process, the control unit 81 (inspection unit 85) compares the captured images and obtains a difference to inspect the area defined by the inspection area information 89 stored in the storage unit 82.

  After the defect inspection is completed, the control unit 81 displays the inspection result on the display unit 83 and outputs it to an external device such as a server (step S62). For example, the control unit 81 displays on the display unit 83 an image that clearly shows the defective part on the wafer map based on the position coordinates of the defective part from the center of the wafer 58, or displays the number of defects on the display unit 83. Or In addition, the control unit 81 outputs the position coordinates of the defective part from the center of the wafer 58 to an external device. Thereby, for example, the operator can easily observe defects on the wafer 58 using an external device (such as an optical microscope or an electron microscope).

  Next, the controller 81 stores the wafer 58 on the stage 52 in the FOUP 71 in the storage chamber 70 (step S64). Thereafter, the control unit 81 determines whether or not it is the last wafer to be subjected to defect inspection (step S66). If it is not the last wafer, the process returns to step S50, and if it is the last wafer, the inspection is terminated.

  In addition, although the inspection apparatus 500 of the comparative example 1 showed the case of the bright field type | mold inspection apparatus as an example, it is a dark field type | mold inspection like the inspection apparatus 600 which concerns on the modification 1 of the comparative example 1 of FIG. It may be a device. As shown in FIG. 7, in the inspection apparatus 600 according to the first modification of the first comparative example, a light source 62 that is, for example, a semiconductor laser and a detection unit 63 that is, for example, an electron multiplier tube (PMT). And are provided. By irradiating the wafer 58 with the laser light emitted from the light source 62, if there is a defect in the wafer 58, the light is scattered. The detection unit 63 can detect the position coordinates of the defect by detecting the scattered light.

  FIG. 8 is a diagram illustrating an inspection apparatus 700 according to the second comparative example. As shown in FIG. 8, the inspection apparatus 700 of Comparative Example 2 includes an inspection room 50, a storage room 70, and a processing unit 80. Since the substage 51, the stage 52, the light source 53, and the imaging unit 54 in the examination room 50 are the same as the substage 11, the stage 12, the light source 13, and the imaging unit 14 in the examination room 10 of the first embodiment, description thereof is omitted. To do. Since the storage chamber 70 and the processing unit 80 are the same as those in the first comparative example, the description thereof is omitted.

  Since the control by the control unit 81 of the inspection apparatus 700 of the comparative example 2 is the same as the control by the control unit 81 of the inspection apparatus 500 of the comparative example 1, the control unit 81 of the inspection apparatus 700 of the comparative example 2 will be described with reference to FIG. The control by will be described. 9A is a diagram for explaining step S56 in FIG. 5, FIG. 9B is a diagram for explaining step S58 in FIG. 5, and FIG. 9C is a diagram for explaining step S60 in FIG. It is. As shown in FIG. 5, the controller 81 first performs steps S50 to S54. Steps S50 to S54 are the same as those in the first comparative example, and a description thereof will be omitted.

  After step S54, the control unit 81 (alignment unit 84) performs low-precision alignment. The storage unit 82 stores a shot area image for alignment as image information 87 of a reference alignment pattern used for low-precision alignment. Further, the storage unit 82 stores position coordinates of the shot area as position information 88 of a reference alignment pattern used for low-precision alignment. The control unit 81 (alignment unit 84) images the entire view of the wafer 58 using the imaging unit 54, and detects a shot area specified by the position information 88 of the reference alignment pattern in the captured image. For example, as shown in FIG. 9A, the control unit 81 (alignment unit 84) has a plurality of (for example, four on the top, bottom, left, and right sides of the wafer) identified by the position information 88 of the reference alignment pattern among the captured images of the entire view of the wafer 58. The shot area 64 at the location) is detected. The control unit 81 (alignment unit 84) collates the detected image of the shot area 64 with the image information 87 of the reference alignment pattern. Then, the control unit 81 (alignment unit 84) compares the detected position coordinates of the shot region 64 with the position information 88 of the reference alignment pattern to calculate a shift amount, and converts the coordinates of the stage 52 into correction coordinates ( Step S56). The shot area 64 is an area that is exposed by one exposure in the reduction exposure apparatus.

  Next, the control unit 81 (alignment unit 84) performs high-precision alignment. The storage unit 82 stores an image of the chip intersection in the alignment shot area as image information 87 of a reference alignment pattern used for high-precision alignment. The storage unit 82 stores the position coordinates of the chip intersection as position information 88 of a reference alignment pattern used for high-precision alignment. The control unit 81 (alignment unit 84) images the wafer 58 using the imaging unit 54, and detects the chip intersection point specified by the position information 88 of the reference alignment pattern in the captured image. For example, as shown in FIG. 9B, the control unit 81 (alignment unit 84) includes a plurality (for example, four locations on the top, bottom, left, and right of the wafer) specified by the position information 88 of the reference alignment pattern in the captured image of the wafer 58. The chip intersection 65 is detected. The control unit 81 (alignment unit 84) collates the detected image of the chip intersection 65 with the image information 87 of the reference alignment pattern. Then, the control unit 81 (alignment unit 84) compares the detected position coordinate of the chip intersection point 65 with the position information 88 of the reference alignment pattern to calculate a deviation amount, and corrects the correction coordinate (step S56).

  Next, the control unit 81 (inspection unit 85) moves the stage 52 based on the layout information 86 stored in the storage unit 82 and the corrected coordinates after correction. The control unit 81 (inspection unit 85) images the wafer 58 by the imaging unit 54 while moving the stage 52, and inspects the defect on the wafer 58 by comparing the captured images (step S60). For example, as shown in FIG. 9C, the control unit 81 (inspection unit 85) aligns in the first direction while performing chip feeding in the second direction based on the layout information 86 and the corrected correction coordinates. However, the image of the area 66 including all the chips 60 is taken at once. In this process, the control unit 81 (inspection unit 85) compares the captured images and obtains the difference, thereby inspecting the defect in the area defined by the inspection area information 89 stored in the storage unit 82.

  After the defect inspection is completed, the control unit 81 performs steps S62 to S66. Steps S62 to S66 are the same as those in the first comparative example, and a description thereof will be omitted.

  According to the comparative example 1 and the comparative example 2, as shown in FIG. 5, after the alignment pattern on the wafer 58 and the reference alignment pattern of the storage unit 82 are compared and low-precision and high-precision alignment is performed, the wafer 58 We are inspecting for defects. By performing the defect inspection along the flow as shown in FIG. 5, the absolute position of the defective portion on the wafer 58 can be acquired. For this reason, the operator can easily observe the defect of the wafer 58 for which the defect inspection has been completed with an external device (for example, an optical microscope or an electron microscope). However, since low-precision and high-precision alignment is performed, the inspection time becomes long. Further, in order to perform low-precision and high-precision alignment, image information 87, position information 88, inspection area information 89, and the like of the reference alignment pattern are determined and stored using an actual wafer that has been previously patterned for each type. Stored in the unit 82. For this reason, the burden on the operator is large, and this is also a factor that increases the inspection time.

  On the other hand, according to the first embodiment, as shown in FIG. 2, the stage 12 is moved based on the layout information 45 without performing alignment for comparing the alignment pattern on the wafer 15 with the reference alignment pattern. The defect is inspected (step S18). Thereby, since the alignment time can be reduced, the inspection time per sheet can be shortened, and the inspection throughput can be improved. In addition, since it is not necessary to previously store image information, position information, and the like of the reference alignment pattern in the storage unit, the burden on the operator is reduced, and the inspection throughput is also improved in this respect.

  Further, according to the first embodiment, the position information 46 of the base point chip 17 a located on the end side of the wafer 15 among the plurality of chips formed on the wafer 15 is stored in the storage unit 42. Then, after moving the stage 12 based on the position information 46 of the base chip 17a, the stage 12 is moved based on the layout information 45 to inspect the wafer 15 for defects. Thereby, the defect inspection of the wafer 15 can be performed efficiently.

  Further, according to the first embodiment, the defect of the pattern of the plurality of chips 17 on the wafer 15 is not detected, and at least one of the foreign matter larger than the pattern of the chip 17 and the color unevenness of the wafer 15 is detected. Inspecting for defects. As a result, as shown in FIG. 10, even when a positional deviation occurs between the captured image (solid line) in the area 18a and the captured image (dotted line) in the area 18b, the respective captured images are not affected by the positional deviation. By comparing, it is possible to inspect the foreign matter 20 and the uneven color. Further, by comparing the captured images with each other and inspecting defects, for example, compared to a reference image stored in advance in the storage unit 42, the process processing variation in the wafer surface is compared with the case of inspecting defects. There is an advantage that the inspection sensitivity is improved by suppressing the erroneous inspection due to.

  In the first embodiment, as an example of the inspection condition stored in the storage unit 42, a condition suitable for the inspection of foreign matters having a size of 100 μm or more and color unevenness is given, but the present invention is not limited thereto. For example, it may be a condition suitable for inspection of a foreign matter having a size of 150 μm or more, or a condition suitable for inspection of a foreign matter having a size of 200 μm or more. Even if a positional deviation occurs in the captured image as shown in FIG. 10, it is difficult to detect a defect in the pattern of the chip 17, and it is sufficient that the foreign matter and the color unevenness larger than the pattern are easily detected. Such an inspection condition can be adjusted by at least one of the wavelength, output, incident angle, and focus of the light emitted from the light source 13, and the position of the imaging unit 14 and the imaging sensitivity.

  In the first embodiment, as shown in FIG. 3C, an example is shown in which a defect is inspected by comparing captured images obtained by collectively capturing a region including a plurality of chips 17 arranged in the first direction. However, this is not the only case. A defect may be inspected by comparing captured images captured for each chip 17, or a defect may be inspected by comparing captured images captured for each shot region. Further, a defect may be inspected by comparing captured images obtained by capturing a plurality of chips 17 or a plurality of shot areas.

  In the first embodiment, the layout information 45 and the base chip position information 46 stored in the storage unit 42 are illustrated as being different for each type of semiconductor device. However, the present invention is not limited to this case. As the base chip position information 46, a common position coordinate among a plurality of types may be stored.

  In the first embodiment, the case of the bright field type inspection apparatus is shown as an example. However, a dark field type inspection apparatus such as the first modification of the comparative example 1 may be used.

  FIG. 11 is a diagram illustrating the inspection apparatus 200 according to the second embodiment. As shown in FIG. 11, in the inspection apparatus 200 according to the second embodiment, the control unit 41 a includes a correction unit 47 that corrects the positional deviation between the stage 12 and the wafer 15 in addition to the inspection unit 44. Other configurations are the same as those of the first embodiment shown in FIG.

  FIG. 12 is a flowchart illustrating control by the control unit 41a of the inspection apparatus 200 according to the second embodiment. FIG. 13 is a diagram for explaining step S36 in FIG. As shown in FIG. 12, the control unit 41a first performs steps S30 to S34 having the same contents as steps S10 to S14 of the first embodiment.

  Next, the control unit 41a (correction unit 47) uses a notch 19 as shown in FIG. 13 and a plurality of (for example, three) marks 21 provided on the outer periphery of the wafer 15 and determined at a distance to the notch 19. The positional deviation between the stage 12 and the wafer 15 is corrected. That is, the control unit 41a (correction unit 47) uses the notch 19 and the plurality of marks 21 to calculate the center position deviation amount and the rotation deviation angle between the wafer 15 and the stage 12. Then, the control unit 41a (correction unit 47) converts the coordinates of the stage 12 into correction coordinates so that the positional deviation between the stage 12 and the wafer 15 is corrected based on the center position deviation amount and the rotation deviation angle (step). S36).

  Next, the control unit 41a (inspection unit 44) moves the stage 12 based on the position information 46 of the base point chip of the type specified by the operator and stored in the storage unit 42 and the correction coordinates ( Step S38). Thereafter, the control unit 41a (inspection unit 44) is stored in the storage unit 42 and moves the stage 12 on the basis of the layout information 45 of the type specified by the operator and the correction coordinates, while the imaging unit 14 moves. Is used to image the surface of the wafer 15. The control unit 41 (inspection unit 44) inspects the defect of the wafer 15 by comparing the images captured by the imaging unit 14 (step S40).

  Then, the control part 41 performs step S42-step S46 of the same content as step S20-step S24 of Example 1. FIG.

  According to the second embodiment, after the wafer 15 is placed on the stage 12, the coordinates of the stage 12 are converted into correction coordinates so that the positional deviation between the wafer 15 and the stage 12 is corrected (step S36). Then, the stage 12 is moved based on the layout information 45 and the correction coordinates, and the defect of the wafer 15 is inspected (step S40). Thereby, since the defect inspection on the wafer 15 can be performed in a state where the positional deviation between the wafer 15 and the stage 12 is corrected, the accuracy of the defect inspection can be improved.

  In the second embodiment, the case where the coordinates of the stage 12 are converted into the correction coordinates using the notch 19 and the plurality of marks 21 has been described as an example. However, the correction is performed using only the plurality of marks 21 without using the notch 19. It may be converted to coordinates.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

In addition, the following additional notes are disclosed regarding the above description.
(Additional remark 1) The stage which hold | maintains a wafer, the memory | storage part which memorize | stores the layout information of the several chip | tip formed on the said wafer, and alignment which compares the alignment pattern on the said wafer with a reference | standard alignment pattern are not performed, An inspection apparatus, comprising: an inspection unit that moves the stage based on the layout information and inspects defects of the wafer held on the stage.
(Additional remark 2) The said memory | storage part memorize | stores the positional information on the base point chip located in the edge side of the said wafer among the said several chips, The said test | inspection part stores the said stage based on the positional information on the said base point chip | tip. 2. The inspection apparatus according to claim 1, wherein after moving the wafer, the stage is moved based on the layout information to inspect the wafer for defects.
(Supplementary Note 3) The inspection unit does not detect a defect of a pattern formed on the plurality of chips, and detects at least one of a foreign matter larger than the pattern attached on the wafer and color unevenness on the wafer. The inspection apparatus according to claim 1 or 2, wherein the wafer is inspected for defects under inspection conditions.
(Additional remark 4) The said inspection part test | inspects the defect on the said wafer on the inspection conditions in which at least one of the foreign material of a magnitude | size of 100 micrometers or more adhering on the said wafer and the color nonuniformity on the said wafer is detected. 4. The inspection device according to any one of appendices 1 to 3, which is characterized.
(Additional remark 5) The said test | inspection part test | inspects the defect of the said wafer by comparing the 1st image which imaged the 1st area | region in the said wafer, and the 2nd image which imaged the 2nd area | region. The inspection apparatus according to any one of supplementary notes 1 to 4.
(Supplementary Note 6) A correction unit that converts the coordinates of the stage into correction coordinates so that a positional deviation between the wafer and the stage is corrected after the wafer is placed on the stage, and the inspection is provided. The inspection apparatus according to any one of appendices 1 to 5, wherein the unit inspects the defect of the wafer by moving the stage based on the layout information and the correction coordinates.
(Supplementary note 7) The stage is mounted based on layout information of a plurality of chips formed on the wafer without performing the step of placing the wafer on the stage and the alignment for comparing the alignment pattern on the wafer with the reference alignment pattern. And inspecting a defect of the wafer held on the stage.
(Supplementary Note 8) The method includes a step of moving the stage that holds the wafer based on position information of a base point chip among the plurality of chips, and the step of inspecting includes the step of moving the stage based on the position information of the base point chip. 8. The inspection method according to appendix 7, wherein after moving the stage, the stage is moved based on the layout information to inspect the wafer for defects.
(Supplementary Note 9) In the inspecting step, a defect of a pattern formed on the plurality of chips is not detected, and at least one of a foreign matter larger than the pattern attached on the wafer and color unevenness on the wafer is detected. 9. The inspection method according to appendix 7 or 8, wherein the wafer is inspected for defects under inspection conditions.
(Supplementary Note 10) The inspection step is to inspect a defect on the wafer under an inspection condition in which at least one of a foreign matter having a size of 100 μm or more adhering to the wafer and color unevenness on the wafer is detected. The inspection method according to any one of appendices 7 to 9, characterized by:
(Additional remark 11) The said test | inspecting step test | inspects the defect of the said wafer by comparing the 1st image which imaged the 1st area | region in the said wafer, and the 2nd image which imaged the 2nd area | region. The inspection method according to any one of appendices 7 to 10.
(Supplementary Note 12) After the step of placing the wafer, the method includes a step of converting the coordinates of the stage into correction coordinates so that a positional deviation between the wafer and the stage is corrected, and the inspection step includes the layout 12. The inspection method according to any one of appendices 7 to 11, wherein the stage is moved based on the information and the correction coordinates to inspect the wafer for defects.

DESCRIPTION OF SYMBOLS 10 Inspection room 11 Substage 12 Stage 13 Light source 14 Image pick-up part 15 Wafer 16 Drive part 17 Chip 17a Base point chip 18a-18n Area | region 19 Notch 20 Foreign material 21 Mark 30 Storage room 40 Processing part 41, 41a Control part 42 Storage part 43 Display part 44 Inspection unit 45 Layout information 46 Base chip position information 47 Correction unit 100, 200 Inspection device

Claims (6)

A stage for holding the wafer;
A storage unit for storing layout information of a plurality of chips formed on the wafer;
An inspection unit that inspects defects of the wafer held on the stage by moving the stage based on the layout information without performing alignment for comparing the alignment pattern on the wafer with a reference alignment pattern; An inspection apparatus comprising: The storage unit stores position information of a base chip located on an end side of the wafer among the plurality of chips;
2. The inspection unit inspects defects of the wafer by moving the stage based on the layout information after moving the stage based on position information of the base chip. The inspection device described.   The inspection unit does not detect a defect of the pattern formed on the plurality of chips, and is an inspection condition in which at least one of a foreign matter larger than the pattern attached on the wafer and color unevenness on the wafer is detected. 3. The inspection apparatus according to claim 1, wherein a defect of the wafer is inspected.   The inspection unit inspects the wafer for defects by comparing a first image obtained by imaging a first area in the wafer and a second image obtained by imaging a second area. 4. The inspection apparatus according to any one of items 1 to 3. A correction unit that converts the coordinates of the stage into correction coordinates so that a positional deviation between the wafer and the stage is corrected after the wafer is placed on the stage;
5. The inspection apparatus according to claim 1, wherein the inspection unit inspects the defect of the wafer by moving the stage based on the layout information and the correction coordinates. 6. Placing the wafer on the stage;
The alignment which compares the alignment pattern on the wafer with the reference alignment pattern is not performed, and the stage is moved based on the layout information of a plurality of chips formed on the wafer, and held on the stage. An inspection method comprising: inspecting a wafer for defects.

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