JP2007317191A - 複数のディスプレイの動的な構成設定 - Google Patents
複数のディスプレイの動的な構成設定 Download PDFInfo
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- JP2007317191A JP2007317191A JP2007133253A JP2007133253A JP2007317191A JP 2007317191 A JP2007317191 A JP 2007317191A JP 2007133253 A JP2007133253 A JP 2007133253A JP 2007133253 A JP2007133253 A JP 2007133253A JP 2007317191 A JP2007317191 A JP 2007317191A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
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Abstract
【解決手段】1つのディスプレイドライバが、オペレーティングシステムと一又は複数のグラフィックスアダプタとの間のインタフェース処理を行う。ディスプレイドライバは、一又は複数のグラフィックスデバイスを再構成設定して、システムをシャットダウン又は再起動することなくアダプタ/ディスプレイの構成設定を変更する。オペレーティングシステムによって実行される従来のシステム再起動とは異なり、ディスプレイドライバは、再構成設定するときにメモリリーク或いはエラー条件が存在していないことを調べる。
【選択図】図3A
Description
Claims (8)
- 複数のグラフィックスアダプタの処理システムであって、
第1のディスプレイデバイスと、
第2のディスプレイデバイスと、
画像データを前記第1のディスプレイデバイスに提供するように構成設定された第1のグラフィックスアダプタと、
画像データを前記第1のグラフィックスアダプタを通じて前記第1のディスプレイデバイスに提供するように、又は、画像データを前記第2のディスプレイデバイスに提供するように、構成設定することができる第2のグラフィックスアダプタと、
前記複数のグラフィックスアダプタの処理システムのオペレーティングシステムとのインタフェース処理を行うように、且つ、前記第1のディスプレイデバイス、前記第2のディスプレイデバイス、前記第1のグラフィックスアダプタ、及び、前記第2のグラフィックスアダプタの構成設定を、前記複数のグラフィックスアダプタの処理システムをシャットダウンせずに第1の構成設定から第2の構成設定に変更するように構成設定されたディスプレイドライバと、
を備えるシステム。 - 前記第2のグラフィックスアダプタが、前記第1の構成設定において前記画像データを前記第1のディスプレイデバイスに提供するように構成設定されており、前記第2の構成設定において前記第1のグラフィックスアダプタと前記第2のグラフィックスアダプタとの間のスケーラブルなリンクインタフェースが使用不可にされる、請求項1に記載のシステム。
- 前記第2のグラフィックスアダプタが、前記第1の構成設定において前記画像データを前記第2のディスプレイデバイスに提供するように構成設定されており、前記第2の構成設定において前記第1のグラフィックスアダプタと前記第2のグラフィックスアダプタとの間のスケーラブルなリンクインタフェースが使用可能にされて、前記第2のグラフィックスアダプタが前記画像データを前記第1のグラフィックスアダプタを通じて前記第1のディスプレイデバイスに提供することができる、請求項1に記載のシステム。
- 前記ディスプレイドライバが、前記第1の構成設定に対応する状態情報を前記第1のグラフィックスアダプタからアンロードするように、更に構成されている、請求項1に記載のシステム。
- 前記ディスプレイドライバが、前記第2の構成設定に対応する状態情報を前記第1のグラフィックスアダプタにロードするように、更に構成されている、請求項1に記載のシステム。
- 前記第1のグラフィックスアダプタが、画像データを前記第2のディスプレイデバイスに提供するように構成設定されている、請求項1に記載のシステム。
- 前記第2の構成設定の指定をユーザから受け取るように構成されている制御パネル、
を更に備えている、請求項1に記載のシステム。 - 前記ディスプレイドライバが、前記複数のグラフィックスアダプタの処理システムにメモリリークが存在しているかを判定するように構成されている、請求項1に記載のシステム。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/419,126 US7535433B2 (en) | 2006-05-18 | 2006-05-18 | Dynamic multiple display configuration |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007317191A true JP2007317191A (ja) | 2007-12-06 |
JP4562045B2 JP4562045B2 (ja) | 2010-10-13 |
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007133253A Active JP4562045B2 (ja) | 2006-05-18 | 2007-05-18 | 複数のディスプレイの動的な構成設定 |
Country Status (5)
Country | Link |
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US (1) | US7535433B2 (ja) |
JP (1) | JP4562045B2 (ja) |
KR (1) | KR100909916B1 (ja) |
CN (1) | CN100541600C (ja) |
TW (1) | TWI340926B (ja) |
Cited By (1)
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JP2020054834A (ja) * | 2014-04-11 | 2020-04-09 | ソニー株式会社 | 信号処理装置、および信号処理方法 |
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US8127310B1 (en) * | 2007-03-26 | 2012-02-28 | Celio Corporation | Method and apparatus for dynamically switching display drivers in mobile device operating system |
US8209673B1 (en) * | 2007-09-25 | 2012-06-26 | Nvidia Corporation | SLI approval policy database |
US8161209B2 (en) * | 2008-03-31 | 2012-04-17 | Advanced Micro Devices, Inc. | Peer-to-peer special purpose processor architecture and method |
US8892804B2 (en) | 2008-10-03 | 2014-11-18 | Advanced Micro Devices, Inc. | Internal BUS bridge architecture and method in multi-processor systems |
US8373709B2 (en) * | 2008-10-03 | 2013-02-12 | Ati Technologies Ulc | Multi-processor architecture and method |
US8514215B2 (en) * | 2008-11-12 | 2013-08-20 | International Business Machines Corporation | Dynamically managing power consumption of a computer with graphics adapter configurations |
US9041719B2 (en) | 2009-12-03 | 2015-05-26 | Nvidia Corporation | Method and system for transparently directing graphics processing to a graphical processing unit (GPU) of a multi-GPU system |
US8370550B2 (en) | 2010-02-12 | 2013-02-05 | Microsoft Corporation | Rule-based assignment of control of peripherals of a computing device |
US9104252B2 (en) * | 2010-02-12 | 2015-08-11 | Microsoft Technology Licensing, Llc | Assignment of control of peripherals of a computing device |
US8736618B2 (en) * | 2010-04-29 | 2014-05-27 | Apple Inc. | Systems and methods for hot plug GPU power control |
US8797332B2 (en) * | 2010-12-15 | 2014-08-05 | Ati Technologies Ulc | Device discovery and topology reporting in a combined CPU/GPU architecture system |
US9489924B2 (en) * | 2012-04-19 | 2016-11-08 | Nvidia Corporation | Boot display device detection and selection techniques in multi-GPU devices |
US11043157B2 (en) | 2018-10-25 | 2021-06-22 | Baylor University | System and method for a six-primary wide gamut color system |
US11532261B1 (en) | 2018-10-25 | 2022-12-20 | Baylor University | System and method for a multi-primary wide gamut color system |
US11475819B2 (en) | 2018-10-25 | 2022-10-18 | Baylor University | System and method for a multi-primary wide gamut color system |
US11289003B2 (en) | 2018-10-25 | 2022-03-29 | Baylor University | System and method for a multi-primary wide gamut color system |
US11315467B1 (en) | 2018-10-25 | 2022-04-26 | Baylor University | System and method for a multi-primary wide gamut color system |
US11403987B2 (en) | 2018-10-25 | 2022-08-02 | Baylor University | System and method for a multi-primary wide gamut color system |
US11069280B2 (en) | 2018-10-25 | 2021-07-20 | Baylor University | System and method for a multi-primary wide gamut color system |
US11587491B1 (en) | 2018-10-25 | 2023-02-21 | Baylor University | System and method for a multi-primary wide gamut color system |
US10997896B2 (en) | 2018-10-25 | 2021-05-04 | Baylor University | System and method for a six-primary wide gamut color system |
US11488510B2 (en) | 2018-10-25 | 2022-11-01 | Baylor University | System and method for a multi-primary wide gamut color system |
US11410593B2 (en) | 2018-10-25 | 2022-08-09 | Baylor University | System and method for a multi-primary wide gamut color system |
US10607527B1 (en) | 2018-10-25 | 2020-03-31 | Baylor University | System and method for a six-primary wide gamut color system |
US11289000B2 (en) | 2018-10-25 | 2022-03-29 | Baylor University | System and method for a multi-primary wide gamut color system |
US11037481B1 (en) | 2018-10-25 | 2021-06-15 | Baylor University | System and method for a multi-primary wide gamut color system |
US11030934B2 (en) | 2018-10-25 | 2021-06-08 | Baylor University | System and method for a multi-primary wide gamut color system |
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KR100768834B1 (ko) * | 2005-11-14 | 2007-10-24 | 주식회사 디엔피시스템 | 듀얼 모니터의 영상출력 제어장치 |
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2006
- 2006-05-18 US US11/419,126 patent/US7535433B2/en active Active
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- 2007-05-15 TW TW096117258A patent/TWI340926B/zh active
- 2007-05-16 CN CNB2007101030466A patent/CN100541600C/zh not_active Expired - Fee Related
- 2007-05-17 KR KR1020070048189A patent/KR100909916B1/ko active IP Right Grant
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JP2020054834A (ja) * | 2014-04-11 | 2020-04-09 | ソニー株式会社 | 信号処理装置、および信号処理方法 |
US11182874B2 (en) | 2014-04-11 | 2021-11-23 | Sony Corporation | Signal processing device and signal processing method |
Also Published As
Publication number | Publication date |
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CN100541600C (zh) | 2009-09-16 |
KR100909916B1 (ko) | 2009-07-29 |
TWI340926B (en) | 2011-04-21 |
US7535433B2 (en) | 2009-05-19 |
US20070268296A1 (en) | 2007-11-22 |
TW200813882A (en) | 2008-03-16 |
KR20070112028A (ko) | 2007-11-22 |
JP4562045B2 (ja) | 2010-10-13 |
CN101083070A (zh) | 2007-12-05 |
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