JP2007316840A - Processor, integrated circuit device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a processor, enabling a user to perform system design without being conscious of the timing enabling interrupt processing. <P>SOLUTION: The processor 10 adapted to receive and branch an interrupt generation signal 70 reporting occurrence of hardware interrupt and an interrupt vector signal 80 to an address to a corresponding interrupt processing program comprises an interrupt state control circuit 20 for asserting a vector control signal when a state capable of generating an interrupt vector is determined based on the state of the processor; an interrupt vector signal latch circuit 30 for latching the interrupt vector signal 80 when the interrupt generation signal 70 is asserted; and a vector address generation circuit 40 for generating, when the vector control signal 26 is asserted, a vector address for branching to the corresponding interrupt processing program based on a latch output of the interrupt vector signal latch circuit 30. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a processor, an integrated circuit device, and an electronic apparatus.

A CPU that is clock-synchronized and interfaces with the interrupt controller with an interrupt generation signal and an interrupt vector, when a hardware interrupt occurs, enters the interrupt processing state in the cycle in which the interrupt can be accepted, and starts interrupt state processing. To generate an address, obtain the branch destination address from the memory indicated by the address, and branch.
Japanese Patent Laid-Open No. 2001-22593 Japanese Patent Laid-Open No. 5-120182

  FIGS. 9A and 9B are diagrams for explaining the problems of the prior art.

  FIG. 9A is a functional block diagram of the CPU 300 that is clock-synchronized and interfaces with an interrupt controller (not shown) by an interrupt generation signal 350 and an interrupt vector by a signal 360. When a hardware interrupt occurs, the CPU 300 enters an interrupt processing state in a cycle in which an interrupt can be accepted, starts interrupt state processing, generates an address by an interrupt vector signal, acquires a branch destination address from the memory indicated by the address, and branches. .

  When a hardware interrupt occurs, the CPU 300 processor receives an interrupt generation signal 350 and an interrupt vector signal 360, but the CPU cannot perform interrupt processing until a cycle in which an interrupt can be accepted. Accordingly, the timing at which the CPU becomes a cycle in which interrupts can be received differs from the timing at which interrupt vectors are received.

  FIG. 9B is a timing chart when an interrupt occurs.

  Reference numeral 370 denotes a state transition generated by the state machine 310. When the interrupt generation signal 340 becomes H level (asserted), the state transits to the interrupt acceptance state 372 at the rising edge of the clock after a predetermined clock. Thereafter, when the CPU becomes capable of interrupt processing, the CPU transits to the vector generation state 374.

  As shown in the figure, since the vector generation state 374 and the clock cycle 362 for receiving the interrupt vector are different, it is necessary to control the vector address generation unit 320 so as not to latch the indefinite vector 274.

  However, the timing of transition to the vector generation state 374 is not constant because it changes depending on the relationship between the instructions before and after the pipeline, the wait state of the bus, and the like, and there is a problem that hardware control by the interrupt controller is difficult.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a processor capable of system design without being aware of the timing at which interrupt processing is possible.

(1) The present invention
A processor that receives an interrupt generation signal and an interrupt vector signal for notifying the occurrence of a hardware interrupt, and branches to an address to the corresponding interrupt processing program,
An interrupt state control circuit that asserts a vector control signal when it is determined that the interrupt vector can be generated based on the state of the processor;
An interrupt vector signal latch circuit that latches an interrupt vector signal when the interrupt generation signal is asserted;
And a vector address generation circuit for generating a vector address for branching to a corresponding interrupt processing program based on the latch output of the interrupt vector signal latch circuit when the vector control signal is asserted.

  The processor of the present invention is clock-synchronized and interfaces with an interrupt controller, an interrupt generation signal, an interrupt vector signal, and the like.

  The processor state includes, for example, an interrupt generation signal reception timing and a bus wait state.

  When a hardware interrupt occurs, the processor receives an asserted interrupt generation signal and an interrupt vector signal, but the processor cannot perform interrupt processing until a cycle in which an interrupt can be accepted (a state in which an interrupt vector can be generated) is reached. Therefore, the timing at which the processor becomes a cycle in which interrupts can be received differs from the timing at which interrupt vectors are received.

  According to the present invention, the interrupt vector signal latch circuit latches the interrupt vector signal when the interrupt generation signal is asserted. Since the interrupt vector reception period is synchronized with the interrupt generation signal assert period, the interrupt vector signal latch circuit can latch a valid value.

  Therefore, the vector address generation circuit can receive a valid interrupt vector signal (not an indefinite value) even if the timing at which the processor enters a cycle in which an interrupt can be accepted differs from the timing at which a valid interrupt vector is received.

  According to the present invention, the system can be designed without being aware of the timing at which the processor can perform interrupt processing. Therefore, the design of the entire system related to interrupts and the control of interrupts by software are facilitated.

(2) The processor of the present invention
The interrupt state control circuit includes:
Based on the state of the processor, at least two interrupt states of a first state for accepting an interrupt and a second state for generating an interrupt vector are transitioned, and control for asserting a vector control signal in the second state is performed. Features.

  The transition of the state depends on reception of an interrupt generation signal and the count value of the counter. For example, the update timing of the count value of the counter changes based on the relationship between the instructions before and after the pipeline, the wait state of the bus, and the like.

(3) The processor of the present invention
The vector signal latch circuit is
When the interrupt generation signal is not asserted, the control is performed so that the latched value is not changed.

(4) The processor of the present invention
The vector signal latch circuit is
A signal for each bit of the interrupt vector is a D input, an output signal is input to the vector address generation circuit, and the interrupt generation signal is configured by a D Philip flop that is enabled when asserted.

(5) The present invention
An integrated circuit device comprising the processor according to any one of the above.

(6) The present invention
A processor according to any of the above,
Means for receiving input information;
Means for outputting a result processed by the information processing device based on input information;
It is an electronic device characterized by including.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

1. CPU
DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

  FIG. 1 is a functional block diagram for explaining a configuration of a CPU (an example of a processor) according to the present embodiment.

  A CPU (an example of a processor) 10 according to the present embodiment is a processor that receives an interrupt generation signal 70 and an interrupt vector signal 80 for notifying the occurrence of a hardware interrupt, and branches to an address to the corresponding interrupt processing program.

  The CPU 10 includes an interrupt state control circuit 20. The interrupt state control circuit 20 asserts the vector control signal 26 when it is determined that the interrupt vector can be generated based on the state of the processor. Based on the state of the processor 10, at least two interrupt states, the first state for accepting an interrupt and the second state for generating an interrupt vector, are transitioned, and the vector control signal 26 is asserted in the second state. May be.

  Here, the interrupt state control circuit 20 functions as a state machine that changes the state according to the state of the processor. The transition of the state depends on reception of an interrupt generation signal and the count value of the counter. For example, the update timing of the count value of the counter changes based on the relationship between the instructions before and after the pipeline, the wait state of the bus, and the like.

  The CPU 10 includes an interrupt vector signal latch circuit 30. The interrupt vector signal latch circuit 30 latches the interrupt vector signal [7: 0] when the interrupt generation signal 70 is asserted. The latch output is input to the vector address generation circuit 40.

  The CPU 10 includes a vector address generation circuit 40. When the vector control signal 26 is asserted, the vector address generation circuit 40 generates a vector address for branching to the corresponding interrupt processing program based on the latch output 82 of the interrupt vector signal latch circuit 30.

  FIG. 2 is a timing chart when the interrupt of the CPU according to the present embodiment occurs.

  A clock 90 is input to the CPU 10.

  Reference numeral 70 denotes an interrupt generation signal received by the CPU 10.

  Reference numeral 80 denotes an interrupt vector signal received by the CPU 10. In this embodiment, since the interrupt vector is 8 bits, the CPU receives signals corresponding to the respective bits of the interrupt vector in parallel.

  A latch output 82 of the interrupt vector latch circuit is input to the vector address generation circuit.

  50 is a state in the state machine, 52 is a first state for accepting an interrupt (interrupt acceptance state), and 54 is a second state (vector generation state) for generating an interrupt vector.

  A vector control signal 26 is asserted when the state of the state machine is the second state (vector generation state).

  When the interrupt generation signal 70 becomes H level (asserted), the CPU simultaneously receives the interrupt vector signal (see 82). Thereafter, when the interrupt generation signal 70 becomes L level, the interrupt vector signal also becomes an indefinite value (see 84).

  When the interrupt generation signal 340 becomes H level (asserted), the state 50 transits to the interrupt acceptance state 52 depending on the state of the CPU at that time (for example, the bus wait state or the instruction execution state). Thereafter, the CPU transits to the vector generation state 54 when interrupt processing becomes possible.

  According to the present embodiment, the interrupt vector signal latch circuit latches the interrupt vector signal at a predetermined timing when the interrupt generation signal 70 is asserted (see 51). While the interrupt generation signal 70 is asserted, the processor receives a valid interrupt vector signal 80 (not an indefinite value) 80, so the latched value is not an indeterminate value.

  When the interrupt generation signal is not asserted, the vector signal latch circuit does not change the latched value. Therefore, the interrupt vector latch circuit continues to hold the latched value until the next interrupt acceptance signal is asserted (83). reference). Therefore, even if the vector generation state 54 is different from the clock cycle 82 for receiving an interrupt vector, the vector address generation circuit can receive a correct interrupt vector signal (not an indefinite value).

  According to the present embodiment, the system can be designed without being aware of the timing at which the processor can perform interrupt processing. Therefore, the design of the entire system related to interrupts and the control of interrupts by software are facilitated.

  FIG. 3 shows an example of the configuration of the interrupt vector latch circuit.

  The interrupt vector signal latch circuit 30 can be composed of a plurality of D Philip flops 30-0 to 30-7 that receive signals 80-0 to 80-7 for each bit of the interrupt vector as D inputs. Output signals 80-0 to 80-7 of the D Philip flops 30-0 to 30-7 are input to the vector address generation circuit as latch outputs.

  The interrupt generation signal 70 becomes an enable input for each D Philip flop 30-0 to 30-7, and each D Philip flop 30-0 to 30-7 is enabled when the interrupt generation signal 70 is asserted.

  Accordingly, the D Philip flops 30-0 to 30-7 latch the signals 80-0 to 80-7 for each bit of the interrupt vector which becomes the D input when the interrupt generation signal 70 is asserted. Subsequently, the interrupt generation signal 70 is held until the next assertion.

  FIG. 4 is a diagram for explaining a specific configuration example of a state machine (interrupt state control circuit).

  The state machine (interrupt state control circuit) 20 can be composed of three types of circuits: an instruction code selection circuit 110, a counter 120, and a decoder 130.

  The instruction code selection circuit 110 receives an instruction code and an interrupt generation signal 70 from the instruction bus, selects an instruction to be decoded, and transmits the selected instruction code 112 to the decoder 130.

  The counter circuit 120 is a circuit that receives the instruction end signal 134 and various wait signals 140 such as a bus wait output from the decoder and updates the count value. Normally, the counter increases by 1 count per clock, but in this embodiment, 1 count increases to several clocks when various waits are applied.

  The decoder receives the instruction code 112 selected by the instruction code selection circuit 110 and the count value 122 output from the counter circuit 120, decodes the instruction code 112, and generates various control signals 132 and vector control signals 26 instruction end signals 134. To do.

  A sequencer composed of three types of circuits, that is, an instruction code selection circuit 110, a counter 120, and a decoder 130, selects data from the instruction bus 150 by the instruction code selection circuit 110 and sends it to the decoder 130 when executing a one-cycle normal instruction. . The decoder 130 generates various control signals 132 and sends an instruction end signal 134 to the counter circuit 120 to reset the counter. Then, the instruction code selection circuit 110 selects an instruction to be executed next.

  When executing an instruction of two cycles or more, the data from the instruction bus 150 is selected by the instruction code selection circuit 110 and sent to the decoder 130. The decoder 130 generates various control signals 132, and the counter circuit 120 counts up the counter. The operation after two cycles is performed, and an instruction end signal 132 is sent to the counter circuit 120 to reset the counter. Then, the instruction code selection circuit 110 selects an instruction to be executed next.

  FIG. 5 is a timing chart when an interrupt occurs in the state machine of this embodiment.

  A clock 90 is input to the CPU 10.

  Reference numeral 70 denotes an interrupt generation signal received by the CPU 10.

  Reference numeral 80 denotes an interrupt vector signal received by the CPU 10. In this embodiment, since the interrupt vector is 8 bits, the CPU receives signals corresponding to the respective bits of the interrupt vector in parallel.

  A latch output 82 of the interrupt vector latch circuit is input to the vector address generation circuit.

  An instruction code 112 is selected by the instruction code selection circuit and output to the decoder.

  Reference numeral 122 denotes a count value output from the count circuit to the decoder.

  A vector control signal 26 is asserted when the state of the state machine is the second state (vector generation state).

  Reference numeral 140 denotes various wait signals such as an instruction bus wait signal, which indicates that the H level is in a wait state.

  Normally, the counter circuit increases by 1 count per clock, but in this embodiment, when various waits are applied, the count increases to several clocks. That is, the count value is configured to change in synchronization with the rising of various wait signals 140. Therefore, the longer the wait state, the longer the counter update cycle.

  When the interrupt generation signal 70 is received, the decoder performs the following operation. When the interrupt count is 0 (see 210), the interrupt acceptance signal is asserted. When the interrupt count is 1 (see 212), the vector control signal 26 is asserted (see 220). During the interrupt count 1, the interrupt vector generation circuit generates a vector address based on the latch output. Then, branching to an interrupt processing routine with an interrupt count of 2, and an instruction end signal 134 is asserted.

2. Microcomputer FIG. 6 is an example of a hardware block diagram of the microcomputer of this embodiment.

  The microcomputer 700 includes a CPU 510, a cache memory 520, an LCD controller 530, a reset circuit 540, a programmable timer 550, a real time clock (RTC) 560, a DRAM controller / bus I / F 570, an interrupt controller 580, a serial interface 590, and a bus controller 600. A / D converter 610, D / A converter 620, input port 630, output port 640, I / O port 650, clock generator 560, prescaler 570 and general-purpose bus 680 connecting them, dedicated bus 730, etc. Various pins 690 and the like are included.

  The CPU 510 has the configuration described with reference to FIGS.

3. Electronic Device FIG. 7 shows an example of a block diagram of the electronic device of this embodiment. The electronic apparatus 800 includes a microcomputer (or ASIC) 810, an input unit 820, a memory 830, a power generation unit 840, an LCD 850, and a sound output unit 860.

  Here, the input unit 820 is for inputting various data. The microcomputer 810 performs various processes based on the data input by the input unit 820. The memory 830 serves as a work area for the microcomputer 810 and the like. The power generation unit 840 is for generating various power sources used in the electronic device 800. The LCD 850 is for outputting various images (characters, icons, graphics, etc.) displayed by the electronic device.

  The sound output unit 860 is for outputting various sounds (sound, game sound, etc.) output from the electronic device 800, and the function can be realized by hardware such as a speaker.

  FIG. 8A illustrates an example of an external view of a mobile phone 950 which is one of electronic devices. The cellular phone 950 includes a dial button 952 that functions as an input unit, an LCD 954 that displays a telephone number, a name, an icon, and the like, and a speaker 956 that functions as a sound output unit and outputs sound.

  FIG. 8B illustrates an example of an external view of a portable game device 960 that is one of electronic devices. The portable game device 960 includes an operation button 962 that functions as an input unit, a cross key 964, an LCD 966 that displays a game image, and a speaker 968 that functions as a sound output unit and outputs game sound.

  FIG. 8C illustrates an example of an external view of a personal computer 970 that is one of electronic devices. The personal computer 970 includes a keyboard 972 that functions as an input unit, an LCD 974 that displays characters, numbers, graphics, and the like, and a sound output unit 976.

  As electronic devices that can use this embodiment, in addition to those shown in FIGS. 8A, 8B, and 8C, a portable information terminal, a pager, an electronic desk calculator, a device including a touch panel, Various electronic devices using an LCD such as a projector, a word processor, a viewfinder type or a monitor direct view type video tape recorder, and a car navigation device can be considered.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

FIG. 3 is a functional block diagram for explaining a configuration of a CPU (an example of a processor) according to the present embodiment. 6 is a timing chart when an interrupt of the CPU according to the present embodiment occurs. It is an example of a structure of an interrupt vector latch circuit. It is a figure for demonstrating the specific structural example of a state machine (interrupt state control circuit). It is a timing chart at the time of interruption occurrence of the state machine of the present embodiment. The hardware block diagram of the microcomputer of this Embodiment. An example of a block diagram of an electronic device including a microcomputer is shown. 8A, 8B, and 8C are examples of external views of various electronic devices. FIGS. 9A and 9B are diagrams for explaining the problems of the prior art.

Explanation of symbols

10 CPU, 20 interrupt state control circuit (state machine), 26 vector control signal, 30 interrupt vector latch circuit, 40 vector address generation circuit, 50 state, 70 interrupt generation signal, 80 interrupt vector signal, 82 latch output, 90 clock, 110 Instruction code selection circuit, 112 instruction code, 120 counter circuit, 122 count value, 130 decoder, 140 various wait signals, 510 CPU, 530 LCD controller, 540 reset circuit, 550 programmable timer, 560 real time clock (RTC), 570 DRAM controller Also bus I / F, 580 interrupt controller, 590 serial interface, 600 bus controller, 610 A / D converter, 620 D / Converter, 630 input port, 640 output port, 650 I / O port, 660 clock generator (PLL), 670 prescaler, 680 general purpose bus, 690 various pins, 700 microcomputer, 710 ROM, 720 RAM, 730 MMU, 740 Clock supply control circuit, 800 electronic equipment, 850 LCD

Claims (6)

A processor that receives an interrupt generation signal and an interrupt vector signal for notifying the occurrence of a hardware interrupt, and branches to an address to the corresponding interrupt processing program,
An interrupt state control circuit that asserts a vector control signal when it is determined that the interrupt vector can be generated based on the state of the processor;
An interrupt vector signal latch circuit that latches an interrupt vector signal when the interrupt generation signal is asserted;
A processor comprising a vector address generation circuit for generating a vector address for branching to a corresponding interrupt processing program based on a latch output of an interrupt vector signal latch circuit when the vector control signal is asserted. In claim 1,
The interrupt state control circuit includes:
Based on the state of the processor, at least two interrupt states of a first state for accepting an interrupt and a second state for generating an interrupt vector are transitioned, and control for asserting a vector control signal in the second state is performed. Feature processor. In any one of Claims 1 thru | or 2.
The vector signal latch circuit is
A processor which is configured to perform control so that a latched value is not changed when an interrupt generation signal is not asserted. In any one of Claims 1 thru | or 3,
The vector signal latch circuit is
A processor comprising: a D lip flop in which a signal for each bit of an interrupt vector is set as a D input, an output signal is input to a vector address generation circuit, and an interrupt generation signal is enabled when asserted.   An integrated circuit device comprising the processor according to claim 1. A processor according to any one of claims 1 to 4;
Means for receiving input information;
Means for outputting a result processed by the information processing device based on input information;
An electronic device comprising:

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