JP2006178725A - Integrated circuit device, communication controller, microcomputer and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit device incorporating a bus interface circuit allowing coping with various bus systems to allow a host side to cope with a contingency in a minimum level even if the contingency occurs in an internal logic circuit. <P>SOLUTION: This integrated circuit device 10 incorporates the bus interface circuit 100 including: an external bus control circuit 110 connected to an external bus 300, controlling input/output; an internal bus control circuit 120 connected to an internal bus 30, controlling input/output; a synchronous control circuit 130 connected to the external bus control circuit and the internal bus control circuit, performing synchronous control of the internal bus and the external bus; an internal status register 140 connected to the external bus control circuit, holding a value of status written by an internal arithmetic circuit, and operating with the same clock as the external bus; and an internal interrupt register 150 connected to the external bus control circuit, holding an internal interrupt value for generating an interrupt in the internal arithmetic circuit, and operating with the same clock as the external bus. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an integrated circuit device, a communication control device, a microcomputer, and an electronic apparatus.

  In an integrated circuit device connected to an external bus, a bus interface part that performs processing for interfacing an external bus and an internal bus may be modularized and configured as a separate block.

  However, the bus interface portion is only related to the bus control, and a register indicating the state of the internal logic circuit exists in the internal logic circuit itself and is not considered as the bus interface portion.

  Therefore, when replacing with other buses, it is the same that only the bus interface part needs to be remade, but there is a problem that diversion to other slave circuit designs is difficult.

  In addition, when the internal logic circuit itself has a malfunction, the host CPU may not be able to cope with it at all.

  The present invention has been made in view of the above problems, and the object of the present invention is to be compatible with various bus systems, and even if an unforeseen situation occurs in the internal logic circuit, the host side is the minimum. An object of the present invention is to provide an integrated circuit device, a communication control device, a microcomputer, and an electronic device that incorporate a bus interface circuit capable of level correspondence.

(1) The present invention
An integrated circuit device connected to an external bus,
An internal bus,
An internal arithmetic circuit connected to the internal bus;
A bus interface circuit connected to the internal bus and the external bus and taking a bus interface between the internal bus and the external bus;
The bus interface circuit is
An external bus control circuit connected to the external bus and controlling input / output of signals to / from the external bus;
An internal bus control circuit that is connected to the internal bus and controls input / output of signals to / from the internal bus;
A synchronization control circuit that is connected to the external bus control circuit and the internal bus control circuit, and performs synchronous control of the external bus and the internal bus;
An internal status register connected to an external bus control circuit, holding the status value written by the internal arithmetic circuit, and operating at the same clock as the external bus;
An internal interrupt register connected to an external bus control circuit, holding an internal interrupt value for generating an interrupt in the internal arithmetic circuit, and operating at the same clock as the external bus;
It is characterized by including.

  In this way, even if an unexpected situation occurs in the internal arithmetic circuit or internal bus, the internal status register and internal interrupt register exist in the bus interface circuit, so the host CPU can handle the lowest level corresponding to the status etc. It can be performed.

  Further, according to the present invention, the internal arithmetic circuit on the slave side and the bus interface circuit can be separated, and the two circuits can be connected according to a separately defined bus standard. In this way, even if the system bus (external bus) format changes, the internal logic circuit and the internal bus remain the same by creating a bus interface circuit that matches the bus standard format with the connection to the internal arithmetic circuit. Since it can be used, it can be easily adapted to various bus systems.

  In addition, by setting the connection to the bus interface part to a predetermined bus standard, it is possible to reuse it for other slaves and to design the bus interface part independently.

(2) The present invention
An integrated circuit device connected to an external bus,
An internal bus,
An internal arithmetic circuit connected to the internal bus;
A bus interface circuit connected to the internal bus and the external bus and interfacing with the internal bus and the external bus;
The bus interface circuit is
An external bus control circuit connected to the external bus and controlling input / output of signals to / from the external bus;
An internal bus control circuit that is connected to the internal bus and controls input / output of signals to / from the internal bus;
A synchronization control circuit that is connected to the external bus control circuit and the internal bus control circuit, and performs synchronous control of the external bus and the internal bus;
An internal status register connected to an external bus control circuit, holding the status value written by the internal arithmetic circuit, and operating at the same clock as the external bus;
It is characterized by including.

(3) The present invention
An integrated circuit device connected to an external bus,
An internal bus,
An internal arithmetic circuit connected to the internal bus;
A bus interface circuit connected to the internal bus and the external bus and interfacing with the internal bus and the external bus;
The bus interface circuit is
An external bus control circuit connected to the external bus and controlling input / output of signals to / from the external bus;
An internal bus control circuit that is connected to the internal bus and controls input / output of signals to / from the internal bus;
A synchronization control circuit that is connected to the external bus control circuit and the internal bus control circuit, and performs synchronous control of the external bus and the internal bus;
An internal interrupt register connected to an external bus control circuit, holding an internal interrupt value for generating an interrupt in the internal arithmetic circuit, and operating at the same clock as the external bus;
It is characterized by including.

(4) The integrated circuit device of the present invention is
The internal status register is connected to an internal arithmetic circuit through a dedicated signal line, and is configured to be writable from the internal arithmetic circuit via the dedicated signal line without going through an internal bus.

(5) The integrated circuit device of the present invention is
The internal interrupt register is connected to the interrupt controller of the internal arithmetic circuit by a dedicated signal line, and is configured to be writable to the interrupt controller of the internal arithmetic circuit via the dedicated signal line without going through the internal bus. Features.

(6) The integrated circuit device of the present invention is
The internal arithmetic circuit and the bus interface circuit are configured to exchange access signals exchanged with an external bus via the internal bus.

  Here, when the internal status register and the internal interrupt register are included in the bus interface circuit, the value of the internal status register and the internal interrupt register are included in the access signal exchanged with the external bus via the internal bus. The value of is not included.

(7) The present invention
An integrated circuit device connected to an external bus,
An internal bus,
An internal arithmetic circuit connected to the internal bus;
A bus interface circuit connected to the internal bus and the external bus and interfacing with the internal bus and the external bus;
The bus interface circuit is
An external bus control circuit connected to the external bus and controlling input / output of signals to / from the external bus;
An internal bus control circuit that is connected to the internal bus and controls input / output of signals to / from the internal bus;
A synchronization control circuit that is connected to the external bus control circuit and the internal bus control circuit and performs synchronization control of the external bus and the internal bus;
The internal arithmetic circuit and the bus interface circuit are configured to exchange access signals exchanged with an external bus via the internal bus.

  According to the present invention, the internal arithmetic circuit on the slave side and the bus interface circuit can be separated, and the two circuits can be connected according to a separately defined bus standard. In this way, even if the format of the system bus (external bus) changes, the internal logic circuit and internal bus remain the same by creating a bus interface circuit that matches the connection with the internal arithmetic circuit to the format of the bus standard. Since it can be used, it can be easily adapted to various bus systems.

  In addition, by setting the connection to the bus interface part to a predetermined bus standard, it is possible to reuse it for other slaves and to design the bus interface part independently.

  (8) The present invention is a microcomputer including any one of the integrated circuit devices described above.

(9) The present invention
A microcomputer as described above;
Means for inputting data to be processed by the microcomputer;
And an output means for outputting data processed by the microcomputer.

1. Integrated Circuit Device Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram for explaining an integrated circuit device according to the present embodiment.

  The integrated circuit device (IC) 10 of this embodiment is an integrated circuit device connected to the external bus 300. For example, the integrated circuit device (IC) of this embodiment is an integrated circuit device (IC) that functions as a slave device, and functions as a host device via the system bus (external bus 300) of the system in which the host CPU 330 exists. The integrated circuit device (IC) 320 may be connected.

  An integrated circuit device (IC) 10 according to the present embodiment includes a bus interface circuit 100 and an internal logic circuit 20.

  The internal logic circuit 20 includes an internal bus 30 and internal arithmetic circuits (including at least one of a CPU 40, a memory 50, an interrupt controller 60, an internal logic control part 70 peripheral unit 80, etc.) connected to the internal bus.

  The bus interface circuit 100 is connected to the internal bus 30 and the external bus 300, and performs processing for interfacing the internal bus 30 and the external bus 300.

  The bus interface circuit 100 is connected to the external bus 300 and controls the input / output of signals to / from the external bus. The bus interface circuit 100 is connected to the internal bus 30 and controls the input / output of signals to / from the internal bus. The internal bus control circuit 120 is connected to the external bus control circuit 110 and the internal bus control circuit 120, and includes a synchronous control circuit (synchronous register in this case) 130 that performs synchronous control of the external bus 300 and the internal bus 30.

  In general, since the external bus 300 and the internal bus 30 operate with different operation clocks, the synchronization control circuit (synchronous register here) 130 performs synchronization control.

  The bus interface circuit 100 is connected to the external bus control circuit 110, holds the status value written by the internal arithmetic circuit (60, 70, 80, etc.), and operates with the same clock as the external bus. 140 may be included.

  Here, the internal status register 140 is connected to an internal arithmetic circuit (60, 70, 80, etc.) by a dedicated signal line (82, 72, 62, etc.), and the internal arithmetic circuit (60, 70, 80, etc.) It may be configured to be writable without the internal bus 30 via the signal lines (82, 72, 62, etc.).

  In this way, even if an unexpected situation occurs in the internal logic circuit 20, the host CPU can issue an interrupt instruction since the register 150 for instructing the internal interrupt to the bus interface circuit exists. The value stored in the internal interrupt register may be temporarily stored in the internal interrupt register 90 provided in the internal logic circuit 20 via the dedicated signal lines 152, 154, and 156 and then input to the interrupt controller 60. Good. Alternatively, the value of 150 of the internal interrupt register may be directly input to the interrupt controller 60 via the dedicated signal lines 152, 154, and 156.

  The bus interface circuit 100 includes an internal interrupt register 150 which is connected to the external bus control circuit 110 and holds an internal interrupt value for generating an interrupt in the internal arithmetic circuit and operates at the same clock as the external bus. Also good.

  Here, the internal interrupt register 150 is connected to the interrupt controller 60 of the internal arithmetic circuit by dedicated signal lines 62, 152, 154, 156, and the dedicated signal lines 62, 152, 154, 156 are connected to the interrupt controller 60 of the internal arithmetic circuit. It may be configured to be writable via 156 without going through the internal bus.

  In this way, even if an unexpected situation occurs in the internal logic circuit 20, since the bus interface circuit has a register (internal status register 140) indicating the state, the host CPU can handle the lowest level corresponding processing corresponding to the status. It can be performed.

  In this embodiment, the slave-side internal logic circuit 20 and the interface circuit 100 can be separated, and the two circuits can be connected according to a separately defined bus standard. In this way, even if the format of the system bus (external bus 300) changes, the internal logic circuit 20 remains the same by creating the interface circuit 100 that matches the connection with the internal logic circuit 20 in accordance with the format of the bus standard. Since it can be used, it can be easily adapted to various bus systems.

  In addition, by setting the connection to the bus interface part to a predetermined bus standard, it is possible to reuse it for other slaves and to design the bus interface part independently.

  FIG. 2 is a diagram for explaining another configuration of the integrated circuit device of the present embodiment.

  The integrated circuit device (IC) 10 ′ according to the present embodiment is an integrated circuit device connected to the external bus 300. For example, the integrated circuit device (IC) of this embodiment is an integrated circuit device (IC) that functions as a slave device, and functions as a host device via the system bus (external bus 300) of the system in which the host CPU 330 exists. The integrated circuit device (IC) 320 may be connected.

  The integrated circuit device (IC) 10 ′ of this embodiment includes a bus interface circuit 100 and an internal logic circuit 220.

  The internal logic circuit 220 includes an internal bus 230 and an internal arithmetic circuit (here, at least one of a plurality of local processors 240, 250, 260, 270, 280) connected to the internal bus.

  The bus interface circuit 100 is connected to the internal bus 230 and the external bus 300, and performs processing for interfacing the internal bus 230 and the external bus 300.

  The bus interface circuit 100 is connected to the external bus 300 and is connected to the external bus control circuit 100 that controls the input / output of signals with the external bus and the internal bus 230, and controls the input / output of signals with the internal bus. The internal bus control circuit 120 is connected to the external bus control circuit 110 and the internal bus control circuit 120, and includes a synchronous control circuit (synchronous register in this case) 130 that performs synchronous control of the external bus 300 and the internal bus 230.

  In general, since the external bus 300 and the internal bus 230 operate with different operation clocks, synchronization control is performed by a synchronization control circuit (here, a synchronization register) 130.

  The bus interface circuit 100 is connected to the external bus control circuit 110, holds the status value written by the internal arithmetic circuit (240, 250, 260, 270, 280, etc.), and operates at the same clock as the external bus. The internal status register 140 may be included.

  Here, the internal status register 140 is an internal arithmetic circuit (here, at least one of a plurality of local processors 240, 250, 260, 270, 280) and a dedicated signal line (242, 252, 262, 272, 282, etc.). Connected and configured to allow writing from an internal arithmetic circuit (240, 250, 260, 270, 280, etc.) via the dedicated signal line (242, 252, 262, 272, 282, etc.) without going through the internal bus 230 You may make it do.

  In this way, even if an unexpected situation occurs in the internal logic circuit 220, the bus interface circuit 100 has a register (internal status register 140) indicating the state of the internal logic circuit 220. The lowest level of response processing can be performed.

  The bus interface circuit 100 is connected to the external bus control circuit 110 and holds internal interrupt values for generating interrupts to the internal arithmetic circuits (240, 250, 260, 270, 280, etc.). An internal interrupt register 150 that operates at the same clock may be included.

  Here, the internal interrupt register 150 is an internal arithmetic circuit (here, at least one of a plurality of local processors 240, 250, 260, 270, 280) and a dedicated signal line (244, 254, 264, 274, 284, etc.). Connected and configured to be able to write to internal arithmetic circuits (240, 250, 260, 270, 280, etc.) via the dedicated signal lines (244, 254, 264, 274, 284, etc.) without going through the internal bus 230 You may make it do.

  In this way, even if an unexpected situation occurs in the internal logic circuit 220, the host CPU can issue an interrupt instruction because the register 150 for instructing the internal interrupt to the bus interface circuit exists.

  In the present embodiment, the internal logic circuit 220 on the slave side and the interface circuit 100 can be separated, and the two circuits can be connected according to a separately defined bus standard. In this way, even if the format of the system bus (external bus 300) changes, the internal logic circuit 220 remains the same by creating the interface circuit 100 in which the connection with the internal logic circuit 220 matches the format of the bus standard. Since it can be used, it can be easily adapted to various bus systems.

  In addition, by setting the connection to the bus interface part to a predetermined bus standard, it is possible to reuse it for other slaves and to design the bus interface part independently.

2. Microcomputer FIG. 3 is an example of a hardware block diagram of the microcomputer of this embodiment.

  The microcomputer 700 includes a CPU 510, a cache memory 520, a RAM 710, a ROM 720, an MMU 730, an LCD controller 530, a reset circuit 540, a programmable timer 550, a real time clock (RTC) 560, a DRAM controller 570, an interrupt controller 580, a communication control device 590, Bus controller 600, A / D converter 610, D / A converter 620, input port 630, output port 640, I / O port 650, clock generator 660, prescaler 670, bus interface circuit 740 and general-purpose connecting them A bus 680, a dedicated bus 750, etc., various pins 690, etc. are included.

  The bus interface circuit 740 has the configuration described in FIG. 1 or FIG.

3. Electronic Device FIG. 4 shows an example of a block diagram of the electronic device of this embodiment. The electronic apparatus 800 includes a microcomputer (or ASIC) 810, an input unit 820, a memory 830, a power generation unit 840, an LCD 850, and a sound output unit 860.

  Here, the input unit 820 is for inputting various data. The microcomputer 810 performs various processes based on the data input by the input unit 820. The memory 830 serves as a work area for the microcomputer 810 and the like. The power generation unit 840 is for generating various power sources used in the electronic device 800. The LCD 850 is for outputting various images (characters, icons, graphics, etc.) displayed by the electronic device. The sound output unit 860 is for outputting various sounds (sound, game sound, etc.) output from the electronic device 800, and the function can be realized by hardware such as a speaker.

  FIG. 5A illustrates an example of an external view of a mobile phone 950 which is one of electronic devices. The cellular phone 950 includes a dial button 952 that functions as an input unit, an LCD 954 that displays a telephone number, a name, an icon, and the like, and a speaker 956 that functions as a sound output unit and outputs sound.

  FIG. 5B illustrates an example of an external view of a portable game device 960 that is one of electronic devices. The portable game device 960 includes an operation button 962 that functions as an input unit, a cross key 964, an LCD 966 that displays a game image, and a speaker 968 that functions as a sound output unit and outputs game sound.

  FIG. 5C illustrates an example of an external view of a personal computer 970 that is one of electronic devices. The personal computer 970 includes a keyboard 972 that functions as an input unit, an LCD 974 that displays characters, numbers, graphics, and the like, and a sound output unit 976.

  By incorporating the microcomputer of this embodiment into the electronic devices in FIGS. 5A to 5C, an electronic device with low cost and high image processing speed can be provided.

  In addition to the devices shown in FIGS. 5A, 5 </ b> B, and 5 </ b> C, electronic devices that can use this embodiment include portable information terminals, pagers, electronic desk calculators, devices equipped with touch panels, Various electronic devices using an LCD such as a projector, a word processor, a viewfinder type or a monitor direct view type video tape recorder, a digital television, a car navigation device can be considered.

  In addition, an electronic device having no display unit such as an LCD such as a DVD recorder may be used.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

It is a figure for demonstrating the integrated circuit device of this Embodiment. It is a figure for demonstrating the other structure of the integrated circuit device of this Embodiment. It is an example of the hardware block diagram of the microcomputer of this Embodiment. An example of a block diagram of an electronic device including a microcomputer is shown. 5A, 5B, and 5C are examples of external views of various electronic devices.

Explanation of symbols

10, 10 ′ IC, 20 internal logic circuit, 30 internal bus, 40 CPU, 50 memory, 60 interrupt controller, 62 signal line, 64 signal line, 70 name part logic circuit, 72 signal line, 80 peripheral part, 82 signal line , 100 bus interface circuit, 110 external bus control unit, 120 internal bus control unit, 130 synchronization register, 220 internal logic circuit, 230 internal bus, 240 local processor 0, 250 local processor 1, 260 local processor 2, 270 local processor 3 280 Local processor 4, 300 External bus, 320 IC, 330 Host CPU, 510 CPU, 520 Cache memory 530 LCD controller, 540 Reset circuit, 550 Programmable timer, 560 Real time clock (RTC), 570 DMA controller / bus I / F, 580 interrupt controller, 590 communication control circuit, 600 bus controller, 610 A / D converter, 620 D / A converter, 630 input port, 640 output port, 650 I / O port, 660 clock generator (PLL), 670 prescaler, 680 general-purpose bus, 690 various pins, 700 microcomputer, 710 ROM, 720 RAM, 730 MMU, 740 bus interface circuit 750 dedicated bus, 800 electronic device, 810 Microcomputer (ASIC), 820 input unit, 830 memory, 840 power generation unit 850 LCD, 860 sound output unit, 950 mobile phone, 952 dial button, 954 LCD, 956 Peaker, 960 portable game device, 962 operation button, 964 cross key, 966 LCD, 968 speaker, 970 personal computer, 972 keyboard, 974 LCD, 976 sound output unit

Claims (9)

An integrated circuit device connected to an external bus,
An internal bus,
An internal arithmetic circuit connected to the internal bus;
A bus interface circuit connected to the internal bus and the external bus and taking a bus interface between the internal bus and the external bus;
The bus interface circuit is
An external bus control circuit connected to the external bus and controlling input / output of signals to / from the external bus;
An internal bus control circuit that is connected to the internal bus and controls input / output of signals to / from the internal bus;
A synchronization control circuit that is connected to the external bus control circuit and the internal bus control circuit, and performs synchronous control of the external bus and the internal bus;
An internal status register connected to an external bus control circuit, holding the status value written by the internal arithmetic circuit, and operating at the same clock as the external bus;
An internal interrupt register connected to an external bus control circuit, holding an internal interrupt value for generating an interrupt in the internal arithmetic circuit, and operating at the same clock as the external bus;
An integrated circuit device comprising: An integrated circuit device connected to an external bus,
An internal bus,
An internal arithmetic circuit connected to the internal bus;
A bus interface circuit connected to the internal bus and the external bus and interfacing with the internal bus and the external bus;
The bus interface circuit is
An external bus control circuit connected to the external bus and controlling input / output of signals to / from the external bus;
An internal bus control circuit that is connected to the internal bus and controls input / output of signals to / from the internal bus;
A synchronization control circuit that is connected to the external bus control circuit and the internal bus control circuit, and performs synchronous control of the external bus and the internal bus;
An internal status register connected to an external bus control circuit, holding the status value written by the internal arithmetic circuit, and operating at the same clock as the external bus;
An integrated circuit device comprising: An integrated circuit device connected to an external bus,
An internal bus,
An internal arithmetic circuit connected to the internal bus;
A bus interface circuit connected to the internal bus and the external bus and interfacing with the internal bus and the external bus;
The bus interface circuit is
An external bus control circuit connected to the external bus and controlling input / output of signals to / from the external bus;
An internal bus control circuit that is connected to the internal bus and controls input / output of signals to / from the internal bus;
A synchronization control circuit that is connected to the external bus control circuit and the internal bus control circuit, and performs synchronous control of the external bus and the internal bus;
An internal interrupt register connected to an external bus control circuit, holding an internal interrupt value for generating an interrupt in the internal arithmetic circuit, and operating at the same clock as the external bus;
An integrated circuit device comprising: In claim 1 or claim 2,
The internal status register is connected to an internal arithmetic circuit via a dedicated signal line, and is configured to be writable from the internal arithmetic circuit via the dedicated signal line without going through an internal bus. . In claim 1 or claim 3,
The internal interrupt register is connected to the interrupt controller of the internal arithmetic circuit by a dedicated signal line, and is configured to be writable to the interrupt controller of the internal arithmetic circuit via the dedicated signal line without going through the internal bus. An integrated circuit device. In any one of Claims 1 to 5,
The integrated circuit device, wherein the internal arithmetic circuit and the bus interface circuit are configured to exchange access signals exchanged with an external bus via the internal bus. An integrated circuit device connected to an external bus,
An internal bus,
An internal arithmetic circuit connected to the internal bus;
A bus interface circuit connected to the internal bus and the external bus and interfacing with the internal bus and the external bus;
The bus interface circuit is
An external bus control circuit connected to the external bus and controlling input / output of signals to / from the external bus;
An internal bus control circuit that is connected to the internal bus and controls input / output of signals to / from the internal bus;
A synchronization control circuit that is connected to the external bus control circuit and the internal bus control circuit and performs synchronization control of the external bus and the internal bus;
The integrated circuit device, wherein the internal arithmetic circuit and the bus interface circuit are configured to exchange access signals exchanged with an external bus via the internal bus.   A microcomputer comprising the integrated circuit device according to claim 1. A microcomputer according to claim 8;
Means for inputting data to be processed by the microcomputer;
An electronic device comprising: output means for outputting data processed by the microcomputer.

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