JP2006277333A - Integrated circuit device, microcomputer, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve security intensity so that the code of software for operating a CPU is not to be read for the purpose of reverse engineering or the like. <P>SOLUTION: The integrated circuit device 10 includes a CPU 20, an on-chip debugging circuit 70, and a memory 30 for command. The integrated circuit device 10 also includes a command bus 50 connected to the CPU 20 and the memory 30 for command, and a data bus 60 that is separated from the command bus 50 and is connected to the CPU 20 and a memory 40 other than the memory 30 for command. The CPU 20 comprises a first terminal 22 connected to the command bus 50, a second terminal 24 connected to the data bus 60, a command code processing section 26 for processing a signal inputted from the first terminal 22, and a data processing section 28 for processing a signal inputted from the second terminal 24. The on-chip debugging circuit 70 is constituted so that the CPU 20 cannot refer to the signal inputted from the first terminal 22. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an integrated circuit device, a microcomputer, and an electronic device.

  In recent years, there has been an increasing demand for microcomputers that can be incorporated into electronic devices such as game devices, car navigation systems, printers, portable information terminals, and DVD recorders having network functions to realize advanced information processing.

  In a system LSI in which a CPU such as an embedded microcomputer is integrated, it is a problem from the viewpoint of security that the code of software (firmware) for operating the CPU is read for the purpose of reverse engineering. .

Conventionally, reading from the outside is prevented by storing the originally encrypted code in the ROM or by storing the code in the ROM built in the IC chip.
JP 2000-347942 A JP-A-5-324480

  However, even if the ROM code is encrypted, the ROM code is decrypted and expanded on the RAM by some method and executed by the CPU. Even if the code is stored in the built-in ROM, it can be referred from the CPU. Therefore, when a pin-saving debugging tool such as ICE is connected to the CPU, there is a possibility that the decrypted code on the RAM or the code on the built-in ROM may be read via the ICE.

  The present invention has been made in view of the technical problems as described above. The purpose of the present invention is to prevent the software code for operating the CPU from being read for purposes such as reverse engineering. An object of the present invention is to provide an integrated circuit device and the like with increased strength.

(1) The present invention
CPU,
An on-chip debugging circuit that communicates with a pin-saving debugging tool to perform on-chip debugging;
An instruction memory storing an instruction code of an instruction executed by the CPU;
An integrated circuit device comprising:
An instruction bus connected to the CPU and the instruction memory;
A data bus separated from the instruction bus and connected to a CPU and a memory other than the instruction memory;
The CPU
A first terminal connected to the instruction bus;
A second terminal connected to the data bus;
An instruction code processing unit for processing a signal input from the first terminal;
A data processing unit that processes a signal input from a second terminal, and configured to execute an instruction read via the instruction bus,
The on-chip debug circuit is
The CPU is configured so that a signal input from the first terminal cannot be referred to.

  Here, the instruction memory may be a non-rewritable memory (for example, ROM, mask ROM, etc.) or a volatile or non-volatile rewritable memory (RAM, flash ROM, etc.).

  According to the present invention, the CPU path is separated by an instruction and data, and the instruction path is configured so that it cannot be referred to from an external debug module via an on-chip debug circuit or the like.

  Therefore, even if a debugging tool such as ICE is used, an instruction code executed by the CPU cannot be extracted to the outside, and an integrated circuit device with high security against reverse engineering using ICE or the like can be provided. it can.

(2) The integrated circuit device of the present invention is
Instruction code executed by the CPU during debugging is stored, and includes a rewritable memory connected to both the instruction bus and the data bus,
The CPU is configured to execute an instruction by reading an instruction code stored in the rewritable memory via the instruction bus during debugging.

  The rewritable memory may be volatile memory (RAM) or non-volatile memory (flash ROM or the like).

  In the present invention, the CPU is configured to execute an instruction by reading an instruction code stored in a rewritable memory via an instruction bus during debugging. The on-chip debug circuit is configured to be able to read out the instruction code stored in the rewritable memory via the data bus during debugging.

  Accordingly, when it is desired to know the contents of the instruction code executed at the time of debugging, for example, the instruction code may be specified by the value of the program counter and read out from the rewritable memory via the data bus.

  As described above, the present embodiment has a rewritable memory in which both the instruction bus and the data bus are connected. During development (debugging), the instruction code is arranged on the rewritable memory to execute instructions. Debugging can be performed while referring to the code, and efficient debugging can be performed.

  When the CPU is normally executed (not when debugging), the instruction code stored in the instruction memory is read out via the instruction bus and the instruction is executed. Upon completion, the instruction code stored in the rewritable memory may be stored in the instruction memory.

(3) The integrated circuit device of the present invention
A decryption processing unit for receiving and decrypting the encrypted data;
The decryption processing unit
Receive and decrypt the encrypted instruction code stored in the external memory,
The instruction memory is
The memory is configured as a rewritable memory, and stores the instruction code decoded by the decoding processing unit.

  In the present invention, the decoded instruction code stored in the instruction memory cannot be referred to by a debug module such as ICE. Accordingly, it is possible to provide an integrated circuit device having a high security strength against reverse engineering using ICE or the like because the decoded instruction code cannot be taken out even when the instruction is executed by decoding the external memory. Can do.

(4) The present invention
A microcomputer including any one of the integrated circuit devices described above.

(5) The present invention
A microcomputer as described above;
An input source of data to be processed by the microcomputer;
And an output device for outputting data processed by the microcomputer.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

1. Features of this Embodiment FIG. 1 is a diagram for explaining an integrated circuit device according to a first embodiment.

  The integrated circuit device 10 according to the first embodiment includes a CPU 20, an on-chip debug circuit 70, an instruction memory 30, an instruction bus 50, and a data bus 60.

  The instruction memory 30 is a built-in memory configured so as not to be read from outside the chip, and stores instruction codes of instructions executed by the CPU 20. The instruction memory 30 may be a non-rewritable memory (for example, ROM) or a volatile or non-volatile rewritable memory (RAM, flash ROM, etc.). The instruction memory 30 is not connected to a bus other than the instruction bus 50 (for example, the data bus 60), and is configured to be readable only via the instruction bus 50.

  The instruction bus 50 is connected to the CPU 20 and the instruction memory 30.

  The data bus 60 is separated from the instruction bus 50 and is connected to the CPU 20 and a memory other than the instruction memory 30 (here, the data memory 40).

  The CPU 20 processes a signal input from the first terminal 52 connected to the instruction bus 50, the second terminal 24 connected to the data bus 60, and the first terminal 22. Unit 26 and a data processing unit 58 that processes a signal input from the second terminal 24. The CPU 20 is configured to read the instruction code stored in the instruction memory 30 via the instruction bus 50 and execute the instruction.

  The instruction code processing unit 26 includes, for example, a fetch circuit that fetches an input instruction code, a decode circuit that decodes an input instruction code, and the like. The data processing unit 58 includes a general-purpose register for holding input data.

  The on-chip debug circuit 70 has a function of performing on-chip debugging by communicating with a pin-saving debug tool, and is configured not to refer to a signal input from the first terminal 22 to the CPU 20.

  The on-chip debug circuit 70 includes a ROM, a RAM, a control register, an SIO, and the like. Various name processes (I / O interface with a debug module, It analyzes the debug command, interrupt processing from the user program to the monitor program, etc.), and is configured so that the instruction register of the CPU cannot be referred to.

  In this embodiment, an instruction memory 30 in which an instruction code is stored and a data memory 40 in which data is stored are provided separately, and are connected to separate buses (酩酊 bus 50 and data bus 40). ing. The command and data are input from separate terminals (first terminal and second terminal) of the CPU.

  Thus, in this embodiment, the CPU path is separated from the instruction and data, and the instruction path is configured so that it cannot be referenced from an external debug module via an on-chip debug circuit or the like.

  In general, the execution code of an instruction can be read by a debug module such as ICE in a case where the memory is accessible from the instruction bus, the data bus, and the data bus. However, the instruction memory 30 of the present embodiment is configured to be accessible from the instruction bus 50 but not from the data bus 60.

  Therefore, even if a debugging tool such as ICE is used, an instruction code executed by the CPU cannot be extracted to the outside, and an integrated circuit device with high security against reverse engineering using ICE or the like can be provided. it can.

  FIG. 2 is a diagram for explaining the integrated circuit device according to the second embodiment.

  The integrated circuit device 10 according to the second embodiment further includes a rewritable memory (debug / general purpose memory) 80 and a bus bridge 82 in addition to the second embodiment.

  In the second embodiment, the same constituent elements as those in the first embodiment are denoted by the same reference numerals as those in FIG.

  A rewritable memory (debug / general purpose memory) 80 stores instruction codes executed by the CPU during debugging and is connected to both the instruction bus and the data bus.

  The rewritable volatile memory may be connected to an instruction bus and a data bus and connected to a bus bridge circuit 82 capable of switching between them, and the bus bridge circuit 82 may be connected to the data bus during debugging. In this way, the internal debug module can refer to the instruction code stored in the rewritable volatile memory (debugging / general purpose memory) 80 during debugging.

  The rewritable memory (debugging / general purpose memory) 80 may be a volatile memory (RAM) or a non-volatile memory (flash ROM or the like).

  In the present embodiment, the CPU 20 is configured to read an instruction code stored in a rewritable memory (debug / general purpose memory) 80 via the instruction bus 50 and execute an instruction during debugging.

  The on-chip debug circuit 70 is configured to be able to read out the instruction code stored in the rewritable memory (debug / general purpose memory) 80 during debugging via the data bus.

  Therefore, when it is desired to know the contents of the instruction code executed at the time of debugging, for example, the instruction code is specified by the value of the program counter and is read from the rewritable memory (debug / general purpose memory) 80 via the data bus. You may do it.

  As described above, the present embodiment has the rewritable memory (debug / general purpose memory) 80 to which both the instruction bus 50 and the data bus 60 are connected, and this rewritable memory (for debug) is being developed (debugging). By arranging the instruction code on the (/ general purpose memory) 80, debugging can be performed while referring to the execution code of the instruction, and efficient debugging can be performed.

  When the CPU is normally executed (not when debugging), the instruction code stored in the instruction memory is read out via the instruction bus and the instruction is executed. Upon completion, the instruction code stored in the rewritable memory may be stored in the instruction memory.

  FIG. 3 is a diagram for explaining an integrated circuit device according to the third embodiment.

  The integrated circuit device 10 according to the third embodiment further includes a decoding circuit 90 in addition to the second embodiment.

  In the second embodiment, the same components as those in the first embodiment and the first embodiment are denoted by the same reference numerals as those in FIG. 1 and FIG.

  The decryption circuit 90 performs a process of receiving and decrypting the encrypted instruction code stored in the external memory 110.

  The instruction memory 30 is configured as a rewritable memory such as a RAM or a flash ROM, and stores the instruction code decoded by the decoding circuit 90.

  In this embodiment, since the decoded instruction code stored in the instruction memory 30 cannot be referred to by a debug module such as ICE, the decoding is performed even when the external memory is decoded and the instruction is executed. Therefore, it is possible to provide an integrated circuit device with high security strength against reverse engineering using ICE or the like.

2. Microcomputer FIG. 4 is an example of a hardware block diagram of the microcomputer of this embodiment.

  The microcomputer 700 includes a CPU 510, a cache memory 520, a RAM 710, a ROM 720, an MMU 730 LCD controller 530, a reset circuit 540, a programmable timer 550, a real-time clock (RTC) 560, a DRAM controller 570, an interrupt controller 580, and a communication control device (serial interface). 590, bus controller 600, A / D converter 610, D / A converter 620, input port 630, output port 640, I / O port 650, clock generator 660, prescaler 670, and general-purpose bus 680 connecting them A debug module 740, a dedicated bus 750, etc., and various pins 690, etc. are included.

3. Electronic Device FIG. 5 shows an example of a block diagram of the electronic device of this embodiment. The electronic apparatus 800 includes a microcomputer (or ASIC) 810, an input unit 820, a memory 830, a power generation unit 840, an LCD 850, and a sound output unit 860.

  Here, the input unit 820 is for inputting various data. The microcomputer 810 performs various processes based on the data input by the input unit 820. The memory 830 serves as a work area for the microcomputer 810 and the like. The power generation unit 840 is for generating various power sources used in the electronic device 800. The LCD 850 is for outputting various images (characters, icons, graphics, etc.) displayed by the electronic device. The sound output unit 860 is for outputting various sounds (sound, game sound, etc.) output from the electronic device 800, and the function can be realized by hardware such as a speaker.

  FIG. 6A illustrates an example of an external view of a mobile phone 950 which is one of electronic devices. The cellular phone 950 includes a dial button 952 that functions as an input unit, an LCD 954 that displays a telephone number, a name, an icon, and the like, and a speaker 956 that functions as a sound output unit and outputs sound.

  FIG. 6B illustrates an example of an external view of a portable game device 960 that is one of electronic devices. The portable game device 960 includes an operation button 962 that functions as an input unit, a cross key 964, an LCD 966 that displays a game image, and a speaker 968 that functions as a sound output unit and outputs game sound.

  FIG. 6C illustrates an example of an external view of a personal computer 970 that is one of electronic devices. The personal computer 970 includes a keyboard 972 that functions as an input unit, an LCD 974 that displays characters, numbers, graphics, and the like, and a sound output unit 976.

  By incorporating the microcomputer of this embodiment into the electronic devices in FIGS. 6A to 6C, an electronic device with low cost and high image processing speed can be provided.

  As electronic devices that can use this embodiment, in addition to those shown in FIGS. 6A, 6B, and 6C, a portable information terminal, a pager, an electronic desk calculator, a device including a touch panel, Various electronic devices using an LCD such as a projector, a word processor, a viewfinder type or a monitor direct view type video tape recorder, and a car navigation device can be considered.

  Electronic devices that do not use an LCD, such as a DVD recorder having a network function, may be used.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

1 is a diagram for explaining an integrated circuit device according to a first embodiment; FIG. 6 is a diagram for explaining an integrated circuit device according to a second embodiment. FIG. 6 is a diagram for explaining an integrated circuit device according to a third embodiment. It is an example of the hardware block diagram of the microcomputer of this Embodiment. An example of a block diagram of an electronic device including a microcomputer is shown. 6A, 6B, and 6C are examples of external views of various electronic devices.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Integrated circuit device, 20 CPU, 22 1st terminal, 24 2nd terminal, 26 Instruction code processing part, 28 Data processing part, 30 Instruction memory, 40
Data memory, 50 instruction bus, 60 data bus, 70 on-chip debug circuit, 80 debug / general purpose memory, 82 bus bridge, 90 decoding circuit, 92 memory interface, 510, CPU, 520 cache memory 530 LCD controller, 540 reset Circuit, 550 Programmable timer, 560 Real time clock (RTC), 570 DMA controller / bus I / F, 580 Interrupt controller, 590 Communication control circuit (serial interface), 600 Bus controller, 610 A / D converter, 620 D / A Converter, 630 input port, 640 output port, 650 I / O port, 660 clock generator (PLL), 670 prescaler, 680 general-purpose bus, 690 various pins, 700 microcompilation 710 ROM, 720 RAM, 730 MMU, 740 picture bag module, 750 dedicated bus, 800 electronic device, 810 microcomputer (ASIC), 820 input unit, 830 memory, 840 power generation unit 850 LCD, 860 sound output unit , 950 mobile phone, 952 dial button, 954 LCD, 956 speaker, 960 portable game device, 962 operation button, 964 cross key, 966 LCD, 968 speaker, 970 personal computer, 972 keyboard, 974 LCD, 976 sound output unit

Claims (5)

CPU,
An on-chip debugging circuit that communicates with a pin-saving debugging tool to perform on-chip debugging;
An instruction memory storing an instruction code of an instruction executed by the CPU;
An integrated circuit device comprising:
An instruction bus connected to the CPU and the instruction memory;
A data bus separated from the instruction bus and connected to a CPU and a memory other than the instruction memory;
The CPU
A first terminal connected to the instruction bus;
A second terminal connected to the data bus;
An instruction code processing unit for processing a signal input from the first terminal;
A data processing unit that processes a signal input from a second terminal, and configured to execute an instruction read via the instruction bus,
The on-chip debug circuit is
An integrated circuit device characterized in that a signal inputted from a first terminal to a CPU cannot be referred to. In claim 1,
Instruction code executed by the CPU during debugging is stored, and includes a rewritable memory connected to both the instruction bus and the data bus,
The integrated circuit device, wherein the CPU is configured to execute an instruction by reading an instruction code stored in the rewritable memory via the instruction bus during debugging. In any one of Claims 1 thru | or 2.
A decryption processing unit for receiving and decrypting the encrypted data;
The decryption processing unit
Receive and decrypt the encrypted instruction code stored in the external memory,
The instruction memory is
An integrated circuit device comprising a rewritable memory and storing an instruction code decoded by the decoding processing unit.   A microcomputer comprising the integrated circuit device according to claim 1. A microcomputer according to claim 4;
An input source of data to be processed by the microcomputer;
And an output device for outputting data processed by the microcomputer.

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