JP2006079332A - Integrated circuit device, microcomputer and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit device, a microcomputer and electronic equipment for performing DMA division transfer by one channel without increasing hardware. <P>SOLUTION: This integrated circuit device includes a DMA transfer control register 110 and a DMA transfer control circuit 130 for dividing transfer object data into a plurality of blocks based on the value of the DMA transfer control register, and for controlling DMA transfer to be performed by block units. The DMA transfer control register 110 includes a block data size storage register 120 and an address offset register 122, and the DMA transfer control circuit 130 counts data transfer amounts, and adds an offset address based on the address offset value when the data transfer amounts reach a block data size value, and calculates the address of the transfer destination of the next block. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an integrated circuit device, a microcomputer, and an electronic apparatus that control DMA transfer between memories.

In general, for data transfer between an I / O device and a memory or between a plurality of memories, a DMA controller that transfers data at high speed without using a CPU is widely used. As this type of DMA controller, for example, a data length is set for each DMA channel, a transfer source address for reading data and a transfer destination address for writing data are designated, and continuous transfer processing is executed by an automatic address update function. There is something to do. In the conventional DMA data transfer method, even a large amount of data is often implemented by one DMA transfer. In addition, when performing divided transfer, for example, a plurality of channels are used and a plurality of channels are connected to perform block transfer, or a schedule table is used, and necessary transfer contents are set in the schedule table. It was.
JP-A-7-306825

  However, if the conventional DMA data transfer method is implemented by a single transfer, the internal bus is secured by DMA data transfer when performing the transfer, and other units need to wait to use the internal bus. There was a problem that it was.

  Further, when the divided transfer is realized using a plurality of channels, it is necessary to prepare channels necessary for the quantity of DMA data to be divided.

  In the case of implementing with the divided schedule table, a dedicated schedule table is required, and a logic circuit for increasing the HW and managing the schedule is required.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an integrated circuit device and a microcomputer capable of DMA division transfer with one channel without causing an increase in hardware. And to provide electronic equipment.

(1) The present invention
An integrated circuit device including a DMA transfer control register and a DMA transfer control circuit that controls transfer of data to be divided into a plurality of blocks based on the value of the DMA transfer control register to perform DMA transfer in units of blocks,
The DMA transfer control register is
A block data size storage register in which the data size of each divided block is stored;
An address offset register in which offset addresses to be added in block units are stored,
The DMA transfer control circuit includes:
A block data transfer end detection circuit that counts the data transfer amount and determines the end of data transfer for one block when the data transfer amount reaches the block data size value stored in the block data size storage register;
A transfer destination address calculation circuit for adding an offset address based on the address offset value stored in the address offset register when calculating the end of data transfer for one block and calculating the address of the transfer destination of the next block Features.

  Here, the DMA transfer control register is set for each channel that performs DMA transfer.

  According to the present invention, the transfer target data is divided into blocks of the data size stored in the block data size storage register, and DMA transfer is performed to an address obtained by adding an offset by the address offset stored in the address offset register in each block unit. It can be performed.

  As described above, according to the present invention, DMA division transfer can be realized with one channel without increasing the hardware scale.

  Moreover, simply specifying the desired values (divided data size and header size) in the block data size storage register and the address offset register automatically secures a header area, which is convenient when adding a header for each block. is there.

(2) The integrated circuit device of the present invention is
The transfer control register is
It further includes a control register storing block management information for managing whether or not the bus is reoccupied in blocks.
The DMA transfer control circuit includes:
And a circuit that controls whether or not the bus is reoccupied on a block basis based on the block management information stored in the control register.

  The control register may be configured to use a part of a register storing various control data used when performing DAM transfer control for block management information.

  According to the present invention, the internal bus is released between block transfers by setting a value for instructing to reexamine the bus in block units to a predetermined position (position of block management information) in the control register. Therefore, the internal bus can be effectively used.

(3) The integrated circuit device of the present invention
An integrated circuit device including a DMA transfer control register and a DMA transfer control circuit that controls transfer of data to be divided into a plurality of blocks based on the value of the DMA transfer control register to perform DMA transfer in units of blocks,
The DMA transfer control register is
A block data size storage register in which the data size of each divided block is stored;
It further includes a control register storing block management information for managing whether or not the bus is reoccupied in blocks.
The DMA transfer control circuit includes:
A block data transfer end detection circuit that counts the data transfer amount and determines the end of data transfer for one block when the data transfer amount reaches the block data size value stored in the block data size storage register;
A circuit that controls whether or not the bus is reoccupied on a block basis based on block management information stored in the control register when the end of data transfer for one block is detected.

  The control register may be configured to use a part of a register storing various control data used when performing DAM transfer control for block management information.

  According to the present invention, the internal bus is released between block transfers by setting a value for instructing to reexamine the bus in block units to a predetermined position (position of block management information) in the control register. Therefore, the internal bus can be effectively used.

(4) The integrated circuit device of the present invention is
The transfer control register is
It further includes a data size register in which the transfer target data size is stored,
The DMA transfer circuit includes:
A data transfer end detection circuit for counting the data transfer amount and detecting the transfer end of the transfer target data when the data transfer amount reaches the data size value stored in the data size register;
The transfer destination address calculation circuit includes:
Until the end of transfer of data to be transferred is detected, it is determined that there is a next block, and a transfer destination address of the next block is calculated.

(5) The integrated circuit device of the present invention is
The transfer control register is
A transfer source address register storing a transfer source address of data; and
A transfer destination address register storing a transfer destination address of the data,
The DMA transfer control circuit includes:
A transfer source address update circuit for updating the transfer source address register value according to the data transfer amount,
The transfer destination address calculation circuit includes:
The transfer destination address register value is updated according to the data transfer amount, and the transfer destination address register value is updated by adding an offset address in units of blocks.
Data transfer control is performed by outputting values of a transfer source address register and a transfer destination address register to an address bus.

(6) The present invention
A microcomputer including any one of the integrated circuit devices described above.

(7) The integrated circuit device of the present invention is
A microcomputer as described above;
Means for inputting data to be processed by the microcomputer;
And an output means for outputting data processed by the microcomputer.

1. Integrated Circuit Device Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram for explaining an integrated circuit device according to the present embodiment.

  The integrated circuit device 10 of this embodiment includes a DMA controller (DMA transfer method) 100.

  The DMA controller (DMA transfer method) 100 responds to a DMA request received from the CPU 20 between a plurality of memories connected to a common bus 50 (internal bus) (for example, external memory via the internal memory 30 and the external memory controller 40). 70), or the DMA transfer between the I / O device and the memory is controlled.

  The DMA controller (DMA transfer method) 100 is a DMA transfer control register 110 and a DMA transfer for controlling the transfer target data to be divided into a plurality of blocks based on the value of the DMA transfer control register 110 and performing the DMA transfer in units of blocks. A control circuit 130 is included.

  The DMA transfer control register 110 includes a block data size storage register (BTC) 120 that stores the data size of each divided block, and an address offset register (DAO) 122 that stores an offset address added to each block. Configure as follows.

  The DMA transfer control circuit 130 counts the data transfer amount, and when the data transfer amount reaches the block data size value stored in the block data size storage register, the block data for determining the end of data transfer for one block When the transfer end detection circuit 132 detects the end of data transfer for one block, transfer that adds an offset address based on the address offset value stored in the address offset register and calculates the transfer destination address of the next block A destination address calculation circuit 134 is included.

  The DMA transfer control register 110 may include a control register (CTL) 116 that stores block management information for managing whether or not the bus is reoccupied in units of blocks.

  The DMA transfer control circuit 130 may include a circuit for controlling whether or not the bus is reoccupied in units of blocks based on block management information stored in the control register (CTL) 116.

  The DMA transfer control register 110 may further include a data size register (TCR) 118 that stores a transfer target data size.

  The DMA transfer control circuit 130 counts the data transfer amount, and when the data transfer amount reaches the data size value stored in the data size register, the DMA transfer control circuit 130 detects a data transfer end detection circuit 136 that detects the transfer end of the transfer target data. Further, it may be included.

  The DMA transfer control register 110 may further include a transfer source address register (SAR) 112 storing a data transfer source address and a transfer destination address register (DAR) 114 storing a data transfer destination address. Good.

A transfer source address update circuit 138 that updates the transfer source address register value according to the data transfer amount;
The DMA transfer control register 110 further includes a transfer source address update circuit 138 that updates the transfer source address register value according to the data transfer amount, and the transfer destination address calculation circuit 134 transfers the transfer destination according to the data transfer amount. It is configured to update the address register value and update the transfer destination address register value by adding an offset address in units of blocks, and transfer the data by outputting the values of the transfer source address register and transfer destination address register to the address bus You may comprise so that control may be performed.

  FIG. 2 is a diagram showing an example of the configuration of the DMA controller.

  The transfer source address register (SAR) 112 is connected to the control bus 170 and the output of the adder / subtractor 152 of the transfer source address arithmetic circuit 138 through the selector 140. A transfer source address is set via the control bus 170, and a transfer source address updated with data transfer is set by the output of the adder / subtractor 152.

  The transfer destination address register (DAR) 114 is connected to the control bus 170 and the output of the adder / subtractor 152 of the transfer destination address calculation circuit 134 via the selector 142. A transfer destination address is set via the control bus 170, and a transfer destination address updated with data transfer is set by the output of the adder / subtractor 152.

  The transfer destination address calculation circuit 134 includes an adder / subtractor 152 and selectors 144 and 146 that select an input to the adder / subtractor 152.

  The adder / subtractor 152 inputs the transfer destination address set in the transfer destination address register (DAR) 114 and a predetermined constant (for example, the number of bytes of the transfer size) 182, and a predetermined constant ( For example, the number of transfer size bytes) 182 is added or subtracted, and the updated transfer destination address is output.

  Further, the adder / subtractor 152 is connected to the address offset register (DAO) 122, and when the end of data transfer for one block is detected, the address offset stored in the address offset register (DAO) 122 and the transfer destination address are added to the offset. Outputs the transfer destination address of the next block with the address added.

  The address offset register (DAO) 122 is connected to the control bus 170, and an offset value at the end of block transfer is set.

  The transfer source address calculation circuit 138 includes an adder / subtracter 152 and selectors 144 and 146 that select an input to the adder / subtractor 152.

  The adder / subtractor 152 inputs the transfer source address set in the transfer source address register (SAR) 112 and a predetermined constant (for example, the number of bytes of transfer size) 182, and a predetermined constant ( For example, the number of transfer size bytes) 182 is added or subtracted, and the updated transfer source address is output.

  The data size register (TCR) 118 is connected to the control bus 170 and the output of the subtracter 154 of the data transfer end detection 136 via the selector 148. The data size of the transfer target data is set via the control bus 170, and the remaining data size updated with the data transfer by the output of the subtracter 154 (the data size of the transfer target data that has not been transferred) ) Is set.

  The data transfer end detection circuit 136 includes a subtracter 154.

  The subtracter 154 inputs the data size set in the data size register (TCR) 118 and a predetermined constant (for example, the number of bytes of the transfer size) 182, and a predetermined constant (for example, the number of bytes of the transfer size) accompanying the transfer. Subtract 182 and output the updated remaining data size.

  When the output remaining data size becomes 0, the end of data transfer is detected.

  The block data size storage register (BTC) 120 is connected to the control bus 170 and its output is connected to the block data size counter (cBTC) 124. The block data size storage register (BTC) 120 is set with the block data size via the control bus 170.

  The block data size counter (cBTC) 124 is connected to the output of the block data size storage register (BTC) 120 and the subtracter 156 of the block data transfer end detection 132 via the selector 150. At the start of the transfer of each block, the value of the block data size storage register (BTC) 120 is set, and the remaining block data size updated with the data transfer by the output of the subtracter 156 (transfer of the block data has been completed) The data size of the part that is not) is set.

  The block data transfer end detection circuit 132 includes a subtracter 156.

  The subtractor 156 inputs the data size set in the block data size counter (cBTC) 124 and a predetermined constant (for example, the number of bytes of the transfer size) 182, and a predetermined constant (for example, the number of bytes of the transfer size) accompanying the transfer. ) Subtract 182 to output the updated remaining block data size.

  When the output remaining block data size becomes 0, the end of block data transfer is detected.

  As described above, in this embodiment, a DMA channel to be divided and transferred is prepared, and the block size when the block is divided into the block data size storage register (BTC) 120 is set for the channel, and the address offset register (DAO) is set. ) 122, an offset to be added to the destination address when shifting to the next block transfer when one block transfer is completed is set.

  When BTC becomes “0”, the transfer of one block is finished, the ownership of the internal bus is released, and the block transfer is started again after the internal bus becomes usable.

  At this time, when DAO is set in the next block transfer, the destination address can be changed by adding DAO to DAR and performing transfer. The block transfer ends when the BTC becomes “0”, but the all-rest transfer ends when the TCR becomes “0”. Therefore, in the last block transfer, even if the BTC does not become “0”, the data transfer can be completed when the TCR becomes “0”.

  3A and 3B are diagrams for explaining the division transfer according to the present embodiment.

  For example, as shown in FIG. 3A, the transfer target data 200 having the data size 1 stored in the address a1 is divided into six blocks B0 to B5 having a block size of Bl, and the address b1 is set to 280. As shown in the drawing, an example will be described in which data is transferred so that offset areas (spaces) of SP1 to SP5 having a size Ol are provided between blocks of the transferred data.

  FIG. 3B shows a setting example of the DMA transfer control register of the channel (for example, channel 1) when the divided transfer as shown in FIG. 3A is performed. "A1" in the transfer source address setting register (SAR) 261, "b1" in the transfer destination address setting register (DAR) 262, "l" in the data size register (TCR) 263, block data size storage register (BTC) “Bl” is set in H.265, and “O1” is set in the address offset register (DAO) 266.

  When the bus occupation is reviewed in units of blocks, a value indicating that is set in the block management information of the control register (CTL) 264.

  When the channel 1 is set in this way, for example, the next transfer destination can be changed to the destination B2 obtained by adding the offset Ol to the trace where the block 0 is transferred. Therefore, the offset region SP1 can be provided between the blocks B0 and B1.

  When channel 1 is set in this way and channel 1 is used to perform DMA data transfer, division transfer can be performed with one channel. As shown by 280, offset areas SP1 to SP5 are provided between blocks. DMA data transfer can be performed.

  Moreover, the offset areas SP1 to SP5, which are the header areas, can be automatically secured simply by setting the header size to DAO 226, which is convenient when adding a header in units of blocks.

  In addition, by setting a value instructing to review the bus occupation in block units in the block management information of the control register (CTL) 264, the internal bus can be released between block transfers, so that the internal bus Effective utilization can be achieved.

  FIG. 4 is a flowchart for explaining an operation example of the present embodiment.

  First, before starting DMA transfer of data to be transferred, necessary DMA transfer control registers (SAR, DAR, CTL, TCR, BTC, DAO) are initialized (step S10).

  Thereafter, a DMA data transfer request is received from the CPU, and DMA data transfer is started with the contents set in the CTL (step S20).

  When DMA transfer is performed, SAR and DAR are updated with the contents set in CTL, and TCR and cBTC are performed as TCR-1 and cBTC-1, respectively (step S30).

  Thereafter, the TCR value is confirmed. If TCR = 0, the transfer is terminated (step S40).

  If TCR = 0, the cBTC value is confirmed. If cBTC = 0, the process returns to step S30. If cBTC = 0, the ownership of the internal bus is released, and data transfer is performed until the internal bus becomes usable. Matsu (step 60, S70).

  When the internal bus becomes usable, the BTC value is set in the cBTC, and the offset address DAO is added to the DAR value to update it, thereby acquiring the right to use the bus (step S80).

2. Microcomputer FIG. 5 is an example of a hardware block diagram of the microcomputer of this embodiment.

  The microcomputer 700 includes a CPU 510, a cache memory 520, a RAM 710, a ROM 720, an MMU 730, an LCD controller 530, a reset circuit 540, a programmable timer 550, a real time clock (RTC) 560, a DRAM controller 570, an interrupt controller 580, a communication control device 590, Bus controller 600, A / D converter 610, D / A converter 620, input port 630, output port 640, I / O port 650, clock generator 660, prescaler 670, transfer processing module 740 and general-purpose connecting them A bus 680, a dedicated bus 750, etc., various pins 690, etc. are included.

  The DMA controller 570 has the configuration described with reference to FIG. 2, for example, and realizes divided data transfer without causing an increase in circuit scale or occupation of a plurality of channels.

3. Electronic Device FIG. 6 shows an example of a block diagram of the electronic device of this embodiment. The electronic apparatus 800 includes a microcomputer (or ASIC) 810, an input unit 820, a memory 830, a power generation unit 840, an LCD 850, and a sound output unit 860.

  Here, the input unit 820 is for inputting various data. The microcomputer 810 performs various processes based on the data input by the input unit 820. The memory 830 serves as a work area for the microcomputer 810 and the like. The power generation unit 840 is for generating various power sources used in the electronic device 800. The LCD 850 is for outputting various images (characters, icons, graphics, etc.) displayed by the electronic device. The sound output unit 860 is for outputting various sounds (sound, game sound, etc.) output from the electronic device 800, and the function can be realized by hardware such as a speaker.

  FIG. 7A illustrates an example of an external view of a mobile phone 950 which is one of electronic devices. The cellular phone 950 includes a dial button 952 that functions as an input unit, an LCD 954 that displays a telephone number, a name, an icon, and the like, and a speaker 956 that functions as a sound output unit and outputs sound.

  FIG. 7B illustrates an example of an external view of a portable game device 960 that is one of electronic devices. The portable game device 960 includes an operation button 962 that functions as an input unit, a cross key 964, an LCD 966 that displays a game image, and a speaker 968 that functions as a sound output unit and outputs game sound.

  FIG. 7C illustrates an example of an external view of a personal computer 970 that is one of electronic devices. The personal computer 970 includes a keyboard 972 that functions as an input unit, an LCD 974 that displays characters, numbers, graphics, and the like, and a sound output unit 976.

  By incorporating the microcomputer of this embodiment into the electronic devices in FIGS. 5A to 5C, an electronic device with low cost and high image processing speed can be provided.

  In addition to the devices shown in FIGS. 5A, 5 </ b> B, and 5 </ b> C, electronic devices that can use this embodiment include portable information terminals, pagers, electronic desk calculators, devices equipped with touch panels, Various electronic devices using an LCD such as a projector, a word processor, a viewfinder type or a monitor direct view type video tape recorder, and a car navigation device can be considered.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  For example, in the present embodiment, the configuration in the case of performing DMA transfer of divided data by adding an offset address in block units has been described as an example, but the present invention is not limited to this. For example, DMA transfer of divided data may be performed by reviewing bus occupation in units of blocks without adding an offset address.

  Further, it may be possible to perform DMA transfer of divided data by adding an offset address by division in units of blocks without reexamining the bus occupation in units of blocks.

It is a figure for demonstrating the integrated circuit device of this Embodiment. It is the figure which showed an example of the structure of a DMA controller. 3A and 3B are diagrams for explaining the division transfer according to the present embodiment. It is a flowchart for demonstrating the operation example of this Embodiment. It is an example of the hardware block diagram of the microcomputer of this Embodiment. An example of a block diagram of an electronic device including a microcomputer is shown. 7A, 7B, and 7C are examples of external views of various electronic devices.

Explanation of symbols

10 IC (integrated circuit device), 20 CPU, 30 built-in memory, 40 external memory controller, 50 internal bus, 60 arbiter, 70 external memory, 100 DMA controller, 110 DMA transfer control circuit, 112 SAR, 114 DAR, 116 CTL, 118 TCR, 120 BTC, 122 DAO, 510 CPU, 520 Cache memory 530 LCD controller, 540 Reset circuit, 550 Programmable timer, 560 Real time clock (RTC), 570 DMA controller / bus I / F, 580 Interrupt controller, 590 Communication control Circuit (serial interface), 600 bus controller, 610 A / D converter, 620 D / A converter, 630 input port, 640 output port, 650 I / O port, 66 Clock generator (PLL), 670 prescaler, 680 general purpose bus, 690 various pins, 700 microcomputer, 710 ROM, 720 RAM, 730 MMU, 750 dedicated bus, 800 electronic device, 810 microcomputer (ASIC), 820 input unit, 830 memory, 840 power generation unit 850 LCD, 860 sound output unit, 950 mobile phone, 952 dial button, 954 LCD, 956 speaker, 960 portable game device, 962 operation button, 964 cross key, 966 LCD, 968 speaker, 970 Personal computer, 972 keyboard, 974 LCD, 976 sound output unit

Claims (7)

An integrated circuit device including a DMA transfer control register and a DMA transfer control circuit that controls transfer of data to be divided into a plurality of blocks based on the value of the DMA transfer control register to perform DMA transfer in units of blocks,
The DMA transfer control register is
A block data size storage register in which the data size of each divided block is stored;
An address offset register in which offset addresses to be added in block units are stored,
The DMA transfer control circuit includes:
A block data transfer end detection circuit that counts the data transfer amount and determines the end of data transfer for one block when the data transfer amount reaches the block data size value stored in the block data size storage register;
A transfer destination address calculation circuit for adding an offset address based on the address offset value stored in the address offset register when calculating the end of data transfer for one block and calculating the address of the transfer destination of the next block An integrated circuit device. In claim 1,
The transfer control register is
It further includes a control register storing block management information for managing whether or not the bus is reoccupied in blocks.
The DMA transfer control circuit includes:
An integrated circuit device comprising: a circuit that controls whether or not the bus is reoccupied in units of blocks based on block management information stored in a control register. An integrated circuit device including a DMA transfer control register and a DMA transfer control circuit that controls transfer of data to be divided into a plurality of blocks based on the value of the DMA transfer control register to perform DMA transfer in units of blocks,
The DMA transfer control register is
A block data size storage register in which the data size of each divided block is stored;
It further includes a control register storing block management information for managing whether or not the bus is reoccupied in blocks.
The DMA transfer control circuit includes:
A block data transfer end detection circuit that counts the data transfer amount and determines the end of data transfer for one block when the data transfer amount reaches the block data size value stored in the block data size storage register;
An integrated circuit device comprising: a circuit that controls whether or not the bus is reoccupied in units of blocks based on block management information stored in a control register when the end of data transfer for one block is detected. In any one of Claims 1 thru | or 3,
The transfer control register is
It further includes a data size register in which the transfer target data size is stored,
The DMA transfer circuit includes:
A data transfer end detection circuit for counting the data transfer amount and detecting the transfer end of the transfer target data when the data transfer amount reaches the data size value stored in the data size register;
The transfer destination address calculation circuit includes:
An integrated circuit device characterized by determining that there is a next block and calculating a transfer destination address of the next block until the end of transfer of data to be transferred is detected. In any one of Claims 1 thru | or 4,
The transfer control register is
A transfer source address register storing a transfer source address of data; and
A transfer destination address register storing a transfer destination address of the data,
The DMA transfer control circuit includes:
A transfer source address update circuit for updating the transfer source address register value according to the data transfer amount,
The transfer destination address calculation circuit includes:
The transfer destination address register value is updated according to the data transfer amount, and the transfer destination address register value is updated by adding an offset address in units of blocks.
An integrated circuit device that performs data transfer control by outputting values of a transfer source address register and a transfer destination address register to an address bus.   A microcomputer comprising the integrated circuit device according to claim 1. A microcomputer according to claim 6;
Means for inputting data to be processed by the microcomputer;
An electronic device comprising: output means for outputting data processed by the microcomputer.

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