JP2007311882A - Signal analyzer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal analyzer for applying analysis processing to a high speed and narrow band signal with low speed internal processing. <P>SOLUTION: In the signal analyzer wherein sampling clocks shifted by a Ts/N each for a prescribed period Ts are given to a plural number N of A/D converters 22 for receiving input signals in common, a data selection unit 23 is controlled to output data obtained by the sampling in time series, a signal extract section 25 receives the output data, extracts a signal component of a desired frequency band, and converts the component into a baseband signal for the analysis processing, N sets of the A/D converters 22 are classified into P sets, wherein one set is M sets of the A/D converters whose sampling sequence is consecutive, and the data selection unit 23 selects output values of N sets of the A/D converters 22 in the unit of the set for a period Ts/P and provides parallel outputs in the M sequence. The signal extract section 25 converts the signals outputted in the M sequence into baseband signals respectively, and obtains a total sum I of in-phase components and a total sum Q of quadrature components respectively for the period Ts/P and outputs the total sums I, Q to an analysis section 38. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention provides a signal analysis apparatus that performs predetermined analysis processing after converting an analog signal into a digital data signal by A / D conversion processing, so that high-speed signal analysis processing can be performed by low-speed internal processing. Regarding technology.

  Currently, a method of performing analysis processing for an analog signal after converting the analog signal into a digital data string by A / D conversion processing is generally employed.

  Here, the upper limit of the frequency of the signal that can be analyzed is determined by the upper limit of the operation speed of the A / D conversion process, but interleaving that slightly shifts the sampling timing of a plurality of A / D converters that commonly receive the input signal. By adopting this method, the upper limit of the frequency can be expanded by the number of A / D converters, and now it is possible to sample signals from DC to GHz band.

  The interleaved A / D converter is disclosed in, for example, the following Patent Document 1.

JP 2000-295105 A

  On the other hand, signal analysis includes, for example, not only wideband spectrum analysis spanning from DC to GHz band, but also narrowband frequency analysis and modulation analysis for any channel of terrestrial digital broadcast waves, for example, In order to perform these narrow-band analyzes, it is necessary to extract a signal component to be analyzed.

  FIG. 8 shows a configuration example of the signal analyzing apparatus 1 that performs narrowband signal extraction using interleaved A / D conversion processing.

  In this signal analyzing apparatus 1, for example, an analog input signal s (t) shown in FIG. 9A is input to the input terminal 1a and branched into a plurality of N (in this example, N = 4) by the branching means 2. And input to the N A / D converters 3 (1) to 3 (4) in phase.

  Each of the A / D converters 3 (1) to 3 (4) is Ts / N at a predetermined cycle Ts (frequency fs) as shown in (b1) to (b4) of FIG. Each of the sampling clocks Cs1 to Cs4 output with a delay is received, the input signal s (t) is sampled at a timing shifted by Ts / N, and the sampling values are as shown in (c1) to (c4) of FIG. Are converted into digital data values S (1), S (2),..., And output to the data selector 4.

  The data selector 4 controls the data values S (1), S (2),... Output from the A / D converters 3 (1) to 3 (4) as shown in FIG. As shown in (d), the output is switched every Ts / N time and output in the order of sampling.

  The data value output from the data selector 4 is equivalent to the input signal s (t) sampled at a cycle of Ts / N. As shown in FIG. -Sampling of signal components up to fs / 2 is possible. For example, if N = 8 and fs = 200 MHz, it is possible to sample signals from DC to 800 MHz.

  The data string obtained in this way is input to the signal extraction unit 6. The signal extraction unit 6 extracts a signal in a frequency band having a predetermined width ± fw centering on the desired frequency fc within the frequency range from the direct current to the frequency N · fs / 2 shown in FIG. As shown in FIG. 10B, the baseband is converted.

  For this signal extraction process, as shown in FIG. 8, a local signal generator 7 and a quadrature demodulator 8 including two mixers (multipliers) 8a and 8b, LPFs 8c and 8d are used.

  The local signal generator 7 generates two-phase local signals Ci and Cq whose phases are 90 ° different from each other at the desired frequency fc, and inputs them to the two mixers 8a and 8b of the quadrature demodulator 8 that commonly receives the data string. The outputs of the mixers 8a and 8b are band-limited by the LPFs 8c and 8d to become baseband signals I and Q having a frequency of fw or less, and are sequentially output as shown in (e) and (f) of FIG.

  Here, as described above, the signal to be analyzed is a narrow band (for example, several MHz in the case of a signal of an arbitrary channel of a terrestrial digital broadcast wave), and the upper limit frequency fw when this is converted to baseband is very high. Low.

  The sampling rate necessary and sufficient for the arithmetic processing for analyzing the baseband signal is twice as high as fw. However, the sampling rate of the baseband signals I and Q output from the quadrature demodulator 8 is increased in the interleaving method. Since the rate is N · fs, the amount of data necessary for the calculation processing for analysis is greatly exceeded, and a lot of excess data is included.

  Therefore, in order not to perform the calculation process for the extra data, the thinning means 9 and 10 use the thinning means 9 and 10, for example, 1 / M (M = 2 in the figure and every other one in FIG. 9). Decimation processing (decimation) is performed, and the baseband signals I ′ and Q ′ subjected to the decimation processing are input to the analysis unit 11 to perform arithmetic processing for frequency analysis and modulation analysis.

  However, in the signal analyzing apparatus 1 having the above-described configuration, it is necessary to perform the output value selection processing and the signal extraction processing of the plurality of N A / D converters 3 at a speed of N · fs. Even if the sampling is performed, the processing speed of the entire apparatus is greatly limited by the speed of the subsequent circuit.

  An object of the present invention is to solve this problem and to provide a signal analysis apparatus capable of performing analysis processing on a high-speed and narrow-band signal by low-speed internal processing.

In order to achieve the above object, a signal analysis apparatus according to claim 1 of the present invention is provided.
A plurality of N A / D converters (22) for commonly receiving an input signal;
A data selector (23) for selectively outputting output values of the plurality of N A / D converters;
A sampling clock shifted by Ts / N at a predetermined period Ts is given to the plurality of N A / D converters, and the data selector is controlled so that data obtained by the sampling is output in time series. A control unit (24) to perform,
A signal extraction unit (25) that receives data output from the data selector, extracts a signal component of a desired frequency band from an input signal, and converts the signal component into a baseband signal;
In the signal analysis device having an analysis unit (38) for performing analysis processing on the baseband signal output from the signal extraction unit,
The plurality of N A / D converters are divided into P sets with a plurality of M pieces in which the sampling order is continuous as one set,
The data selector is composed of N to M switches, and is controlled to select the output values of the plurality of N A / D converters in units of groups at a period Ts / P and to output them in parallel in M series,
Furthermore, the signal extraction unit
A local signal generator (26) for generating two-phase local signals that are 90 ° out of phase with each other at a desired frequency;
Filters (30, 31) subjected to polyphase decomposition corresponding to the thinning-out processing of the number M, each receiving signals output in M series from the data selector, and baseband using the two-phase local signals A plurality of M quadrature demodulators (27) for converting into signals and outputting;
A first accumulator (35) for obtaining and outputting a sum of in-phase components of outputs of the plurality of M quadrature demodulators at a period Ts / P;
It is characterized by comprising a second accumulator (36) for obtaining and outputting the sum of the orthogonal components of the outputs of the plurality of M orthogonal demodulators with a period Ts / P.

The signal analysis device according to claim 2 of the present invention is:
A plurality of N A / D converters (22) for commonly receiving an input signal;
A control unit (24) for providing a sampling clock shifted by Ts / N at a predetermined cycle Ts to the plurality of N A / D converters;
A signal extraction unit (25) that receives data output from the plurality of N A / D converters, extracts a signal component of a desired frequency band from an input signal, and converts the signal component into a baseband signal;
In the signal analysis device having an analysis unit (38) for performing analysis processing on the baseband signal output from the signal extraction unit,
The signal extraction unit is
A local signal generator (26) for generating two-phase local signals that are 90 ° out of phase with each other at a desired frequency;
A filter (30, 31) subjected to polyphase decomposition corresponding to the number N thinning-out processing is received, and the signals output in N series from the A / D converter are respectively received by the local signals of the two phases. A plurality of N quadrature demodulators (27) which respectively convert and output baseband signals;
A first accumulator (35) for obtaining and outputting a sum of in-phase components of the outputs of the plurality of N quadrature demodulators at a period Ts;
It is characterized by comprising a second accumulator (36) for obtaining and outputting the sum of the orthogonal components of the outputs of the plurality of N orthogonal demodulators with a period Ts.

  With this configuration, in the signal analysis apparatus according to the first aspect of the present invention, the selection process, the signal extraction process, and the thinning process for the data values output from the plurality of A / D converters are performed at the rate of P / Ts. In other words, by reducing the ratio P (= N / M) of N and M, signal analysis processing can be performed at higher speed with low-speed internal processing.

  In the signal analysis apparatus according to claim 2 of the present invention, N and M in claim 1 are equal (P = 1), and data selection processing is not required, and the fastest analysis processing is possible.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows the configuration of a signal analysis device 20 to which the present invention is applied.

  This signal analyzing apparatus 20 performs N branching on an analog input signal s (t) input to an input terminal 20a by a branching unit 21, and a plurality of N (here, N = 8 examples) A / D converters. Input in-phase to 22 (1) to 22 (8).

  Each of the A / D converters 22 (1) to 22 (8) receives sampling clocks Cs1 to Cs8 shifted by Ts / 8 hours (phase angle 2π / 8) by a predetermined period Ts from the control unit 24, respectively. The input signal s (t) is sampled at different timings by Ts / 8, and the sampled values are converted into digital data values S (1), S (2),... And output to the data selector 23.

  In this case, the plurality of N A / D converters 22 (1) to 22 (8) include a plurality of M sets (M = 4 in this example) in which the sampling order is continuous, In the example, P = 2). That is, the A / D converters 22 (1) to 22 (4) are the first set, and the A / D converters 22 (5) to 22 (8) are the second set.

  The data selector 23 is for selectively outputting the output values of a plurality of N A / D converters 22 (1) to 22 (8), and N: M (8: 4 in this example). The control unit 24 is configured by a switch so that the output values of the eight A / D converters 22 (1) to (8) are selected in units of the group at a cycle of Ts / P and are output in parallel in M series. Is controlled by a switching signal Ca output at a cycle Ts / P. The data selector 23 has a data latch function, and latches and outputs the input data when receiving the switching signal Ca.

  The control unit 24 generates and outputs sampling clocks Cs1 to Cs8, a switching signal Ca to the data selector 23, and an integration instruction signal Cb for a first integrator 35 and a second integrator 36 described later.

  The M-sequence data selected by the data selector 23 is input to the signal extraction unit 25. The signal extraction unit 25 receives the M-sequence data output from the data selector 23, extracts a signal component of a desired frequency band to be analyzed from the input signal, and converts it into a baseband signal.

  Here, the signal extraction unit 25 includes local signal generators 26, 4 (= M) orthogonal demodulators 27 (1) to 27 (4), a first integrator 35, and a second integrator 36. It is comprised by.

  The local signal generator 26 generates two-phase local signals Ci and Cq (discrete signals by numerical values) at a center frequency (local frequency) fc in a desired frequency band to be analyzed and having a phase difference of 90 ° from each other. Each quadrature demodulator 27 (1) to 27 (4) is provided.

  Quadrature demodulators 27 (1) to 27 (4) receive input signals in common and receive mixers (multipliers) 28 and 29 that receive local signals Ci and Cq, respectively, and filtering processing on the outputs of the mixers 28 and 29. Filters 30 and 31 that respectively perform conversion of signals in desired frequency bands to baseband signals i and q, respectively, and output the converted signals.

  The first integrator 35 receives the integration instruction signal Cb output at the cycle Ts / N from the control unit 24, and outputs the in-phase component output from the M orthogonal demodulators 27 (1) to 27 (4). The sum I of the signals i (1) to i (4) is obtained and output.

  Further, every time the second integrator 36 receives the integration instruction signal Cb output at the cycle Ts / N from the control unit 24, the second integrator 36 outputs the second integrator 36 from the M orthogonal demodulators 27 (1) to 27 (4). The sum Q of the quadrature component signals q (1) to q (4) is obtained and output.

  Note that the filters 30 and 31 of each of the quadrature demodulators 27 (1) to 27 (4) are set to characteristics obtained by polyphase decomposition corresponding to the 1 / M decimation process, and the first integration is performed. Together with the integration process of the calculator 35 and the second integrator 36, an operation equivalent to the 1 / M thinning process is shown.

Hereinafter, this point will be described.
First, as a premise technique of the present invention, a case is considered in which arithmetic processing and thinning processing are performed on a mixer output signal of the quadrature demodulator 27 using a 4-tap digital filter expressed by the following equations (1a) to (1c). .

H (z) = h (0) + h (1) z ⁻¹ + h (2) z ⁻² + h (3) z ⁻³
(1a)
= H (0) + h (2) z ⁻² + z ⁻¹ [h (1) + h (3) z ⁻² ]
(1b)
= E ₀ (z ² ) + z ⁻¹ E ₁ (z ² )
(1c)
However, E ₀ (z) = h (0) + h (2) z ⁻¹
E ₁ (z) = h (1) + h (3) z ⁻¹

  As shown in FIG. 2A, a data string x (i) is input to the filter 100 of the transfer equation H (z), and the output y (j) is halved by the thinning means 101. Consider performing decimation processing. The output y (j) of the filter with respect to the input data x (i) is as follows.

y (0) = h (0) x (0) + h (1) x (−1)
+ H (2) x (-2) + h (3) x (-3)
y (1) = h (0) x (1) + h (1) x (0)
+ H (2) x (-1) + h (3) x (-2)
y (2) = h (0) x (2) + h (1) x (1)
+ H (2) x (0) + h (3) x (-1)
y (3) = h (0) x (3) + h (1) x (2)
+ H (2) x (1) + h (3) x (0)
…………

  Of the output y (j), ½ decimation processing is performed with y (0), y (2),... As valid data and y (1), y (3),. As a result, the final output Y is an even-numbered output y (2k).

Here, in correspondence with the above equation (1b), the filter 100 includes a delay unit 100a, an arithmetic unit 100b represented by the equation of h (0) + h (2) z− ² , as shown in FIG. , H (1) + h (3) z ⁻² , and an adder 100d.

And although not described in detail, when performing filtering and thinning processing on a data string in cascade, a technique of Noble identity conversion indicating that the order of filtering and thinning processing can be changed by changing the number of filter taps. When used, the circuit shown in FIG. 2B is transformed by using a circuit that calculates E ₀ (z) and E ₁ (z) in the above equation (1c) as shown in FIG. 2C. be able to.

In the circuit of FIG. 2C, the thinning means 101a and 101b perform a half thinning process. The calculation unit 100e calculates h (0) + h (2) z− ¹ , and the calculation unit 100f calculates h (1) + h (3) z− ¹ .

  Here, among the input data x (i), the even-numbered data x (2k) is input to the calculation unit 100e, and the odd-numbered data x (2k + 1) is input to the calculation unit 100f.

  Therefore, the circuit shown in FIG. 2C is equivalent to a circuit in which input data is alternately distributed to the arithmetic unit 100e and the arithmetic unit 100f by the switch 100g as shown in FIG. The filter of the form (d) in FIG. 2 is called a polyphase configuration.

  By connecting this polyphase configuration to the mixer output of each quadrature demodulator, processing equivalent to 1/2 decimation processing can be performed.

The description of FIG. 2 assumes that M = 2, but when M = 4, the number of switching of the switch 100g is 4, as shown in FIG. 3, and E _{0 to} E ₃ for every fourth data. Four arithmetic units 100e to 100h that perform arithmetic operations are provided, and the sum of the outputs is obtained by an adder 100d.

  However, as the data distribution speed by the switch 100g, the sampling speed N · fs in the interleave method is required regardless of the thinning-out number M.

  Therefore, in the present invention, the selection processing of the output data of the plurality of A / D converters and the data switching processing necessary for the filter processing of the polyphase configuration are integrated to reduce the speed of the data selection processing and the signal extraction processing. It is possible.

  That is, in this embodiment, the A / D converters 22 (1) to 22 (N) are divided into P groups (P is 2 or more) by taking a plurality of M pieces in which the sampling order is continuous as one set, and data selection is performed. The M 23 is configured as an N-to-M switch, and the selected M-sequence data is input to M sets of quadrature demodulators 27 (1) to 27 (N) constituting the signal extraction unit 25, and the mixer output is input to the poly A band limiting process is performed by the phase-decomposed filters 30 and 31, the in-phase components of the outputs are added by the first integrator 35, and the quadrature components are added by the second integrator 36, and the baseband signal I Q. Each time the first integrator 35 and the second integrator 36 receive the integration instruction signal Cb output from the control unit 24 at the cycle Ts / P, the integration is performed.

Next, an operation example of the above embodiment will be described.
Sampling clocks Cs1 to Cs8 shifted by Ts / 8 time as shown in (b1) to (b8) of the input signal s (t) in FIG. 4 (a) are A / D converters 22 (1 ) To 22 (8), respectively, and the data S (1) to S (8) from the A / D converters 22 (1) to 22 (8) as shown in (c1) to (c8) of FIG. Are sequentially output and input to the data selector 23.

  As shown in FIG. 4 (d), the data selector 23 is supplied with a switching signal Ca having a period Ts / 2, and the rising timing thereof (in this case, synchronized with the sampling clocks Cs1 and Cs5). The data is latched and the switching operation is performed.

  Therefore, as shown in (a1) to (a4) of FIG. 5, the data selector 23 sequentially outputs data S (i, j) in four series with a cycle Ts / 2. The data is subjected to frequency conversion, component separation processing and filter processing by each of the quadrature demodulators 27 (1) to 27 (4), and the in-phase components of the outputs are integrated by the first integrator 35, The quadrature components are integrated by the second integrator 36, and the respective integration results are sequentially output as the baseband signals I and Q at the cycle Ts / 2 as shown in (b) and (c) of FIG.

Here, when representing the output when the data C · S (i-j) is input to the filter of the transfer equation _{E U} and _{C · E U (i-j} ), the baseband signals I, Q are the following It becomes like this.

I (1) = Ci (1) [E ₀ (1-1) + E ₁ (2-1) + E ₂ (3-1) + E ₃ (4-1)]
Q (1) = Cq (1) [E ₀ (1-1) + E ₁ (2-1) + E ₂ (3-1) + E ₃ (4-1)]

I (2) = Ci (1) [E ₀ (5-1) + E ₁ (6-1) + E ₂ (7-1) + E ₃ (8-1)]
Q (2) = Cq (1) [E ₀ (5-1) + E ₁ (6-1) + E ₂ (7-1) + E ₃ (8-1)]

I (3) = Ci (2) [E ₀ (1-2) + E ₁ (2-2) + E ₂ (3-2) + E ₃ (4-2)]
Q (3) = Cq (2) [E ₀ (1-2) + E ₁ (2-2) + E ₂ (3-2) + E ₃ (4-2)]

I (4) = Ci (2) [E ₀ (5-2) + E ₁ (6-2) + E ₂ (7-2) + E ₃ (8-2)]
Q (4) = Cq (2) [E ₀ (5-2) + E ₁ (6-2) + E ₂ (7-2) + E ₃ (8-2)]
…………

  The baseband signals I and Q are equal to the result of performing the band limiting process by the filter 100 and the ¼ decimation process by the decimation unit 101 based on the principle of the Noble identity conversion.

  In addition, the operation from the data selector 23 to the integrators 35 and 36 can be performed at a relatively low speed that is twice (P times) the sampling frequency fs of each A / D converter 22, which is a low-speed internal process. Baseband signals I and Q necessary for high-speed narrowband signal analysis can be obtained.

  The analysis unit 38 performs processing equivalent to the thinning-out processing as described above, receives baseband signals I and Q input at a relatively slow rate of 2 fs, and performs frequency analysis (FFT) and modulation analysis (MER, BER). Etc.), and the analysis result is output to a display (not shown) or the like.

  In the above embodiment, an example in which N = 8 and M = 4 is shown, but other numerical examples can be realized as long as the relationship of N = M · P is satisfied. However, from the standpoint of ease of manufacturing the device, it is practically desirable to set the power of 2 as M = 64, 32, 16,..., P = 2, 4, 8,.

  Further, when the bandwidth of the signal to be analyzed is arbitrarily changed, the output sequence number M (that is, the thinning number) of the data selector 23 and each filter transfer equation E can be changed and set according to the band. Also good.

  A case where P = 1, that is, a case where N = M is also conceivable. In this case, unlike the N = 4 signal analysis apparatus 20 'shown in FIG. 6, a data selector is unnecessary, and the outputs of the A / D converters 22 (1) to 22 (4) are connected to the quadrature modulator 27 ( 1) to 27 (4) can be directly connected to each other. In this case, data is output from the quadrature modulators 27 (1) to 27 (4) as shown in (a1) to (a4) of FIG. 7, and the 1 / N decimation process is equivalently performed. The band signals I and Q are output at a rate of fs as shown in FIGS. 7B and 7C.

The figure which shows the structure of embodiment of this invention The figure for demonstrating the principle of operation of this invention The figure for demonstrating the principle of operation of this invention Timing chart for explaining the operation of the embodiment Timing chart for explaining the operation of the embodiment The figure which shows the structure of other embodiment of this invention. Timing chart for explaining the operation of the embodiment of FIG. The figure which shows the structural example of the signal analysis apparatus which performs the A / D conversion process of an interleave system, and the extraction process of a narrow band signal Timing diagram for explaining the operation of the apparatus of FIG. The figure which shows the frequency band of the A / D conversion processing of the interleaving system, and the band of the analysis object signal

Explanation of symbols

  20, 20 '... Signal analysis device, 21 ... Branch means, 22 (1) to 22 (8) ... A / D converter, 23 ... Data selector, 24 ... Control unit, 25 ... Signal Extraction unit 26... Local signal generator 27 (1) to 27 (4)... Quadrature demodulator 28, 29... Mixer (multiplier) 30, 31. Accumulator 36 ... Second integrator 38 ... Analysis unit

Claims (2)

A plurality of N A / D converters (22) for commonly receiving an input signal;
A data selector (23) for selectively outputting output values of the plurality of N A / D converters;
A sampling clock shifted by Ts / N at a predetermined period Ts is given to the plurality of N A / D converters, and the data selector is controlled so that data obtained by the sampling is output in time series. A control unit (24) to perform,
A signal extraction unit (25) that receives data output from the data selector, extracts a signal component of a desired frequency band from an input signal, and converts the signal component into a baseband signal;
In the signal analysis device having an analysis unit (38) for performing analysis processing on the baseband signal output from the signal extraction unit,
The plurality of N A / D converters are divided into P sets with a plurality of M pieces in which the sampling order is continuous as one set,
The data selector is composed of N to M switches, and is controlled to select the output values of the plurality of N A / D converters in units of groups at a period Ts / P and to output them in parallel in M series,
Furthermore, the signal extraction unit
A local signal generator (26) for generating two-phase local signals that are 90 ° out of phase with each other at a desired frequency;
Filters (30, 31) subjected to polyphase decomposition corresponding to the thinning-out processing of the number M, each receiving signals output in M series from the data selector, and baseband using the two-phase local signals A plurality of M quadrature demodulators (27) for converting into signals and outputting;
A first accumulator (35) for obtaining and outputting a sum of in-phase components of outputs of the plurality of M quadrature demodulators at a period Ts / P;
A signal analyzer comprising: a second integrator (36) for obtaining and outputting a sum of orthogonal components of outputs of the plurality of M orthogonal demodulators at a period Ts / P. A plurality of N A / D converters (22) for commonly receiving an input signal;
A control unit (24) for providing a sampling clock shifted by Ts / N at a predetermined cycle Ts to the plurality of N A / D converters;
A signal extraction unit (25) that receives data output from the plurality of N A / D converters, extracts a signal component of a desired frequency band from an input signal, and converts the signal component into a baseband signal;
In the signal analysis device having an analysis unit (38) for performing analysis processing on the baseband signal output from the signal extraction unit,
The signal extraction unit is
A local signal generator (26) for generating two-phase local signals that are 90 ° out of phase with each other at a desired frequency;
A filter (30, 31) subjected to polyphase decomposition corresponding to the number N thinning-out processing is received, and the signals output in N series from the A / D converter are respectively received by the two-phase local signals. A plurality of N quadrature demodulators (27) which respectively convert and output baseband signals;
A first integrator (35) for obtaining and outputting a sum of in-phase components of the outputs of the plurality of N quadrature demodulators at a period Ts;
A signal analyzer comprising: a second accumulator (36) configured to obtain and output a sum of orthogonal components of outputs of the plurality of N orthogonal demodulators at a period Ts.

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