JP2007311678A - Mounting method and mounting structure of electronic component - Google Patents

Mounting method and mounting structure of electronic component Download PDF

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JP2007311678A
JP2007311678A JP2006141160A JP2006141160A JP2007311678A JP 2007311678 A JP2007311678 A JP 2007311678A JP 2006141160 A JP2006141160 A JP 2006141160A JP 2006141160 A JP2006141160 A JP 2006141160A JP 2007311678 A JP2007311678 A JP 2007311678A
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electronic component
substrate
solder
component
wall
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JP4736948B2 (en
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Takeshi Watanabe
健史 渡辺
Yuji Otani
祐司 大谷
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10135—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10145—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10165—Alignment aids
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81139—Guiding structures on the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the generation of a solder bridge due to scrubbing in a mounting structure constituted of soldering respective electrodes of an electronic component to respective electrodes of a substrate, by using solder die bonder technology for mounting the electronic component having a plurality of electrodes on the substrate without using flux. <P>SOLUTION: In a state that one surface 10a of the electronic component 10 is opposed to one surface 20a of the substrate 20, and solders 30 are applied between respective component electrodes 12 and substrate electrodes 21; a wall 13 for interrupting both solders 30 extruded from one surface 10a is formed on a portion existing between adjacent solders 30 out of the one surface 10a of the electronic component 10, and in the state, scrubbing is performed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、複数個の部品電極を有する電子部品を基板上に搭載し、電子部品におけるそれぞれの電極を基板の基板電極にはんだ付けしてなる電子部品の実装方法およびそのような電子部品の実装構造に関し、特に、フラックスを使用しないはんだダイボンダ技術に関する。   The present invention relates to a mounting method of an electronic component in which an electronic component having a plurality of component electrodes is mounted on a substrate, and each electrode in the electronic component is soldered to the substrate electrode of the substrate, and mounting of such an electronic component In particular, the present invention relates to solder die bonder technology that does not use flux.

この種の電子部品の実装構造は、一面側に複数個の部品電極が配置されているシリコン素子などの電子部品と、一面側に電子部品の部品電極に対応して複数個の基板電極が配置されているセラミック基板などの基板とを用意し、電子部品の一面と基板の一面とを対向させ、それぞれの部品電極と基板電極との間に、はんだを介在させ、両電極間をはんだによって接続してなる。   This type of electronic component mounting structure has an electronic component such as a silicon element in which a plurality of component electrodes are arranged on one side, and a plurality of substrate electrodes on the one side corresponding to the component electrodes of the electronic component. Prepare a substrate such as a ceramic substrate, one surface of the electronic component and one surface of the substrate are opposed, solder is interposed between each component electrode and the substrate electrode, and the two electrodes are connected by solder Do it.

ここで、一般には、はんだとしてはフラックスを使用したものを用い、窒素などの雰囲気において、はんだをリフローさせることにより、はんだ付けを行う（たとえば、特許文献１〜３参照）。しかし、この場合、はんだ接合後にフラックスを除去するための洗浄が必要である。   Here, in general, solder using a flux is used, and soldering is performed by reflowing the solder in an atmosphere such as nitrogen (see, for example, Patent Documents 1 to 3). However, in this case, cleaning is necessary to remove the flux after soldering.

近年の高密度化への要求のため、はんだの配置密度が増す傾向にあるが、このような場合、はんだ付け後のはんだ間の隙間が狭くなり、洗浄液がはんだの間に入りにくくなるため、電子部品と基板との間に付着したフラックスを除去することが難しくなる。また、フラックスを使用することで、はんだ飛散や、はんだ中のボイドの発生等の不具合も発生しやすくなる。   Due to the demand for higher density in recent years, the solder placement density tends to increase, but in such a case, the gap between the solder after soldering becomes narrower, and the cleaning liquid becomes difficult to enter between the solder. It becomes difficult to remove the flux adhered between the electronic component and the substrate. Moreover, by using the flux, problems such as solder scattering and the generation of voids in the solder are likely to occur.

フラックスを使用しない技術として、はんだダイボンダがある。このはんだダイボンダでは、還元雰囲気にて、電子部品の一面と基板の一面とを対向させるとともに、それぞれの部品電極と基板電極との間に、はんだを介在させた状態で、スクラブを行う。   As a technique that does not use flux, there is a solder die bonder. In this solder die bonder, scrubbing is performed in a reducing atmosphere such that one surface of an electronic component and one surface of a substrate are opposed to each other and solder is interposed between each component electrode and the substrate electrode.

具体的に、はんだダイボンダでは、雰囲気に水素などを含んでいるため、還元作用が働き、接合材の表面酸化物を除去することができ、フラックスが不要である。そして、基板下からの加熱と電子部品を保持するコレットによるスクラブにより、部品電極と基板電極とをはんだ付けする。   Specifically, since the solder die bonder contains hydrogen or the like in the atmosphere, the reducing action works, the surface oxide of the bonding material can be removed, and no flux is required. Then, the component electrode and the substrate electrode are soldered by heating from below the substrate and scrubbing with a collet that holds the electronic component.

このように、はんだダイボンダ技術によれば、フラックスを使用していないため、上記したフラックス除去のための洗浄の必要はなく、また、はんだ飛散はなくなり、はんだ内のボイド率は減少する。
特開平２−２４６２３６号公報 特開平８−１８１１４２号公報 特開平１０−２０９６２３号公報 Thus, according to the solder die bonder technique, since no flux is used, there is no need for the above-mentioned cleaning for removing the flux, solder scattering is eliminated, and the void ratio in the solder is reduced.
JP-A-2-246236 JP-A-8-181142 JP-A-10-209623

しかしながら、このはんだダイボンダの場合、スクラブにより、はんだブリッジが発生しやすくなる。具体的には、ダイボンド中、加熱によりはんだが溶融するが、スクラブにより、この溶融したはんだが動くため、隣り合うはんだ同士において、はんだブリッジが発生しやすくなる。   However, in the case of this solder die bonder, a solder bridge is likely to occur due to scrubbing. Specifically, the solder is melted by heating during die bonding, but the melted solder moves by scrubbing, so that solder bridges are likely to occur between adjacent solders.

そのため、従来のはんだダイボンダは、ＣＳＰやフリップチップのはんだ付けには使用されず、使用可能な範囲としては、はんだブリッジが発生しないシリコン素子の裏面電極の基板電極上へのはんだ付けに限られていた。   Therefore, the conventional solder die bonder is not used for CSP or flip chip soldering, and the usable range is limited to the soldering of the back electrode of the silicon element on which the solder bridge does not occur on the substrate electrode. It was.

本発明は、上記問題に鑑みてなされたものであり、複数個の電極を有する電子部品を基板上に搭載し、フラックスを使用しないはんだダイボンダ技術を用いて、電子部品におけるそれぞれの電極を基板の電極にはんだ付けしてなる実装構造において、スクラブによるはんだブリッジの発生を抑制することを目的とする。   The present invention has been made in view of the above problems, and an electronic component having a plurality of electrodes is mounted on a substrate, and each electrode in the electronic component is mounted on the substrate using a solder die bonder technique that does not use flux. An object of the present invention is to suppress the generation of solder bridges due to scrubbing in a mounting structure formed by soldering to electrodes.

上記目的を達成するため、本発明は、それぞれの部品電極（１２）と基板電極（２１）との間にはんだ（３０）を介在させた状態では、電子部品（１０）の一面（１０ａ）のうち隣り合うはんだ（３０）同士の間に位置する部位に、当該電子部品（１０）の一面（１０ａ）から突出し当該両はんだ（３０）同士を遮断する壁（１３）が設けられた状態とし、この状態でスクラブを行うことを、第１の特徴とする。   In order to achieve the above-described object, the present invention provides an electronic component (10) having one surface (10a) in a state where solder (30) is interposed between the component electrode (12) and the substrate electrode (21). Of these, a portion located between adjacent solders (30) is provided with a wall (13) that protrudes from one surface (10a) of the electronic component (10) and blocks the solders (30). The first feature is to perform scrub in this state.

それによれば、スクラブ時には、隣り合うはんだ（３０）同士の間が電子部品（１０）の一面（１０ａ）から突出する壁（１３）によって遮断された状態となることから、スクラブによって溶融した両はんだ（３０）同士が接触することが極力防止されるため、スクラブによるはんだブリッジの発生を抑制することができる。   According to this, during scrubbing, the adjacent solders (30) are blocked by the wall (13) protruding from one surface (10a) of the electronic component (10). (30) Since contact with each other is prevented as much as possible, generation of solder bridges due to scrub can be suppressed.

この場合、それぞれの部品電極（１２）と基板電極（２１）との間にはんだ（３０）を介在させた状態では、電子部品（１０）の一面（１０ａ）から突出する壁（１３）の先端部が基板（２０）の一面（２０ａ）に接触した状態となるようにすれば、この壁（１３）が、両部材（１０、２０）を支持する形となり、はんだ（３０）の高さを確保するためのスペーサとして機能する。   In this case, in the state where the solder (30) is interposed between each component electrode (12) and the substrate electrode (21), the tip of the wall (13) protruding from one surface (10a) of the electronic component (10) If the portion is in contact with one surface (20a) of the substrate (20), the wall (13) will support both members (10, 20), and the height of the solder (30) will be increased. It functions as a spacer for securing.

また、この場合、壁（１３）を、さらに電子部品（１０）の一面（１０ａ）の端部にも設け、基板（２０）の一面（２０ａ）側に開口部（２４）を形成した後、電子部品（１０）の一面（１０ａ）と基板（２０）の一面（２０ａ）とを対向させるにあたって、電子部品（１０）の一面（１０ａ）の端部に設けられた壁（１３）を、開口部（２４）に挿入して電子部品（１０）の位置決めを行うようにすることが好ましい。   In this case, the wall (13) is further provided at the end of the one surface (10a) of the electronic component (10), and the opening (24) is formed on the one surface (20a) side of the substrate (20). When facing one surface (10a) of the electronic component (10) and one surface (20a) of the substrate (20), the wall (13) provided at the end of the one surface (10a) of the electronic component (10) is opened. Preferably, the electronic component (10) is positioned by being inserted into the portion (24).

それによれば、電子部品（１０）の一面（１０ａ）の端部に設けられた壁（１３）と基板（２０）側の開口部（２４）とのかみ合いにより、電子部品（１０）の位置決めが容易となる。   According to this, the positioning of the electronic component (10) is achieved by the engagement between the wall (13) provided at the end of the one surface (10a) of the electronic component (10) and the opening (24) on the substrate (20) side. It becomes easy.

また、本発明は、それぞれの部品電極（１２）と基板電極（２１）との間にはんだ（３０）を介在させた状態では、基板（２０）の一面（２０ａ）のうち隣り合うはんだ（３０）同士の間に位置する部位に、当該基板（２０）の一面（２０ａ）から突出し当該両はんだ（３０）同士を遮断する壁（２２）が設けられた状態とし、この状態でスクラブを行うことを、第２の特徴とする。   Further, according to the present invention, in the state where the solder (30) is interposed between each component electrode (12) and the substrate electrode (21), the adjacent solder (30) on one surface (20a) of the substrate (20). ) A wall (22) that protrudes from one surface (20a) of the substrate (20) and blocks the solder (30) is provided at a position located between them, and scrubbing is performed in this state. Is the second feature.

それによれば、スクラブ時には、隣り合うはんだ（３０）同士の間が基板（２０）の一面（２０ａ）から突出する壁（２２）によって遮断された状態となることから、スクラブによって溶融した両はんだ（３０）同士が接触することが極力防止されるため、スクラブによるはんだブリッジの発生を抑制することができる。   According to this, during scrubbing, the adjacent solders (30) are blocked by the wall (22) protruding from one surface (20a) of the substrate (20), so both solders melted by scrub ( 30) Since contact with each other is prevented as much as possible, generation of solder bridges due to scrub can be suppressed.

この場合、それぞれの部品電極（１２）と基板電極（２１）との間にはんだ（３０）を介在させた状態では、基板（２０）の一面（２０ａ）から突出する壁（２２）の先端部が電子部品（１０）の一面（１０ａ）に接触した状態となるようにすれば、この壁（２２）が、両部材（１０、２０）を支持する形となり、はんだ（３０）の高さを確保するためのスペーサとして機能する。   In this case, in the state where the solder (30) is interposed between each component electrode (12) and the substrate electrode (21), the tip of the wall (22) protruding from one surface (20a) of the substrate (20) If it comes to be in the state which contacted one side (10a) of the electronic component (10), this wall (22) will become a form which supports both members (10, 20), and the height of solder (30) is made. It functions as a spacer for securing.

さらに、壁（２２）の先端部と電子部品（１０）の一面（１０ａ）との間に、これら両者の接触による電子部品（１０）のダメージを軽減する緩衝部材（２３）を介在させるようにすれば、壁（２２）の先端部と電子部品（１０）の一面（１０ａ）との接触時およびスクラブ時におけるダメージ軽減ができる。   Further, a buffer member (23) that reduces damage to the electronic component (10) due to the contact between the tip of the wall (22) and one surface (10a) of the electronic component (10) is interposed. If it does, the damage reduction at the time of contact with the front-end | tip part of a wall (22) and one surface (10a) of an electronic component (10) and a scrub can be performed.

また、上記第２の特徴を有する製造方法においては、基板（２０）の一面（１０ａ）側のうち電子部品（１０）と重なり合う部位に、電子部品（１０）の一面（１０ａ）側が挿入可能な開口部（２５）を形成した後、電子部品（１０）の一面（１０ａ）と基板（２０）の一面（２０ａ）とを対向させるにあたって、電子部品（１０）の一面（１０ａ）側を、開口部（２５）に挿入して電子部品（１０）の位置決めを行うようにすることが好ましい。   Moreover, in the manufacturing method having the second feature, the one surface (10a) side of the electronic component (10) can be inserted into a portion of the one surface (10a) side of the substrate (20) that overlaps the electronic component (10). After forming the opening (25), when the one surface (10a) of the electronic component (10) and the one surface (20a) of the substrate (20) are opposed to each other, the one surface (10a) side of the electronic component (10) is opened. Preferably, the electronic component (10) is positioned by being inserted into the portion (25).

それによれば、電子部品（１０）の外周端面とこの開口部（２５）とのかみ合いにより、電子部品（１０）の位置決めが容易となる。   According to this, the positioning of the electronic component (10) is facilitated by the engagement between the outer peripheral end face of the electronic component (10) and the opening (25).

また、本発明は、一面（１０ａ）側に複数個の部品電極（１２）が配置されている電子部品（１０）と、一面（２０ａ）側に複数個の基板電極（２１）が配置されている基板（２０）とを備え、これら両者（１０、２０）の一面（１０ａ、２０ａ）を対向して配置し、それぞれの部品電極（１２）と基板電極（２１）との間が、はんだ（３０）を介して接続されている電子部品の実装構造において、隣り合うはんだ（３０）同士の間に位置する部位に、電子部品（１０）の一面（１０ａ）または基板（２０）の一面（２０ａ）から突出し当該両はんだ（３０）同士を遮断する壁（１３、２２）を設けたことを、第３の特徴とする。   The present invention also includes an electronic component (10) having a plurality of component electrodes (12) arranged on one side (10a) side and a plurality of substrate electrodes (21) arranged on the one side (20a) side. And one surface (10a, 20a) of the two (10, 20) is arranged to face each other, and a solder (between each component electrode (12) and the substrate electrode (21) is provided. 30) In the mounting structure of electronic components connected via 30), one surface (10a) of the electronic component (10) or one surface (20a) of the substrate (20) is located at a position located between adjacent solders (30). ) Is provided with walls (13, 22) that project from the two solders (30) and shield the two solders (30) from each other.

この実装構造において、電子部品（１０）の一面（１０ａ）突出する壁（１３）を設けたものについては、上記第１の特徴を有する製造方法により、また、基板（２０）の一面（２０ａ）から突出する壁（２２）を設けたものについては、上記第２の特徴を有する製造方法により適切に製造されるものである。   In this mounting structure, one surface (10a) of the electronic component (10) provided with a protruding wall (13) is manufactured by the manufacturing method having the first feature, and the one surface (20a) of the substrate (20). What provided the wall (22) which protrudes from this is manufactured appropriately by the manufacturing method which has the said 2nd characteristic.

なお、特許請求の範囲およびこの欄で記載した各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示す一例である。   In addition, the code | symbol in the parenthesis of each means described in a claim and this column is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

以下、本発明の実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、説明の簡略化を図るべく、図中、同一符号を付してある。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are given the same reference numerals in the drawings in order to simplify the description.

（第１実施形態）
図１は、本発明の第１実施形態に係る電子部品１０の基板２０への実装構造の概略断面構成を示す図であり、図２は、この電子部品１０の一面１０ａ側の部分的な平面構成を、当該一面１０ａ上にはんだ３０が設けられた状態にて示す図である。なお、図１は、図２において、はんだ３０および壁１３を通る線にて切断した断面を示している。 (First embodiment)
FIG. 1 is a diagram showing a schematic cross-sectional configuration of a structure for mounting an electronic component 10 on a substrate 20 according to a first embodiment of the present invention. FIG. 2 is a partial plan view on the one surface 10a side of the electronic component 10. It is a figure which shows a structure in the state in which the solder 30 was provided on the said one surface 10a. 1 shows a cross section taken along a line passing through the solder 30 and the wall 13 in FIG.

電子部品１０は、その一面１０ａ側（図１中の下面側）に、複数個の部品電極１２が配置されているものである。このような構成を持つものであれば、特に限定するものではないが、本例では、電子部品１０は、シリコン基板１１よりなるＣＳＰ（チップサイズパッケージ）である。   The electronic component 10 has a plurality of component electrodes 12 arranged on the one surface 10a side (the lower surface side in FIG. 1). In this example, the electronic component 10 is a CSP (chip size package) made of the silicon substrate 11, as long as it has such a configuration.

このシリコン基板１１には、半導体プロセスなどにより製造された図示しないトランジスタ素子などが形成され、これら素子により図示しないＩＣ回路が構成されている。そして、電子部品１０の各部品電極１２は、例えば、シリコン基板１１に対して不純物拡散を行ったり、または、銅やアルミニウム、金などのスパッタや蒸着を行ったりすることで形成されたものである。   On the silicon substrate 11, transistor elements (not shown) manufactured by a semiconductor process or the like are formed, and these elements constitute an IC circuit (not shown). Each component electrode 12 of the electronic component 10 is formed by, for example, performing impurity diffusion on the silicon substrate 11 or performing sputtering or vapor deposition of copper, aluminum, gold, or the like. .

本実装構造において、それぞれの部品電極１２には、はんだ３０が接続されており、その平面パターンは図２に示される。なお、図２では、部品電極１２は、その上に位置するはんだ３０によって隠れているが、当該部品電極１２の位置は、このはんだ３０の位置と実質的に同じである。つまり、電子部品１０の一面１０ａにおいて、各部品電極１２は、格子状に配列された形となっている。   In this mounting structure, the solder 30 is connected to each component electrode 12, and the plane pattern is shown in FIG. In FIG. 2, the component electrode 12 is hidden by the solder 30 located thereon, but the position of the component electrode 12 is substantially the same as the position of the solder 30. That is, on the one surface 10a of the electronic component 10, the component electrodes 12 are arranged in a grid pattern.

また、基板２０は、板状のものであり、例えばセラミック基板、プリント基板、金属基板など各種の配線基板を採用することができる。本例では、基板２０は、アルミナなどのグリーンシートよりなるセラミック層を複数枚積層し焼成してなるセラミック積層基板として構成されている。   Moreover, the board | substrate 20 is a plate-shaped thing, For example, various wiring boards, such as a ceramic board | substrate, a printed circuit board, and a metal substrate, are employable. In this example, the board | substrate 20 is comprised as a ceramic laminated substrate formed by laminating | stacking and baking several ceramic layers which consist of green sheets, such as an alumina.

この基板２０において、電子部品１０の一面１０ａと対向する一面２０ａには、複数個の基板電極２１が設けられている。   In the substrate 20, a plurality of substrate electrodes 21 are provided on the one surface 20 a facing the one surface 10 a of the electronic component 10.

各基板電極２１は、電子部品１０のそれぞれの部品電極１２に対応して配置されており、具体的には、各部品電極１２と対向する位置に配置されている。このような基板電極２１は、通常の配線基板上の電極と同様の構成とすることができるが、例えば銅の上に金メッキを施してなるものにできる。   Each substrate electrode 21 is disposed corresponding to each component electrode 12 of the electronic component 10, and specifically, is disposed at a position facing each component electrode 12. Such a substrate electrode 21 can have the same configuration as an electrode on a normal wiring board, but can be formed by, for example, applying gold plating on copper.

そして、これら電子部品１０および基板電極２０は、電子部品１０の一面１２と基板２０の一面２１とを対向させた状態で配置されており、図１に示されるように、それぞれの部品電極１２と基板電極２１との間が、はんだ３０を介して接続されている。このようなはんだ３０としては、たとえば、一般的な共晶はんだや鉛フリーはんだなどを採用することができる。   The electronic component 10 and the substrate electrode 20 are arranged with the one surface 12 of the electronic component 10 and the one surface 21 of the substrate 20 facing each other, and as shown in FIG. The substrate electrode 21 is connected via the solder 30. As such solder 30, for example, general eutectic solder or lead-free solder can be employed.

ここにおいて、本実施形態では、図１、図２に示されるように、隣り合うはんだ３０同士の間に位置する部位には、電子部品１０の一面１０ａから突出する壁１３が設けられている。そして、この壁１３により、当該隣り合う両はんだ３０同士が実質的に遮断された状態となっている。   Here, in this embodiment, as shown in FIGS. 1 and 2, a wall 13 protruding from one surface 10 a of the electronic component 10 is provided at a portion located between adjacent solders 30. The wall 13 is in a state where the adjacent solders 30 are substantially blocked from each other.

以下、この壁１３を電子部品側の壁１３と言うことにするが、本例では、図２に示されるように、この電子部品側の壁１３は、個々のはんだ３０を取り囲むように格子状の平面パターンをなしている。   Hereinafter, the wall 13 will be referred to as an electronic component side wall 13. In this example, as shown in FIG. 2, the electronic component side wall 13 has a lattice shape so as to surround individual solders 30. It has a flat pattern.

この電子部品側の壁１３は、はんだ３０とは接合しない樹脂やセラミックなどの材料よりなるものである。そして、このような電子部品側の壁１３は、電子部品１０の一面１０ａに対して、マスクを用いた成膜法やホトリソグラフ法を用いた成膜法によるパターニング、さらには接着などによる貼り付けなどによって形成できる。   The wall 13 on the electronic component side is made of a material such as resin or ceramic that is not bonded to the solder 30. Such a wall 13 on the electronic component side is attached to one surface 10a of the electronic component 10 by patterning by a film forming method using a mask or a film forming method using a photolithographic method, and further by adhesion or the like. It can be formed by.

本例では、電子部品側の壁１３はポリイミドである。ポリイミドは、ＣＳＰの表面の保護膜として用いられているものであり、ＣＳＰよりなる本例の電子部品１０では、その一面１０ａに元々、一般的に形成されるものである。つまり、本例では、電子部品１０の保護膜の形成工程を利用して電子部品側の壁１３を形成することができる。   In this example, the wall 13 on the electronic component side is polyimide. Polyimide is used as a protective film on the surface of the CSP, and in the electronic component 10 of this example made of CSP, it is generally formed on one surface 10a from the beginning. That is, in this example, the wall 13 on the electronic component side can be formed by using the protective film forming process of the electronic component 10.

次に、本実施形態の電子部品の実装構造を形成するための実装方法について、上記例に基づいて述べる。図３は、本実装方法を示す工程図であり、各部を断面的に示すものである。   Next, a mounting method for forming the electronic component mounting structure of the present embodiment will be described based on the above example. FIG. 3 is a process diagram showing the present mounting method, and shows each section in section.

まず、一面１０ａ側に複数個の部品電極１２が配置されている電子部品１０と、一面２０ａ側に電子部品１０の部品電極１２に対応して複数個の基板電極２１が配置されている基板２０と、を用意する。   First, the electronic component 10 in which a plurality of component electrodes 12 are arranged on the one surface 10a side, and the substrate 20 in which a plurality of substrate electrodes 21 are arranged corresponding to the component electrodes 12 of the electronic component 10 on the one surface 20a side. And prepare.

本例では、電子部品１０としては、その一面１０ａに上記したポリイミドよりなる電子部品側の壁１３が形成されるとともに、各部品電極１２にはんだ３０を接続したＣＳＰを用意する。   In this example, as the electronic component 10, a CSP in which a wall 13 on the electronic component side made of the above-described polyimide is formed on one surface 10 a and a solder 30 is connected to each component electrode 12 is prepared.

本例におけるポリイミドよりなる電子部品側の壁１３の形成方法としては、図示しないマスクを用いて、電子部品１０の一面１０ａのうち部品電極１２およびその周辺を被覆し、当該マスクで被覆されている以外の部位にて、印刷法などによりポリイミドを成長させる。ここで、マスキングする部位は、例えば１辺が部品電極１２の直径＋１００μｍの正方形とする。   As a method of forming the wall 13 on the electronic component side made of polyimide in this example, the component electrode 12 and its periphery are covered on the one surface 10a of the electronic component 10 using a mask (not shown), and the mask is covered with the mask. The polyimide is grown by a printing method or the like at a site other than the above. Here, the part to be masked is, for example, a square whose one side is the diameter of the component electrode 12 +100 μm.

そして、上記マスクを除去した後、はんだ３０をそれぞれの部品電極１２に接続する。このはんだ３０の接続は、フラックスを含まないはんだ材料を用い、例えばはんだボール法、はんだメッキなどの一般的な方法により行うことができる。   Then, after removing the mask, the solder 30 is connected to each component electrode 12. The solder 30 can be connected by using a solder material that does not contain a flux, for example, by a general method such as a solder ball method or solder plating.

なお、電子部品側の壁１３の形成方法としては、電子部品１０の一面１０ａの全面をポリイミド膜で覆い、このポリイミド膜のうち部品電極１２とその周辺を覆う部位を、フォトリソグラフ法などによるエッチング等にて完全に除去することによっても行える。この場合も、その後は上記同様に、はんだ３０を形成する。   As a method for forming the wall 13 on the electronic component side, the entire surface 10a of the electronic component 10 is covered with a polyimide film, and a portion of the polyimide film covering the component electrode 12 and its periphery is etched by a photolithographic method or the like. It can also be done by removing completely with, for example. Also in this case, the solder 30 is formed thereafter as described above.

次に、はんだダイボンダ技術により、電子部品１０と基板２０とをはんだ付けする。まず、還元雰囲気にて、電子部品１０の一面１０ａと基板２０の一面２０ａとを対向させるとともに、それぞれの部品電極１２と基板電極２１との間に、はんだ３０を介在させた状態とする。   Next, the electronic component 10 and the substrate 20 are soldered by a solder die bonder technique. First, in the reducing atmosphere, the one surface 10a of the electronic component 10 and the one surface 20a of the substrate 20 are opposed to each other, and the solder 30 is interposed between the component electrode 12 and the substrate electrode 21.

ここで、還元雰囲気としては、フラックスを含まないはんだ３０の酸化を防止する雰囲気であればよく、具体的には、例えば、水素が数％〜数十％で残部は窒素であるようなガス雰囲気とする。   Here, the reducing atmosphere may be an atmosphere that prevents oxidation of the solder 30 that does not contain flux. Specifically, for example, a gas atmosphere in which hydrogen is several percent to several tens percent and the balance is nitrogen. And

この還元雰囲気にて、図３（ａ）に示されるように、コレット２００を用い、このコレット２００に電子部品１０の上端部を吸着した状態で、電子部品１０を基板２０上に位置させ、電子部品１０の一面１０ａと基板２０の一面２０ａとを対向させる。   In this reducing atmosphere, as shown in FIG. 3A, a collet 200 is used, the electronic component 10 is positioned on the substrate 20 with the upper end of the electronic component 10 adsorbed to the collet 200, and the electronic The one surface 10a of the component 10 and the one surface 20a of the substrate 20 are opposed to each other.

ここで、コレット２００は、はんだダイボンダに用いられる一般的なものを採用できる。具体的には、コレット２００は、ダイボンダにおける上下動作、水平動作や旋回動作が可能なピックアンドプレースユニットの先端に配置され、電子部品１０を吸着し且つ昇降機能およびスクラブ機能を持つ。   Here, the collet 200 can employ a general one used for a solder die bonder. Specifically, the collet 200 is disposed at the tip of a pick-and-place unit capable of vertical movement, horizontal movement, and turning movement in the die bonder, sucks the electronic component 10, and has a lifting function and a scrub function.

ここでは、コレット２００は、図３に示されるように、底部側の端部が開口した開口部２１０となっている中空角錐形状をなす。そして、図示しない頭部側から図示しない真空ポンプなどにより吸引したときに開口部２１０に発生する吸引力によって、電子部品１０を拾い上げて保持するようになっている。   Here, as shown in FIG. 3, the collet 200 has a hollow pyramid shape having an opening 210 with an end on the bottom side opened. The electronic component 10 is picked up and held by a suction force generated in the opening 210 when sucked from a head (not shown) by a vacuum pump (not shown).

そして、図３（ａ）に示される状態から電子部品１０を下降させ、図３（ｂ）に示されるように、それぞれの部品電極１２と基板電極２１との間に、はんだ３０を介在させた状態とする。そして、この状態にて、コレット２００によってスクラブを行う。   Then, the electronic component 10 is lowered from the state shown in FIG. 3A, and the solder 30 is interposed between the component electrode 12 and the substrate electrode 21 as shown in FIG. 3B. State. In this state, the collet 200 is used for scrubbing.

このスクラブの方向、すなわちはんだ３０と基板電極２１との擦り合わせの方向は、特に限定するものではないが、一例としては、図３（ｂ）および上記図２に示されるように、基板２０の一面２０ａに沿った平面にて四角形を描くような方向とすることができる。そして、そのスクラブにおけるコレット２００の動く領域は、例えば□１００±５０μｍ程度のものである。   The direction of scrubbing, that is, the direction of rubbing between the solder 30 and the substrate electrode 21 is not particularly limited. As an example, as shown in FIG. 3B and FIG. The direction can be such that a quadrilateral is drawn on a plane along the surface 20a. The moving area of the collet 200 in the scrub is, for example, about □ 100 ± 50 μm.

また、このスクラブの際には、基板２０は、たとえばその下方から図示しないヒータなどにより加熱されており、この熱によりはんだ３０が溶融する。そして、スクラブの終了後、はんだ３０が固化することにより、それぞれの部品電極１２と基板電極２１とがはんだ３０にて接続される。こうして、電子部品１０の基板２０へのはんだ接合が完了し、上記図１に示される実装構造ができあがる。   Further, during scrubbing, the substrate 20 is heated, for example, by a heater (not shown) from below, and the solder 30 is melted by this heat. Then, after the scrubbing, the solder 30 is solidified to connect the component electrodes 12 and the substrate electrodes 21 with the solder 30. Thus, the solder joint of the electronic component 10 to the substrate 20 is completed, and the mounting structure shown in FIG. 1 is completed.

ここで、上記実装方法においては、電子部品１０の一面１０ａに予め上記電子部品側の壁１３を設けることにより、それぞれの部品電極１２と基板電極２１との間にはんだ３０を介在させた状態においては、電子部品１０の一面１０ａのうち隣り合うはんだ３０同士の間に位置する部位に、当該一面１０ａから突出し当該両はんだ３０同士を遮断する壁１３が設けられた状態となる。   Here, in the mounting method, by providing the electronic component side wall 13 in advance on one surface 10 a of the electronic component 10, the solder 30 is interposed between the component electrode 12 and the substrate electrode 21. Is a state in which a wall 13 that protrudes from the one surface 10 a and blocks the two solders 30 is provided in a portion located between the adjacent solders 30 in the one surface 10 a of the electronic component 10.

そして、この状態でスクラブを行うが、スクラブ時には、隣り合うはんだ３０同士の間が電子部品側の壁１３によって遮断された状態が確保されている。   Then, scrubbing is performed in this state. At the time of scrubbing, a state in which the adjacent solders 30 are blocked by the wall 13 on the electronic component side is ensured.

このことから、隣り合うはんだ３０同士が、スクラブによって溶融し動いたとしても、電子部品側の壁１３以外には接触しないため、これら両はんだ３０同士の接触が極力防止される。そのため、本実装方法によれば、スクラブによるはんだブリッジの発生を抑制することができる。   For this reason, even if the adjacent solders 30 are melted and moved by scrubbing, they do not come in contact with any part other than the wall 13 on the electronic component side, so that contact between these two solders 30 is prevented as much as possible. Therefore, according to this mounting method, it is possible to suppress the generation of solder bridges due to scrubbing.

また、本実施形態では、スクラブ時に溶融したはんだ３０が横に広がるのを抑制するために、ある程度、基板２０の一面２０ａから突出する基板電極２１の高さを高くし、基板電極２１からはみだすはんだ３０を基板電極２１の側面にも付着させることが望ましい。例えば、このような効果を得るための基板電極２１の高さは、従来の一般的な基板電極の高さの５倍以上（例えば５０μｍ）とする。   In this embodiment, in order to prevent the solder 30 melted during scrubbing from spreading laterally, the height of the substrate electrode 21 protruding from the one surface 20a of the substrate 20 is increased to some extent, and the solder protruding from the substrate electrode 21 is increased. It is desirable to attach 30 to the side surface of the substrate electrode 21 as well. For example, the height of the substrate electrode 21 for obtaining such an effect is set to be five times or more (for example, 50 μm) of the height of a conventional general substrate electrode.

また、本実施形態によれば、一面１０ａ側に複数個の部品電極１２が配置されている電子部品１０と、一面２０ａ側に複数個の基板電極２１が配置されている基板２０とを備え、これら両者１０、２０の一面１０ａ、２０ａを対向して配置し、それぞれの部品電極１２と基板電極２１との間が、はんだ３０を介して接続されている電子部品の実装構造において、隣り合うはんだ３０同士の間に位置する部位に、電子部品１０の一面１０ａから突出し当該両はんだ３０同士を遮断する壁１３を設けてなる電子部品の実装構造を提供することができる。   In addition, according to the present embodiment, the electronic component 10 having a plurality of component electrodes 12 arranged on the one surface 10a side and the substrate 20 having a plurality of substrate electrodes 21 arranged on the one surface 20a side are provided. In the mounting structure of the electronic component in which the surfaces 10a and 20a of the both 10 and 20 are arranged to face each other and the component electrode 12 and the substrate electrode 21 are connected via the solder 30, the adjacent solders It is possible to provide a mounting structure for an electronic component in which a wall 13 that protrudes from one surface 10a of the electronic component 10 and blocks the solders 30 is provided in a portion located between the 30.

（第２実施形態）
図４は、本発明の第２実施形態に係る電子部品１０の基板２０への実装構造の概略断面構成を示す図である。上記第１実施形態では、隣り合うはんだ３０同士の間を遮断する壁を電子部品１０の一面１０ａ側に設けたが、本実施形態は、これとは反対に、当該壁２２を基板２０の一面２０ａ側に設けたものである。 (Second Embodiment)
FIG. 4 is a diagram showing a schematic cross-sectional configuration of the mounting structure of the electronic component 10 on the substrate 20 according to the second embodiment of the present invention. In the first embodiment, a wall that blocks between adjacent solders 30 is provided on the one surface 10a side of the electronic component 10, but in the present embodiment, the wall 22 is disposed on one surface of the substrate 20 on the contrary. It is provided on the 20a side.

本実施形態の実装構造も、図４に示されるように、一面１０ａ側に複数個の部品電極１２が配置されている電子部品１０と、一面２０ａ側に部品電極１２に対応して複数個の基板電極２１が配置されている基板２０とを備え、電子部品１０の一面１０ａと基板２０の一面２０ａとが対向して配置され、それぞれの部品電極１２と基板電極２１との間が、はんだ３０を介して接続されている。   As shown in FIG. 4, the mounting structure of the present embodiment also includes an electronic component 10 in which a plurality of component electrodes 12 are arranged on one surface 10 a side, and a plurality of components corresponding to the component electrodes 12 on the one surface 20 a side. A substrate 20 on which the substrate electrode 21 is disposed, the one surface 10a of the electronic component 10 and the one surface 20a of the substrate 20 are disposed to face each other, and a solder 30 is provided between each component electrode 12 and the substrate electrode 21. Connected through.

ここにおいて、本実施形態では、図４に示されるように、隣り合うはんだ３０同士の間に位置する部位には、基板２０の一面２０ａから突出する壁２２が設けられており、この壁２２により当該隣り合う両はんだ３０同士が遮断されている。一方、電子部品１０の一面１０ａには、上記実施形態に示した壁は存在しない。   Here, in this embodiment, as shown in FIG. 4, a wall 22 protruding from one surface 20 a of the substrate 20 is provided at a portion located between adjacent solders 30, and this wall 22 The adjacent solders 30 are blocked from each other. On the other hand, the wall shown in the above embodiment does not exist on one surface 10a of the electronic component 10.

以下、この壁２２を基板側の壁２２と言うことにする。本例では、図は省略するが、この基板側の壁２２は、上記図２に示される電子部品側の壁１３のパターンと同様に、個々のはんだ３０を取り囲むように格子状の平面パターンをなしている。   Hereinafter, the wall 22 is referred to as a substrate-side wall 22. In this example, although not shown in the figure, the board-side wall 22 has a grid-like plane pattern so as to surround individual solders 30 in the same manner as the pattern of the electronic component-side wall 13 shown in FIG. There is no.

この基板側の壁２２は、はんだ３０とは接合しない樹脂やセラミックなどの材料よりなるものであり、基板２０の一面２０ａに対して、上記電子部品側の壁１３と同じく、マスクを用いた成膜法やホトリソグラフ法を用いた成膜法、さらには接着などにより形成することができる。また、基板２０の表面を切削などにより凹ませ、この凹みの周囲の部分を基板側の壁２２として構成してもよい。   The substrate-side wall 22 is made of a material such as resin or ceramic that is not bonded to the solder 30, and is formed with a mask on one surface 20 a of the substrate 20, as with the electronic component-side wall 13. The film can be formed by a film formation method, a film formation method using a photolithography method, or by adhesion. Alternatively, the surface of the substrate 20 may be recessed by cutting or the like, and a portion around the recess may be configured as the wall 22 on the substrate side.

本例では、基板２０は、アルミナなどのセラミック層を複数枚積層してなるセラミック積層基板よりなる。そのため、各基板電極２１の部分が開口したグリーンシートを、基板２０の一面２０ａ上に重ねて焼成することにより、この焼成されたグリーンシートを基板側の壁２２として構成している。   In this example, the substrate 20 is formed of a ceramic laminated substrate in which a plurality of ceramic layers such as alumina are laminated. For this reason, the fired green sheet is configured as the substrate-side wall 22 by stacking and firing the green sheet in which the portion of each substrate electrode 21 is opened on the one surface 20a of the substrate 20.

次に、本実施形態の電子部品の実装構造を形成するための実装方法について、上記例に基づいて述べる。図５は、本実装方法を示す工程図であり、各部を断面的に示すものである。本実施形態の実装方法も、はんだダイボンダ技術により電子部品１０と基板２０とをはんだ付けするものである。   Next, a mounting method for forming the electronic component mounting structure of the present embodiment will be described based on the above example. FIG. 5 is a process diagram illustrating the present mounting method, and shows each section in cross-section. The mounting method of this embodiment also solders the electronic component 10 and the substrate 20 by the solder die bonder technique.

まず、一面１０ａ側に複数個の部品電極１２が配置されている電子部品１０と、一面２０ａ側に電子部品１０の部品電極１２に対応して複数個の基板電極２１が配置されている基板２０とを用意する。   First, the electronic component 10 in which a plurality of component electrodes 12 are arranged on the one surface 10a side, and the substrate 20 in which a plurality of substrate electrodes 21 are arranged corresponding to the component electrodes 12 of the electronic component 10 on the one surface 20a side. And prepare.

本例では、電子部品１０としては、その一面１０ａにおいて各部品電極１２にはんだ３０を接続したものを用意し、一方、基板２０としては、その一面２０ａに上記したグリーンシートよりなる基板側の壁２２が形成されたものを用意する。   In this example, the electronic component 10 is prepared by connecting a solder 30 to each component electrode 12 on one surface 10a, while the substrate 20 is a substrate-side wall made of the above-described green sheet on the one surface 20a. Prepare one with 22 formed.

次に、図５（ａ）に示されるように、上記第１実施形態と同様にして、水素などの還元雰囲気にて、コレット２００を用い、電子部品１０の一面１０ａと基板２０の一面２０ａとを対向させる。   Next, as shown in FIG. 5A, in the same manner as in the first embodiment, using the collet 200 in a reducing atmosphere such as hydrogen, the one surface 10a of the electronic component 10 and the one surface 20a of the substrate 20 Face each other.

そして、図５（ａ）に示される状態から電子部品１０を下降させ、図５（ｂ）に示されるように、それぞれの部品電極１２と基板電極２１との間に、はんだ３０を介在させた状態とする。   Then, the electronic component 10 is lowered from the state shown in FIG. 5A, and the solder 30 is interposed between the component electrode 12 and the substrate electrode 21 as shown in FIG. 5B. State.

そして、この状態にて、上記第１実施形態と同様に、基板２０を加熱しながら、コレット２００によってスクラブを行う。このスクラブの終了に伴い、それぞれの部品電極１２と基板電極２１とがはんだ３０にて接続され、上記図４に示される本実施形態の実装構造ができあがる。   In this state, scrubbing is performed by the collet 200 while heating the substrate 20 as in the first embodiment. As the scrubbing is completed, the component electrodes 12 and the substrate electrodes 21 are connected by the solder 30, and the mounting structure of the present embodiment shown in FIG. 4 is completed.

ここで、本実施形態の実装方法においては、基板２０の一面２０ａに予め上記基板側の壁２２を設けることにより、それぞれの部品電極１２と基板電極２１との間にはんだ３０を介在させた状態においては、基板２０の一面２０ａのうち隣り合うはんだ３０同士の間に位置する部位に、当該一面２０ａから突出し当該両はんだ３０同士を遮断する壁２２が設けられた状態となる。   Here, in the mounting method of the present embodiment, a state in which the solder 30 is interposed between each component electrode 12 and the substrate electrode 21 by previously providing the substrate-side wall 22 on the one surface 20a of the substrate 20 is provided. In this case, a wall 22 that protrudes from the one surface 20a and blocks the two solders 30 is provided at a portion of the one surface 20a of the substrate 20 located between the adjacent solders 30.

そして、この状態でスクラブを行うが、スクラブ時には、隣り合うはんだ３０同士の間が基板側の壁２２によって遮断された状態となる。このことから、本実装方法においても、これら両はんだ３０同士の接触が極力防止される。そのため、本実装方法によれば、スクラブによるはんだブリッジの発生を抑制することができる。   Then, scrubbing is performed in this state. At the time of scrubbing, the adjacent solders 30 are blocked by the substrate-side wall 22. From this, also in this mounting method, the contact between these two solders 30 is prevented as much as possible. Therefore, according to this mounting method, it is possible to suppress the generation of solder bridges due to scrubbing.

また、本実施形態においても、スクラブ時に溶融したはんだ３０が横に広がるのを抑制するために、上記第１実施形態と同様に、ある程度、基板２０の一面２０ａから突出する基板電極２１の高さを高くすることが望ましい。   Also in the present embodiment, the height of the substrate electrode 21 protruding from the one surface 20a of the substrate 20 to some extent, as in the first embodiment, is suppressed in order to prevent the solder 30 melted during scrubbing from spreading laterally. It is desirable to increase the value.

また、本実施形態によれば、一面１０ａ側に複数個の部品電極１２が配置されている電子部品１０と、一面２０ａ側に複数個の基板電極２１が配置されている基板２０とを備え、これら両者１０、２０の一面１０ａ、２０ａを対向して配置し、それぞれの部品電極１２と基板電極２１との間が、はんだ３０を介して接続されている電子部品の実装構造において、隣り合うはんだ３０同士の間に位置する部位に、基板２０の一面２０ａから突出し当該両はんだ３０同士を遮断する壁２２を設けてなる電子部品の実装構造を提供することができる。   In addition, according to the present embodiment, the electronic component 10 having a plurality of component electrodes 12 arranged on the one surface 10a side and the substrate 20 having a plurality of substrate electrodes 21 arranged on the one surface 20a side are provided. In the mounting structure of the electronic component in which the surfaces 10a and 20a of the both 10 and 20 are arranged to face each other and the component electrode 12 and the substrate electrode 21 are connected via the solder 30, the adjacent solders It is possible to provide a mounting structure for an electronic component in which a wall 22 that protrudes from one surface 20a of the substrate 20 and blocks the solders 30 is provided in a portion located between the members 30.

（第３実施形態）
図６は、本発明の第３実施形態に係る電子部品１０の基板２０への実装方法を断面的に示す工程図である。図６では、コレット２００によってスクラブを行っている状態が示されている。 (Third embodiment)
FIG. 6 is a cross-sectional process diagram illustrating a method of mounting the electronic component 10 on the substrate 20 according to the third embodiment of the present invention. FIG. 6 shows a state in which scrubbing is being performed by the collet 200.

本実施形態の実装方法は、上記第１実施形態の実装方法（上記図３参照）と同様に、それぞれの部品電極１２と基板電極２１との間にはんだ３０を介在させた状態において、隣り合うはんだ３０同士の間に位置する部位に、電子部品１０の一面１０ａから突出し当該両はんだ３０同士を遮断する電子部品側の壁１３が設けられた状態とし、この状態でスクラブを行うものである。   Similar to the mounting method of the first embodiment (see FIG. 3), the mounting method of the present embodiment is adjacent to each other in the state where the solder 30 is interposed between the component electrodes 12 and the substrate electrode 21. The wall 13 on the electronic component side that protrudes from the one surface 10a of the electronic component 10 and blocks the solder 30 is provided in a portion located between the solders 30, and scrubbing is performed in this state.

ここで、上記第１実施形態では、それぞれの部品電極１２と基板電極２１との間にはんだ３０を介在させた状態では、電子部品側の壁１３の先端部が基板２０の一面２０ａから離れていたが、本実施形態では、電子部品側の壁１３の先端部が基板２０の一面２０ａに接触した形とする。   Here, in the first embodiment, in the state where the solder 30 is interposed between each component electrode 12 and the substrate electrode 21, the tip portion of the wall 13 on the electronic component side is separated from the one surface 20 a of the substrate 20. However, in the present embodiment, the tip of the wall 13 on the electronic component side is in contact with the one surface 20 a of the substrate 20.

このように電子部品側の壁１３の先端部が基板２０の一面２０ａに接することにより、当該壁１３を介して、電子部品１０と基板２０とが支持された形となる。そのため、この場合の電子部品側の壁１３は、各々のはんだ３０の高さを確保するためのスペーサとして機能する。   In this way, the tip of the wall 13 on the electronic component side contacts the one surface 20 a of the substrate 20, so that the electronic component 10 and the substrate 20 are supported via the wall 13. Therefore, the wall 13 on the electronic component side in this case functions as a spacer for securing the height of each solder 30.

そのため、上記第１実施形態と同様に、スクラブによるはんだブリッジの発生を抑制できるとともに、本実施形態によれば、複数個のはんだ３０の高さをほぼ一定に決めることができ、電子部品１０と基板２０との間の傾きも極力防止できる。   Therefore, as in the first embodiment, the generation of solder bridges due to scrub can be suppressed, and according to the present embodiment, the height of the plurality of solders 30 can be determined to be substantially constant, and the electronic component 10 and Tilt between the substrate 20 and the substrate 20 can be prevented as much as possible.

なお、本実施形態では、スクラブの終了に伴い、はんだ接続がなされ、隣り合うはんだ３０同士の間に位置する部位に電子部品側の壁１３を設けた実装構造ができあがるが、このできあがりの時点では、電子部品側の壁１３の先端部と基板２０の一面２０ａとは、接触したままの状態でもよいし、コレット２００を離したときの反発力などにより離れた状態であってもよい。   In the present embodiment, with the end of scrubbing, solder connection is made, and a mounting structure in which a wall 13 on the electronic component side is provided in a portion located between adjacent solders 30 is completed. At the time of completion, The tip of the wall 13 on the electronic component side and the one surface 20a of the substrate 20 may be in contact with each other, or may be in a separated state due to a repulsive force when the collet 200 is released.

（第４実施形態）
図７は、本発明の第４実施形態に係る電子部品１０の基板２０への実装方法を断面的に示す工程図である。 (Fourth embodiment)
FIG. 7 is a cross-sectional process diagram illustrating a method of mounting the electronic component 10 on the substrate 20 according to the fourth embodiment of the present invention.

本実施形態の実装方法は、上記第２実施形態の実装方法（上記図５参照）と同様に、それぞれの部品電極１２と基板電極２１との間にはんだ３０を介在させた状態において、隣り合うはんだ３０同士の間に位置する部位に、基板２０の一面２０ａから突出し当該両はんだ３０同士を遮断する基板側の壁２２が設けられた状態とし、この状態でスクラブを行うものである。   Similar to the mounting method of the second embodiment (see FIG. 5), the mounting method of the present embodiment is adjacent to each other in the state where the solder 30 is interposed between the component electrode 12 and the substrate electrode 21. Scrub is performed in a state in which a substrate-side wall 22 that protrudes from one surface 20a of the substrate 20 and blocks the solders 30 is provided in a portion located between the solders 30.

具体的には、図７（ａ）に示されるように、コレット２００によって電子部品１０を基板２０上に配置させた状態から、図７（ｂ）に示されるようにコレット２００を下降させ、スクラブを行う。   Specifically, as shown in FIG. 7A, the collet 200 is lowered as shown in FIG. 7B from the state in which the electronic component 10 is disposed on the substrate 20 by the collet 200, and scrubbing is performed. I do.

ここで、上記第２実施形態では、それぞれの部品電極１２と基板電極２１との間にはんだ３０を介在させた状態では、基板側の壁２２の先端部が電子部品１０の一面１０ａから離れていたが、本実施形態では、基板側の壁２２の先端部が電子部品１０の一面１０ａに接触した状態とする。   Here, in the second embodiment, in a state where the solder 30 is interposed between the component electrodes 12 and the substrate electrodes 21, the front end portion of the wall 22 on the substrate side is separated from the one surface 10 a of the electronic component 10. However, in the present embodiment, the tip of the board-side wall 22 is in contact with the one surface 10 a of the electronic component 10.

このように基板側の壁２２の先端部が電子部品１０の一面１０ａに接することにより、当該壁２２が、両部材１０、２０を支持する形となり、各はんだ３０の高さを確保するためのスペーサとして機能する。   Thus, when the front-end | tip part of the wall 22 by the side of a board | substrate contacts the one surface 10a of the electronic component 10, the said wall 22 will be in the form which supports both the members 10 and 20, and it is for securing the height of each solder 30 Functions as a spacer.

そのため、上記第２実施形態と同様に、スクラブによるはんだブリッジの発生を抑制できるとともに、本実施形態によれば、複数個のはんだ３０の高さをほぼ一定に決めることができ、電子部品１０と基板２０との間の傾きも極力防止できる。   Therefore, as in the second embodiment, the generation of solder bridges due to scrubs can be suppressed, and according to the present embodiment, the height of the plurality of solders 30 can be determined to be substantially constant, Tilt between the substrate 20 and the substrate 20 can be prevented as much as possible.

また、本実施形態では、スクラブの終了に伴い、はんだ接続がなされ、隣り合うはんだ３０同士の間に位置する部位に基板側の壁２２を設けた実装構造ができあがるが、このできあがりの時点では、基板側の壁２２の先端部と基板２０の一面２０ａとは、接触したままの状態でもよいし、コレット２００を離したときの反発力などにより離れた状態であってもよい。   Further, in this embodiment, with the end of scrubbing, solder connection is made, and a mounting structure in which a substrate-side wall 22 is provided in a portion located between adjacent solders 30 is completed. At the time of completion, The tip of the substrate-side wall 22 and the one surface 20a of the substrate 20 may be in contact with each other, or may be in a separated state due to repulsive force when the collet 200 is released.

また、本例の実装方法においては、図７に示されるように、基板側の壁２２の先端部と電子部品１０の一面１０ａとの間には、これら両者１０ａ、２２の接触による電子部品１０のダメージを軽減する緩衝部材２３を介在させる。   Further, in the mounting method of this example, as shown in FIG. 7, the electronic component 10 due to the contact between these two parts 10 a, 22 is disposed between the front end portion of the board-side wall 22 and one surface 10 a of the electronic component 10. A buffer member 23 for reducing the damage is interposed.

この緩衝部材２３は、基板側の壁２２と電子部品１０との当たりの衝撃をやわらげる材料であれば、特に限定されないが、たとえば樹脂やゴムなどよりなる。そして、これらの材料に係る一般的な成膜方法や貼り付けなどにより設けられたものとして緩衝部材２３は構成される。   The buffer member 23 is not particularly limited as long as it is a material that can soften the impact on the board-side wall 22 and the electronic component 10, but is made of, for example, resin or rubber. And the buffer member 23 is comprised as what was provided by the general film-forming method and sticking etc. which concern on these materials.

本例では、緩衝部材２３は、予め基板２０において、基板側の壁２２の先端部に接着などにより取り付けている。なお、この緩衝部材２３は、本例のように、基板２０側ではなく、予め電子部品１０の一面１０ａにおける基板側の壁２２の先端部が接する部位に、接着などにより取り付けてもよい。   In this example, the buffer member 23 is previously attached to the tip of the substrate-side wall 22 by bonding or the like in the substrate 20. Note that the buffer member 23 may be attached not by the substrate 20 side but by adhesion or the like in advance to the portion where the front end portion of the wall 22 on the substrate side of the one surface 10a of the electronic component 10 contacts, as in this example.

本実施形態においては、このような緩衝部材２３は無くてもよい。つまり、基板側の壁２２の先端部が直接、電子部品１０の一面１０ａに接触していてもよく、それにより、上記したスペーサの機能が発揮される。   In the present embodiment, such a buffer member 23 may be omitted. That is, the front end portion of the wall 22 on the substrate side may be in direct contact with the one surface 10a of the electronic component 10, whereby the function of the spacer described above is exhibited.

しかしながら、このように緩衝部材２３を存在させることにより、この壁２２によるスペーサの機能に加えて、基板側の壁２２の先端部と電子部品１０の一面１０ａとの接触時およびスクラブ時における電子部品１０のダメージを軽減することができる。   However, by providing the buffer member 23 in this way, in addition to the function of the spacer by the wall 22, the electronic component at the time of contact and scrubbing between the front end portion of the wall 22 on the substrate side and the one surface 10a of the electronic component 10 10 damage can be reduced.

また、本実施形態において、基板側の壁２２の先端部が電子部品１０の一面１０ａに接触するということは、基板側の壁２２が直接的に接触することだけでなく、上記した緩衝部材２３のような介在物を介して間接的に接触していることをも含むものである。そして、上述したように、基板側の壁２２がスペーサの役目を果たすべく電子部品１０と基板２０とを支持していればよいものである。   Further, in the present embodiment, the fact that the tip of the board-side wall 22 contacts the one surface 10a of the electronic component 10 not only directly contacts the board-side wall 22 but also the buffer member 23 described above. Indirect contact via an inclusion such as is also included. As described above, the substrate-side wall 22 only needs to support the electronic component 10 and the substrate 20 so as to serve as a spacer.

（第５実施形態）
図８は、本発明の第５実施形態に係る電子部品１０の基板２０への実装方法を断面的に示す工程図である。本実施形態は、上記第４実施形態の実装方法（上記図７参照）において、基板側の壁２２の形状を変形したものである。 (Fifth embodiment)
FIG. 8 is a cross-sectional process diagram illustrating a method of mounting the electronic component 10 on the substrate 20 according to the fifth embodiment of the present invention. The present embodiment is obtained by modifying the shape of the substrate-side wall 22 in the mounting method of the fourth embodiment (see FIG. 7).

本実施形態の実装方法も、図８（ａ）、（ｂ）に示されるように、コレット２００によって電子部品１０を基板２０上に配置させ、コレット２００を下降させることにより、それぞれの部品電極１２と基板電極２１との間にはんだ３０を介在させ、基板側の壁２２が設けられた状態にてスクラブを行うものである。   As shown in FIGS. 8A and 8B, the mounting method according to the present embodiment also places the electronic component 10 on the substrate 20 by the collet 200 and lowers the collet 200, whereby each component electrode 12 is disposed. And the substrate electrode 21 with the solder 30 interposed, and scrubbing is performed with the substrate-side wall 22 provided.

ここで、本実施形態では、図８に示されるように、基板側の壁２２をピン状のものとする。このような基板側の壁２２は、例えば、このピン状の形状を持つようにパターニングされたグリーンシートを基板２０の一面２０ａに重ねて、基板２０を作製することにより形成できる。   Here, in this embodiment, as shown in FIG. 8, the wall 22 on the substrate side is a pin-like one. Such a substrate-side wall 22 can be formed, for example, by manufacturing the substrate 20 by superimposing the green sheet patterned so as to have this pin shape on the one surface 20a of the substrate 20.

そして、本実施形態においては、上記した基板側の壁２２によるはんだブリッジの発生の抑制、およびスペーサの効果が発揮されるとともに、基板側の壁２２をこのようなピン状とすることで、基板側の壁２２の先端部が電子部品１０の一面１０ａに接触する面積を小さくでき、電子部品１０のダメージのさらなる低減が図れる。   And in this embodiment, while suppressing generation | occurrence | production of the solder bridge | bridging by the above-mentioned board | substrate side wall 22, and the effect of a spacer are demonstrated, the board | substrate side wall 22 is made into such a pin shape, and a board | substrate is carried out. The area where the tip of the side wall 22 contacts the one surface 10a of the electronic component 10 can be reduced, and damage to the electronic component 10 can be further reduced.

（第６実施形態）
図９は、本発明の第６実施形態に係る電子部品１０の基板２０への実装方法を断面的に示す工程図である。 (Sixth embodiment)
FIG. 9 is a cross-sectional process diagram illustrating a method of mounting the electronic component 10 on the substrate 20 according to the sixth embodiment of the present invention.

本実施形態の実装方法は、上記第１実施形態の実装方法（上記図３参照）と同様に、それぞれの部品電極１２と基板電極２１との間にはんだ３０を介在させた状態では、隣り合うはんだ３０同士の間に位置する部位に、電子部品側の壁１３が設けられた状態とし、この状態でスクラブを行うものである。   Similar to the mounting method of the first embodiment (see FIG. 3), the mounting method of the present embodiment is adjacent to each other in the state where the solder 30 is interposed between the component electrode 12 and the substrate electrode 21. The electronic component side wall 13 is provided in a portion located between the solders 30, and scrubbing is performed in this state.

ここで、本実施形態では、図９（ａ）、（ｂ）に示されるように、電子部品側の壁１３は、隣り合うはんだ３０同士の間だけでなく、さらに電子部品１０の一面１０ａの端部にも設けられている。   Here, in this embodiment, as shown in FIGS. 9A and 9B, the wall 13 on the electronic component side is not only between the adjacent solders 30 but also on one surface 10 a of the electronic component 10. It is also provided at the end.

このような電子部品１０を用意するとともに、本実施形態では、基板２０として、基板２０の一面２０ａ側に開口部２４を形成したものを用意する。ここでは、開口部２４は、電子部品１０の一面１０ａの外形と相似形状であって一回り大きな開口形状を有するものである。   In addition to preparing such an electronic component 10, in this embodiment, a substrate 20 having an opening 24 formed on the one surface 20 a side of the substrate 20 is prepared. Here, the opening 24 has a shape similar to the outer shape of the one surface 10a of the electronic component 10 and has a slightly larger opening shape.

そして、本実施形態の実装方法では、図９（ａ）、（ｂ）に示されるように、コレット２００によって電子部品１０を基板２０上に配置させ、コレット２００を下降させることにより、それぞれの部品電極１２と基板電極２１との間にはんだ３０および電子部品側の壁１３を介在させる。   In the mounting method of the present embodiment, as shown in FIGS. 9A and 9B, the electronic component 10 is placed on the substrate 20 by the collet 200 and the collet 200 is lowered, so that each component is lowered. A solder 30 and a wall 13 on the electronic component side are interposed between the electrode 12 and the substrate electrode 21.

ここで、本実装方法では、電子部品１０の一面１０ａと基板２０の一面２０ａとを対向させるにあたって、電子部品１０の一面１０ａの端部に設けられた壁１３を開口部２４に挿入して電子部品１０の位置決めを行う。   Here, in this mounting method, when the one surface 10a of the electronic component 10 and the one surface 20a of the substrate 20 are opposed to each other, the wall 13 provided at the end portion of the one surface 10a of the electronic component 10 is inserted into the opening 24 to perform the electronic operation. The component 10 is positioned.

その後、この図９（ｂ）に示される状態でスクラブを行うことで、隣り合うはんだ３０同士の間に位置する部位に、電子部品側の壁１３を設けてなる電子部品の実装構造ができあがる。   Thereafter, scrubbing is performed in the state shown in FIG. 9B, thereby completing an electronic component mounting structure in which a wall 13 on the electronic component side is provided in a portion located between adjacent solders 30.

ここで、図９（ｂ）に示される例では、それぞれの部品電極１２と基板電極２１との間にはんだ３０を介在させた状態では、電子部品１０の一面１０ａから突出する電子部品側の壁１３の先端部が基板２０の一面２０ａに接触しているが、これらは互いに離れていてもよい。   Here, in the example shown in FIG. 9B, in the state where the solder 30 is interposed between each component electrode 12 and the substrate electrode 21, the wall on the electronic component side protruding from the one surface 10a of the electronic component 10 is provided. Although the tip portions of 13 are in contact with one surface 20a of the substrate 20, they may be separated from each other.

本実施形態によれば、スクラブによるはんだブリッジの発生を抑制できるとともに、電子部品１０の一面１０ａの端部に設けられた電子部品側の壁１３と基板２０側の開口部２４とのかみ合いにより、電子部品１０の位置決めが容易となる。つまり、開口部２４に電子部品１０の一面１０ａの端部に設けられた壁１３が嵌め込まれることで、電子部品１０と基板２０との位置ずれが防止される。   According to the present embodiment, the occurrence of solder bridges due to scrub can be suppressed, and the engagement between the wall 13 on the electronic component side provided at the end of the one surface 10a of the electronic component 10 and the opening 24 on the substrate 20 side allows The electronic component 10 can be easily positioned. In other words, the wall 13 provided at the end portion of the one surface 10a of the electronic component 10 is fitted into the opening 24, so that the positional deviation between the electronic component 10 and the substrate 20 is prevented.

なお、開口部２４は、電子部品１０の一面１０ａの外形と相似形状であって一回り大きな開口形状を有するものでなくてもよく、電子部品１０を基板２０に搭載したとき、上記した位置あわせの効果が得られるように、電子部品１０の一面１０ａの端部に設けられている電子部品側の壁１３が挿入され、かみ合わされる形状であればよい。   The opening 24 may be similar to the outer shape of the one surface 10a of the electronic component 10 and may not have a larger opening shape. When the electronic component 10 is mounted on the substrate 20, the above-described alignment is performed. The wall 13 on the electronic component side provided at the end portion of the one surface 10a of the electronic component 10 may be inserted and meshed so that the above effect can be obtained.

（第７実施形態）
図１０は、本発明の第７実施形態に係る電子部品１０の基板２０への実装方法を断面的に示す工程図である。 (Seventh embodiment)
FIG. 10 is a cross-sectional process diagram illustrating a method of mounting the electronic component 10 on the substrate 20 according to the seventh embodiment of the present invention.

本実施形態の実装方法は、上記第２実施形態の実装方法（上記図５参照）と同様に、それぞれの部品電極１２と基板電極２１との間にはんだ３０を介在させた状態では、隣り合うはんだ３０同士の間に位置する部位に、基板側の壁２２が設けられた状態とし、この状態でスクラブを行うものである。   Similar to the mounting method of the second embodiment (see FIG. 5), the mounting method of the present embodiment is adjacent in the state where the solder 30 is interposed between the component electrode 12 and the substrate electrode 21. Scrub is performed in a state where the substrate-side wall 22 is provided in a portion located between the solders 30.

ここで、本実施形態では、図１０に示されるように、基板２０として、基板２０の一面２０ａ側のうち電子部品１０と重なり合う部位に、電子部品１０の一面１０ａ側が挿入可能な開口部２５を形成したものを用意する。ここでは、開口部２５は、電子部品１０の一面１０ａの外形と相似形状であって一回り大きな開口形状を有するものである。   Here, in the present embodiment, as shown in FIG. 10, as the substrate 20, an opening 25 into which the one surface 10 a side of the electronic component 10 can be inserted is formed in a portion overlapping the electronic component 10 on the one surface 20 a side of the substrate 20. Prepare what you have formed. Here, the opening 25 has a shape similar to the outer shape of the one surface 10a of the electronic component 10 and has a slightly larger opening shape.

そして、本実施形態の実装方法では、図１０（ａ）、（ｂ）に示されるように、コレット２００によって電子部品１０を基板２０上に配置させ、コレット２００を下降させることにより、それぞれの部品電極１２と基板電極２１との間にはんだ３０および基板側の壁２２を介在させる。   In the mounting method of the present embodiment, as shown in FIGS. 10A and 10B, the electronic component 10 is placed on the substrate 20 by the collet 200 and the collet 200 is lowered, so that each component is lowered. A solder 30 and a substrate-side wall 22 are interposed between the electrode 12 and the substrate electrode 21.

ここで、本実装方法では、電子部品１０の一面１０ａと基板２０の一面２０ａとを対向させるにあたって、電子部品１０の一面１０ａ側を開口部２５に挿入して電子部品１０の位置決めを行う。   Here, in this mounting method, when the one surface 10a of the electronic component 10 and the one surface 20a of the substrate 20 are opposed to each other, the one surface 10a side of the electronic component 10 is inserted into the opening 25 and the electronic component 10 is positioned.

その後、この図１０（ｂ）に示される状態でスクラブを行うことで、隣り合うはんだ３０同士の間に位置する部位に、基板側の壁２２を設けてなる電子部品の実装構造ができあがる。   Thereafter, scrubbing is performed in the state shown in FIG. 10B, thereby completing an electronic component mounting structure in which a substrate-side wall 22 is provided in a portion located between adjacent solders 30.

ここで、図１０（ｂ）に示される例では、それぞれの部品電極１２と基板電極２１との間にはんだ３０を介在させた状態では、基板２０の一面２０ａから突出する基板側の壁２２の先端部が電子部品１０の一面１０ａに接触しているが、これらは互いに離れていてもよい。   Here, in the example shown in FIG. 10B, in the state where the solder 30 is interposed between each component electrode 12 and the substrate electrode 21, the board-side wall 22 that protrudes from the one surface 20 a of the substrate 20. Although the front-end | tip part is contacting the one surface 10a of the electronic component 10, these may mutually be separated.

本実施形態によれば、スクラブによるはんだブリッジの発生を抑制できるとともに、電子部品１０の外周端面とこの開口部２５とのかみ合いにより、電子部品１０の位置決めが容易となる。   According to the present embodiment, generation of solder bridges due to scrub can be suppressed, and positioning of the electronic component 10 is facilitated by the engagement between the outer peripheral end surface of the electronic component 10 and the opening 25.

この開口部２５は、電子部品１０の一面１０ａ側が挿入されて位置あわせができる形状ならばよく、電子部品１０の一面１０ａと相似形状でなくてもよい。   The opening 25 may be any shape that can be aligned by inserting the one surface 10 a side of the electronic component 10, and may not be similar to the one surface 10 a of the electronic component 10.

たとえば、電子部品１０の一面１０ａが矩形ならば、その４辺すべてでなく、そのうちの任意の２辺もしくは３辺が開口部２５の側面に当たって位置決めがなされたり、あるいは電子部品１０の一面１０ａの隅部のみが、開口部２５の側面に当たって位置決めがなされるような形状であってもよい。   For example, if the one surface 10a of the electronic component 10 is rectangular, positioning is performed by contacting any two or three sides of the electronic component 10 with the side surface of the opening 25, or the corner of the one surface 10a of the electronic component 10 The shape may be such that only the portion hits the side surface of the opening 25 and positioning is performed.

（他の実施形態）
なお、上記各実施形態では、はんだ３０の配設は、予め電子部品１０側に行っているが、電子部品１０側ではなく基板２０側であってもよい。この場合においても、はんだ３０は、例えば、はんだボール法、メッキ、印刷などの各種の方法により基板２０上に設けることができる。 (Other embodiments)
In each of the above embodiments, the solder 30 is disposed on the electronic component 10 side in advance, but it may be on the substrate 20 side instead of the electronic component 10 side. Also in this case, the solder 30 can be provided on the substrate 20 by various methods such as a solder ball method, plating, and printing.

さらには、はんだ３０は、予め電子部品１０と基板２０との両方に配置し、電子部品１０の一面１０ａと基板２０の一面２０ａとを対向させ、対向する両はんだ３０の先端部を接触させ、スクラブを行うようにしてもよい。この場合も、上記した壁１３、２２を設ければ同様の効果が発揮される。   Furthermore, the solder 30 is arranged in advance on both the electronic component 10 and the substrate 20, the one surface 10a of the electronic component 10 and the one surface 20a of the substrate 20 are opposed, and the tip portions of the two solders 30 facing each other are brought into contact with each other. Scrub may be performed. Also in this case, the same effect can be achieved by providing the walls 13 and 22 described above.

また、上記各実施形態において、はんだ接合を行った後に、電子部品１０と基板２０との間にアンダーフィルを充填し、電子部品１０と基板２０との接合強度を補強するようにしてもよい。   In each of the above embodiments, after soldering, an underfill may be filled between the electronic component 10 and the substrate 20 to reinforce the bonding strength between the electronic component 10 and the substrate 20.

また、コレット２００としては、はんだダイボンダに用いられるコレットとして、電子部品１０の保持、搭載、スクラブなどが可能なものであればよく、上記の各図に示される角錐形状のものに限定するものではない。   Further, the collet 200 may be any collet used for a solder die bonder as long as it can hold, mount, scrub, etc. the electronic component 10, and is not limited to the pyramid shape shown in each of the above drawings. Absent.

たとえば、コレットとしては、電子部品１０を吸引する部分の面が平坦面であり、この平坦面にコレットの開口部が開口したものであってもよい。また、スクラブの方向は、上記例に限定されるものではなく、はんだ接続が可能な方向において種々の方向を採ることが可能である。   For example, as a collet, the surface of the part which attracts | sucks the electronic component 10 may be a flat surface, and the opening part of the collet may open to this flat surface. Further, the direction of scrubbing is not limited to the above example, and it is possible to adopt various directions in the direction in which solder connection is possible.

また、電子部品１０としては、一面１０ａ側に複数個の部品電極１２が配置されているものであればよく、上記したＣＳＰ以外にも、例えばフリップチップやＱＦＮ（クワッドフラットノンリード）パッケージなどのモールドパッケージなどであってもよい。また、部品電極１２の配列形態は特に限定されるものではない。   Further, the electronic component 10 may be any component as long as a plurality of component electrodes 12 are arranged on the one surface 10a side. In addition to the above-described CSP, for example, a flip chip, a QFN (quad flat non-lead) package, or the like. It may be a mold package or the like. Further, the arrangement form of the component electrodes 12 is not particularly limited.

また、電子部品側の壁１３や基板側の壁２２の平面パターンは、上記図２に示されるものに限定されるものではなく、これらの壁１３、２２は、隣り合うはんだ３０同士の間に位置し当該両はんだ３０同士を遮断するように配置されていればよい。   Further, the plane pattern of the wall 13 on the electronic component side and the wall 22 on the board side is not limited to the one shown in FIG. 2, and these walls 13, 22 are located between adjacent solders 30. It suffices if it is positioned and arranged so as to block the solders 30 from each other.

このような電子部品側の壁１３の平面パターンの一変形例を、図１１（ａ）および（ｂ）に示す。なお、この図１１に示される例は、基板側の壁２２にも適用可能であることはもちろんである。   FIGS. 11A and 11B show a modification of the planar pattern of the wall 13 on the electronic component side. Of course, the example shown in FIG. 11 can also be applied to the wall 22 on the substrate side.

本発明の第１実施形態に係る電子部品の実装構造の概略断面図である。It is a schematic sectional drawing of the mounting structure of the electronic component which concerns on 1st Embodiment of this invention. 図１中の電子部品の一面側の部分的な平面図である。FIG. 2 is a partial plan view of one surface side of the electronic component in FIG. 1. 第１実施形態の実装方法を示す工程図である。It is process drawing which shows the mounting method of 1st Embodiment. 本発明の第２実施形態に係る電子部品の実装構造の概略断面図である。It is a schematic sectional drawing of the mounting structure of the electronic component which concerns on 2nd Embodiment of this invention. 第２実施形態の実装方法を示す工程図である。It is process drawing which shows the mounting method of 2nd Embodiment. 本発明の第３実施形態の実装方法を示す工程図である。It is process drawing which shows the mounting method of 3rd Embodiment of this invention. 本発明の第４実施形態の実装方法を示す工程図である。It is process drawing which shows the mounting method of 4th Embodiment of this invention. 本発明の第５実施形態の実装方法を示す工程図である。It is process drawing which shows the mounting method of 5th Embodiment of this invention. 本発明の第６実施形態の実装方法を示す工程図である。It is process drawing which shows the mounting method of 6th Embodiment of this invention. 本発明の第７実施形態の実装方法を示す工程図である。It is process drawing which shows the mounting method of 7th Embodiment of this invention. 電子部品側の壁の平面パターンの変形例を示す概略平面図である。It is a schematic plan view which shows the modification of the plane pattern of the wall by the side of an electronic component.

符号の説明Explanation of symbols

１０…電子部品、１０ａ…電子部品の一面、１２…部品電極、
１３…電子部品側の壁、２０…基板、２０ａ…基板の一面、２１…基板電極、
２２…基板側の壁、２３…緩衝部材、２４、２５…基板の一面側の開口部、
３０…はんだ。 DESCRIPTION OF SYMBOLS 10 ... Electronic component, 10a ... One side of electronic component, 12 ... Component electrode,
13 ... Wall on electronic component side, 20 ... Substrate, 20a ... One side of substrate, 21 ... Substrate electrode,
22 ... Wall on the substrate side, 23 ... Buffer member, 24, 25 ... Opening on one side of the substrate,
30: Solder.

Claims (8)

一面（１０ａ）側に複数個の部品電極（１２）が配置されている電子部品（１０）と、一面（２０ａ）側に前記電子部品（１０）の前記部品電極（１２）に対応して複数個の基板電極（２１）が配置されている基板（２０）とを用意し、
還元雰囲気にて、前記電子部品（１０）の一面（１０ａ）と前記基板（２０）の一面（２０ａ）とを対向させるとともに、それぞれの前記部品電極（１２）と前記基板電極（２１）との間に、はんだ（３０）を介在させた状態で、スクラブを行うことにより、前記両電極（１２、２１）間を前記はんだ（３０）によって接続するようにした電子部品の実装方法において、
前記それぞれの前記部品電極（１２）と前記基板電極（２１）との間に前記はんだ（３０）を介在させた状態では、前記電子部品（１０）の一面（１０ａ）のうち隣り合う前記はんだ（３０）同士の間に位置する部位に、前記電子部品（１０）の一面（１０ａ）から突出し当該両はんだ（３０）同士を遮断する壁（１３）が設けられた状態とし、この状態で前記スクラブを行うことを特徴とする電子部品の実装方法。 An electronic component (10) having a plurality of component electrodes (12) arranged on one side (10a) side, and a plurality corresponding to the component electrodes (12) of the electronic component (10) on one side (20a) side. A substrate (20) on which a plurality of substrate electrodes (21) are arranged,
In a reducing atmosphere, the one surface (10a) of the electronic component (10) and the one surface (20a) of the substrate (20) face each other, and the component electrode (12) and the substrate electrode (21) In the mounting method of the electronic component in which the electrodes (12, 21) are connected by the solder (30) by scrubbing with the solder (30) interposed therebetween,
In a state where the solder (30) is interposed between the component electrodes (12) and the substrate electrode (21), the adjacent solder (1a) (10a) on the one surface (10a) of the electronic component (10). 30) It is assumed that a wall (13) that protrudes from one surface (10a) of the electronic component (10) and that blocks the solders (30) is provided in a portion located between the scrubbing members. A method for mounting an electronic component, comprising: 前記それぞれの前記部品電極（１２）と前記基板電極（２１）との間に前記はんだ（３０）を介在させた状態では、前記電子部品（１０）の一面（１０ａ）から突出する前記壁（１３）の先端部が前記基板（２０）の一面（２０ａ）に接触した状態となるものであることを特徴とする請求項１に記載の電子部品の実装方法。 In a state where the solder (30) is interposed between each of the component electrodes (12) and the substrate electrode (21), the wall (13) protruding from one surface (10a) of the electronic component (10). 2. The electronic component mounting method according to claim 1, wherein a tip end portion of the first substrate is in contact with one surface (20 a) of the substrate (20). 前記壁（１３）は、さらに前記電子部品（１０）の一面（１０ａ）の端部にも設けられるものであり、
前記基板（２０）の一面（２０ａ）側に開口部（２４）を形成した後、
前記電子部品（１０）の一面（１０ａ）と前記基板（２０）の一面（２０ａ）とを対向させるにあたって、前記電子部品（１０）の一面（１０ａ）の端部に設けられた前記壁（１３）を前記開口部（２４）に挿入して前記電子部品（１０）の位置決めを行うようにしたことを特徴とする請求項１または２に記載の電子部品の実装方法。 The wall (13) is also provided at an end of one surface (10a) of the electronic component (10),
After forming the opening (24) on the one surface (20a) side of the substrate (20),
When the one surface (10a) of the electronic component (10) and the one surface (20a) of the substrate (20) are opposed to each other, the wall (13) provided at the end of the one surface (10a) of the electronic component (10). The electronic component mounting method according to claim 1 or 2, wherein the electronic component (10) is positioned by being inserted into the opening (24). 一面（１０ａ）側に複数個の部品電極（１２）が配置されている電子部品（１０）と、一面（２０ａ）側に前記電子部品（１０）の前記部品電極（１２）に対応して複数個の基板電極（２１）が配置されている基板（２０）とを用意し、
還元雰囲気にて、前記電子部品（１０）の一面（１０ａ）と前記基板（２０）の一面（２０ａ）とを対向させるとともに、それぞれの前記部品電極（１２）と前記基板電極（２１）との間に、はんだ（３０）を介在させた状態で、スクラブを行うことにより、前記両電極（１２、２１）間を前記はんだ（３０）によって接続するようにした電子部品の実装方法において、
前記それぞれの前記部品電極（１２）と前記基板電極（２１）との間に前記はんだ（３０）を介在させた状態では、前記基板（２０）の一面（２０ａ）のうち隣り合う前記はんだ（３０）同士の間に位置する部位に、前記基板（２０）の一面（２０ａ）から突出し当該両はんだ（３０）同士を遮断する壁（２２）が設けられた状態とし、この状態で前記スクラブを行うことを特徴とする電子部品の実装方法。 An electronic component (10) having a plurality of component electrodes (12) arranged on one side (10a) side, and a plurality corresponding to the component electrodes (12) of the electronic component (10) on one side (20a) side. A substrate (20) on which a plurality of substrate electrodes (21) are arranged,
In a reducing atmosphere, the one surface (10a) of the electronic component (10) and the one surface (20a) of the substrate (20) face each other, and the component electrode (12) and the substrate electrode (21) In the mounting method of the electronic component in which the electrodes (12, 21) are connected by the solder (30) by scrubbing with the solder (30) interposed therebetween,
In the state where the solder (30) is interposed between the component electrodes (12) and the substrate electrode (21), the adjacent solder (30) on one surface (20a) of the substrate (20). ) In a state where the wall (22) protruding from one surface (20a) of the substrate (20) and blocking the solders (30) is provided at a position located between them, and the scrub is performed in this state An electronic component mounting method characterized by the above. 前記それぞれの前記部品電極（１２）と前記基板電極（２１）との間に前記はんだ（３０）を介在させた状態では、前記基板（２０）の一面（２０ａ）から突出する前記壁（２２）の先端部が前記電子部品（１０）の一面（１０ａ）に接触した状態となるものであることを特徴とする請求項４に記載の電子部品の実装方法。 In the state where the solder (30) is interposed between the component electrode (12) and the substrate electrode (21), the wall (22) protruding from one surface (20a) of the substrate (20). The electronic component mounting method according to claim 4, wherein the tip end portion of the electronic component is in contact with one surface (10 a) of the electronic component (10). 前記壁（２２）の先端部と前記電子部品（１０）の一面（１０ａ）との間には、これら両者の接触による前記電子部品（１０）のダメージを軽減する緩衝部材（２３）を介在させることを特徴とする請求項５に記載の電子部品の実装方法。 A buffer member (23) that reduces damage to the electronic component (10) due to the contact between the tip of the wall (22) and one surface (10a) of the electronic component (10) is interposed. The electronic component mounting method according to claim 5, wherein: 前記基板（２０）の一面（１０ａ）側のうち前記電子部品（１０）と重なり合う部位に、前記電子部品（１０）の一面（１０ａ）側が挿入可能な開口部（２５）を形成した後、
前記電子部品（１０）の一面（１０ａ）と前記基板（２０）の一面（２０ａ）とを対向させるにあたって、前記電子部品（１０）の一面（１０ａ）側を前記開口部（２５）に挿入して前記電子部品（１０）の位置決めを行うようにしたことを特徴とする請求項４ないし６のいずれか１つに記載の電子部品の実装方法。 After forming the opening (25) into which the one surface (10a) side of the electronic component (10) can be inserted in the portion overlapping the electronic component (10) on the one surface (10a) side of the substrate (20),
When the one surface (10a) of the electronic component (10) and the one surface (20a) of the substrate (20) are opposed, the one surface (10a) side of the electronic component (10) is inserted into the opening (25). The electronic component mounting method according to claim 4, wherein the electronic component is positioned. 一面（１０ａ）側に複数個の部品電極（１２）が配置されている電子部品（１０）と、
一面（２０ａ）側に前記電子部品（１０）の前記部品電極（１２）に対応して複数個の基板電極（２１）が配置されている基板（２０）とを備え、
前記電子部品（１０）の一面（１０ａ）と前記基板（２０）の一面（２０ａ）とが対向して配置され、
それぞれの前記部品電極（１２）と前記基板電極（２１）との間が、はんだ（３０）を介して接続されている電子部品の実装構造において、
前記隣り合う前記はんだ（３０）同士の間に位置する部位には、前記電子部品（１０）の一面（１０ａ）または前記基板（２０）の一面（２０ａ）から突出し当該両はんだ（３０）同士を遮断する壁（１３、２２）が設けられていることを特徴とする電子部品の実装構造。 An electronic component (10) in which a plurality of component electrodes (12) are arranged on one side (10a);
A substrate (20) on which a plurality of substrate electrodes (21) are arranged corresponding to the component electrodes (12) of the electronic component (10) on one surface (20a) side;
One surface (10a) of the electronic component (10) and one surface (20a) of the substrate (20) are arranged to face each other,
In the mounting structure of the electronic component in which the component electrode (12) and the substrate electrode (21) are connected via the solder (30),
The part located between the adjacent solders (30) protrudes from one surface (10a) of the electronic component (10) or one surface (20a) of the substrate (20), and the solders (30) are connected to each other. A mounting structure for an electronic component, characterized in that a blocking wall (13, 22) is provided.
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