1333405 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種防焊層開口方法’尤指高對準度的防焊層 開口方法。 【先前技術】 覆晶（Flip Chip)封裝的型式可分為FCIp(FUp Chip化1333405 IX. Description of the Invention: [Technical Field] The present invention relates to a method of opening a solder resist layer, particularly a method of opening a solder resist layer with high alignment. [Prior Art] The type of Flip Chip package can be divided into FCIp (FUp Chipization).
Package)與FC0B(Flip Chip on Board)二種。這其中，FCIp 需搭 配如職、csp等封裝型式，且利用覆晶作為晶粒與基板的接;^ 術’藉著覆晶技術具有更高I/O密度的特性，將可滿足未來高階 產品在高⑽_需求。_财直接將晶粒接合於印刷電路板 (Printed Circuit Board ; PCB)上，為一種直接晶片接合(DirectPackage) and FC0B (Flip Chip on Board). Among them, FCIp needs to be matched with the package type such as job, csp, etc., and uses flip chip as the connection between the die and the substrate; ^'s technology with higher I/O density by flip chip technology will meet future high-end products. At high (10) _ demand. _ _ _ directly bonded to the printed circuit board (PCB), for a direct wafer bonding (Direct
Chip Attachment ; DCA)的技術，主要使用於較低1/〇的應用產品 上。若覆晶技術應·液晶顯示H上時，由於基板是玻璃，也被 稱為 C0G(Chip 〇n Glass>。 未來的SMT趨勢中，FC0B ( Flip Chip 〇n B〇ard)料及組裝 成本、縮短電路傳輸路徑，達更高、更密、更小、更全的電子產 品需求成為開發方向。由於PCB需要因應直接封裝需求故在焊塾 間距及尺寸上需因應1/〇增加而縮小形成pCB傳統製作技術尚需 突破之瓶頸。 1333405 2 PCB而言，隨著烊塾間距縮小，導致阻制開口縮小，進 吏得對位此力需求提高，這將直接影響到卿設計及製程能力。 比般PCB防谭製作能力在間距0· π咖時防焊對位及阻焊劑開口 皆已達到上限，而間距G· 2麵時不管，smd(s餘職k祕㈣ 喻觸紅__繼，峨技術或 έ門、=求。為此，本發明主要是在提出防焊製射應用於微 、，，田間距需求下所需的精麟位製作方式。 【發明内容】 主幻發j之主要目的在提供—種高對準度的防焊層開口方法， 顏用雷射來進行高解朗口辦，以避免後續上錫球時產 生問題。 树明高對準度的防焊層開口方法，針對複數個焊塾之間的 =、於〇· 25mm _焊怖絲，刪謝錄高的雷 ==焊層上形成相對的防焊開口，而非採用精確性較差的曝 走•顯影技術。複數個焊塾e 執铷甘α 破元成在印刷電路板上，且複數個烊 〇基板上已完成防烊製程，而覆蓋有防焊層。 關於本發明之優點與精神 式得到進一步的瞭解。藉由以下的發明詳述及所附圖 6 1333405 【實施方式】 請參閱第1A〜ID圖’第1A〜ID圖為本發明高對準度的防焊層 開口方法之示意圖。如第1A〜1D圖所示’左側為電路板剖面圖， 而右側為電路板俯視圖。 如第1A圖所示’按照一般線路製作方法，圖案化在基板 上的一層金屬層，而形成複數個焊墊12a〜12b、1½〜14b(pad)。這 其中’焊墊12a〜12b之間的間距小於0. 25mm，而焊墊i4a〜14b之 間的間距則大於〇· 25mm。須特別注意的是，焊墊丨2a〜丨2b、丨私〜1牝 的形成方法不盡然必須圖案化一層金屬層，亦可利用選擇性電鍍 來形成。 為了保護焊墊12a〜12b、14a~14b，先在焊墊UaWb'Ma〜14b 進行防焊製程，亦即先在印刷電路板上的複數個焊墊12a~12b、 14a〜14b之上，覆蓋有防焊層16，如第比圖所示。此時，焊墊 12a〜12b、14a〜14b已暫時完全被防焊層16遮蔽住。 為了焊墊12a〜12b、14a〜14b能與其他電子元件或電路板有電 性連接職，焊墊12a〜12b、14a〜14b的正面至少必須被曝露出來。 由於焊塾⑷〜恤之間的間距則大於G 25mm，可輕易地利用現有 曝光顯影技術來形成防焊開口 18a，如第1G圖所示。 對於焊塾12a〜12b之間的間距小於〇. 25咖，則對著複數個焊 12a 12b ’利用雷射在防谭層16上形成相對的防焊開口⑽， 如第1D圖所示。 7 1333405 如此一來’當需要電性連接其他電子元件或電路板時，在埴 入錫球至防焊開口 18b時，就能順利地接觸到焊塾他〜既的表 面，而避免上錫球時產生問題。 捕別注意的是，如第職所示之製程步驟，可選擇在⑺ 圖所示之製程步驟之後才實行。 藉㈣上較佳具體實關之詳述，鱗望能更加清楚描述本 X明之特徵與精神’而並非以上述所揭露的較佳具體實施例來對 本發明之鱗純關。相反地，其目岐希望能涵蓋各種改變 及具相等性的安排於本發騎欲中請之專利顧的範缚内。 【圖式簡單說明】 第1A〜ID B林發明高解度的轉層開口方法之示意圖 【主要元件符號說明】Chip Attachment; DCA) technology is mainly used in lower 1/〇 applications. If the flip chip technology should be on the liquid crystal display H, since the substrate is glass, it is also called C0G (Chip 〇n Glass). In the future SMT trend, FC0B (Flip Chip 〇n B〇ard) material and assembly cost, shortened The circuit transmission path, the demand for higher, denser, smaller and more complete electronic products has become the development direction. Since the PCB needs to meet the direct packaging requirements, the pitch and the size of the soldering are required to be reduced to form a pCB tradition. The manufacturing technology still needs to break through the bottleneck. 1333405 2 PCB, as the spacing of the crucible is reduced, the resistance opening is reduced, and the demand for this force is improved, which will directly affect the design and process capability of the company. PCB anti-tanting ability has reached the upper limit of the anti-welding alignment and the solder resist opening at the interval of 0· π coffee, and the gap is not the same as the G·2 surface, smd(s remaining ko secret (four) 触 触 _ _ _ 继For this reason, the present invention mainly proposes a fine-lining production method required for the application of solder-proof welding to micro, and field spacing requirements. [Summary of the Invention] The purpose is to provide a high-alignment anti-welding The opening method, the use of laser to carry out the high solution Langkou to avoid problems after the subsequent soldering ball. Shuming high-alignment solder mask opening method, for the multiple soldering = =, 〇 · 25mm _ welding wire, acknowledgment of the height of the mine = = the formation of the opposite solder joints on the solder layer, rather than the use of less accurate exposure and development technology. Multiple soldering e The anti-mite process has been completed on the circuit board and on a plurality of germanium substrates, and is covered with a solder resist layer. Further advantages and spirits of the present invention are further understood. The following detailed description of the invention and FIG. 6 1333405 [Embodiment] Please refer to FIG. 1A to IDA. FIG. 1A to IDD are schematic diagrams showing a high-alignment solder mask opening method according to the present invention. As shown in FIGS. 1A to 1D, the left side is a circuit board sectional view, and The right side is a top view of the circuit board. As shown in Fig. 1A, a metal layer on the substrate is patterned according to the general circuit fabrication method, and a plurality of pads 12a to 12b, 11⁄2 to 14b (pad) are formed. The gap between the pads 12a to 12b is less than 0. 25mm, and the soldering The spacing between the pads i4a to 14b is greater than 〇·25mm. It is important to note that the method of forming the pads a2a~丨2b and 丨1~1牝 does not necessarily have to be patterned with a metal layer, and selective plating is also possible. In order to protect the pads 12a~12b, 14a~14b, a solder resist process is first performed on the pads UaWb'Ma~14b, that is, a plurality of pads 12a-12b, 14a~14b on the printed circuit board. The solder resist layer 16 is covered, as shown in the figure. At this time, the pads 12a to 12b, 14a to 14b are temporarily completely shielded by the solder resist layer 16. In order for the pads 12a to 12b, 14a to 14b to be electrically connected to other electronic components or boards, the front faces of the pads 12a to 12b, 14a to 14b must be exposed at least. Since the pitch between the solder fillets (4) and the shirt is larger than G 25 mm, the existing solder resist opening 18a can be easily formed by the conventional exposure developing technique as shown in Fig. 1G. For the spacing between the solder fillets 12a to 12b being less than 〇. 25, the opposite solder resist openings (10) are formed on the anti-tank layer 16 against the plurality of solders 12a 12b', as shown in Fig. 1D. 7 1333405 In this way, when it is necessary to electrically connect other electronic components or boards, when the solder ball is inserted into the solder resist opening 18b, the surface of the solder bump can be smoothly contacted, and the solder ball is avoided. There was a problem. It is important to note that the process steps shown in the first job can be carried out after the process steps shown in (7). By way of a detailed description of the preferred embodiments, it is understood that the features and spirit of the present invention are more clearly described and the preferred embodiment of the invention is not to be construed as a limitation. On the contrary, it is intended to cover all kinds of changes and equivalence arrangements within the scope of the patent application of this issue. [Simple diagram of the diagram] 1A ~ ID B Lin invented a schematic diagram of the high-resolution transition opening method [Major component symbol description]
10基板 12a〜12b、14a〜14b 焊塾 16防焊層 18a、18b防焊開口10 substrates 12a~12b, 14a~14b solder 塾 16 solder mask 18a, 18b solder mask opening