JP2007266025A - Chip package structure - Google Patents

Chip package structure Download PDF

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JP2007266025A
JP2007266025A JP2006084870A JP2006084870A JP2007266025A JP 2007266025 A JP2007266025 A JP 2007266025A JP 2006084870 A JP2006084870 A JP 2006084870A JP 2006084870 A JP2006084870 A JP 2006084870A JP 2007266025 A JP2007266025 A JP 2007266025A
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chip package
package structure
groove
thin film
metal core
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Hinka Shu
品華 朱
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Walton Advanced Engineering Inc
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Walton Advanced Engineering Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip package that has improved heat radiation properties, and can reduce costs and thickness and improve heat-resistant stress. <P>SOLUTION: The chip package comprises: a thin-film substrate 210 that has a groove 211, and comprises a pattern metal core layer 212 and surface dielectric layers 215, 216, where a plurality of internal fingers 213 and a plurality of pads 214 for circumscription are formed on the pattern metal core layer 212, and the internal finger 213 is arranged at the periphery of the groove 211; a chip 220 for forming a plurality of electrode edges 223 on an active surface 221, and adhering the active surface 221 to the thin-film substrate 210 when the electrode edges 223 are arranged toward the inside of the groove 211; a plurality of bonding wires 230 that are passed through the groove 211 and connect the electrode edge 223 and the internal finger 213 electrically; and a sealing body 240 that is formed on the thin-film substrate 210 and in the groove 211, and seals the chip 220 and the bonding wire 230. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は一種のチップパッケージ、特にＣＯＢ（Chip-On-Board）形態のチップパッケージに関するものである。   The present invention relates to a kind of chip package, in particular, a chip package in a COB (Chip-On-Board) form.

現在、ＣＯＢ（Chip-On-Board）パッケージは、集積回路パッケージにおいて従来良く知られ、主に（１）チップを直接溝を持つ基板上に粘着させ、（２）ボンディングワイヤーを溝に通して基板とチップを電気的に接続させ、（３）チップを封止する、というプロセスを含む。特に、その上にソルダボール（solder ball）を形成してボールグリッドアレイパッケージ（BGA Package）となる。近来、メモリチップパッケージは、ＣＯＢ（Chip-On-Board）の形態に進展しており、従来公知の薄型かつ小型のＴＳＯＰ（Thin Small Outline Package）の代わりにＣＯＢがよく使われて、しかもより高速化にできない課題を解決することも可能となる。   Currently, COB (Chip-On-Board) packages are well known in integrated circuit packages. Mainly, (1) chips are directly adhered onto a substrate having a groove, and (2) a bonding wire is passed through the substrate. And (3) a process of sealing the chip. In particular, a solder ball is formed thereon to form a ball grid array package (BGA Package). Recently, memory chip packages have progressed to the form of COB (Chip-On-Board), COB is often used instead of the conventionally known thin and small TSOP (Thin Small Outline Package), and higher speed. It is also possible to solve problems that cannot be realized.

図１に示すように、ＣＯＢ型のチップパッケージ構造１００は、基本的に硬質基板１１０、チップ１２０、複数個のボンディングワイヤー１３０、及び封止体１４０を備える。硬質基板１１０は、上表面１１１、下表面１１２、及び溝１１３を有し、溝１１３は上表面１１１と下表面１１２とを貫通するのでボンディングワイヤーを通過させることができる。通常、硬質基板１１０は、単／多層ＰＣＢ（Print Circuit Board）であり、少なくとも一層のガラス繊維含浸樹脂コア層１１４、内部フィンガー１１５、及び外接用パッド１１６を備える銅箔層、及びソルダマスク層１１７（solder mask）で構成されてかなり厚いものであり、耐熱応力特性が劣って熱抵抗も高すぎる。チップ１２０は、能動面１２１及び能動面１２１と反対側にある背面１２２を有し、能動面１２１上に複数個のボンディングパッド（bonding pad）１２３が形成される。ダイアタッチ層１２４（die attach layer）を介してチップ１２０の能動面１２１を硬質基板１１０の上表面１１１に粘着させる。ボンディングパッド１２３は溝１１３の内部に設置させており、ボンディングワイヤー１３０は溝１１３を通してボンディングパッド１２３と内部フィンガー１１５とを接続している。更に、封止体１４０は硬質基板１１０の上表面１１１及び溝１１３内に形成され、チップ１２０とボンディングワイヤー１３０とを封止する。なお、外接用パッド１１６上に複数個のソルダボールを形成することができる。従って、周知のチップパッケージ構造１００においての厚み、放熱性、及び熱応力緩衝特性は不具合となり、改善される必要がある。これに対し、ＣＯＢからなる改良で上記硬質基板１１０の代わりにＰＩ（Polyimide）材料で出来る可撓性のある基板を使うと、基板としてのコストは大幅に増加し、かつＰＩ材料の導熱性が劣るのでチップパッケージ構造全体にとって優れる放熱効果を得ることができない。
また、発明者は、特許文献１開示されるマルチーボードＢＧＡパッケージ（Multi-Board BGA Package）を提出する時に、一種のＣＯＢ（Chip-On-Board）形態のチップパッケージも開示した。 As shown in FIG. 1, the COB type chip package structure 100 basically includes a hard substrate 110, a chip 120, a plurality of bonding wires 130, and a sealing body 140. The hard substrate 110 has an upper surface 111, a lower surface 112, and a groove 113. Since the groove 113 penetrates the upper surface 111 and the lower surface 112, a bonding wire can pass therethrough. Usually, the hard substrate 110 is a single / multi-layer PCB (Print Circuit Board), a copper foil layer including at least one glass fiber impregnated resin core layer 114, internal fingers 115, and external pads 116, and a solder mask layer 117 ( It is composed of a solder mask) and is quite thick, with poor thermal stress characteristics and too high thermal resistance. The chip 120 has an active surface 121 and a back surface 122 opposite to the active surface 121, and a plurality of bonding pads 123 are formed on the active surface 121. The active surface 121 of the chip 120 is adhered to the upper surface 111 of the hard substrate 110 through a die attach layer 124. The bonding pad 123 is installed inside the groove 113, and the bonding wire 130 connects the bonding pad 123 and the internal finger 115 through the groove 113. Further, the sealing body 140 is formed in the upper surface 111 and the groove 113 of the hard substrate 110 and seals the chip 120 and the bonding wire 130. A plurality of solder balls can be formed on the circumscribed pad 116. Accordingly, the thickness, heat dissipation, and thermal stress buffering characteristics in the known chip package structure 100 are defective and need to be improved. On the other hand, if a flexible substrate made of PI (Polyimide) material is used instead of the hard substrate 110 due to the improvement made of COB, the cost as the substrate is greatly increased and the heat conductivity of the PI material is increased. Since it is inferior, the heat dissipation effect which is excellent for the whole chip package structure cannot be obtained.
The inventor also disclosed a kind of chip package of COB (Chip-On-Board) when submitting a multi-board BGA package disclosed in Patent Document 1.

台湾特許第４９８５１１号Taiwan Patent No. 498511

本発明の第一目的は一種のチップパッケージを提供する。このチップパッケージはＣＯＢ形態パッケージであり、まず、溝を有する薄膜基板或は複数個共面の間に形成されるワイヤーボンディング溝を有する薄膜基板を準備し、チップ能動面を直接に薄膜基板上に接着させる。この薄膜基板はパターン金属コア層と少なくとも一つの表面誘電体層で構成され、複数個の内部フィンガーと複数個の外接用パッドを有することにより、チップにとって優れた放熱ルートがある。他に、基板コストの低下、パッケージ全体厚みの低減、及び耐熱応力の向上などを得ることも可能となる。   The first object of the present invention is to provide a kind of chip package. This chip package is a COB type package. First, a thin film substrate having a groove or a thin film substrate having a wire bonding groove formed between a plurality of coplanar surfaces is prepared, and the chip active surface is directly on the thin film substrate. Adhere. This thin film substrate is composed of a patterned metal core layer and at least one surface dielectric layer, and has a plurality of internal fingers and a plurality of external pads, thereby providing an excellent heat dissipation route for the chip. In addition, it is possible to reduce the substrate cost, reduce the overall thickness of the package, and improve the heat stress.

本発明の第二目的は一種のチップパッケージを提供する。このチップパッケージ中では、薄膜基板のパターン金属コア層は複数個の連結バーを有し、これらの連結バーは、外接用パッドと薄膜基板の周縁、内部フィンガーと溝の周縁、或は両者とも連結させることによって、内部フィンガーと外接用パッドを電気メッキすることが可能となり、かつ内部フィンガーと外接用パッドの連結力が増強されるので、接触不良による電気ショットを未然に回避できる。
本発明の第三目的は一種のチップパッケージを提供する。このチップパッケージ中では、パターン金属コア層の外接用パッドは不規則に拡散するよう配置され、かつ表面誘電体層の開孔は円形の排列であるので、放熱能力が向上され、さらに、その上にソルダボール（solder ball）を形成してＢＧＡパッケージになることも可能である。 The second object of the present invention is to provide a kind of chip package. In this chip package, the patterned metal core layer of the thin film substrate has a plurality of connecting bars, and these connecting bars connect the peripheral pad and the peripheral edge of the thin film substrate, the internal finger and the peripheral edge of the groove, or both. By doing so, it becomes possible to electroplate the internal finger and the external pad, and since the connecting force between the internal finger and the external pad is enhanced, an electrical shot due to poor contact can be avoided in advance.
The third object of the present invention is to provide a kind of chip package. In this chip package, the circumscribed pads of the patterned metal core layer are arranged so as to diffuse irregularly, and the openings in the surface dielectric layer are arranged in a circular manner, so that the heat dissipation capability is improved, and further, It is also possible to form a solder ball to form a BGA package.

上記目的を達成するためのチップパッケージは、少なくとも一つの薄膜基板、チップ、複数個のボンディングワイヤー、及び封止体を備える。薄膜基板は、溝或はワイヤーボンディング溝を有し、パターン金属コア層と少なくとも一つの表面誘電体層で構成される。パターン金属コア層に複数個の内部フィンガーと複数個の外接用パッドが形成され、内部フィンガーが溝の周辺に配置される。チップの能動面上にも複数個の電極端が形成される。溝内に向かって複数個の電極端が配置される際に、能動面を薄膜基板に粘着させる。よって、ボンディングワイヤーは溝を通されて電気的に電極端と内部フィンガーとを接続することができる。尚、封止体は薄膜基板上と溝内とに形成され、少なくとも部分的にチップ及びボンディングワイヤーを封止する。   A chip package for achieving the above object includes at least one thin film substrate, a chip, a plurality of bonding wires, and a sealing body. The thin film substrate has a groove or a wire bonding groove, and is composed of a patterned metal core layer and at least one surface dielectric layer. A plurality of internal fingers and a plurality of circumscribed pads are formed on the patterned metal core layer, and the internal fingers are disposed around the groove. A plurality of electrode ends are also formed on the active surface of the chip. When a plurality of electrode ends are arranged in the groove, the active surface is adhered to the thin film substrate. Therefore, the bonding wire can be passed through the groove to electrically connect the electrode end and the internal finger. The sealing body is formed on the thin film substrate and in the groove, and at least partially seals the chip and the bonding wire.

本発明の第一実施例では、溝型金属薄膜上にワイヤーボンディングチップを搭載するパッケージを披露する。図２に示すように、チップパッケージ２００は基本的に薄膜基板２１０、チップ２２０、複数個のボンディングワイヤー２３０、及び封止体２４０を備える。薄膜基板２１０は、パターン金属コア層２１２と少なくとも一つの表面誘電体層で構成され、細長い溝２１１を有し、この溝２１１は薄膜基板２１０の上下表面を貫通する。パターン金属コア層２１２は、複数個の内部フィンガー２１３と複数個の外接用パッド２１４とを有し、内部フィンガー２１３は溝２１１の周辺に配置され、外接用パッド２１４は方陣状或は双／多直線で排列されることができる。内部フィンガー２１３と対応の外接用パッド２１４とはパターン金属コア層２１２の電気導通バー２１２Ａ（図４参照）を介して電気的に接続される。本実施例において、パターン金属コア層２１２は、一般のフレキシブルプリント回路基板に使う銅箔厚み（約３５μｍ）より厚くなり、６０μｍから１００μｍの厚みを持ち、薄膜基板２１０にして適当な硬度となり、且つ電気的な接続及び放熱ルートをも提供しているので、同時に周知のフレキシブルプリント回路基板に使うＰＩ誘電体コア層及び銅箔配線層の代わりに使用され、より高放熱効果、より薄型化、かつより低コスト等が望まれる。ほかに、薄膜基板２１０の表面誘電体層は、二層にすることができ、第一表面誘電体層２１５と第二表面誘電体層２１６を有し、この二層の間にパターン金属コア層２１２が挟まる。第一表面誘電体層２１５及び第二表面誘電体層２１６は一般的なグリーンソルダマスク（green solder mask）かブラックソルダマスク（black solder mask）を選んで使うこととなる。一方、第一表面誘電体層２１５はパターン化される必要があり、外接用パッド２１４及び内部フィンガー２１３を露出するため、複数個の開孔２１７または溝孔（図４に示すように、溝孔は溝２１１を形成する所定位置の両側にある）の少なくともいずれかを形成し、第二表面誘電体層２１６ではパターン化される必要がない。第一表面誘電体層２１５の材質はできるだけ感光性誘電材料、たとえば、グリーンソルダマスク（green solder mask）を選んで、第二表面誘電体層２１６では一般な無感光性誘電材料、たとえば、ブラックソルダマスク（black solder mask）を使用するだけでよい。   In the first embodiment of the present invention, a package in which a wire bonding chip is mounted on a grooved metal thin film will be shown. As shown in FIG. 2, the chip package 200 basically includes a thin film substrate 210, a chip 220, a plurality of bonding wires 230, and a sealing body 240. The thin film substrate 210 includes a patterned metal core layer 212 and at least one surface dielectric layer, and has an elongated groove 211, which penetrates the upper and lower surfaces of the thin film substrate 210. The patterned metal core layer 212 includes a plurality of internal fingers 213 and a plurality of circumscribed pads 214, and the inner fingers 213 are disposed around the groove 211, and the circumscribed pads 214 are square or double / multiple. Can be arranged in a straight line. The internal fingers 213 and the corresponding external pads 214 are electrically connected via the electric conduction bar 212A (see FIG. 4) of the pattern metal core layer 212. In this embodiment, the patterned metal core layer 212 is thicker than the copper foil thickness (about 35 μm) used for a general flexible printed circuit board, has a thickness of 60 μm to 100 μm, has a suitable hardness for the thin film substrate 210, and Since it also provides electrical connection and heat dissipation route, it is used in place of the PI dielectric core layer and copper foil wiring layer used in the well-known flexible printed circuit board at the same time, higher heat dissipation effect, thinner, and Lower cost is desired. In addition, the surface dielectric layer of the thin film substrate 210 can be made into two layers, and has a first surface dielectric layer 215 and a second surface dielectric layer 216, and a patterned metal core layer between the two layers. 212 is caught. For the first surface dielectric layer 215 and the second surface dielectric layer 216, a general green solder mask or black solder mask is selected and used. On the other hand, the first surface dielectric layer 215 needs to be patterned, and a plurality of apertures 217 or slots (as shown in FIG. 4) are exposed to expose the circumscribing pads 214 and the internal fingers 213. At least one of the predetermined positions where the groove 211 is formed), and the second surface dielectric layer 216 does not need to be patterned. As the material of the first surface dielectric layer 215, a photosensitive dielectric material, for example, a green solder mask is selected as much as possible. In the second surface dielectric layer 216, a general non-photosensitive dielectric material, for example, black solder is used. You only need to use a black solder mask.

チップ２２０には、能動面２２１及び能動面２２１と対応する一背面２２２を有し、運算時に発熱する集積回路素子は能動面２２１の上に設置される。能動面２２１上に複数個の電極端２２３、たとえば、ボンディングパッド（bonding pad）或はバンプ（bump）が形成され、それらの電極端２２３は能動面２２１の中央か周辺に位置して単列か多列で配置される。溝内に向かって複数個電極端が配置される際に、ダイアタッチ層２２４（die attach layer）を介して能動面を薄膜基板に粘着させ、ボンディングワイヤー２３０が溝２１１を通過することができるので電気的に電極端２２３と内部フィンガー２１３とが接続される。他に、薄膜基板２１０上と溝２１１内に封止体２４０が形成され、少なくとも一部でチップ２２０とボンディングワイヤー２３０とを封止する。一部でチップ２２０の側面を覆うか或は完全にチップ２２０を密封する封止体２４０はモールド樹脂（mold compound）、下部充填材料（underfill material）、或はディスペンス樹脂（dispense compound）などを使うことができる。チップパッケージ２００の構造によれば、更に複数個のソルダボール（solder ball）２５０を具備することができ、それらのソルダボール（solder ball）２５０が外接用パッド２１４上に設置されることによって、ＣＯＢとＢＧＡとを兼ねるパッケージとなる。   The chip 220 has an active surface 221 and a back surface 222 corresponding to the active surface 221, and an integrated circuit element that generates heat during operation is installed on the active surface 221. A plurality of electrode ends 223, for example, bonding pads or bumps, are formed on the active surface 221, and the electrode ends 223 are located in the center or the periphery of the active surface 221 and are in a single row. Arranged in multiple rows. When a plurality of electrode ends are disposed in the groove, the active surface is adhered to the thin film substrate via the die attach layer 224, and the bonding wire 230 can pass through the groove 211. The electrode end 223 and the internal finger 213 are electrically connected. In addition, a sealing body 240 is formed on the thin film substrate 210 and in the groove 211 to seal the chip 220 and the bonding wire 230 at least partially. The sealing body 240 that partially covers the side surface of the chip 220 or completely seals the chip 220 uses a mold compound, an underfill material, or a dispense compound. be able to. According to the structure of the chip package 200, a plurality of solder balls 250 can be further provided, and the solder balls 250 are installed on the external pad 214, so that the COB can be provided. And BGA package.

このチップパッケージ２００の構造により、パターン金属コア層２１２がチップ２２０の能動面２２１にとても接近して、チップ２２０の能動面２２１から出る熱は自然にパターン金属コア層２１２に沿って発散され、よって、ＣＯＢ薄膜パッケージとしての放熱効果が著しく改善される。他に、基板コストの削減、パッケージ全体厚みの減少、及び耐熱応力の向上などの効果を得ることも可能である。   Due to the structure of the chip package 200, the patterned metal core layer 212 is very close to the active surface 221 of the chip 220, and the heat emitted from the active surface 221 of the chip 220 is naturally dissipated along the patterned metal core layer 212. The heat dissipation effect as a COB thin film package is remarkably improved. In addition, it is possible to obtain effects such as reduction in substrate cost, reduction in the overall package thickness, and improvement in heat stress.

図４のように、パターン金属コア層２１２は、できるだけ更に複数個の第一連結バー２１８を持ち、それらの第一連結バー２１８で外接用パッド２１４と薄膜基板２１０の周縁とを連結し、あるいは、パターン金属コア層２１２は更に複数個の第二連結バー２１９を持ち、それらの第二連結バー２１９で内部フィンガー２１３と溝２１１の周縁とを連結する。この実施例では、パターン金属コア層２１２は同時に第一連結バー２１８と第二連結バー２１９とを有するので、内部フィンガー２１３及び外接用パッド２１４の上面に一電気メッキ層２６０を形成し易くなり、かつ内部フィンガー２１３と外接用パッド２１４の固定力が従来より一段と強くなる。パッケージする前に、第一連結バー２１８は、外接用パッド２１４やワイヤーバー２１２Ａを介して両薄膜基板２１０間にあるダイシングラインのメッキ連結バー２１に連結し、第二連結バー２１９は、内部フィンガー２１３を介してメッキ連結バー２２に連結し、このメッキ連結バー２２は薄膜基板２１０上に溝２１１を設ける所に位置する。そして、内部フィンガー２１３と外接用パッド２１４との漏出面に電気メッキ層２６０（たとえば、Ｎｉ−Ａｕ層）が形成されることができる。更に、電気メッキ層２６０によって、内部フィンガー２１３、外接用パッド２１４、及びパターン金属コア層２１２のワイヤーバー２１２Ａが同時に安定することが可能で、第一表面誘電体層２１５及び第二表面誘電体層２１６の形成が比較的容易にできるため、不当の電気ショットを回避し、内部フィンガー２１３の配置をもっと狭ピッチにすることが可能となる。   As shown in FIG. 4, the patterned metal core layer 212 has a plurality of first connection bars 218 as much as possible, and connects the circumscribed pad 214 and the peripheral edge of the thin film substrate 210 with the first connection bars 218. The patterned metal core layer 212 further includes a plurality of second connection bars 219, and the second connection bars 219 connect the inner fingers 213 and the peripheral edge of the groove 211. In this embodiment, since the patterned metal core layer 212 has the first connection bar 218 and the second connection bar 219 at the same time, it is easy to form one electroplating layer 260 on the upper surfaces of the internal fingers 213 and the external pads 214, In addition, the fixing force between the internal finger 213 and the external pad 214 becomes stronger than before. Prior to packaging, the first connection bar 218 is connected to the plating connection bar 21 of the dicing line between the thin film substrates 210 via the circumscribed pad 214 and the wire bar 212A, and the second connection bar 219 is an internal finger. It connects with the plating connection bar 22 via 213, and this plating connection bar 22 is located in the place which provides the groove | channel 211 on the thin film substrate 210. FIG. Then, an electroplating layer 260 (for example, a Ni—Au layer) can be formed on the leakage surface between the internal finger 213 and the external pad 214. Furthermore, the electroplating layer 260 can simultaneously stabilize the internal fingers 213, the external pads 214, and the wire bars 212A of the patterned metal core layer 212, and the first surface dielectric layer 215 and the second surface dielectric layer. Since 216 can be formed relatively easily, it is possible to avoid undue electrical shots and to arrange the inner fingers 213 at a narrower pitch.

再び図２に示すように、並び方として、外接用パッド２１４は不規則的拡散にすれば放熱面積が拡大でき、開孔２１７は円形な排列にすればソルダボール（solder ball）２５０を設置し易くなる。ゆえに、第一表面誘電体層２１５の開孔２１７は、外接用パッド２１４より小さく外接用パッド２１４の周辺を覆う。第一表面誘電体層２１５としてソルダマスク（solder mask）を使う場合、外接用パッド２１４をＳＭＤパッド（solder mask defined pad）にすることができる。   As shown in FIG. 2 again, as a way of arrangement, if the circumscribed pad 214 is irregularly diffused, the heat radiation area can be expanded, and if the openings 217 are arranged in a circular manner, a solder ball 250 can be easily installed. Become. Therefore, the opening 217 of the first surface dielectric layer 215 is smaller than the circumscribed pad 214 and covers the periphery of the circumscribed pad 214. When a solder mask is used as the first surface dielectric layer 215, the circumscribed pad 214 can be an SMD pad (solder mask defined pad).

図３Ａから図３Ｉに参考して上述のチップパッケージ２００の製造プロセスを説明する。先ず、図３Ａに示すように、金属薄膜１０は、６０μｍから１００μｍ程度の厚みを提供する。そして、露光、現像、及びエッチングなどの技術を利用して金属薄膜１０をパターン化し、図３Ｂに示すように、金属薄膜１０がパターン化された後、内部フィンガー２１３と外接用パッド２１４とを有する上述パターン金属コア層２１２を構成する。尚、本実施例において、図４に示すように、外接用パッド２１４は第一連結バー２１８を介してダイシングラインに位置するメッキ連結バー２１に連結され、内部フィンガー２１３は第二連結バー２１９を介して溝２１１に位置するメッキ連結バー２２に連結され、この際に溝２１１はまだ形成されていない。次に、図３Ｃに示すように、プリント技術を利用してパターン金属コア層２１２の下表面と上表面にそれぞれ第一表面誘電体層２１５及び第二表面誘電体層２１６を形成する。ここで、複数個の開孔２１７と溝孔が内部フィンガー２１３と外接用パッド２１４とを露出するように第一表面誘電体層２１５上に形成される。次に、図３Ｄに示すように、メッキプロセスを行い、内部フィンガー２１３及び外接用パッド２１４の漏出表面上に電気メッキ層２６０を形成した後、溝２１１を設置する。図３Ｅに示すように、溝２１１が形成された後、上記薄膜基板２１０を得ることができる。本実施例において、溝２１１を形成する際に、第二連結バー２１９が除去され、第一連結バー２１８が薄膜基板２１０内に保留されるため、溝２１１を形成する時に起きるバー（burr）問題を少なくすることができる。そして、図３Ｆに示すように、ダイアタッチ（die attach）ステップを行い、チップ２２０の能動面２２１を薄膜基板２１０の上表面に貼付け、ここで、チップ２２０の電極端２２３は溝２１１内に露出する。次に、図３Ｇに示すように、ワイヤーボンディングステップを行い、ワイヤーボンディングされて形成するボンディングワイヤーは溝２１１を通過して電極端２２３と内部フィンガー２１３とを接続する。また、図３Ｈに示すように、モルディング（molding）技術を利用して封止ステップを行うと、薄膜基板２１０の上表面と溝２１１内とに形成される封止体２４０は少なくとも一部のチップ２２０及びボンディングワイヤー２３０を封止し、外接用パッド２１４を電気的に接続できるような状態にする。この後、リフロー（reflow）やソルダボール接合技術によってソルダボール２５０を外接用パッド２１４上に接合する。最後に、ダイシングステップを行って、図２に示すチップパッケージ２００を得ることができる。   A manufacturing process of the above-described chip package 200 will be described with reference to FIGS. 3A to 3I. First, as shown in FIG. 3A, the metal thin film 10 provides a thickness of about 60 μm to 100 μm. Then, the metal thin film 10 is patterned using techniques such as exposure, development, and etching. As shown in FIG. 3B, after the metal thin film 10 is patterned, it has an internal finger 213 and a circumscribed pad 214. The patterned metal core layer 212 is configured. In this embodiment, as shown in FIG. 4, the circumscribed pad 214 is connected to the plating connecting bar 21 located on the dicing line via the first connecting bar 218, and the internal finger 213 is connected to the second connecting bar 219. In this case, the groove 211 is not formed yet. Next, as shown in FIG. 3C, a first surface dielectric layer 215 and a second surface dielectric layer 216 are formed on the lower surface and the upper surface of the patterned metal core layer 212 using a printing technique, respectively. Here, a plurality of openings 217 and grooves are formed on the first surface dielectric layer 215 so as to expose the internal fingers 213 and the circumscribed pad 214. Next, as shown in FIG. 3D, a plating process is performed to form the electroplating layer 260 on the leaking surfaces of the internal fingers 213 and the external pads 214, and then the grooves 211 are installed. As shown in FIG. 3E, the thin film substrate 210 can be obtained after the grooves 211 are formed. In this embodiment, when the groove 211 is formed, the second connection bar 219 is removed, and the first connection bar 218 is retained in the thin film substrate 210. Therefore, a bar problem occurs when the groove 211 is formed. Can be reduced. Then, as shown in FIG. 3F, a die attach step is performed to attach the active surface 221 of the chip 220 to the upper surface of the thin film substrate 210, where the electrode end 223 of the chip 220 is exposed in the groove 211. To do. Next, as shown in FIG. 3G, a wire bonding step is performed, and the bonding wire formed by wire bonding passes through the groove 211 to connect the electrode end 223 and the internal finger 213. As shown in FIG. 3H, when the sealing step is performed using a molding technique, at least a part of the sealing body 240 formed on the upper surface of the thin film substrate 210 and the groove 211 is formed. The chip 220 and the bonding wire 230 are sealed so that the external pad 214 can be electrically connected. Thereafter, the solder ball 250 is joined onto the external pad 214 by a reflow or solder ball joining technique. Finally, a dicing step is performed to obtain the chip package 200 shown in FIG.

本発明の第二実施例には、上記溝２１１を有する単一な薄膜基板２１０の代わりに、複数個の薄膜基板２１０を使うこととなり、このチップパッケージは上記のようなチップ２２０、ボンディングワイヤー２３０、封止体２４０、及び図５に示す第一薄膜基板３１０、第二薄膜基板３２０などで構造される。チップ２２０の能動面２２１は同時に第一薄膜基板３１０と第二薄膜基板３２０に貼着され、図５と図６に示すように、第一薄膜基板３１０と第二薄膜基板３２０とは互い共面関係を持ち、第一薄膜基板３１０と第二薄膜基板３２０との間に少なくとも一つのワイヤーボンディング溝３３０を形成することによって、ボンディングワイヤーにワイヤーボンディング溝３３０を容易に通過させることができる。第一薄膜基板３１０は、パターン金属コア層３１１と少なくとも一つの表面誘電体層３１２とを備え、パターン金属コア層３１１は複数個の内部フィンガー３１３と複数個の外接用パッド３１４とを有し、内部フィンガー３１３はワイヤーボンディング溝３３０の周辺に排列されて、外接用パッド３１４ではグリッドアレイ（grid array）状で配列される。同様に、第二薄膜基板３２０は、パターン金属コア層３２１と少なくとも一つの表面誘電体層３２２を持ち、パターン金属コア層３２１は複数個の内部フィンガー３２３と複数個の外接用パッド３２４とを有する。チップパッケージに対し、互いに分離している第一薄膜基板３１０と第二薄膜基板３２０とはストレスバッファー（stress buffer）を起こし、即ち、チップパッケージを外部の印刷回路基板に表面接合する場合、熱循環による熱応力が互い共面関係を持ちしかも分離している第一薄膜基板３１０と第二薄膜基板３２０とにより分散されて、上方のチップに影響を直接に与えないよう、有効にチップと薄膜基板３１０、３２０と間の剥離を避けられる。更にＣＯＢ形態パッケージの薄型化、放熱性の向上、及び基板コストの低下などの効果を達成することもできる。
本発明の保護範囲は特許申請範囲で限定されて、この保護範囲に基準して、本発明の精神と範囲内に触れるどんな変更や修正は本発明の保護範囲に属する。 In the second embodiment of the present invention, a plurality of thin film substrates 210 are used instead of the single thin film substrate 210 having the groove 211, and the chip package includes the chip 220 and the bonding wire 230 as described above. , The sealing body 240, and the first thin film substrate 310 and the second thin film substrate 320 shown in FIG. The active surface 221 of the chip 220 is simultaneously attached to the first thin film substrate 310 and the second thin film substrate 320, and the first thin film substrate 310 and the second thin film substrate 320 are coplanar as shown in FIGS. By forming at least one wire bonding groove 330 between the first thin film substrate 310 and the second thin film substrate 320, the wire bonding groove 330 can be easily passed through the bonding wire. The first thin film substrate 310 includes a patterned metal core layer 311 and at least one surface dielectric layer 312, and the patterned metal core layer 311 includes a plurality of internal fingers 313 and a plurality of external pads 314. The internal fingers 313 are arranged around the wire bonding groove 330 and are arranged in a grid array on the circumscribed pad 314. Similarly, the second thin film substrate 320 has a patterned metal core layer 321 and at least one surface dielectric layer 322, and the patterned metal core layer 321 has a plurality of internal fingers 323 and a plurality of external pads 324. . The first thin film substrate 310 and the second thin film substrate 320 which are separated from each other with respect to the chip package generate a stress buffer, that is, when the chip package is surface-bonded to an external printed circuit board, thermal circulation is performed. The chip and the thin film substrate are effectively prevented from being dispersed by the first thin film substrate 310 and the second thin film substrate 320 that are coplanar and separated from each other and directly affect the upper chip. Peeling between 310 and 320 can be avoided. Furthermore, effects such as reduction in the thickness of the COB package, improvement in heat dissipation, and reduction in substrate cost can be achieved.
The scope of protection of the present invention is limited by the scope of patent application, and any change or modification that comes within the spirit and scope of the present invention based on this scope of protection belongs to the protection scope of the present invention.

周知のチップパッケージ構造を示す断面図である。It is sectional drawing which shows a known chip package structure. 本発明の第１実施例によるチップパッケージ構造を示す断面図である。1 is a cross-sectional view illustrating a chip package structure according to a first embodiment of the present invention. 本発明の第１実施例に係るチップパッケージの製造プロセスを示す断面図である。It is sectional drawing which shows the manufacturing process of the chip package which concerns on 1st Example of this invention. 本発明の第１実施例に係るチップパッケージの製造プロセスを示す断面図である。It is sectional drawing which shows the manufacturing process of the chip package which concerns on 1st Example of this invention. 本発明の第１実施例に係るチップパッケージの製造プロセスを示す断面図である。It is sectional drawing which shows the manufacturing process of the chip package which concerns on 1st Example of this invention. 本発明の第１実施例に係るチップパッケージの製造プロセスを示す断面図である。It is sectional drawing which shows the manufacturing process of the chip package which concerns on 1st Example of this invention. 本発明の第１実施例に係るチップパッケージの製造プロセスを示す断面図である。It is sectional drawing which shows the manufacturing process of the chip package which concerns on 1st Example of this invention. 本発明の第１実施例に係るチップパッケージの製造プロセスを示す断面図である。It is sectional drawing which shows the manufacturing process of the chip package which concerns on 1st Example of this invention. 本発明の第１実施例に係るチップパッケージの製造プロセスを示す断面図である。It is sectional drawing which shows the manufacturing process of the chip package which concerns on 1st Example of this invention. 本発明の第１実施例に係るチップパッケージの製造プロセスを示す断面図である。It is sectional drawing which shows the manufacturing process of the chip package which concerns on 1st Example of this invention. 本発明の第１実施例に係るチップパッケージの製造プロセスを示す断面図である。It is sectional drawing which shows the manufacturing process of the chip package which concerns on 1st Example of this invention. 本発明の第１実施例に係るチップパッケージがメッキされる前のパターン金属コア層を示す一部の底面図である。FIG. 3 is a partial bottom view showing a patterned metal core layer before the chip package according to the first embodiment of the present invention is plated. 本発明の第２実施例に係るチップパッケージの複数個の薄膜基板を示す底面図である。It is a bottom view showing a plurality of thin film substrates of a chip package according to a second embodiment of the present invention. 本発明の第２実施例によるチップパッケージ構造を示す断面図である。6 is a cross-sectional view illustrating a chip package structure according to a second embodiment of the present invention. FIG.

符号の説明Explanation of symbols

１０金属薄膜、２１、２２ 連結バー、２００ チップパッケージ構造、２１０ 薄膜基板、２１１ 溝、２１２ パターン金属コア層、２１２Ａ ワイヤーバー、２１３ 内部フィンガー、２１４ 外接用パッド、２１５ 第一表面誘電体層、２１６ 第二表面誘電体層、２１７ 開孔、２１８ 第一連結バー、２１９ 第二連結バー、２２０ チップ、２２１ 能動面、２２２ 背面、２２３ 電極端、２２４ ダイアタッチ層、２３０ ボンディングワイヤー、２４０ 封止体、２５０ ソルダボール、２６０ 電気メッキ層、３１０ 第一薄膜基板、３１１ パターン金属コア層、３１２ 表面誘電体層、３１３ 内部フィンガー、３１４ 外接用パッド、３２０ 第二薄膜基板、３２１ パターン金属コア層、３２２ 表面誘電体層、３２３ 内部フィンガー、３２４ 外接用パッド、３３０ ワイヤーボンディング溝   10 metal thin film, 21, 22 connecting bar, 200 chip package structure, 210 thin film substrate, 211 groove, 212 pattern metal core layer, 212A wire bar, 213 internal finger, 214 external pad, 215 first surface dielectric layer, 216 Second surface dielectric layer, 217 opening, 218 first connection bar, 219 second connection bar, 220 chip, 221 active surface, 222 back surface, 223 electrode end, 224 die attach layer, 230 bonding wire, 240 sealing body , 250 solder balls, 260 electroplated layer, 310 first thin film substrate, 311 pattern metal core layer, 312 surface dielectric layer, 313 internal finger, 314 external pad, 320 second thin film substrate, 321 pattern metal core layer, 322 Surface dielectric layer, 323 Gar, 324 circumscribing pad, 330 a wire bonding groove

Claims (18)

溝を有し、パターン金属コア層（patterned metal core layer）と少なくとも一つの表面誘電体層とを備え、該パターン金属コア層は複数個の内部フィンガーと複数個の外接用パッドを有し、該内部フィンガーが溝の周りに配列される薄膜基板と、
能動面上に複数個の電極端が形成され、該電極端が溝内に向かって配置される際に該能動面を該薄膜基板に貼着するチップと
溝を通過して電気的に該電極端と該内部フィンガーとを接続する複数個のボンディングワイヤーと、
該薄膜基板上と該溝内とに形成され、少なくとも一部で該チップ及び該ボンディングワイヤーを封止する封止体と、
を備えることを特徴とするチップパッケージ構造。 A groove having a patterned metal core layer and at least one surface dielectric layer, the patterned metal core layer having a plurality of internal fingers and a plurality of external pads, A thin film substrate in which internal fingers are arranged around the groove;
A plurality of electrode ends are formed on the active surface, and when the electrode ends are arranged in the groove, the electrode is electrically passed through the chip and the groove for attaching the active surface to the thin film substrate. A plurality of bonding wires connecting the extreme and the internal fingers;
A sealing body that is formed on the thin film substrate and in the groove and seals the chip and the bonding wire at least partially;
A chip package structure comprising: 該パターン金属コア層は６０μｍから１００μｍの厚みを持つことを特徴とする請求項１に記載のチップパッケージ構造。   2. The chip package structure according to claim 1, wherein the patterned metal core layer has a thickness of 60 μm to 100 μm. 該パターン金属コア層は更に複数個の連結バーを有し、該連結バーは該外接用パッドと該薄膜基板の周縁とを連結することを特徴とする請求項１に記載のチップパッケージ構造。   2. The chip package structure according to claim 1, wherein the patterned metal core layer further includes a plurality of connecting bars, and the connecting bars connect the circumscribed pad and the peripheral edge of the thin film substrate. 該パターン金属コア層は更に複数個の連結バーを有し、該連結バーは該内部フィンガーと該溝の周縁とを連結することを特徴とする請求項１又は３に記載のチップパッケージ構造。   4. The chip package structure according to claim 1, wherein the pattern metal core layer further includes a plurality of connecting bars, and the connecting bars connect the inner fingers and the peripheral edge of the groove. 5. 該表面誘電体層は、該外接用パッドより小さい複数個の開孔を有することによって該外接用パッドの周辺を覆うことを特徴とする請求項１に記載のチップパッケージ構造。   2. The chip package structure according to claim 1, wherein the surface dielectric layer covers a periphery of the circumscribed pad by having a plurality of openings smaller than the circumscribed pad. 3. 該外接用パッドは不規則な拡散状で配置され、該開孔は円形状に排列されることを特徴とする請求項５に記載のチップパッケージ構造。   6. The chip package structure according to claim 5, wherein the circumscribed pads are arranged in an irregular diffusion shape, and the openings are arranged in a circular shape. ソルダマスク（solder mask）は表面誘電体層として使われ、該外接用パッドはＳＭＤパッド（solder mask defined pad）であることを特徴とする請求項５に記載のチップパッケージ構造。   6. The chip package structure according to claim 5, wherein a solder mask is used as a surface dielectric layer, and the circumscribed pad is an SMD pad (solder mask defined pad). 該外接用パッド上に設置される複数個のソルダボール（solder ball）を有することを特徴とする請求項１に記載のチップパッケージ構造。   2. The chip package structure as claimed in claim 1, further comprising a plurality of solder balls installed on the external pad. 該薄膜基板は更に第二表面誘電体層を備えるため、該パターン金属コア層は両表面誘電体層の間に挟まれることを特徴とする請求項１に記載のチップパッケージ構造。   2. The chip package structure according to claim 1, wherein the thin film substrate further includes a second surface dielectric layer, and the patterned metal core layer is sandwiched between both surface dielectric layers. 間に少なくとも一つのワイヤーボンディング溝が形成され、パターン金属コア層（patterned metal core layer）と少なくとも一つの表面誘電体層とを有し、該パターン金属コア層は複数個の内部フィンガーと複数個の外接用パッドとを有し、該内部フィンガーが該ワイヤーボンディング溝の周辺に排列される互い共面関係を持つ複数個の薄膜基板と、
複数個の電極端が能動面上に形成され、該電極端が該ワイヤーボンディング溝内に向かって配置される際に該能動面を該薄膜基板に貼着するチップと、
ワイヤーボンディング溝を通過して電気的に該電極端と該内部フィンガーを接続する複数個のボンディングワイヤーと、
該薄膜基板上と該ワイヤーボンディング溝内に形成され、少なくとも一部で該チップと該ボンディングワイヤーとを封止する封止体と、
を備えることを特徴とするチップパッケージ構造。 At least one wire bonding groove is formed therebetween, and has a patterned metal core layer and at least one surface dielectric layer, wherein the patterned metal core layer includes a plurality of internal fingers and a plurality of plurality of inner fingers. A plurality of thin film substrates having a coplanar relationship, wherein the internal fingers are arranged around the wire bonding grooves,
A plurality of electrode ends formed on the active surface, and a chip for adhering the active surface to the thin film substrate when the electrode ends are disposed toward the wire bonding groove;
A plurality of bonding wires that electrically connect the electrode ends and the internal fingers through the wire bonding grooves;
A sealing body which is formed on the thin film substrate and in the wire bonding groove and seals the chip and the bonding wire at least partially;
A chip package structure comprising: 該パターン金属コア層は６０μｍから１００μｍの厚みを持つことを特徴とする請求項１０に記載のチップパッケージ構造。   11. The chip package structure according to claim 10, wherein the patterned metal core layer has a thickness of 60 μm to 100 μm. 該パターン金属コア層は更に複数個の連結バーを有し、該連結バーは該外接用パッドと該薄膜基板の周縁とを連結することを特徴とする請求項１０に記載のチップパッケージ構造。   11. The chip package structure according to claim 10, wherein the patterned metal core layer further includes a plurality of connecting bars, and the connecting bars connect the circumscribed pad and the peripheral edge of the thin film substrate. 該パターン金属コア層は更に複数個の連結バーを有し、該連結バーは該内部フィンガーと該ワイヤーボンディング溝の周縁とを連結することを特徴とする請求項１０又は１２に記載のチップパッケージ構造。   13. The chip package structure according to claim 10, wherein the patterned metal core layer further includes a plurality of connecting bars, and the connecting bars connect the inner fingers and the peripheral edge of the wire bonding groove. . 該表面誘電体層は、該外接用パッドより小さい複数個の開孔を有することによって該外接用パッドの周辺を覆うことを特徴とする請求項１０に記載のチップパッケージ構造。   11. The chip package structure according to claim 10, wherein the surface dielectric layer covers a periphery of the circumscribed pad by having a plurality of openings smaller than the circumscribed pad. 該外接用パッドは不規則な拡散状で配置され、該開孔は円形状に排列されることを特徴とする請求項１４項に記載のチップパッケージ構造。   15. The chip package structure according to claim 14, wherein the circumscribed pads are arranged in an irregular diffusion shape, and the openings are arranged in a circular shape. ソルダマスク（solder mask）は表面誘電体層として使われ、該外接用パッドはＳＭＤパッド（solder mask defined pad）であることを特徴とする請求項１０に記載のチップパッケージ構造。   11. The chip package structure according to claim 10, wherein a solder mask is used as a surface dielectric layer, and the circumscribed pad is an SMD pad (solder mask defined pad). 更に該外接用パッド上に設置される複数個のソルダボール（solder ball）を有することを特徴とする請求項１０に記載のチップパッケージ構造。   11. The chip package structure according to claim 10, further comprising a plurality of solder balls installed on the circumscribed pad. 各薄膜基板は更に第二表面誘電体層を備えるため、該パターン金属コア層は両表面誘電体層の間に挟まれることを特徴とする請求項１０に記載のチップパッケージ構造。



11. The chip package structure according to claim 10, wherein each thin film substrate further includes a second surface dielectric layer, so that the patterned metal core layer is sandwiched between both surface dielectric layers.



JP2006084870A 2006-03-27 2006-03-27 Chip package structure Pending JP2007266025A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011159944A (en) * 2010-01-29 2011-08-18 Samsung Electro-Mechanics Co Ltd Single-layer on-chip package board and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011159944A (en) * 2010-01-29 2011-08-18 Samsung Electro-Mechanics Co Ltd Single-layer on-chip package board and method of manufacturing the same

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