JP2007265143A - Information processing method, information processing system, information processor, multiprocessor, information processing program, and computer-readable storage medium storing information processing program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing technique capable of shortening processing time or improving processing efficiency in processing of a plurality of files by further effectively utilizing parallel processing property by a multiprocessor. <P>SOLUTION: A PU 8 divides, upon receipt of processing instruction to processing object files stored in a flash memory 20, the processing object files into groups. The PU 8 assigns a reading buffer and a writing buffer for each group to a RAM 16, and assigns each SPU 3a-3h to each group. The PU 8 reads all the processing object files from an HD 33 to each reading buffer corresponding to each group. The PU makes each SPU 3a-3h perform processing to each processing object file read to each reading buffer, and write the processed file to each writing buffer. The PU 8 writes the processed file written to each writing buffer by each SPU 3a-3h to the HD 33. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to an information processing technique for processing a plurality of files stored in a non-volatile storage using a multiprocessor.

  In recent years, non-volatile storage such as hard disks has become cheaper and larger in capacity. Also, downloading music files over a network, ripping data files stored on CDs (Compact Disk), and editing image files taken with digital still cameras and video cameras have become widespread. ing. Along with such a situation, a large number of files are generally held in a nonvolatile storage. As the use of such files increases, the following processing for files has been increasingly required. For example, because there are multiple video codecs and audio codecs, processing to convert from one codec to another, processing to scan files for viruses, and encrypting files in a batch to ensure file safety For example.

  For example, there is a method of performing such processing on a plurality of files at once. For example, WINDOWS (registered trademark) of Microsoft Corporation provides a means for encrypting all files included in a folder on a folder basis. Examples of such means include a single processor and a multiprocessor. In the former case, one processor sequentially reads a file from the non-volatile storage, performs a process of encrypting the file, and performs a process of rewriting the encrypted file in the non-volatile storage. In this case, since the processing capacity of a single processor is limited, for example, even if parallel processing is attempted using multithread technology, considering the switching time etc., processing time reduction and processing efficiency due to parallelization are considered. I cannot expect much improvement.

  On the other hand, in the latter case, a plurality of files can be read from the non-volatile storage one after another and assigned to a plurality of processors so that the processors can be processed in parallel. In this case, first, a process of reading a file and assigning it to a processor is sequentially performed. A multiprocessor that performs such processing is disclosed in Patent Document 1, for example.

JP-A-2005-251163

  However, in such a multiprocessor, it is necessary to cause the processor to wait for synchronization while reading each file from the nonvolatile storage. If such synchronization waiting frequently occurs, there is a possibility that the processing efficiency is lowered and the processing time is extended. Further, in a multiprocessor having a configuration in which a plurality of processors share nonvolatile storage, it is necessary to synchronize the nonvolatile storage when parallel processing is performed by each processor. For this reason, a considerable bottleneck may cause a reduction in processing efficiency and an increase in processing time.

  Therefore, even if parallel processing is performed on a plurality of files using a multiprocessor, it is difficult to effectively utilize the parallel processing performance and to shorten the processing time or improve the processing time.

  Therefore, the present invention has been made in view of the above-described problems, and can effectively reduce the processing time and improve the processing efficiency when processing a plurality of files by making more effective use of parallel processing by a multiprocessor. An object is to provide information processing technology.

  In the present invention, when a multiprocessor including a main memory and a plurality of processors performs a predetermined process on a plurality of processing target files stored in a nonvolatile storage connected to the multiprocessor, One processor divides the plurality of processing target files into a plurality of file groups, assigns each divided file group to at least one target processor among the plurality of processors, and reads each corresponding to each file group A buffer is set in the main memory. A storage controller in which the one processor instructs a target processor to which the file group is assigned to start a processing program for performing the predetermined processing, and controls reading and writing of data with respect to the nonvolatile storage Is instructed to read out the processing target file stored in the nonvolatile storage to the reading buffer set in the main memory in association with the file group to which the processing target file belongs.

  The number of files to be processed divided into file groups may be the same as the number of processors included in the multiprocessor, or may be more or less than the number of processors.

  The target processor to which the file group is assigned may or may not include the one processor in which the plurality of processing target files are divided into a plurality of file groups.

  The one processor may be a processor that functions as a main processor, and the target processor may be a processor that functions as a sub processor.

  ADVANTAGE OF THE INVENTION According to this invention, the time at the time of reading the several process object file memorize | stored in the non-volatile storage can be shortened, processing time can be shortened and processing efficiency can be improved.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, the same code | symbol is attached | subjected to the common part in each figure. Moreover, this Example shows one aspect | mode of this invention, This invention is not limited, It can change arbitrarily in the scope of the present invention.

[Example 1]
(1) Configuration <Configuration of information processing apparatus>
FIG. 1 is a block diagram illustrating the internal configuration of the information processing apparatus 1 according to this embodiment.

  The information processing apparatus 1 includes a one-chip multiprocessor 2, a RAM (Random Access Memory) 16 used as a main memory, a south bridge 18, a network interface 19, a flash memory 20, a flash memory controller 31, and a DVD (Digital A Versatile Disk (USB) driver 21, a USB (Universal Serial Bus) 22, a graphic card 24, an ADC (analog digital converter) 27, and an RF (Radio Frequency) processing unit 28 are included. Although not shown, an input device for inputting an instruction from the user is connected to the information processing device 1.

  The flash memory controller 31 controls data reading and data writing to the flash memory 20. The flash memory 20 stores an operating system, various programs such as an encryption program described later, and various files.

  The RAM 16 stores various programs executed by the one-chip multiprocessor 2, various data used when executing the various programs, and various tables described later.

  The graphic card 24 is a card for realizing an image processing function, and has a built-in frame memory 25 and is connected to a monitor device 26. The graphic card 24 draws an image in the frame memory 25 under the control of the one-chip multiprocessor 2 and causes the monitor device 26 to display the drawn image.

  The RF processing unit 28 includes a down converter 29 and controls wireless communication with an external device via the antenna 30. The ADC 27 converts the analog signal supplied from the RF processing unit 28 into a digital signal, and supplies this to the one-chip multiprocessor 2.

  The DVD driver 21 is a DVD-ROM (Digital Versatile Disk Random Access Memory) or DVD-RAM (Digital Versatile Disk Random Access Memory) mounted on a disk mounting unit (not shown) under the control of the one-chip multiprocessor 2. The reading and writing of data to the DVD 32 are controlled.

  The USB 22 controls various peripheral devices via the controller 23 under the control of the one-chip multiprocessor 2. Various storage devices such as HD (Hard Disc) 33 and various storage media are connected to the controller 23. The controller 23 functions as a hard disk controller and controls data reading and data writing to the HD 33. The HD 33 stores a file to be encrypted later. Each file is assigned a file ID that can uniquely identify these files. Each file may be any various file such as a text file, a music file, and an image file.

  The network interface 19 controls data communication via a network such as the Internet or a LAN under the control of the one-chip multiprocessor 2.

<Configuration of one-chip multiprocessor>
The one-chip multiprocessor 2 includes a main processor (PU) 8, eight sub processors (SPUs) 3a to 3h, an input / output interface (Input / Output Interface) 17, and a memory controller ( MC: Memory Controller) 15. These are each connected to the ring bus 14 and can operate in parallel.

  The PU 8 and the SPUs 3a to 3h are instruction set architectures having different instruction sets. The PU 8 controls the operations of the SPUs 3a to 3h, and the SPUs 3a to 3h execute various processes in parallel and independently under the control of the PU 8. The PU 8 accepts all interrupts, but the SPUs 3a to 3h do not accept interrupts. When an interrupt is applied to the SPUs 3a to 3h, the PU 8 performs processing for the interrupt. Each of these processors is assigned a processor ID that can be uniquely identified in the one-chip multiprocessor 2. The processor ID of the sub processor (SPU) is stored in the processor management table 160 of the RAM 16 as shown in FIG. 2, for example. In the management table 160, the processor ID is stored in association with a group ID described later. Here, for convenience of explanation, the same processor ID is used for each processor ID assigned to each of the SPUs 3a to 3h.

  The PU 8 includes a processor core 9, a memory flow controller (MFC) 12 having a DMAC (Direct Memory Access Controller) 13, an L1 cache 10, and an L2 cache 11.

  The SPU 3a includes a processor core 4a, a local storage (LS) 5a, and an MFC 6a incorporating a DMAC 7a.

  Unlike the cache, the LS 5a does not require support for cache coherency, ie cache coherency. The LS 5a is preferably configured as a DRAM (Dynamic Random Access Memory). Various programs are loaded into the LS 5a in accordance with control commands from the PU 8.

  The DMAC 7a accesses various programs and various data stored in the RAM 16 under the control of the SPU 3a. That is, when accessing the RAM 16, the SPU 3a issues a read or write command to the MFC 6a having the DMAC 7a without using the PU 8, and reads or writes various programs and various data from the RAM 16 via the MFC 6a. The read or write command includes the processor ID of the SPU 3a and the address of the access request destination on the RAM 16.

  Note that the SPUs 3b to 3h are substantially the same as the configuration of the SPU 3a, and thus the description thereof is omitted. Hereinafter, when it is not necessary to distinguish between the SPUs 3a to 3h, they are simply referred to as SPU3. Moreover, it is necessary to distinguish and describe each SPU, and when it is necessary to distinguish and describe each component of each SPU, a to h are added to the end of each symbol.

  MC15 is connected to RAM16 and mediates access to RAM16 of PU8 and each SPU3a-3h.

  The input / output interface 17 is connected to the south bridge 18, the graphics card 24, and an ADC 27 connected to an RF (Radio Frequency) processing unit 28. The input / output interface 17 controls the PU 8 and the SPU 3 to control the external device and to transmit / receive data to / from the external device.

  The south bridge 18 is connected to a network interface 19, a flash memory control 31 connected to the flash memory 20, a DVD driver 21, and a USB (Universal Serial Bus) 22, and relays data between them.

<Functional configuration>
Next, the functional configuration of the one-chip multiprocessor 2 will be described. In this embodiment, the PU 8 executes the operating system and application program stored in the flash memory 20, and the SPUs 3a to 3h perform various processes in accordance with the control instructions of the PU 8 in the execution process of the process, and the following functions are performed. Is realized.

  When a processing command such as encryption processing is performed on the file stored in the HD 33, the PU 8 groups the files to be processed. Then, a read buffer and a write buffer for each group are allocated to the RAM 16, and each SPU 3a to 3h is allocated to each group. Then, the PU 8 instructs the controller 23 to read all the files to be processed from the flash memory 20 to each read buffer corresponding to each group. The controller 23 reads all files to be processed from the HD 33 to each read buffer corresponding to each group in accordance with the instruction. Then, the PU 8 causes the SPUs 3a to 3h to perform processing on the file read to each read buffer, and causes the processed file to be written to each write buffer. Next, the PU 8 instructs the controller 23 to write the processed file written in the write buffer by the SPUs 3 a to 3 h to the HD 33. The controller 23 writes the processed file written in the write buffer by the SPUs 3a to 3h to the HD 33 in accordance with the instruction.

(2) Operation Next, the operation according to the present embodiment will be described with reference to FIG. In the present embodiment, an operation for performing encryption processing on a plurality of files stored in the HD 33 as an example of nonvolatile storage will be described.

  When the main power is turned on to the information processing apparatus 1, the PU 8 loads various control programs such as an operating system and various application programs such as an encryption program into the RAM 16. As a program loading procedure, the PU 8 issues a program read command to the flash memory controller 31 via the input / output interface 17 and the south bridge 18, and the flash memory controller 31 reads the program from the flash memory 20 according to the command. Next, the PU 8 writes the program into the RAM 16 via the MC 15. The PU 8 controls each unit of the information processing apparatus 1 by executing a control program loaded in the RAM 16. Various functions are realized by executing various application programs.

  Here, when the PU 8 is executing an application program, if an instruction to perform a process of collectively encrypting a plurality of files stored in the HD 33 is input from the user via the input device, the PU 8 The instruction signal corresponding to the instruction is received via the USB 22, the south bridge 18, and the input / output interface 17. Then, the PU 8 reads the encrypted program from the flash memory 20 via the input / output interface 17 and the south bridge 18 in accordance with the instruction signal, and loads the program into the RAM 16 via the MC 15.

  Then, as shown in step S1 of FIG. 3, the PU 8 first counts the total number of processors that can perform processing. Here, this number is the total number of sub-processors that the one-chip multiprocessor 2 has. Specifically, the management table 160 stored in the RAM 16 is referred to, and the number of sub processors is counted based on the processor ID stored in the management table 160. Alternatively, a register (not shown) is configured to always record the number of sub-processors that can execute the current processing in a part of the memory such as the RAM 16 or the flash memory 20, May be used as the “total number of processors capable of processing”. Alternatively, the sub processor scheduler may be configured to manage the number of sub processors capable of executing processing, and this number may be used as the “total number of processors capable of performing processing”. Next, the PU 8 specifies a file to be processed stored in the HD 33, and detects the file ID and file size of each specified file.

Next, the PU 8 calculates the number of groups into which the files to be processed are grouped by the following formula (1) (step S2).
(Number of groups) = MAX (1, FLOOR ((total number of sub-processors capable of performing processing) / (parallel degree of processing))) (1)
Here, FLOOR (X) is a function that returns the maximum integer that does not exceed “X”. MAX (1, Y) is a function that returns a larger number of “1” and “Y”. “Processing parallelism” indicates the number of programs when the execution of the processing is realized by executing a plurality of programs capable of operating in parallel. When the execution of processing is realized by executing one program, the “degree of parallelism of processing” is “1”. That is, in step S2, the number of sub-processors that can perform processing is determined in consideration of the parallel execution possibility of the processing program executed for processing, and the processing target is assigned to the determined number of groups. Separate files.

  In the present embodiment, the sub processors that can perform processing are SPUs 3a to 3h, and therefore, “the total number of sub processors that can perform processing” is “8”. In addition, since the number of encryption programs executed for performing the encryption processing is one and no parallel processing is required, the “parallel degree of processing” is “1”.

  Therefore, in this embodiment, the “number of groups” is “8”. In step S3, it is determined whether or not the “number of groups” is larger than “1”. If it is smaller than “1”, the grouping described below is not performed, and the process proceeds to step S12. Here, since the “number of groups” is larger than “1”, the determination result of step S3 becomes affirmative, and the PU 8 next performs the process of step S4. In step S4, the PU 8 divides the processing target file into eight groups, and assigns a group ID to each file. In addition, when dividing a process object file into a group, it is desirable to equalize the processing amount for every group and distribute a file to each group so that the processing amount for every group may become substantially the same amount. Specifically, the file distribution to each group is based on the file size and on the number of files. When allocating files according to file size, the files belonging to each group are allocated so that the total file size is substantially the same, that is, the file sizes are equalized. Note that the total file size of files belonging to each group does not necessarily have to be the same. When allocating files according to the number of files, the total number of files belonging to each group is substantially equal, that is, the number of files is equalized. Note that the total number of files belonging to each group is not necessarily the same. In this invention, you may distribute by any method. In this embodiment, distribution is performed according to the number of files. For example, if there are eight files to be processed, one file is allocated to each group. Specifically, a group with a group ID “Group1” is assigned to a file with a file ID “File1”, and similarly, a group ID “Group2” to a file ID “File2” to “File8” is assigned to each file. Assign each group of “Group8”. The PU 8 also provides an area (hereinafter referred to as a file information area) for managing information of each file belonging to each group in the RAM 16. For example, as shown in FIG. 4, the PU 8 writes the file ID and file size detected in step S1 and the group ID of the group assigned in step S4 for each file in the file information area.

  Further, the PU 8 associates the sub processor with the group thus grouped (step S5). Specifically, the SPU 3a having the processor ID “3a” is associated with the group “Group1”, and similarly, the processor IDs “3b” to “” are assigned to the groups “Group2” to “Group8”. Each SPU 3b-3h of 3h "is made to correspond. Then, for example, as shown in FIG. 2, the PU 8 writes each group ID corresponding to the processor ID of each sub processor in the management table 160 stored in the RAM 16.

  Next, the PU 8 sets a buffer for reading from the HD 33 and a buffer for writing to the HD 33 in the RAM 16 for each group (step S6). For example, for the group with the group ID “Group1”, an area of the memory location “MR1” is assigned as a read buffer, and an area of the memory location “MW1” is assigned as a write buffer. Similarly, for each group of group IDs “Group2” to “Group8”, the memory locations “MR2” to “MR8” are allocated as read buffers, and the memory locations “MW2” to “MW8” are used as write buffers. Assign each area. Further, the PU 8 provides a buffer management area in the RAM 16, and writes each memory location of each buffer allocated to each group in the buffer management area as shown in FIG. It is assumed that the size of each buffer is sufficiently larger than the total file size of files belonging to each group. In other words, it is desirable to limit the number of files that can be processed at one time to a number that does not exceed the size of the assignable buffer.

  Next, the PU 8 generates eight processing threads of the cryptographic processing program loaded in the RAM 16, and assigns a group ID to each processing thread (step S7). Specifically, the PU 8 assigns the SPUs 3a to 3h corresponding to the groups to the processing threads, and stores the assigned processing threads in the LSs 5a to 5h of the SPUs 3a to 3h. Then, the PU 8 issues an instruction to each of the SPUs 3a to 3h so as to execute each processing thread assigned to each SPU, and sets each of them to a synchronization waiting state.

  Thereafter, the PU 8 issues a read command for reading all the files to be processed stored in the HD 33 to the controller 23 (step S8). Specifically, the first block of each file, the number of blocks, and the write position in the read buffer assigned for each group ID of each file are designated, each file is read from the HD 33, and this is read buffer corresponding to each. To write to the write position. It should be noted that the write position in the read buffer for each group ID is increased by the file size of the file read immediately before the file is read when the reading of each file corresponding to each read buffer is instructed. Updated. On the other hand, the controller 23 reads all the files to be processed stored in the HD 33 to the corresponding read buffers in accordance with the read command from the PU 8.

  At the same time as the read command, the PU 8 cancels the synchronization waiting state of each processing thread assigned to the SPUs 3a to 3h, and causes each SPU 3a to 3h to start executing each processing thread. That is, the PU 8 causes the SPUs 3a to 3h to start executing the processing thread all at once. In accordance with the application program, the PU 8 enters the synchronization waiting state of the encryption processing completion notification from any of the SPUs 3a to 3h when the execution of all the read instructions is completed.

  Next, the operation of the SPU 3 will be described with reference to FIG. Since the operations performed by the SPUs 3a to 3h are substantially the same, only the SPU 3a will be described.

  The SPU 3a executes the processing thread assigned to the own device and stored in the LS 5a (step S20), and reads the file from the read buffer corresponding to the group ID assigned to the own device (step S22). Then, the encryption process for the file is started (step S23).

  Specifically, the SPU 3a accesses the RAM 16 via the MFC 6a and MC 15 having the DMAC 7a, refers to the information written in the file information area, and reads the buffer (here, the memory location is “MR1”). Each file stored in (area) is read. When reading each file, data corresponding to the file size of each file is read from the storage start position of each file (corresponding to the write position described above) in the read buffer. Each time a file is read, the storage start position of the read buffer is updated so as to increase by the file size of the file read immediately before reading the file. Thereby, each file memorize | stored on the buffer for reading can be read correctly.

  Subsequently, the SPU 3a performs an encryption process on the file read in this way. When the encryption process for the file is completed, the SPU 3a then accesses the RAM 16 via the DMAC 7a and MC 15, and assigns the file subjected to the encryption process (hereinafter referred to as an encrypted file) to the SPU 3a. The data is written into the write buffer corresponding to the group ID (step S24). Then, in the file information area as shown in FIG. 4, the head position of the area where the encrypted file is written (hereinafter referred to as post-processing head address), the file size, and the processor ID are written (step S25).

  As described above, the SPU 3a performs the processing of steps S20 to S25 for each file. When the encryption process for all the processing target files assigned to the own device is completed (step S21: YES), the SPU 3a notifies the PU 8 of the end of the encryption process (hereinafter referred to as encryption). Interruption (referred to as processing end notification) is performed (step S26).

  At the same time as the writing of the encrypted file, the SPU 3a delivers to the SPU 3b the position where the file has been written in the write buffer MW1 and the file size, and at the same time releases the synchronization waiting state and starts the process.

  For the other SPUs 3b to 3h, the same processing as that for the SPU 3a is performed.

  Next, returning to FIG. 3, when the PU 8 receives the encryption processing end notification from any of the SPUs 3 a to 3 h (step S 10: YES), the writing is ended with reference to the file information area according to the application program. The start address on the encrypted file write buffer and the file size of the file are read out, and a command is issued to the controller 23 to write the file to the HD 33 (step S11). Note that the encrypted file that has been written can be determined by, for example, determining whether or not the processor ID corresponding to each file in the file information area and the processed file size are written. . On the other hand, the controller 23 writes the encrypted file written in the write buffer to the HD 33 in accordance with the write command from the PU 8.

  Further, when a cryptographic process end notification is received from another SPU when issuing a write command, the PU 8 performs the process of step S11 each time the notification is received. At the end of execution of the write command, if an encryption processing end notification from another SPU has not been received, the synchronization waiting state is set again. When all files are written in the file information area (step S9: YES), the PU 8 proceeds to the next process according to the application program. The next process is, for example, a process of displaying on the monitor 26 a message indicating that the encryption process has been completed.

  If the “number of groups” calculated in step S2 is “1” (step S3: NO), the PU 8 selects a sub-processor capable of performing processing from the SPUs 3a to 3h according to the operating system. The selected sub processor is made to perform encryption processing for all the files to be processed (step S12).

  Further, when the number of groups is calculated in the above-described step S2, if “the degree of parallelism of processing” is greater than “1” and the determination result in step S3 is affirmative, the PU 8 has the same number of sub-groups as the calculated number of groups. A processor is selected from the SPUs 3a to 3h, and the above-described steps S5 to S11 are performed on the selected sub-processor. Further, when “the degree of parallelism” is larger than “1”, that is, when the execution of the processing is realized by executing a plurality of programs capable of operating in parallel, the PU 8 Commands the processor to execute each program.

  As described above, the main processor divides a plurality of files to be processed into groups and assigns each buffer to each group, whereby all the files to be processed can be read at once. On the other hand, since the sub processor has the DMAC, it can access each buffer without going through the main processor. Therefore, unlike the conventional case, when the main processor reads a file from the non-volatile storage, an interrupt instruction is not issued, and therefore it is possible to eliminate the synchronization waiting time at the time of the interrupt that has been conventionally required. . As a result, the processing time can be shortened and the processing efficiency can be improved.

[Example 2]
In the first embodiment described above, the embodiment has been described in which there is one nonvolatile storage in which a file to be processed is stored. In the present embodiment, an embodiment in which files to be processed are stored in a plurality of nonvolatile storages will be described. Hereinafter, the description of the parts common to the first embodiment will be omitted, or the same reference numerals will be used for description.

(1) Configuration The electrical internal configuration of the information processing apparatus 1A in the present embodiment will be described with reference to FIG. In the present embodiment, the information processing apparatus 1A includes a one-chip multiprocessor 40 having one PU 41 as a main processor and two SPUs 42 and 43 as sub-processors, and a RAM 46 connected thereto via a bus 44, There are four nonvolatile storages 48 to 51 connected to these via an input / output interface 45 and a bridge 47, and a storage controller 53.

  The storage controller 53 controls data reading and data writing to the nonvolatile storages 48 to 51, respectively.

  Each of the non-volatile storages 48 to 51 stores various programs such as various control programs such as an operating system, various application programs, and files to be encrypted. Each of the nonvolatile storages 48 to 51 is associated with a memory ID that can uniquely identify them, and each file is associated with a file ID that can uniquely identify them. These correspondences are stored in the RAM 46 as a pre-file management table 460 as shown in FIG. Here, for convenience of explanation, the same memory ID as that assigned to the nonvolatile storages 48 to 51 is used for each memory ID.

  Since other configurations are the same as those of the first embodiment, description and illustration thereof are omitted.

(2) Operation Next, an operation according to the present embodiment will be described. In the present embodiment, a process for encrypting a plurality of files stored in the plurality of nonvolatile storages 48 to 51 will be described.

  While executing the application program, the PU 41 reads the encryption program from the nonvolatile storage (for example, the nonvolatile storage 48) in the same manner as in the first embodiment, and can execute the process. Load to local storage (not shown) of all sub-processors. And PU41 performs the process of step S1-S2 of FIG. 3, and calculates the number of groups by the above-mentioned calculation formula (1).

  In this embodiment, since the sub processors capable of performing processing are the SPUs 42 and 43, the “total number of sub processors capable of performing processing” is “2”, and “the degree of parallel processing” "Is assumed to be" 1 "as in the first embodiment described above. Therefore, the “number of groups” is “2”. Next, the PU 8 associates each group with each SPU. Here, the SPU 42 is associated with the group with the group ID “Group1”, and the SPU 43 is associated with the group with the group ID “Group2”.

  As described in the first embodiment, the file distribution to each group is based on the number of files and on the file size. Here, the description will be made assuming that distribution is performed according to the number of files.

  It is assumed that the non-volatile storages 48 to 51 store the following number of files to be processed. There are 20 in the non-volatile storage 48, 30 in the non-volatile storage 49, 40 in the non-volatile storage 50, and 50 in the non-volatile storage 51.

  In this case, when the total number of files stored in the nonvolatile storages 48 to 51 is divided by the number of groups calculated in step S2, “70” is obtained. Therefore, 70 files are allocated to each group. Specifically, all the files in the non-volatile storage 48 and 49 are group 1, 20 of the non-volatile storage 50 files are in the “Group 1” group, and the remaining 20 are in the “Group 2” group. All the files in the non-volatile storage 51 are assigned to the “Group2” group.

  As described above, the files stored in the plurality of nonvolatile storages 48 to 51 are assigned to each group.

  Thereafter, the PU 41 performs the processes of steps S3 to S12 in the same manner as in the first embodiment described above. In addition, the SPUs 42 and 43 perform the processing of steps S20 to S26 in FIG. 6 in the same manner as in the first embodiment.

  When the PU 41 performs the process of step S11, the efficiency of the parallel processing changes depending on which of the nonvolatile storages 48 to 51 writes the encrypted file. In order to perform writing most efficiently, it is desirable to sequentially assign encrypted files to the nonvolatile storages 48 to 51. That is, one or a plurality of encrypted files are recursively assigned to the non-volatile storages 49, 50, 51, 48, 49. That is, the encrypted file is written to the nonvolatile storage regardless of the nonvolatile storage stored before the encryption process. As a result, the encrypted file can be evenly and efficiently written to each nonvolatile storage.

  In the present embodiment, the time for issuing the read command in step S8 or the time for issuing the write command in step S11 is almost the time required for file transfer from or to the non-volatile storage 48-51. If it can be ignored, the four non-volatile storages 48 to 51 start the file transfer almost simultaneously. Also, assuming that the access to the RAM 46 from the input / output interface 45 that relays access to each of the non-volatile storages 48 to 51 occurs almost on average, for the group of “Group 1”, all 70 assigned to the group are all included. The time taken to transfer these files to the read buffer corresponding to the group is substantially equal to the time taken to transfer the 30 files stored in the non-volatile storage 49 that transfers the largest number of files. . For the group “Group 2”, the time required to complete the transfer of all files to be processed to the corresponding read buffer is 50 stored in the non-volatile storage 51 that transfers the largest number of files. Is approximately equal to the time it takes to transfer another file. That is, when a plurality of files assigned to a group are distributed and stored in a plurality of nonvolatile storages, file transfer in each nonvolatile storage can be performed asynchronously. Files can be transferred in parallel. For this reason, the time required to transfer all the files assigned to the group can be greatly reduced.

  As described above, in this embodiment, since the time required for file transfer can be greatly reduced, the overall processing time can be shortened, and the processing efficiency can be greatly improved. Furthermore, the efficiency can be improved by executing all executable processes in parallel.

[Example 3]
In each of the above-described embodiments, one one-chip multiprocessor is handled. In this embodiment, an embodiment will be described in which a plurality of one-chip multiprocessors cooperate to perform processing. Hereinafter, the description of the parts common to the first embodiment will be omitted, or the same reference numerals will be used for description.

(1) Configuration The electrical internal configuration of the information processing system S in this embodiment will be described with reference to FIG. In the information processing system S according to the present embodiment, the information processing apparatuses 1B to 1E are connected to each other via the switching network N. The switching network N is a network that connects a plurality of information processing devices to each other, such as the Internet or a LAN (Local Area Network). The information processing apparatus 1B includes a one-chip multiprocessor 60, a RAM 61, a nonvolatile storage 63 connected to these via a bridge 62, and a storage controller 64. The one-chip multiprocessor 60 has one PU 60a as a main processor and six SPUs 60b to 60g as sub processors.

  The information processing apparatus 1 </ b> C includes a one-chip multiprocessor 70, a RAM 71, a nonvolatile storage 73 connected to these via a bridge 72, and a storage controller 74. The one-chip multiprocessor 70 has one PU 70a as a main processor and two SPUs 70b to 70c as sub processors.

  The information processing apparatus 1D includes a one-chip multiprocessor 80, a RAM 81, a nonvolatile storage 83 connected to these via a bridge 82, and a storage controller 84. The one-chip multiprocessor 80 has one PU 80a as a main processor and two SPUs 80b to 80c as sub processors.

  The information processing apparatus 1E includes a one-chip multiprocessor 90, a RAM 91, three nonvolatile storages 93, 94, and 95 connected to these via a bridge 92, and a storage controller 96. The one-chip multiprocessor 90 has one PU 90a as a main processor and two SPUs 90b to 90c as sub processors.

  Each nonvolatile storage 63, 73, 83, 93 to 95 stores various programs such as various control programs such as an operating system, various application programs, and files to be encrypted. Each PU 60a, 70a, 80a, 90a executes various control programs such as an operating system in this embodiment, so that a procedure for connecting to another information processing apparatus via the switching network N, or a connection to the switching network N A function of discriminating another information processing apparatus being used and a configuration of the other information processing apparatus is realized. Specifically, the PU and SPU and the number of them, the nonvolatile storage and the number of each information processing apparatus are determined, and for example, a network management table NTTBL as shown in FIG. 10 is generated. In FIG. 10, the same IDs as those assigned to the respective devices are used for convenience of explanation. In the network management table NTTBL, the terminal ID, the processor ID of the main processor, the processor ID of the sub processor, and the memory ID are stored for each of the information processing apparatuses 1B to 1E. The terminal ID is information for uniquely identifying each of the information processing apparatuses 1B to 1E. The main processor ID is information for uniquely identifying each main processor 60a, 70a, 80a, 90a. The processor ID is information for uniquely identifying each of the sub processors 60b to 60g, 70b to 70c, 80b to 80c, and 90b to 90c. The memory ID is information for uniquely identifying each nonvolatile storage 63, 73, 83, 93-95. Such a network management table NTTBL is stored in the RAMs 61, 71, 81, 91 of the information processing apparatuses 1B to 1E, respectively.

  In addition, the correspondence between each of the non-volatile storages 63, 73, 83, 93 to 95 and these stored files is the same as that of the file pre-management table 460 in the second embodiment described above, and the respective memory IDs. Correspondences with file IDs are stored in the RAMs 61, 71, 81, 91, respectively.

  Other configurations of the information processing apparatuses 1B to 1E are substantially the same as those of the information processing apparatus 1 in the first embodiment described above, and thus the description and illustration thereof are omitted.

(2) Operation Next, the operation in this embodiment will be described with reference to FIG. In the present embodiment, a process for encrypting a plurality of files stored in the six nonvolatile storages 63, 73, 83, 93 to 95 in the same manner as in the above-described embodiments will be described. Here, when the PU 60a is executing the application program, the encrypted program is read from the nonvolatile storage 63 and loaded into the RAM 61 in the same manner as in the first embodiment. And PU41 performs the process of step S1-S2, and calculates the number of groups by the above-mentioned calculation formula (1).

  In step S1, the PU 60a identifies a file to be processed, counts the total number thereof, and refers to the network management table NTTBL in the same manner as in the first embodiment, and can perform processing by referring to the network management table NTTBL. Count the total number of Here, the sub-processors that can perform the processing are SPUs 60b to 60g, 70b to 70c, 80b to 80c, and 90b to 90c, so the total number is “12”.

  Next, in step S2, the PU 60a calculates the number of groups using the calculation formula (1) in the same manner as in the first embodiment described above. Here, the degree of parallelism of processing is “1”. Therefore, here, the number of groups to be subjected to parallel processing is “12”. For this reason, here, the determination result of step S3 becomes affirmative, and the process proceeds to step S4.

  Next, in step S4, the PU 60a divides the files to be processed stored in the six nonvolatile storages into 12 groups. Also in this embodiment, the distribution of files to each group is performed according to the number of files. Here, it is assumed that the number of files to be processed stored in each of the nonvolatile storages 63, 73, 83, 93 to 95 is the same. For example, the number is 50. Then, 50 files stored in each of the six nonvolatile storages 63, 73, 83, and 93 to 95 are divided into 12 groups. For this reason, 25 files stored in each of the non-volatile storages 63, 73, 83, 93 to 95 are divided into two groups. For example, the PU 60 a assigns a group ID “Group1” to 25 files stored in the nonvolatile storage 63 and assigns a group ID “Group2” to the remaining 25 files. Similarly, group IDs “Group3” and “Group4” are assigned to each of 25 files for the files stored in the nonvolatile storage 73. Similarly, group IDs “Group5” to “Group12” are assigned to each of 25 files in the same manner for the files stored in the non-volatile storage 83, 93 to 95.

  Next, in step S5, the PU 8 associates the group IDs “Group1” to “Group12” with the SPUs 60a to 60g, 70b to 70c, 80b to 80c, and 90b to 90c, respectively.

  That is, the file of group ID “Group1” stored in the nonvolatile storage 63 is assigned to the SPU 60b of the one-chip multiprocessor 60, and the file of group ID “Group2” stored in the nonvolatile storage 63 is assigned to the SPU 60c. For the SPUs 60d and 60e, files of group IDs “Group9” and “Group10” stored in the nonvolatile storage 94 are allocated. For the SPUs 60f and 60g, files of group IDs “Group11” and “Group12” stored in the nonvolatile storage 95 are assigned. To the SPUs 70b and 70c of the one-chip multiprocessor 70, files of group I “Group3” and “Group4” stored in the nonvolatile storage 73 are allocated. To the SPUs 80b and 80c of the one-chip multiprocessor 80, files of group IDs “Group5” and “Group6” stored in the nonvolatile storage 83 are assigned. To the SPUs 90b and 90c of the one-chip multiprocessor 90, files of group IDs “Group7” and “Group8” stored in the nonvolatile storage 93 are assigned. These correspondences are shown as shown in FIG. 11, for example.

  The PU 60a performs such grouping and writes information to a processor management table (not shown) as in the above embodiments.

  Next, in step S <b> 6, the PU 60 a of the information processing apparatus 1 </ b> B allocates the read buffer and the write buffer for each group allocated to the SPUs 60 b to 60 g of the own apparatus on the RAM 61. In addition, the PU 60a has a read buffer and a write buffer corresponding to the SPU of each of its own devices in the RAMs 71, 81, and 91 of its own device with respect to each of the PUs 70a, 80a, and 90a of the other information processing devices 1C to 1E. Issue an instruction to allocate a buffer. Each of the PUs 70a, 80a, and 90a allocates a read buffer and a write buffer corresponding to the SPU that each device has to the RAMs 71, 81, and 91 that each device has according to the instruction. Further, the PU 60a writes the memory location of each allocated buffer in the buffer management area, as in the first embodiment described above. Furthermore, the PU 60a provides a file information area in the RAM 61, and writes information in the file information area in the same manner as described above.

  Next, in step S7, the PU 60a generates the same number of processing threads as the number of groups of the cryptographic processing program, assigns a group ID to each processing thread, and assigns each processing thread to the SPUs 60b-60g, 70b-70c, 80b- 80c and 90b to 90c are associated with each other. Then, for the processing threads corresponding to the SPUs 60b to 60g, the PU 60a issues an instruction to execute the corresponding processing thread to each of the SPUs 60b to 60g, and puts them in a synchronization waiting state. Further, the PU 60a, with respect to the processing threads corresponding to the SPUs 70b to 70c, 80b to 80c, and 90b to 90c of the other information processing apparatuses 1C to 1E, is directed to the PUs 70a, 80a, and 90a of the other information processing apparatuses 1C to 1E. Then, an instruction is issued to execute a processing thread corresponding to each SPU of each device, and an instruction is issued to cause each processing thread to be in a synchronization waiting state. As a result, each processing thread is loaded into a local storage (not shown) of the corresponding SPU, executed by each SPU, and enters a synchronization waiting state.

  Next, in step S <b> 8, the PU 60 a instructs the storage controller 64 to read all the files to be processed stored in the nonvolatile storage 63 to the above-described read buffer allocated to the RAM 61. Also, the PU 60a sends all the files to be processed stored in the non-volatile storage 73, 83, 93 to 95 of its own device to each of the PUs 70a, 80a, and 90a of the other information processing devices 1C to 1E. Then, an instruction is issued to read the data to the above-described read buffers allocated to the RAMs 61, 71, 81, 91, respectively. Each of the PUs 70a, 80a, and 90a of the other information processing apparatuses 1C to 1E follows the read command, and the storage controllers 74, 84, and 96 that the respective apparatuses have, respectively, the nonvolatile storages 73, 83, and 93 that the respective apparatuses have A command is issued to read all files to be processed stored in .about.95. As described above, the PU 60a reads the processing target files stored in the non-volatile storages 73, 83, and 93 to 95 connected to the other information processing apparatuses 1C to 1E. An instruction is given to the storage controllers 74, 84, and 96 corresponding to the nonvolatile storages 73, 83, and 93 to 95 via the PUs 70a, 80a, and 90a of 1E. On the other hand, each storage controller 64, 74, 84, 96 reads all corresponding files to be processed stored in each nonvolatile storage 63, 73, 83, 93-95 in accordance with the above read commands. Read to buffer.

  At the same time as the read command, the PU 60a cancels the synchronization waiting state of each processing thread assigned to the SPUs 60b to 60g, and causes each SPU to start executing the processing thread. At the same time, the PU 60a processes each processing thread assigned to each SPU of the other information processing apparatuses 1C to 1E via each PU 70a, 80a, 90a of the other information processing apparatuses 1C to 1E. The thread is released from the synchronization waiting state, and each SPU is started to execute the processing thread. Thereafter, the same processing as steps S9 to S11 is performed in the same manner as in the first embodiment described above. In step S11, when the encrypted file written in the write buffer is written to the nonvolatile storage 63, 73, 83, 93 to 95, the PU 60a performs the storage controller 64 for writing to the nonvolatile storage 63. A write command is issued to each of the non-volatile storages 73, 83, 93 to 95, and the write commands are respectively sent to the corresponding storage controllers 74, 84, 96 via the corresponding PUs 70a, 80a, 90a. Put out. As for the allocation of the non-volatile storage for writing the encrypted file, the encrypted file may be sequentially allocated to the non-volatile storage 73, 83, 93 to 95 as in the second embodiment.

  With the configuration as described above, a file stored in a non-volatile storage connected to each of different information processing apparatuses can be assigned to each sub-processor of the one-chip multiprocessor of each information processing apparatus and processed in parallel. it can. That is, it is possible to distribute the processing to the one-chip multiprocessors of each of the plurality of information processing apparatuses and to process the subprocessors of each one-chip multiprocessor in parallel. As a result, the processing time can be greatly shortened and the processing efficiency can be greatly improved.

  Note that the above-described information system S is preferably configured under the following environment, for example. The transfer speed of the file via the switching network N is sufficiently fast, and the time required to transfer the file between the nonvolatile storage and the RAM via the bridge in one information processing apparatus, and each information processing apparatus In this environment, the time taken to transfer a file between the connected nonvolatile storage and the RAM via the switching network N is substantially the same. In such an environment, a one-chip processor of an information processing apparatus hardly causes a time loss in processing a file stored in a nonvolatile storage connected to another information processing apparatus. It is.

[Modification]
<Modification 1>
In the first embodiment described above, the HD 33 that is a non-volatile storage is provided outside the information processing apparatus 1. In the second and third embodiments described above, each of the nonvolatile storages 48 to 51, 63, 73, 83, and 93 to 95 is inside each information processing apparatus and outside each one-chip multiprocessor. It comprised so that it might provide. In the present invention, each nonvolatile storage may be provided either outside or inside the information processing apparatus 1, or may be arranged outside or inside the one-chip multiprocessor. Further, what is used as the non-volatile storage may be various storage devices and storage media such as a hard disk, a flash memory, and a DVD.

  In the first embodiment described above, the HD 33 is connected to the information processing apparatus 1 via the USB 22, but the present invention is not limited to this.

  In the first embodiment described above, the HD 33 is used as the nonvolatile storage for storing the processing target file, and the controller 23 is used as the storage controller. However, the present invention is not limited to this, and various storage devices such as a DVD and a flash memory and various storage media may be used as nonvolatile storage for storing files to be processed. For example, when the file to be processed is stored on the DVD 32 in FIG. 1, the DVD driver 21 functions as the storage controller described above. That is, in step S8, the PU 8 issues an instruction to read the file to be processed stored in the DVD 32 to the DVD driver 21. In step S11, the PU 8 instructs the DVD driver 21 to write the processed file to the DVD 32. The DVD driver 21 reads and writes a file from the DVD 32 according to these instructions. Further, when the file to be processed is stored in the flash memory 20 in FIG. 1, the flash memory controller 31 functions as the above-described storage controller. That is, the PU 8 issues an instruction to read the file to be processed stored in the flash memory 20 to the flash memory controller 31 in step S8, and after the processing to the HD 33 to the flash memory controller 31 in step S11. A file write command is issued, and the flash memory controller 31 reads and writes the file to the flash memory 20 in accordance with these commands.

  In addition, a non-volatile storage is provided in another information processing apparatus different from the information processing apparatus according to each embodiment described above, and the other information processing apparatus and the information processing apparatus according to each embodiment described above are connected via a network. The one-chip multiprocessor connected to the information processing apparatus according to each of the above embodiments may access the nonvolatile storage via the network and the other information processing apparatus.

  In the second and third embodiments described above, the storage controller 53 and the storage controllers 64, 74, 84, and 96 are configured to control data reading and data writing with respect to a plurality of nonvolatile storages, respectively. . However, the present invention is not limited to this, and one nonvolatile storage controller may be provided for each nonvolatile storage. In this case, in step S8, the main processor issues a read command for the processing target file stored in each nonvolatile storage to each storage controller corresponding to each nonvolatile storage, and in step S11, each nonvolatile memory. A command to write a file to the storage device after processing is issued to each storage controller corresponding to each nonvolatile storage, and each storage controller reads and writes a file to each corresponding nonvolatile storage according to these commands. Do.

  Further, in each of the above-described embodiments, the nonvolatile storage and the storage controller are provided separately, but they may be provided integrally.

  In each of the above-described embodiments, an asymmetric multi-core processor having a plurality of cores in one chip and having different configurations of the main processor and sub-processor is used as the multi-processor. However, the present invention is not limited to this, and a multiprocessor having a plurality of single processors or a single-core multiprocessor may be used. For example, as shown in FIGS. A symmetric multiprocessor having a plurality of processors having the same configuration may be used. A multiprocessor 500 shown in FIG. 12A includes two processors 501 and a memory controller 505 ′ connected to them via a bus. Each processor 501 includes a CPU 502 as a core, and includes an L1 cache 503 and an L2 cache 504 ′ as cache memories. A multiprocessor 500 ′ shown in FIG. 12B includes two processors 501 ′, a memory controller 505 connected to the processors 501 ′ via a bus, and caches an L2 cache 504 ′ shared by the processors 501 ′. Prepare as memory. Each processor 501 ′ includes a CPU 502 as a core and an L1 cache 503 as a cache memory. In the multiprocessors 500 and 500 ′ having such a configuration, at least one of the cache memories 502, 503, 504, and 504 ′ may function as a local memory, or each processor 501 may be configured. , 501 ′ may be provided with a separate local memory. When such a symmetric multiprocessor having a plurality of processors having the same configuration is used, any one of the plurality of processors functions as, for example, the PU 8 (main processor) in the first embodiment described above, and the like. These processors may function as SPU3 (sub-processor). Further, even when any one of the plurality of processors is caused to function as a main processor, the group in which the one processor is grouped in step S4 in the above-described first embodiment is assigned in step S5. It may be a processor.

<Modification 2>
In each of the embodiments described above, the encryption process is performed on a plurality of files. However, the present invention is not limited to this. For example, a decryption process for canceling encryption, a codec conversion process, an image process, a virus scan, and a file compression process can be performed for a plurality of files at once. Or various processes, such as an expansion | deployment process, may be sufficient.

<Modification 3>
In the above-described embodiments, the operating system is configured to be executed by the main processor. However, the present invention is not limited to this, and the sub processor may be configured to execute a program that forms a part of the operating system (for example, a part of a device driver or a system program). Further, as an operating system, a dedicated operating system for controlling the entire sub-processor may be provided.

<Modification 4>
In each of the above-described embodiments, the file assigned to the group corresponding to each SPU is read into the read buffer on the RAM and processed. However, the present invention is not limited to this, and the configuration is such that the processing target file assigned to the SPU is stored in the local storage of each SPU, and this is written to the write buffer on the RAM after the encryption process. You may do it.

<Modification 5>
In each of the above-described embodiments, the file is distributed to each group according to the number of files or the file size. However, the present invention is not limited to this. For example, file attribute information such as file type, file update date and time, and file usage frequency may be used.

<Modification 6>
In the third embodiment described above, each process shown in FIG. 3 described above is performed by the PU 60a, but may be performed by another PU. In steps S14 and S15 described above, a read buffer and a write buffer corresponding to each group are provided in each RAM in the same information processing apparatus as each SPU. However, the present invention is not limited to this, and each buffer corresponding to the SPU of another information processing apparatus may be provided in the RAM of another information processing apparatus, or each group may be supported on one of the RAMs. It may be configured to provide all the buffers.

  Further, each one-chip multiprocessor 60, 70, 80, 90 is configured to be provided in different information processing apparatuses 1B to 1E, but may be configured to be provided in one information processing apparatus.

  The above description of each embodiment is an example of the present invention. For this reason, the present invention is not limited to the above-described embodiments, and various modifications can be made even outside the above-described embodiments as long as they do not depart from the technical idea according to the present invention. Of course.

  The present invention is suitable for information processing technology that uses a multiprocessor to process a plurality of files stored in a nonvolatile storage.

It is a block diagram which illustrates the internal structure of the information processing apparatus which concerns on one Example of this invention. It is a figure which illustrates the processor management table concerning the Example. It is a flowchart which illustrates the flow of operation | movement of the main processor which concerns on the same Example. It is a figure which illustrates the information memorized by the file information area concerning the example. It is a figure which illustrates the information memorized by the buffer management area concerning the example. It is a flowchart which illustrates the flow of operation | movement of the sub processor based on the Example. It is a block diagram which illustrates the internal structure of the information processing apparatus which concerns on the other Example of this invention. It is a figure which illustrates the pre-file management table which concerns on the same Example. It is a block diagram which illustrates the internal structure of the information processing apparatus which concerns on the other Example of this invention. It is a figure which illustrates the network management table which concerns on the Example. It is a figure which illustrates the correspondence of file ID of the grouped file which concerns on the Example, memory ID of the non-volatile storage in which the said file is stored, processor ID of a sub processor, and group ID. It is a block diagram which illustrates the internal structure of the multiprocessor which concerns on the other Example of this invention.

Explanation of symbols

1, 1A, 1B, 1C, 1D, 1E ... information processing device, 2 ... one-chip multiprocessor, 3, 3a, 3b, 3c, 3d, 3e, 3f, 3g, 3h, 42, 43, 60b, 60c, 60d, 60e, 60f, 60g, 70b, 70c, 80b, 80c, 90b, 90c... Sub-processor, 4, 4a, 4b, 4c, 4d, 4e, 4f, 4g, 4h, 9,. -Processor core, 5, 5a, 5b, 5c, 5d, 5e, 5f, 5g, 5h ... local storage, 6, 6a, 6b, 6c, 6d, 6e, 6f, 6g, 6h, 12 ... memory Flow controller 7, 7a, 7b, 7c, 7d, 7e, 7f, 7g, 7h, 13... Direct memory access controller, 8, 41, 60a, 70a, 80a, 90a. Processor: 10 ... L1 cache, 11 ... L2 cache, 15 ... Memory controller, 16, 46, 61, 71, 81, 91 ... RAM, 17 ... Input / output interface, 18. South bridge, 20 ... flash memory, 31 ... flash memory controller, 64, 74, 84, 96 ... storage controller, 32 ... DVD, 33 ... HD, 48, 49, 50, 51, 63, 73, 83, 93, 94, 95... Nonvolatile storage, 47, 62, 72, 82, 92... Bridge, 160... Processor management table, 460. , N ... switching network, S ... information processing system, NTTBL ... network management table

Claims (24)

An information processing method in which a multiprocessor including a main memory and a plurality of processors performs predetermined processing on a plurality of processing target files stored in a nonvolatile storage connected to the multiprocessor,
One of the processors, a grouping step for dividing the plurality of files to be processed into a plurality of file groups;
An assigning step in which the one processor assigns each file group divided in the grouping step to at least one target processor among the plurality of processors;
A setting step in which the one processor sets a read buffer corresponding to each file group divided in the grouping step in the main memory;
An activation instructing step for instructing activation of a processing program for performing the predetermined processing to the target processor to which the one processor has allocated the file group in the allocation step;
A group of files to which the processing target file belongs in the setting step with respect to the processing target file stored in the non-volatile storage for a storage controller in which the one processor controls reading and writing of data to and from the non-volatile storage. A reading instruction step for instructing reading to each of the reading buffers set in the main memory in association with the information processing method. The target processor has a local memory;
The storage controller reads each of the processing target files instructed in the reading instructing step into a reading buffer set in the main memory in association with the file group to which the processing target files belong in the setting step Steps,
A second setting step in which the one processor sets a write buffer corresponding to each file group divided in the grouping step in the main memory;
The target processor stores the processing program instructed in the start instructing step in the local memory of the target processor, starts the program, and stores it in the read buffer corresponding to the file group assigned to the target processor. An execution step of performing the predetermined processing on the read processing target file and writing the processed file after the processing into the write buffer corresponding to the file group assigned to the target processor. The information processing method according to claim 1. A write instruction step in which the one processor instructs the storage controller to write the processed file written in the write buffer in the execution step to the nonvolatile storage;
The information processing method according to claim 2, further comprising: a writing step in which the storage controller writes the processed file instructed in the writing instructing step into the non-volatile storage. The target processor has a direct memory access controller that controls reading and writing of data to the main memory;
In the execution step, the processing target file corresponding to the file group assigned to the target processor is read from the read buffer via the direct memory access controller, and the direct memory access controller is The information processing method according to claim 2, wherein the post-processing file corresponding to the file group assigned to the target processor is written to the write buffer. 2. The information processing method according to claim 1, wherein in the grouping step, the plurality of files to be processed are divided into a number of file groups having an upper limit on the number of the processors. In the grouping step, the number of the file groups is determined based on the number of processors and the number of processing programs that can be executed in parallel to perform the predetermined process, and the determined number of file groups Dividing a plurality of files to be processed,
In the assigning step, the same number of processors as the number of file groups divided in the grouping step among the plurality of processors are selected as the target processors, and the file groups are assigned to the selected target processors. The information processing method according to claim 5, wherein: In the grouping step, the files are divided into the file groups so that the processing amounts of the target processors performing predetermined processing on the files in the execution step are substantially the same. The information processing method according to claim 2. The information processing method according to claim 7, wherein in the grouping step, the files are divided into the file groups so that the total number of the files belonging to the file groups is substantially the same. 8. The information according to claim 7, wherein, in the grouping step, the files are divided into the file groups so that the total amount of all the files belonging to the file groups is substantially the same. Processing method. The one processor is a main processor;
The information processing method according to claim 1, wherein the target processor is a sub-processor. A plurality of the nonvolatile storages are connected to the multiprocessor;
In the writing step, for each file instructed in the writing instruction step, one non-volatile storage is selected from the plurality of non-volatile storages in the order written in the writing buffer, and the non-volatile storage is written, 4. When selecting one non-volatile storage, a non-volatile storage different from the non-volatile storage to which the file written in the write buffer is written immediately before the file is written is selected. The information processing method described. The nonvolatile storage and the storage controller are connected to an information processing device connected to the multiprocessor via a network,
In the reading instruction step, the processing target file instructed in the reading instruction step is associated with the file group to which the processing target file belongs in the setting step with respect to the storage controller via the information processing apparatus. The information processing method according to claim 1, wherein each of the read buffers set in the main memory is instructed to be read. An information processing method in which a multiprocessor including a main processor and a plurality of sub-processors having a local memory performs predetermined processing on a plurality of processing target files stored in a nonvolatile storage connected to the multiprocessor. There,
The main processor divides the plurality of files to be processed into a plurality of file groups;
The main processor assigns each group of files divided in the grouping step to the sub-processors, and
A setting step in which the main processor sets a read buffer corresponding to each file group divided in the grouping step in the local memory of each sub-processor to which each file group is assigned;
An activation instruction step for instructing activation of a processing program for performing the predetermined processing to the sub processor to which the main processor has allocated the file group in the allocation step;
For the storage controller that controls the reading and writing of data to and from the nonvolatile storage, the main processor converts the processing target file stored in the nonvolatile storage into the file group to which the processing target file belongs in the setting step. A reading instruction step for instructing reading to each of the reading buffers set in the local memory in association with each other. A first multiprocessor including a first main memory and a plurality of first processors and a second multiprocessor including a second main memory and a plurality of second processors are connected via a network, and the first or first 2 is an information processing method for performing predetermined processing on a plurality of processing target files stored in a non-volatile storage connected to a multiprocessor,
A grouping step in which one first processor among the plurality of first processors divides the processing target file into a plurality of file groups;
An allocation step in which the one first processor allocates each file group divided in the grouping step to at least one target processor of the plurality of first processors and second processors;
The one first processor sets a read buffer corresponding to each file group allocated to the first processor among the target processors in the first main memory, and one of the plurality of second processors. A setting step for instructing the second processor to set, in the second main memory, a read buffer corresponding to each file group allocated to the second processor among the target processors;
A start instruction step in which the one first processor instructs a target processor to which the file group is assigned in the assignment step to start a processing program for performing the predetermined process;
The processing target file stored in the non-volatile storage belongs to the processing target file in the setting step to a storage controller in which the one first processor controls reading and writing of data to and from the non-volatile storage. A reading instruction step for instructing reading to each reading buffer set in at least one of the first main memory and the second main memory in association with a file group. Processing method. In the reading instruction step, when the nonvolatile storage is connected to the second multiprocessor, the processing target file stored in the nonvolatile storage is transmitted to the storage controller via the one second processor. Are read in the reading buffer set in at least one of the first main memory and the second main memory in association with the file group to which the processing target file belongs in the setting step. The information processing method according to claim 14. An information processing system in which a multiprocessor including a main memory and a plurality of processors performs predetermined processing on a plurality of processing target files stored in a nonvolatile storage connected to the multiprocessor,
One of the processors is
A grouping means for dividing the plurality of files to be processed into a plurality of file groups;
Assigning means for assigning each file group divided by the grouping means to at least one target processor among the plurality of processors;
Setting means for setting a read buffer corresponding to each file group divided by the grouping means in the main memory;
Start instruction means for instructing a target processor to which the assigning means assigns the file group to start a processing program for performing the predetermined processing;
For the storage controller that controls reading and writing of data to and from the nonvolatile storage, the processing target file stored in the nonvolatile storage is associated with the file group to which the processing target file belongs by the setting unit. An information processing system comprising: a read instructing unit for instructing each read to a read buffer set in a main memory. A first multiprocessor including a first main memory and a plurality of first processors and a second multiprocessor including a second main memory and a plurality of second processors are connected via a network, and the first or first 2 is an information processing system for performing predetermined processing on a plurality of processing target files stored in a non-volatile storage connected to a multiprocessor,
One first processor of the plurality of first processors is
A grouping means for dividing the file to be processed into a plurality of file groups;
Assigning and assigning each file group divided by the grouping means to at least one target processor of the plurality of first processors and second processors;
A read buffer corresponding to each file group allocated to the first processor among the target processors is set in the first main memory, and the target is set for one second processor among the plurality of second processors. Setting means for instructing to set, in the second main memory, a read buffer corresponding to each file group allocated to the second processor among the processors;
Start instruction means for instructing a target processor to which the assigning means assigns the file group to start a processing program for performing the predetermined processing;
For the storage controller that controls reading and writing of data to and from the nonvolatile storage, the processing target file stored in the nonvolatile storage is associated with the file group to which the processing target file belongs by the setting unit. An information processing system comprising: a read instructing unit that instructs reading to a read buffer set in at least one of the first main memory and the second main memory. An information processing apparatus that includes a multiprocessor including a main memory and a plurality of processors, and performs predetermined processing on a plurality of processing target files stored in a nonvolatile storage connected to the multiprocessor,
One of the processors is
A grouping means for dividing the plurality of files to be processed into a plurality of file groups;
Allocating means for allocating each file group divided by the grouping means to at least one target processor among the plurality of processors;
Setting means for setting a read buffer corresponding to each file group divided by the grouping means in the main memory;
Start instruction means for instructing start of a processing program for performing the predetermined processing to the target processor to which the assigning means has assigned the file group;
For the storage controller that controls reading and writing of data to and from the nonvolatile storage, the processing target file stored in the nonvolatile storage is associated with the file group to which the processing target file belongs by the setting unit. An information processing apparatus comprising: a read instructing unit for instructing reading to each read buffer set in a main memory. A second information processing apparatus including a first multiprocessor including a first main memory and a plurality of first processors, and including a second multiprocessor including a second main memory and a plurality of second processors, and a network. An information processing apparatus that performs predetermined processing on a plurality of processing target files stored in a non-volatile storage connected to the first or second multiprocessor,
One first processor of the plurality of first processors is
A grouping means for dividing the file to be processed into a plurality of file groups;
Allocating means for allocating each file group divided by the grouping means to at least one target processor among the plurality of first processors and the second processor,
A read buffer corresponding to each file group allocated to the first processor among the target processors is set in the first main memory, and the target is set for one second processor among the plurality of second processors. Setting means for instructing to set, in the second main memory, a read buffer corresponding to each file group allocated to the second processor among the processors;
Start instruction means for instructing a target processor to which the assigning means assigns the file group to start a processing program for performing the predetermined processing;
For the storage controller that controls reading and writing of data to and from the nonvolatile storage, the processing target file stored in the nonvolatile storage is associated with the file group to which the processing target file belongs by the setting unit. An information processing apparatus comprising: a read instructing unit that instructs reading to a read buffer set in at least one of the first main memory and the second main memory. A multiprocessor that includes a main memory and a plurality of processors, and performs predetermined processing on a plurality of files to be processed stored in a nonvolatile storage connected to the multiprocessor,
One of the processors is
A grouping means for dividing the plurality of files to be processed into a plurality of file groups;
Assigning means for assigning each file group divided by the grouping means to at least one target processor among the plurality of processors;
Setting means for setting a read buffer corresponding to each file group divided by the grouping means in the main memory;
Start instruction means for instructing a target processor to which the assigning means assigns the file group to start a processing program for performing the predetermined processing;
For the storage controller that controls reading and writing of data to and from the nonvolatile storage, the processing target file stored in the nonvolatile storage is associated with the file group to which the processing target file belongs by the setting unit. A multiprocessor comprising: a read instructing unit for instructing each read to a read buffer set in a main memory. A first multiprocessor comprising a first main memory and a plurality of first processors, and a second multiprocessor comprising a second main memory and a plurality of second processors, connected via a network; A multiprocessor that performs predetermined processing on a plurality of files to be processed stored in a connected non-volatile storage,
One first processor of the plurality of first processors is
A grouping means for dividing the file to be processed into a plurality of file groups;
Allocating means for allocating each file group divided by the grouping means to at least one target processor among the plurality of first processors and second processors;
A read buffer corresponding to each file group allocated to the first processor among the target processors is set in the first main memory, and the target is set for one second processor among the plurality of second processors. Setting means for instructing to set, in the second main memory, a read buffer corresponding to each file group allocated to the second processor among the processors;
Start instruction means for instructing a target processor to which the assigning means assigns the file group to start a processing program for performing the predetermined processing;
For the storage controller that controls reading and writing of data to and from the nonvolatile storage, the processing target file stored in the nonvolatile storage is associated with the file group to which the processing target file belongs by the setting unit. A first multiprocessor, comprising: a read instructing unit that instructs reading to a read buffer set in at least one of the first main memory and the second main memory. A multiprocessor including a main memory and a plurality of processors is an information processing program for performing predetermined processing on a plurality of processing target files stored in a nonvolatile storage connected to the multiprocessor,
A step of dividing the plurality of files to be processed into a plurality of file groups;
Assigning each file group divided in the grouping step to at least one target processor of the plurality of processors;
A setting step of setting a read buffer corresponding to each file group divided in the grouping step in the main memory;
An activation instruction step for instructing activation of a processing program for performing the predetermined processing to the target processor to which the file group is allocated in the allocation step;
For the storage controller that controls reading and writing of data to and from the nonvolatile storage, the processing target file stored in the nonvolatile storage is associated with the file group to which the processing target file belongs in the setting step. An information processing program for causing a single processor of the multiprocessor to execute a read instruction step for instructing reading to a read buffer set in a main memory. A first multiprocessor including a first main memory and a plurality of first processors and a second multiprocessor including a second main memory and a plurality of second processors are connected via a network, and the first or first 2 is an information processing program for performing predetermined processing on a plurality of processing target files stored in a non-volatile storage connected to a multiprocessor,
A step of dividing the file to be processed into a plurality of file groups;
An allocating step of allocating each file group divided in the grouping step to at least one target processor among the plurality of first processors and second processors;
A read buffer corresponding to each file group allocated to the first processor among the target processors is set in the first main memory, and the target is set for one second processor among the plurality of second processors. A setting step for instructing to set, in the second main memory, a read buffer corresponding to each file group allocated to the second processor among the processors;
An activation instruction step for instructing activation of a processing program for performing the predetermined processing to the target processor to which the file group is allocated in the allocation step;
For the storage controller that controls reading and writing of data to and from the nonvolatile storage, the processing target file stored in the nonvolatile storage is associated with the file group to which the processing target file belongs in the setting step. A read instruction step for instructing reading to each of the read buffers set in at least one of the first main memory and the second main memory. Information processing program.   24. A computer-readable storage medium storing the information processing program according to claim 22.

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