JP2018063505A - Memory management control unit, memory management control method and memory management control program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve response of a memory management control unit in a swap-out according to one embodiment.SOLUTION: A memory management control unit according to one embodiment includes a memory including a data area and a swap area, and a processor. The processor compresses data at a first compression rate when predetermined conditions are met in swapping data, stored in the data area, out to the swap area. The processor compresses data at a second compression rate lower than the first compression rate when the predetermined conditions are not met in swapping the data, stored in the data area, out to the swap area.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a memory management control device, a memory management control method, and a memory management control program.

  In recent years, the size of physical memory used by an operating system (OS) in memory management control devices has increased. Note that the memory management control device includes, for example, a device that performs memory management and control, such as a mobile phone, a smartphone, a tablet terminal, an in-vehicle device (for example, a car navigation system), and a ubiquitous product. In order to cope with an increase in the size of the physical memory used by the OS, for example, a technique for efficiently using the physical memory is known (for example, Patent Document 1 and Patent Document 2).

JP 2014-1116017 A JP 2002-24082 A

  In order to use the memory efficiently, the data stored in the memory may be swapped out to the swap area, and the data may be compressed when the data is swapped out. In this case, swap-out has overhead such as searching for a memory area to be swapped, compression of the memory area to be swapped, and memory copy for swap-out. And, for example, when there is insufficient performance in the processing capacity of the processor that performs these processes and the speed of reading and writing of the memory, or when those resources are used by other processes, the response of the memory management control device is It may be late.

  In one aspect, the present invention aims to improve the response of the memory management control device at the time of swap-out.

  A memory management control device according to one aspect of the present invention includes a memory including a data area and a swap area, and a processor. When swapping out data stored in the data area to the swap area, the processor compresses the data at the first compression rate if a predetermined condition is satisfied. When swapping out the data stored in the data area to the swap area, the processor compresses the data at a second compression rate lower than the first compression rate if a predetermined condition is not satisfied. .

  The response of the memory management control device at the time of swap-out can be improved.

It is a figure which shows the hardware constitutions of an example memory management control apparatus. It is a figure which illustrates the area | region of a physical memory. It is a figure which shows the area | region securing process of an example memory. It is a figure which shows the area | region ensuring process of the memory which concerns on 1st Embodiment. It is a figure which illustrates the swap-out process which concerns on 1st Embodiment. It is a figure which illustrates the history information concerning an embodiment. It is a figure which illustrates the swap information which concerns on 1st Embodiment. It is a figure which illustrates the swap-out process which concerns on 2nd Embodiment. It is a figure which illustrates the swap information which concerns on 2nd Embodiment. It is a figure which illustrates the operation | movement flow of the swap-in process which concerns on 2nd Embodiment.

  Hereinafter, some embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol is attached | subjected to the corresponding element in several drawing.

  FIG. 1 is a diagram illustrating a hardware configuration of an exemplary memory management control device 100. Note that the memory management control device 100 may be, for example, a mobile phone, a smartphone, a tablet terminal, an in-vehicle device (for example, a car navigation system), a ubiquitous product, or the like. The memory management control device 100 may include, for example, a processor 101, a memory 102, a storage device 103, an input device 104, and a display device 105. Note that the processor 101, the memory 102, the storage device 103, the input device 104, and the display device 105 are connected to each other via a bus 110, for example.

  The processor 101 controls each unit of the memory management control device 100. Further, the processor 101 executes a procedure of an operation flow to be described later by reading and executing a memory management control program stored in the memory 102, for example. The processor 101 may be a single processor or a processor including a multiprocessor and a multicore, for example.

  The memory 102 is, for example, a semiconductor memory, and may include a RAM area and a ROM area. Note that the memory 102 is a memory that is actually mounted in the memory management control device 100, and in the following description, the memory 102 may be referred to as a physical memory 102. The storage device 103 is a semiconductor memory such as a flash memory such as eMMC, a hard disk, or an external storage device. Note that RAM (ram) is an abbreviation for Random Access Memory. ROM (ROM) is an abbreviation for Read Only Memory. eMMC (EMC) is an abbreviation for Embedded Multi Media Card.

  The input device 104 is a device that accepts inputs such as buttons and keys, for example. The display device 105 may be a display, for example. The input device 104 and the display device 105 may be combined and implemented as a touch panel. Further, the memory management control device 100 may further include a communication interface that transmits / receives data to / from the outside in accordance with an instruction from the processor 101. The memory management control device 100 may also include other input / output devices such as a voice output device and a voice input device.

  As described above, for example, in the memory management control device 100, the size of the physical memory used by the operating system has increased. In order to cope with this, for example, if a large-capacity physical memory is mounted, the cost of the memory management control device 100 increases. Therefore, a memory saving control technique for efficiently using a memory with a limited capacity is desired.

  In an example of memory saving control, a swap area may be provided in the physical memory 102, and swap target data on the physical memory 102 may be compressed into the swap area and swapped out. FIG. 2 is a diagram illustrating an area of the physical memory 102 when a swap area is provided in the physical memory 102. In this case, a swap area 201 is secured in a part of the physical memory 102. Further, an area used as a normal memory other than the swap area 201 on the physical memory 102 is hereinafter referred to as a data area 202. In the data area 202, for example, data referred to by an operating system, an application, or the like is stored. When the memory is insufficient, the swap target data is compressed and swapped out in the swap area 201 secured in the physical memory 102. Since the data swapped out to the swap area 201 is compressed, the memory can be used efficiently. The data area 202 may include a management area 203 in which information used for memory management is stored. The management area 203 may store information such as history information 600 and swap information 700 and 900, which will be described later. As an example of a memory management method in which the swap area 201 is provided in the physical memory 102 in this way, there is a method called Linux (registered trademark) ZRAM.

  FIG. 3 is a diagram illustrating an area securing process of the exemplary memory 102. For example, when an area reservation request for requesting to secure a memory area in the data area 202 is input from another application or the like, the processor 101 may start the exemplary area reservation process of FIG.

  In step 301 (hereinafter, the step is described as “S”, for example, expressed as S301), the processor 101 determines whether or not the memory 102 has sufficient free space to secure the requested memory area. To do. If there is free space in the memory 102 (there is S301), the flow proceeds to S306. In this case, in S306, the processor 101 secures the area requested by the memory securing request in a free area, and the operation flow ends. On the other hand, when there is no free space in the memory 102 (S301 is absent), the flow proceeds to S302.

  In S302, the processor 101 searches the data area 202 for a memory area to be swapped. For example, the processor 101 may search for a memory area to be swapped by LRU (Least Recently Used). In the LRU, for example, a memory area in which data that has passed the most time since it was last referred to is stored in the data stored in the data area 202 of the memory 102. The memory area may be a page unit area, for example.

  In S303, the processor 101 sets the searched memory area as a swap target. In S304, the processor 101 compresses data stored in the memory area to be swapped at a predetermined compression rate. In step S305, the processor 101 swaps out the compressed data to the swap area 201. In S306, the processor 101 releases the memory area after swapping out the data, secures the area requested by the memory securing request, and the operation flow ends.

  For example, as described above, it is assumed that the swap area 201 is provided in the memory 102 and the data is compressed at a predetermined compression rate and swapped out when the memory 102 has insufficient free space. In this case, swap-out has overhead such as searching for a memory area to be swapped, compression of the memory area to be swapped, and memory copy for swap-out. And, for example, when there is insufficient performance in the processing capacity of the processor that performs these processes and the speed of reading and writing of the memory, or when those resources are used by other processes, the response of the memory management control device is It may be late. Therefore, for example, a technique that can improve the response of the apparatus is desired.

Therefore, in the embodiment, the compression rate at the time of compressing the data to be swapped is dynamically changed, thereby improving the response of the memory management control device 100 and improving the performance of the memory management control device 100. To do. In the embodiment, in order to dynamically change the compression rate at the time of data swap-out to the swap area 201, the following information is used for the determination of determining the swap-out compression rate.
(1) Operation status of the memory management control device 100 (2) Processor usage rate (3) Time interval from swap-out to swap-in to the swap area 201

  Regarding (1), for example, even if the compression processing load is high and the response of the memory management control device 100 is delayed, if the user does not use the memory management control device 100, the response will not be felt. . Therefore, for example, if the operation status of the memory management control device 100 is not in operation, the compression rate may be set to a high compression rate and compression may be executed.

  With regard to (2), for example, when the processor usage rate is already high, increasing the compression rate causes a further load on the processor 101. For this reason, for example, it is preferable to reduce the compression ratio to reduce the load on the processor 101.

  With regard to (3), for example, when the time interval from swap-out to swap area 201 to swap-in is short, there is a high possibility that swap-in will be performed immediately after swap-out. If the data is not stored in the swap area 201 for a long period of time, compression with a low compression rate is preferable to compression with a low compression rate, which can reduce the time and processing load required for compression. . On the other hand, if the data is stored in the swap area 201 for a long period of time, the memory can be used efficiently by compressing the data at a high compression rate and suppressing the area that occupies the memory 102.

  The processor 101 can suppress an excessive load on the processor 101 by determining the compression rate at the time of swap-out in consideration of the above information, for example. On the other hand, when it is determined that the memory management control device 100 is not used based on the situation where the processing capacity of the processor 101 is sufficient or the operation status of the memory management control device 100, a high compression ratio is set. The efficiency of using the memory 102 can be increased. The first embodiment will be described below.

<First Embodiment>
FIG. 4 is a diagram showing an area securing process of the memory 102 according to the first embodiment. For example, when an area securing request for securing a memory area in the data area 202 is input from another application or the like, the processor 101 starts the area securing process according to the first embodiment of FIG. Good.

  In S401, the processor 101 determines whether or not there is free space in the memory. When there is free space in the memory (there is S401), this operation flow ends. On the other hand, if there is no free space in the memory (S401 is none), the flow proceeds to S402.

  In S402, the processor 101 searches the data area 202 for a memory area to be swapped. For example, the processor 101 may search for a memory area to be swapped by LRU. In S403, the processor 101 sets the searched memory area as a swap target. In S404, the processor 101 performs swap-out processing. Details of the swap-out process will be described later with reference to FIG. 5. In the swap-out process, data is compressed by dynamically changing the compression rate, and swap-out is executed. In step S405, the processor 101 releases the memory area after swapping out the data, secures the memory area requested by the area securing request, and the operation flow ends.

  FIG. 5 is a diagram illustrating a swap-out process according to the first embodiment. For example, when the processor 101 proceeds to S <b> 404 in FIG. 4, the processor 101 may start the swap-out process in FIG. 5.

  In step S <b> 501, the processor 101 acquires operation information indicating the operation status of the memory management control device 100. In step S <b> 502, the processor 101 may determine whether or not the memory management control device 100 is in use based on the acquired operation information indicating the operation status. For example, the processor 101 may use information as to whether or not the display screen of the display device 105 of the memory management control device 100 is turned off as operation information indicating the operation status. In this case, if the display screen of the display device 105 is turned off, the processor 101 may determine that the user is not using the memory management control device 100. On the other hand, when the display screen of the display device 105 is lit, the processor 101 may determine that the user is using the memory management control device 100. In another embodiment, a user may use a login status to the memory management control device 100 as operation information indicating the operation status. If the memory management control device 100 is not used in S502 (S502 is not used), the flow proceeds to S509, and the processor 101 sets the compression rate to the first compression rate. The first compression rate is a higher compression rate than a second compression rate described later. In this way, in a situation where it is estimated that the memory management control device 100 is not in use, even if the response decreases, the user is unlikely to experience it, and the processor 101 performs compression using a high compression rate. Yes, you may save memory. On the other hand, if the memory management control device 100 is in use in S502 (S502 is in use), the flow proceeds to S503.

  In step S <b> 503, the processor 101 acquires information on the usage rate of the processor 101. In S504, the processor 101 determines whether the usage rate of the processor 101 is high. For example, the processor load average may be used as the usage rate of the processor 101. For example, the processor 101 may determine whether the usage rate of the processor is high based on whether the load average exceeds a predetermined threshold. For example, the processor 101 may determine that the usage rate is high when the usage rate of the processor 101 is equal to or greater than a predetermined threshold. On the other hand, the processor 101 may determine that the usage rate is low if the usage rate of the processor 101 is lower than a predetermined threshold. For example, when the swap target data is compressed at a high compression rate in a state in which the predetermined threshold is exceeded, the predetermined threshold is set to a value that can determine that the response of the memory management control device 100 is likely to be affected. May be. If the usage rate of the processor 101 is high in S504 (YES in S504), the flow proceeds to S507. On the other hand, when the usage rate of the processor 101 is not high (NO in S504), the flow proceeds to S505.

  In step S505, the processor 101 acquires the swap-out and swap-in time intervals of the swap target data based on the history information 600 that stores the history of swap-out and swap-in executed in the past.

  FIG. 6 is a diagram illustrating history information 600 according to the embodiment. In the history information 600, entries corresponding to swap-out and swap-in executed in the past are registered. The entry may include, for example, virtual address, type, and date / time information in association with each other. As the virtual address, for example, a virtual address of data to be processed by swap-out or swap-in corresponding to the entry is registered. The type is information indicating whether the entry includes swap-in information or swap-out information. The date and time is information indicating the date and time when the swap-in or swap-out corresponding to the entry was executed.

  For example, the processor 101 may identify an entry having a virtual address of data to be swapped from the history information 600 and obtain a time interval from swap-out to swap-in performed in the past. The time interval may be based on one time interval such as the time interval from the last time executed for swap target data to swap-out to swap-in. Alternatively, in another embodiment, the time interval may be, for example, a representative value representing a time interval from a plurality of swap-outs to a swap-in executed in the past on the data to be swapped. The representative value may be, for example, an average value of time intervals from a plurality of past swap-outs to swap-in for data to be swapped, or may be other values such as a maximum value and a minimum value.

  In step S506, the processor 101 determines whether the time interval from swap-out to swap-in of the data to be swapped is short. When the time interval from swap-out to swap-in of the data to be swapped is longer than the predetermined time, the processor 101 determines that the time interval is long (S506 is long), and the flow proceeds to S509. In S509, the processor 101 sets the compression rate to the first compression rate that is high.

  On the other hand, in S506, for example, when the time interval from swap-out to swap-in of the data to be swapped is equal to or shorter than a predetermined time, the processor 101 determines that the time interval is short (S506 is short), and the flow goes to S507. move on. If the history information 600 has no history and is the first swap-out of data to be swapped, it may be determined that the time interval is short. In S507, the processor 101 sets the compression rate to the second compression rate lower than the first compression rate. If the time interval from swapping out the swapped data to swapping in is long, the data has been swapped out for a long time. In that case, the memory can be efficiently used by compressing at a high compression rate. On the other hand, if the time interval from swap-out of the memory area to be swapped to swap-in is short, swap-in may be performed again immediately. Therefore, the processor 101 is compressed by compressing at a low compression rate. It is possible to reduce the load on the machine.

  In S508, the processor 101 records information regarding swap-out. For example, the processor 101 may register an entry relating to the swap-out execution time in the history information 600 stored in the management area 203. For example, the processor 101 registers the virtual address of the data to be swapped as the virtual address of the entry of the history information 600, registers the swap out as the type, and records the current time as the execution time of the swap out at the date and time. Do it. Note that, as exemplified in the second embodiment to be described later, it is assumed that the swap-in execution time is also registered in the history information 600 at the time of swap-in.

  Further, the processor may record an entry including information regarding swap-out in the swap information 700 stored in the management area 203. FIG. 7 is a diagram illustrating swap information 700 according to the embodiment. The swap information 700 includes, for example, a virtual address, a swap-out destination address, and a size. The virtual address is, for example, an address on a virtual address space assigned to swap target data. The swap-out destination address is an address in the swap area 201 that stores data to be swapped. The size is the size of data to be swapped.

  In S510, the processor 101 swaps out the compressed swap target data to the memory area in the swap area 201 corresponding to the swap-out destination address registered in the swap information 700, the operation flow ends, and the flow is S405. Continue to processing.

  As described above, according to the embodiment, the processor 101 may, for example, perform swapping in a situation where it is estimated that the memory management control device 100 that is less likely to be experienced by the user even if the response is affected is unused. The first compression rate with a high compression rate is used for out. Thereby, memory can be saved.

  Further, according to the embodiment, when executing the swap-out, the processor 101 uses the second compression rate that is lower than the first compression rate when the usage rate of the processor 101 is high. By using the second compression rate with a low compression rate when the load on the processor 101 is high, the influence of the swap-out process on the processor 101 is suppressed, thereby reducing the response of the memory management control device 100. Can be suppressed.

  Further, according to the embodiment, when the swap-out is executed, the processor 101 has a second compression rate lower than the first compression rate if the time interval between the swap-out and swap-in of the data to be swapped is short. Use compression ratio. On the other hand, when the time interval between swap-out and swap-in of data to be swapped is long, the first compression rate is used. As described above, for data having a short time until the swap-in is executed again, the compression and decoding loads can be suppressed by using the second compression rate having a low compression rate. On the other hand, for data having a long time until the swap-in is executed again, the use efficiency of the memory can be increased by using the first compression ratio having a high compression ratio.

  Therefore, according to the embodiment, it is possible to suppress the influence of the swap-out process on the processor 101, thereby suppressing the response of the memory management control device 100 from being lowered.

  In another embodiment, for example, the compression rate may be set using any one of the above-described information (1) to (3). For example, when it is determined in S502 of FIG. 5 that the device is in use, the flow may be advanced to S507, and an operation flow may be set in which the compression rate is set according to the operation status. Similarly, after the processing of S501, the flow may proceed to S503, and if NO is determined in the next S504, the flow may proceed to S509 to set the compression rate based on the processor usage rate. Furthermore, after the processing of S501, the flow may proceed to S505, and an operation flow may be set in which the compression rate is set according to the time interval from swap-out to swap-in of the data to be swapped. Or in another embodiment, you may set a compression rate using two of the information of the above-mentioned (1)-(3).

  Further, for example, in another embodiment, when it is determined in S506 in FIG. 5 that the time interval is short, the compression rate is further set based on the time interval of the processing of the task that references the swap target data. A process of allocating to either the compression rate or the second compression rate may be included. In this case, for example, when the task processing time interval is long, the processor 101 may allocate the compression rate to the first compression rate of S509. Further, when the task processing time interval is short, the processor 101 may allocate the compression rate to the second compression rate in S507. In this way, it is possible to further improve the memory usage efficiency and the like by assigning the compression ratio using further parameters.

<Second Embodiment>
In the first embodiment, the case where the compression rate is changed by changing the parameter for setting the compression rate at the time of compression is illustrated, but the embodiment is not limited to this. The second embodiment exemplifies a case where the compression rate is changed by changing the compression algorithm.

  FIG. 8 is a diagram illustrating a swap-out process according to the second embodiment. For example, when the processor 101 proceeds to S <b> 404 in FIG. 4, the processor 101 may start the swap-out process in FIG. 8.

  In FIG. 8, the processes from S801 to S806 correspond to the processes from S501 to S506 in FIG. In step S809, the processor 101 compresses the swap target data using the first algorithm having a high compression rate. In S807, the processor 101 compresses the data to be swapped with the second compression algorithm that compresses the data at a compression rate lower than that of the first algorithm. As an example, the first algorithm may be 7-ZIP and the second algorithm may be ZIP. Other compression algorithms such as RAR may also be used.

  In step S808, the processor 101 records information regarding swap-out. For example, the processor 101 may register an entry relating to the swap-out execution time in the history information 600. For example, the processor 101 may record information about swap-out in the swap information 900 according to the second embodiment stored in the management area 203 of the memory 102.

  FIG. 9 is a diagram illustrating swap information 900 according to the second embodiment. The swap information 900 includes, for example, a virtual address, a swap-out destination address, a size, and a compression method. Note that the virtual address, the swap-out destination address, and the size may be information corresponding to the virtual address, the swap-out destination address, and the size of the swap information 700, respectively. In the compression method, information for identifying the compression algorithm used for compressing the swap target data in the processing of S807 or S809 is registered.

  In step S810, the processor 101 swaps out the compressed swap target data to the memory area in the swap area 201 corresponding to the swap-out destination address registered in the swap information 900, and the operation flow ends. Follows the process of S405.

  As exemplified in the above second embodiment, the embodiment may be implemented by changing the compression rate by other methods such as changing the compression algorithm in addition to the parameters at the time of compression. Further, for example, by appropriately selecting a compression algorithm, it is possible to further improve the compression rate and reduce the load applied to the processor.

  FIG. 10 is a diagram illustrating an operation flow of the swap-in process according to the second embodiment. For example, when an instruction for calling data saved in the swap area 201 is input, the processor 101 may start the swap-in process of FIG.

  In S1001, the processor 101 searches the swap area 201 for the called data. It is determined whether or not the search for the data called in S1002 has succeeded. If the search fails (S1002 fails), the flow proceeds to S1003, the processor 101 outputs an error, and the operation flow ends. If the search is successful (S1002 is successful), the flow proceeds to S1004.

  In S1004, the processor 101 refers to the swap information 900 and specifies the compression method of the entry corresponding to the data to be called. In S1005, the processor 101 reads data having a size defined by the data size from the swap-out destination address of the entry corresponding to the data to be called in the swap information 900, and decodes it using the specified compression method. In step S <b> 1006, the processor 101 swaps the decrypted data into a free area secured in the memory in association with the virtual address of the entry.

  In S1006, the processor 101 updates information regarding swap-in. For example, the processor 101 deletes the entry corresponding to the swapped-in data from the swap information 900. In addition, the processor 101 registers an entry related to the swap-in execution time in the history information 600. When the update of information is completed in S1006, this operation flow ends.

  As described above, in the second embodiment, the processor 101 also stores the compression format in the swap information 900 at the time of swap-out. Therefore, the processor 101 can decode data by selecting an appropriate compression format at the time of swap-in.

  FIG. 10 illustrates the swap-in process when changing the compression format according to the second embodiment. However, for example, when the compression parameter is changed instead of the compression algorithm, the processing of S1004 is omitted, and decoding is performed using a predetermined compression algorithm in S1005, so that the swap-in corresponding to the first embodiment is performed. Can be executed.

  As described above, according to the above-described embodiment, the response of the memory management control device 100 at the time of swap-out can be improved.

  The processing capability of the processor 101, the number of tasks, and the processing amount of each task differ depending on the model of the memory management control device 100 and the like. Therefore, the parameter values and compression algorithms that are actually used in each compression of the high compression rate and the low compression rate may be investigated in advance to determine the optimal solution.

  In the above, although embodiment was illustrated, embodiment is not limited to this. For example, in the above-described embodiment, the example in which the embodiment is applied when the swap area 201 is provided in the memory 102 has been described. However, the embodiment is not limited to this. For example, the embodiment can also be applied when the swap area 201 is provided in another storage device 103 such as a hard disk. Also in that case, for example, the compression rate can be changed in consideration of the influence of the response of the memory management control device 100 at the time of swap-out. Further, for example, in a situation where the influence on the response of the memory management control device 100 is slight, the storage area for storing data by swap-out can be reduced by using a high compression rate. Further, for example, when the reading / writing speed of the storage device 103 is low, the data compressed using the high compression rate is written or read, so that the data can be written at the time of swap-out or swap-in. The time required for loading can be reduced. Therefore, the embodiment can be applied to a memory management control device 100 such as a personal computer (PC) or a notebook PC.

  Further, for example, the above-described operation flow is an example, and the embodiment is not limited to this. If possible, the operation flow may be executed by changing the order of processing, may include additional processing, or some processing may be omitted.

  In the above, several embodiments are described. However, the embodiments are not limited to the above-described embodiments, and should be understood as including various modifications and alternatives of the above-described embodiments. For example, it will be understood that various embodiments can be embodied by modifying the components without departing from the spirit and scope thereof. It will be understood that various embodiments can be implemented by appropriately combining a plurality of components disclosed in the above-described embodiments. Further, various embodiments may be implemented by deleting or replacing some components from all the components shown in the embodiments, or adding some components to the components shown in the embodiments. Those skilled in the art will appreciate that this can be done.

100 Memory Management Control Device 101 Processor 102 Memory 103 Storage Device 104 Input Device 105 Display Device 110 Bus 201 Swap Area 202 Data Area 203 Management Area

Claims (8)

Memory including data area and swap area;
When swapping out data stored in the data area to the swap area, the data is compressed at the first compression rate if a predetermined condition is satisfied, and if the predetermined condition is not satisfied, the data is compressed. A processor that compresses data at a second compression rate that is lower than the first compression rate;
A memory management control device. Compression of the data at the first compression rate is performed with a first compression algorithm;
The compression of the data at the second compression rate is performed by a second compression algorithm having a compression rate lower than that of the first compression algorithm,
The memory management control device according to claim 1. The predetermined condition is that the processor determines that the memory management control device is not used based on operation information indicating an operation status of the memory management control device.
The processor compresses the data at the first compression rate when the memory management controller determines that the memory management controller is not in use.
The memory management control device according to claim 1, wherein the memory management control device is a memory management control device. The predetermined condition includes that the usage rate of the processor is lower than a predetermined threshold;
The processor compresses the data at the second compression rate when the usage rate of the processor is equal to or greater than a predetermined threshold;
The memory management control device according to claim 1, wherein the memory management control device is a memory management control device. The predetermined condition is that a time interval from the swap-out of the data based on a history of swap-out and swap-in executed to the data in the past is longer than a predetermined time,
When the processor determines that the time interval is longer than a predetermined time, the processor compresses the data at the first compression rate.
The memory management control device according to claim 1, wherein the memory management control device is a memory management control device. The predetermined condition is based on the operation information indicating the operation status of the memory management control device, the usage rate of the processor, and the swap-out of the data based on the history of swap-out and swap-in executed in the past. Including a plurality of judgment conditions using a plurality of information of the time interval until the swap-in,
The processor compresses the data using a compression rate determined based on the plurality of determination conditions from the first compression rate and the second compression rate.
The memory management control device according to claim 1, wherein the memory management control device is a memory management control device. When data stored in the data area of the memory is swapped out to the swap area of the memory, if a predetermined condition is satisfied, the data is compressed at the first compression rate, and the predetermined condition is satisfied. Otherwise, the data is compressed at a second compression rate that is lower than the first compression rate.
A memory management control method executed by the memory management control device. When data stored in the data area of the memory is swapped out to the swap area of the memory, if a predetermined condition is satisfied, the data is compressed at the first compression rate, and the predetermined condition is satisfied. Otherwise, the data is compressed at a second compression rate that is lower than the first compression rate.
A memory management control program for causing a memory management control device to execute processing.

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