JP5505195B2 - Memory control device and control method - Google Patents

Description

  The present application discloses a memory control device and a control method.

  In recent years, devices such as a processor and a memory included in a computer have various functions for reducing power consumption (see, for example, Patent Documents 1 and 2).

Japanese Patent Laid-Open No. 5-19917 Japanese Patent Laid-Open No. 7-105686

When a computer handles data by the LIFO (Last In First Out) method, the following types of areas are generated in the memory of the computer. The first area is, for example, an area in which specific data that may be accessed immediately is stored. The second area is, for example, an area in which other data that cannot be accessed unless the first area is accessed is stored. The third area is, for example, an area where data cannot be stored for the time being.

  By the way, with an increase in memory capacity, power consumption in an area where no power supply is required cannot be ignored depending on the data storage state. However, since the data storage state changes every moment according to the progress of processing in the processor, it is difficult to realize power saving by appropriately allocating necessary power to each area in the memory.

  Therefore, an object of the present application is to provide a memory control device and a control method capable of suppressing power consumption in accordance with a data storage state.

The present application discloses the following apparatus.
A plurality of memory blocks for storing data in the stack that is processed in a first-in first-out manner from the base point of the stack toward the empty area by the stack pointer, and a power supply unit capable of independently supplying power to the memory block An address information holding unit for holding address information at the boundary of each memory block of the memory device;
A power control unit that suppresses power supplied to a memory block other than the specific memory block in which the address indicated by the stack pointer exists among the memory blocks, compared to the power supplied to the specific memory block. ,
Memory control device.

Moreover, this application discloses the following methods.
A plurality of memory blocks for storing data in the stack that is processed in a first-in first-out manner from the base point of the stack toward the empty area by the stack pointer, and a power supply unit capable of independently supplying power to the memory block Access the address information holding unit that holds the address information of the boundary of each memory block of the memory device,
Among the memory blocks, the power supplied to the memory blocks other than the specific memory block where the address indicated by the stack pointer exists is suppressed from the power supplied to the specific memory block.
Memory control method.

  It is possible to suppress power consumption according to the data storage state.

It is a block diagram of a memory control apparatus. It is a figure which shows the content of a table. It is a processing flow figure which a memory control device performs. It is the 1st figure which showed the data and power mode of the stack area. It is the 2nd figure which showed the data and power supply mode of the stack area. It is the 3rd figure showing the data and power mode of a stack field. It is the 4th figure showing the data and power mode of a stack field. It is a processing flow figure which the memory control device concerning a modification performs. It is the 1st figure showing the data and power mode of the stack area concerning a modification. It is the 2nd figure showing the data and power mode of the stack area concerning a modification. It is the 3rd figure showing the data and power mode of the stack area concerning a modification. It is the 4th figure showing the data and power mode of the stack field concerning a modification. It is the figure which showed the relationship between a virtual storage space and a physical storage space when a single application is executed. It is the figure which showed the relationship between virtual storage space and a physical storage space when a some application is performed. It is a processing flow figure which OS of the computer concerning a modification performs. It is the figure which showed the relationship between virtual storage space and physical storage space when there are multiple stack areas. It is a processing flow figure which OS of the computer concerning a modification performs. It is the figure which showed the computer which concerns on a modification.

The configuration of the memory control device is shown in FIG. As shown in FIG. 1, the memory control device 1 is built in a computer 4 including a CPU (Central Processing Unit) 2 and a memory 3.
Note that the memory control device 1 may be built in the memory 3.

  The memory control device 1 acquires an address (hereinafter referred to as an SP value) indicated by a stack pointer stored in the register 10 of the CPU 2 and controls a power control mode of the memory 3 and each block of the memory 3. And a table 6 for holding address information.

  The mode control unit 5 is based on an acquisition unit 5A that acquires the SP value acquired from the register 10 of the CPU 2, a comparison unit 5B that compares the SP value acquired by the acquisition unit 5A with the table 6, and a comparison result of the comparison unit 5B. A determination unit 5C for determining the power mode of the memory 3. The mode control unit 5 controls the selector 7 of the memory 3 so that the power mode of the memory 3 becomes the power mode determined by the determination unit 5C.

The acquisition unit 5A may acquire the SP value by accessing the register 10 of the CPU 2 every clock cycle, or may access the register 10 in response to a change in the SP value. May be obtained. When the acquisition unit 5A operates in response to a change in the SP value, the acquisition unit 5A may trigger a signal notified from the CPU 2 when the SP value changes, or may indicate that the SP value of the register 10 has changed. A circuit for detection may be provided separately, and a signal notified from this circuit may be used as a trigger. Similarly to the acquisition unit 5A, the comparison unit 5B and the determination unit 5C may repeat the comparison process and the determination process every clock cycle, or execute the process in response to a change in the SP value. Also good.

The CPU 2 is hardware that performs various operations, and is an ALU (Arithmetic Logic Unit).
) 8, LSU (Load / Store Unit) 9, a register 10, and a program counter 11.

  The memory 3 is a volatile memory that requires a memory holding operation. The memory 3 includes a memory cell array 12 in which m × n memory cells are arranged in an array, and a selector 7 that controls power supplied to each memory cell. The selector 7 controls the switch group 13 in accordance with a command from the memory control device 1, and supplies each block 14 </ b> A to 14 </ b> D of the memory cell array 12 with power line L <b> 1 for supplying power for operation and power for holding data. Connect to power line L2. That is, the memory cell array 12 can control the power mode for each block. Each of the blocks 14A to 14D is used as a stack area. The memory 3 may have a general-purpose memory area in addition to the stack memory area.

Each of the blocks 14A to 14D enters a normal operation state (On) in which data can be read / written when power is supplied from the power line L1, and enters a data retention state (Retention) in which data cannot be read / written when power is supplied from the power line L2. Thus, when the supply of power is cut off, it enters a stopped state (Off) in which not only reading and writing of data but also holding of data is impossible. Regarding power consumption, the power consumption in the normal operation state (On) is the largest, the power consumption in the data retention state (Retention) is the next largest, and the power consumption in the stop state (Off) is the smallest.

  As shown in FIG. 2, the table 6 holds the address range (block boundary address) of each block 14A to D of the memory cell array 12, for example, information on the head address and the end address of each block. Yes. In FIG. 2, the first to fourth blocks correspond to the reference numerals 14A to 14D in FIG. Further, in FIG. 2, for convenience of explanation, a column of “block name” is shown, but the table 6 only needs to have a column of “address”.

  The processing executed by the memory control device 1 will be described with reference to the processing flowchart of FIG. In this embodiment, the memory control device 1 as hardware is provided in the computer 4 separately from the CPU 2, but the processing executed by the memory control device 1 may be realized by the CPU 2 by software. Good.

  When the computer 4 is activated, a memory area for stacking data is secured in the memory 3 as shown in FIG. At this time, since the data is not yet stored in the stack, the SP value indicates an address which is the base point of the stack (the lower end of the stack in FIG. 4). In the present application, the end point is the side opposite to the base point of the stack (the direction in which data is accumulated) (the upper end of the stack in FIG. 4).

  When data is stored in the stack by processing by the CPU 2, the SP value is changed by the size of the stored data as shown in FIG.

  Here, the mode control unit 5 acquires the SP value from the register 10 of the CPU 2 (S101). The processing in step S101 is repeatedly executed regardless of whether or not the SP value has changed when the acquisition unit 5A operates every clock cycle, and when the acquisition unit 5A operates in response to a signal notified from the CPU 2. Is executed in response to this signal.

  The mode control unit 5 identifies the block to which the address indicated by the stack pointer belongs from the correlation between the acquired SP value and the table of FIG. If there is no change in the block to which the address indicated by the stack pointer belongs, the mode control unit 5 repeats the process of step S101 again (S102). Further, if there is a change in the block, the mode control unit 5 controls the selector 7 to switch the power mode of each of the blocks 14A to 14D (S103).

  Assume that data is further stored in the stack by processing by the CPU 2 and the block to which the address indicated by the stack pointer belongs has changed from the first block to the second block as shown in FIG. In this case, the mode control unit 5 detects that the block to which the address indicated by the stack pointer belongs has been changed from the correlation between the SP value and the table of FIG. 2, and controls the selector 7 to control each of the blocks 14A to 14D. The power mode is switched (S103).

  In the example shown in FIG. 6, since the block in which the address indicated by the stack pointer exists has changed from the first block to the second block, the selector 7 changes the power line connected to the first block from the power line L1 to the power line L2. Switching, the power line L1 is connected to the second block. As a result, the power mode of the first block is switched from the normal operation state (On) to the data retention state (Retention), and the power mode of the second block is switched from the stop state (Off) to the normal operation state (On). Note that the Wait signal is sent from the mode control unit 5 to the LSU 9 after the selector 7 starts switching the block until the second block transitions to the normal operation state (On) and data can be written. The data written from the CPU 2 to the memory 3 is held in the LSU 9.

On the other hand, it is assumed that the data of the stack is extracted by the processing by the CPU 2 and the block to which the address indicated by the stack pointer belongs changes from the second block to the first block as shown in FIG. In this case, the selector 7 disconnects the power line L1 connected to the second block, and switches the power line connected to the second block from L2 to the power line L1. As a result, the power mode of the second block is switched from the normal operation state (On) to the stop state (Off).
The power mode of the first block is switched from the data retention state (Retention) to the operation state (On).

  When the memory control device 1 appropriately controls the power supply of each block, the power consumption of the memory 3 is reduced. In addition, since the power supply of each block is automatically controlled by the memory control device 1, the memory 3 does not cause malfunction of the memory 3 even if the creator of the application does not consider the power control of the memory 3. Power consumption can be automatically reduced. In the above-described embodiment, the memory area is divided into four blocks 14A to 14D, but is not limited to four blocks. That is, as long as the stack memory area is divided into a plurality of power supply areas, it may be divided into any number of blocks.

  A first modification of the above embodiment will be described. Since it takes time to switch the power mode by the selector 7, in the above embodiment, data may be held in the LSU 9. However, if the mode control unit 5 controls the selector 7 as follows, data can be seamlessly stored in the stack.

  In this modification, when the address indicated by the stack pointer approaches the block boundary, the mode control unit 5 executes the control of the selector 7. A processing flow executed by the mode control unit 5 in this modification is shown in FIG.

In this modification, a boundary area as shown in FIG. 9 is set in the vicinity of the boundary of each block, and when the SP value falls within the boundary area (S202), the mode control unit 5 Is connected to the power line L1 (S203). The boundary region may be specified by, for example, information added to the table shown in FIG. 2, or specified by adding or subtracting a predetermined offset amount from the boundary address value of each block shown in the table of FIG. It may be done.

  The larger the boundary area, the more seamlessly the data can be stored, but there is a trade-off relationship with power consumption. Therefore, the size of the boundary area may be appropriately determined according to the amount of data processed by the CPU 2 and the processing speed of the selector 7.

It is assumed that data is further stored in the stack by the processing by the CPU 2 and the SP value indicates a boundary area between the first block and the second block as shown in FIG. In this case, the mode control unit 5 controls the selector 7 to connect the power line L1 to the second block, and switches the power mode of the second block from the stop state (Off) to the normal operation state (On). This
Both the first block and the second block are in a normal operation state (On).

  It is assumed that data is further stored in the stack by the processing by the CPU 2, and the SP value indicates the second block outside the boundary area as shown in FIG. 11 (S204). In this case, since the stack pointer indicates the second block (S205), the mode control unit 5 connects the power line L2 to the first block and changes the power mode of the first block from the normal operation state (On) to the data. Switch to Retention state.

  On the other hand, it is assumed that the data in the stack area is erased by the processing by the CPU 2 from the state shown in FIG. 10, and the SP value is out of the boundary area as shown in FIG. In this case, the mode control unit 5 disconnects the second block from the power line L2, and switches the power mode of the second block from the normal operation state (On) to the stop state (Off).

  By controlling the selector 7 as described above, the mode control unit 5 can seamlessly store data in the stack even when the SP value increases or decreases and the power mode of each block is switched.

  A second modification of the above embodiment will be described. In the virtual storage system, the correlation between the logical address and the physical address is not uniquely determined, and changes according to the conditions at the time of activation. For this reason, if no measures are taken, it is impossible to specify at which position the stack area is secured on the physical address.

  On the other hand, each block of the memory 3 is partitioned by an actual circuit configuration, and the table of FIG. 2 also shows physical addresses. Therefore, when performing the power control based on the SP value as described above in the virtual storage system, the computer 4 is modified as follows.

  That is, the OS is defined in advance so that the application stack is secured in a specific virtual storage space corresponding to each block in the virtual storage space formed by the OS (Operating System) of the computer 4. For example, the virtual address of the stack space in the virtual storage space formed by the OS is mapped corresponding to the physical addresses of the blocks 14A to 14D. Further, the virtual address of the space for storing general-purpose data in the virtual storage space formed by the OS is mapped in correspondence with the physical address of any area in the memory 3 other than the blocks 14A to 14D.

In this OS, data stored in the stack among data handled by the application is stored in a specific virtual storage space corresponding to each of the blocks 14A to 14D, while data not stored in the stack is stored in the virtual storage space. It is stored in a space other than the specific virtual storage space.

  As described above, the data stored in the stack is stored in a specific virtual storage space corresponding to the blocks 14A to 14D in the virtual storage space. Data stored in the physical storage spaces of the blocks 14A to 14D and not stored in the stack is stored in other physical storage spaces.

  Since the SP value indicated by the register 10 indicates a physical address, the memory control device 1 controls the power supply mode of each of the blocks 14A to 14D based on the physical address indicated by the table of FIG. 2 and the SP value of the register 10. Then, the power consumption of the memory 3 can be automatically reduced without inducing a malfunction of the memory 3.

  When a plurality of applications are executed as shown in FIG. 14, the data stored in the stack is processed as follows.

  FIG. 15 shows a processing flow of stack data to be executed by the OS when a plurality of applications are executed in parallel by switching tasks. When task switching occurs due to a user operation, input / output waiting, or the like, the OS moves the data of the blocks 14A to 14D stored in the stack to another memory area (S301). Here, the other memory area is an area for saving stack data, and may be any storage medium as long as data can be saved. When the data in the blocks 14A to D are moved to another memory area, the data is read from all the areas below the address indicated by the SP value in the blocks 14A to 14D. Sets the power mode of not only the block in which the address of the SP value exists but also all the blocks storing data to the normal operation state (On).

When the OS saves the task stack before switching, the OS next reads the stack data of the task after switching from other memory areas and stores them in the blocks 14A to 14D (S302). When the data of the stack of the task after switching is stored in the blocks 14A to 14D, the memory control device 1 next maintains the power supply mode of the block in which the address of the SP value exists in the normal operation state (On). Then, the power mode of the other block is set to the stop state (Off) or the data retention state (Retention).

  When a plurality of applications are executed in parallel by switching tasks, the plurality of applications can be executed while reducing the power consumption of the memory 3 by processing the stack data stored in the blocks 14A to 14D as described above.

  When a plurality of stack memory areas such as blocks 14A to 14D are prepared in the computer 4 as shown in FIG. 16, the data stored in the stack of each application is processed as follows. .

  FIG. 17 shows a stack data processing flow to be executed by the OS when there are a plurality of stack memory areas in which the power mode of each block can be switched independently, and a plurality of applications are executed in parallel by switching tasks. Show. When task switching occurs due to a user operation or the like, the OS determines whether or not the stack corresponding to the application is in the stack memory areas A to C (S401). If the determination is affirmative, the task is switched without performing any processing.

On the other hand, if the determination process in step S401 is negative, the OS determines whether any of the stack memory areas A to C is free based on the SP values of the memory areas A to C. (S402). If the determination is affirmative, the OS moves the application stack data of the new task to a free memory area (S405).

  On the other hand, if the determination process in step S402 is negative, the OS selects a stack to be erased (S403). The priority of the stack to be erased is determined based on, for example, the frequency of selecting a task, the size of data stored in the stack, and the like.

  The OS moves the data stored in the stack to be erased selected in step S403 to another memory area (S404). In this case, as in step S301 described above, the memory control device 1 sets the power mode of all blocks storing data to the normal operation state (On) as well as the block having the SP value address. To do.

  When the OS saves the stack of the task before switching, the OS reads the data of the stack of the task after switching from another memory area and stores it in the blocks 14A to 14D (S405). Similar to step S302 described above, when the stack data of the task after switching is stored in the blocks 14A to D, the memory control device 1 next sets the power mode of the block in which the SP value address exists to the normal power mode. While the operation state (On) is maintained, the power mode of other blocks is set to the stop state (Off) or the data retention state (Retention).

  When there are a plurality of stack memory areas, if the stack data of each application is handled as described above, tasks can be switched seamlessly while executing a plurality of applications while reducing the power consumption of the memory 3. it can.

  The memory control device 1 includes peripheral devices 15 such as a display, a NIC (Network Interface Card), a wireless LAN, a hard disk drive, a Blu-ray (registered trademark) disk drive, a DVD drive, as shown in FIG. It may be built in a computer provided. Further, the memory control device 1 may be applied to a mobile phone, a PDA, an in-vehicle device, a server device or the like instead of the computer 1.

1 ... Memory control device 2 ... CPU
3, memory 4, computer 5, mode control unit 6, table 7, selectors 14A to D, block

Claims (4)

A plurality of memory blocks for storing data in the stack that is processed in a first-in first-out manner from the base point of the stack toward the empty area by the stack pointer, and a power supply unit capable of independently supplying power to the memory block An address information holding unit for holding address information at the boundary of each memory block of the memory device;
A power control unit that suppresses power supplied to a memory block other than the specific memory block in which the address indicated by the stack pointer exists among the memory blocks, compared to the power supplied to the specific memory block. ,
The power supply controller supplies power for data retention to a memory block closer to the base point than the specific memory block among the memory blocks.
Memory control device. The power supply control unit cuts off the power supplied to the memory block on the free area side from the specific memory block among the memory blocks.
The memory control device according to claim 1 . When the stack pointer indicates an address within a predetermined range from the boundary of the specific memory block, the power control unit supplies power for operation to a memory block adjacent to the specific memory block across the boundary To
The memory control device according to claim 1 or 2 . A plurality of memory blocks for storing data in the stack that is processed in a first-in first-out manner from the base point of the stack toward the empty area by the stack pointer, and a power supply unit capable of independently supplying power to the memory block Access the address information holding unit that holds the address information of the boundary of each memory block of the memory device,
Among the memory blocks, the power supplied to the memory blocks other than the specific memory block where the address indicated by the stack pointer exists is suppressed from the power supplied to the specific memory block ,
At the time of suppression, power for holding data is supplied to the memory block on the base point side of the specific memory block among the memory blocks.
Memory control method.

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