CN111221756A - Method for efficiently transmitting downlink data of upper computer - Google Patents
Method for efficiently transmitting downlink data of upper computer Download PDFInfo
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- CN111221756A CN111221756A CN201911103984.5A CN201911103984A CN111221756A CN 111221756 A CN111221756 A CN 111221756A CN 201911103984 A CN201911103984 A CN 201911103984A CN 111221756 A CN111221756 A CN 111221756A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a method for efficiently transmitting data to lower-layer equipment by upper computer software, which comprises the following steps: the upper computer initializes the memory allocation structure and writes the initialized related information into the lower-layer equipment; the upper computer and the lower layer equipment respectively establish a circular queue with the depth of M, N to store corresponding information; when data is transmitted, the upper computer software copies the data to be transmitted into the c sub-block of the large block memory block with the sequence number a, integrates the sequence number a, the sequence number c and the data length L into a numerical value R, and writes the numerical value R to the lower-layer equipment in a register writing mode; the lower layer device obtains a physical address ADDR for storing the data through calculation, and then initiates DMA operation to obtain the data according to the data length L analyzed from the integration value R. The method of the invention has the advantages of simpler processing flow, better cross-system portability and higher transmission efficiency.
Description
Technical Field
The invention describes a method for efficiently transmitting data to lower-layer equipment by an upper computer, which has the advantages of simpler processing flow, better cross-system portability and higher transmission efficiency.
Background
When the upper computer transmits data to the lower layer equipment, a common method is write register or DMA transmission, the write register has low efficiency, and the requirement of high-speed data transmission cannot be met; the DMA transmission has two modes, one mode is that the upper computer calls a system interface function to actively initiate the DMA operation, and the other mode is that the upper computer informs the lower layer device of the physical address and the length information of the data transmitted by the DMA, and the lower layer device initiates the DMA operation. In any DMA method, the problems of confirmation of completion of DMA data transfer and multiplexing of physical memory need to be considered.
If the DMA transmission efficiency needs to be improved, the continuity of multiple DMA operations needs to be improved, and the interval between each DMA operation needs to be reduced as much as possible. For this reason, a better transmission control method is required to reduce the influence of data transmission confirmation on the operation continuity.
Disclosure of Invention
The invention designs an upper computer downlink data transmission method based on the DMA operation initiated by lower-layer equipment, which can realize continuous DMA operation through a simple algorithm and reduce the influence of each DMA data transmission confirmation on continuous DMA transmission, thereby greatly improving the efficiency of upper computer downlink data transmission. Because the mode of initiating the DMA operation by the lower-layer equipment is adopted, the upper computer software of the invention does not need to call the interface function of the operating system to initiate DMA transmission, thereby avoiding the influence caused by the difference of the using flow and the mode of the DMA interface function of each operating system and having very good cross-system portability.
The invention adopts the mode that the lower layer equipment initiates DMA transmission to realize data transmission, so that the physical address information of the memory for storing data in each DMA transmission needs to be informed to the lower layer equipment; in a 32-bit system, a physical address needs to occupy 32 bits for storage, in a 64-bit system, physical address information needs to occupy 64 bits for storage, and in addition to the need to inform the physical address information of DMA transmission of lower layer equipment, the need to inform the data length of DMA transmission of the lower layer equipment also needs to inform, and then a certain number of bits (assuming that Nbit is needed, N must be greater than 0) are needed to store the data length information. Therefore, each time the upper computer needs to transmit data to the lower layer device, the lower layer device needs to be informed of the information of 32bit + N bit (32 bit system) or 64bit + N bit (64 bit system) first, so that the lower layer device can initiate the DMA operation. If the information is informed by adopting a register writing mode, the calculation is carried out according to the information length, according to the 32-bit register writing mode, a 32-bit system needs to write a register for 2 times, and a 64-bit system needs to write the register for 3 times to send data to equipment.
Writing the register 2 times or 3 times can inform the lower layer device of the necessary information to initiate one DMA operation, and under the condition of realizing continuous DMA operation, higher efficiency can be realized. However, due to the limitation of the read-write speed of the register, the register write operation can still become the bottleneck of data transmission, the method of writing physical address information into lower-layer equipment in advance and then writing simplified information corresponding to an address during DMA operation is adopted to compress the number of times of writing the register by DMA operation into 1 time, and the efficiency bottleneck caused by the register write operation is solved.
Another reason for affecting the data transmission efficiency is the completion confirmation of the DMA operation, and if a second DMA operation is initiated after the completion confirmation of the data transmission is waited after the initiation of the DMA operation once, the time for waiting for the confirmation in the middle is wasted, which greatly affects the data transmission efficiency. The invention designs a simple and reliable operation design for confirming the completion of DMA transmission to realize the batch transmission and batch confirmation of DMA.
The invention realizes the batch transmission and confirmation of DMA by adopting a mode that the upper computer and the lower layer equipment both use the circular queue. The lower-layer equipment establishes a queue with the depth of N for storing DMA information written by the upper computer, and the upper computer writes the DMA information into the lower-layer equipment in a register writing mode every time the upper computer initiates DMA data transmission. The lower layer device stores this information in a circular queue. The circular queue has a storing pointer DIP and a completed pointer DFP, each time a DMA message is newly stored, the DIP moves forward, the device continuously reads the completed pointer DFP, if the DFP is not equal to the DIP, the DMA transfer is not completed, the device initiates the DMA transfer according to the DMA message pointed by the current DFP, and after the DMA transfer operation corresponding to the current DFP is completed, the DFP pointer moves forward until the DFP is equal to the DIP, the DMA transfer is completed. In addition, the lower layer device is also provided with a writable DMA information quantity register for recording the quantity of free storage blocks of the self circulation queue, and the upper computer can determine whether the DMA information can be continuously written or not by reading the register. The upper computer is provided with a counter REG _ FIFO and a circular queue with the depth of M, in order to simplify the algorithm, M is required to be more than or equal to the depth N of the circular queue of the lower layer equipment, and each storage item of the circular queue of the upper computer corresponds to a continuous physical memory. The upper computer reads the value of the DMA information writable quantity register of the lower-layer equipment and stores the value into the counter REG _ FIFO, and whether the DMA information can be continuously written into the lower-layer equipment can be judged by judging whether the value of the REG _ FIFO is 0 or not. The circular queue of the upper computer also has two pointers: when the write pointer WP and the release pointer FP initiate downlink data transmission, firstly, data copy needing to be transmitted is put into a continuous physical memory pointed by the WP, and then after confirming that the REG _ FIFO is larger than 0, the write register informs a physical memory address pointed by the lower layer device WP and data length information (the information can be simplified and compressed into 32 bits according to the design in the invention and is only written into the register once). After writing the DMA information to the lower layer device, the WP pointer is moved forward and REG _ FIFO is decremented by 1. After multiple writes of successive data transfers, REG _ FIFO is reduced to 0, at which point the register of the lower device is again read to update the value of REG _ FIFO, which should be a value n greater than 0 because the lower device has completed a portion of the DMA transfer during this time. The read value n also indicates the number of DMA completed in this period of time, so the release pointer FP of the upper computer software queue can be moved forward by n positions. Through the cooperation of the circular queue of the lower-layer device, the circular queue of the upper computer, the number register and the counter of writable DMA information, continuous DMA operation can be realized without waiting for the completion of the current DMA operation in each data transmission, and thus, the data transmission efficiency is greatly improved.
Drawings
Fig. 1 shows the upper computer memory structure and the information compression principle of the present invention.
FIG. 2 illustrates a flow of a batch continuous DMA operation implementation of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention is applied to the host equipment to control the data to be sent to the lower layer I/O equipment through the upper computer, and the initialization work is firstly needed during the specific implementation.
When the device is not used, the value is the depth N of the data transmission DMA information buffer queue of the lower layer device.
And then the upper computer applies for a large continuous physical memory (A is greater than or equal to 1) of the block A in the host device according to the configuration parameters, and in order to improve the application success rate, the length of the continuous physical memory is generally recommended to be 1MB or 2 MB. After the application of the continuous physical memory is completed, dividing the continuous physical memory with the size of each block into C (C is more than or equal to 1) sub-blocks according to the maximum single DMA data length K of practical application. In order to simplify the complexity of controlling data transmission flow, it is necessary to ensure that a times C is greater than or equal to N, that is, the number of memory blocks allocated by the upper computer and capable of storing downlink DMA data is greater than the data buffer queue depth of the lower layer device. The purpose of the design is that only whether the device cache queue is full is needed to be considered during transmission control so as to suspend and wait for partial DMA transmission to be completed, and whether the memory applied by the upper computer software is full is not needed to be considered simultaneously, so that the complexity of transmission control is simplified.
After the memory application and the division are completed, the number A of the memory blocks, the number C of the sub-blocks divided by each memory block, the length K of each sub-block and the initial physical addresses of the A memory blocks are written into the lower-layer equipment. So far, the initialization work is completed, and the upper computer can start to control continuous transmission of data to the lower-layer equipment.
The purpose of the initialization work is to control the device to initiate a DMA transfer request by writing less information (32 bits) into the register by the upper computer during actual data transfer, and on the other hand, to reduce the storage resource usage of the lower layer device. The memory structure and the information compression principle of the upper computer are shown in fig. 1.
The following describes the memory structure of the upper computer and the principle that the upper computer writes compressed information into the lower layer device to control DMA transmission during data transmission in detail:
in order to realize continuous DMA operation during batch data transmission, the upper computer stores the data content transmitted each time in a memory block queue mode, and the lower layer equipment also stores DMA information written by the upper computer in each data transmission in a queue mode. And the lower-layer equipment completes the data transmission operation corresponding to the DMA information stored firstly according to the sequence of the information stored in the queue, and the storable information count can be increased after the DMA data transmission operation is completed once. The upper computer determines the finished data transmission quantity and releases the record written firstly according to the change condition of the storable information count by reading the storable information count. The two parties confirm the completion of the batch data transmission through counting, so that the efficiency of data transmission can be greatly improved.
In order to reduce the length of DMA information written to the lower-layer device by the upper computer during each data transmission so as to reduce the times of writing the register as much as possible, a method of directly writing the physical address and the data length of each DMA cannot be adopted, but the physical address needs to be converted into a corresponding positioning serial number, the lower-layer device can quickly calculate the physical address of the memory according to the positioning serial number, and then the DMA is initiated to acquire data according to the length information.
However, the storage resources of the lower layer device are usually extremely limited, and if each physical address of the memory block queue of the upper computer is stored, the limited storage resources are greatly wasted. The design of the invention can reduce the storage information of the lower layer device and still ensure higher transmission efficiency.
The upper computer applies for a large block of memory and then divides the large block of memory according to a fixed length to obtain a plurality of transmission data cache regions. The number of large blocks of memories applied by the upper computer is A, each large block of memory is divided into C sub-blocks according to the length K, then the sub-blocks are utilized to form a queue, and the queue depth M = A multiplied by C.
When initializing, the upper computer will have large memory block number A, each large memoryWriting the number C of the sub-blocks and the length K of the sub-blocks into a lower computer device, and then writing the initial physical addresses A of the large-block memory one by one0、A1、A2……A(A-1)。
During data transmission, the upper computer copies data into the c-th sub-block of the large block memory block with the sequence number a, integrates the sequence number a, the sequence number c and the data length L into a 32-bit value R, and writes the value into lower-layer equipment in a register writing mode.
The lower layer device can obtain a physical address Aa of the large block memory according to the sequence number a, then calculate and obtain a physical address ADDR stored in the data according to a formula ADDR = Aa + (c × K), and then initiate a DMA operation according to the L analyzed from the integrated value to obtain the data.
After the upper computer and the lower layer equipment complete initialization operation, continuous and efficient data transmission operation can be realized according to the following process. The following describes in detail an implementation flow of the batch continuous data transmission of the upper computer with reference to fig. 2:
s201, starting batch downlink data transmission;
s202, reading a register value of the DMA information quantity which can be written into the lower-layer equipment, and updating a counter REG _ FIFO;
s203, judging whether the REG _ FIFO is 0, if so, indicating that a large amount of transmission data of the lower-layer equipment is not transmitted, and needing to enter S204 to wait for a few milliseconds in a waiting process; if the REG _ FIFO is not 0, the flow may proceed to S205 to start data transmission;
s204, when the REG _ FIFO is 0, waiting for a few milliseconds, and then jumping to S202 to read the register again to update the value of the REG _ FIFO;
s205, the release pointer FP is moved forward according to the newly read register value n until the position is moved forward by n or the release pointer FP catches up with the write pointer WP. When the release pointer FP is larger than or equal to the memory sub-block M during the forward movement, the release pointer FP moves to the sub-block 0 again. When the REG _ FIFO is 0, reading the register again to obtain a value n which is not 0, and storing the value n into the REG _ FIFO, which indicates that the lower-layer device has completed n initial data DMA transfer operations, so that the upper computer software can move a release pointer FP to release the initial written data record for later use after vacating the memory block;
s206, copying a copy of downlink data to the DMA cache physical memory block pointed by the write pointer WP;
and S207, the register is written to the lower layer device to inform the write pointer WP of the position information and the data length of the DMA cache physical memory block pointed by the write pointer WP. In the step, the information compression method introduced and described above is adopted, 32bit values consisting of the sub-block sequence number c of the large block memory sequence number a and the data length L are written into the register for 1 time in a register writing mode, and necessary information of DMA transmission of lower-layer equipment is informed;
s208, moving the write pointer WP forward;
s209, judging whether WP > = memory subblock M, if WP is larger than or equal to M, executing S210 to move WP to the initial position 0 of the buffer queue, otherwise executing S211;
s210, pointing a WP pointer to a physical memory block 0 of the DMA cache queue;
s211, checking whether downlink data need to be transmitted or not, if the data exist, jumping to S212 to continue execution, and if all the downlink data are transmitted, jumping to S213 to end the operation;
s212, checking whether the counter REG _ FIFO is 0, and if the counter REG _ FIFO is 0, jumping to S202 to read the value of the register to update the REG _ FIFO again; if not, jumping to S206 to start the next data copy;
and S213, finishing the batch transmission, and ending the process execution.
Having described the present invention in detail with respect to a method for downlink data transmission, it will be apparent to one skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (3)
1. A method for efficient downlink data transmission of an upper computer is characterized by comprising the following steps:
s1, allocating A large blocks of continuous memories, dividing the large blocks of continuous memories into C sub-blocks with equal length according to a preset length K, and writing the quantity A of the memory blocks allocated after initialization, the quantity C of the sub-blocks divided by each memory block, the length K of each sub-block and the initial physical address of each of the A memory blocks into lower-layer equipment;
s2, the upper computer and the lower layer device respectively establish a circular queue with the depth of M, N, M is larger than or equal to N, each storage item of the circular queue of the upper computer corresponds to a continuous physical memory, and the circular queue of the lower layer device is used for storing DMA information written by the upper computer;
s3, during data transmission, the upper computer copies data to be transmitted into the c-th sub-block of the large block memory block with the sequence number a, integrates the sequence number a, the sequence number c and the data length L into a numerical value R, and writes the numerical value to the lower-layer equipment in a register writing mode;
and S4, the lower layer device acquires the physical address Aa of the large block memory according to the sequence number a, calculates and acquires the physical address ADDR of the data storage according to a formula ADDR = Aa + (c × K), and then initiates a DMA operation according to the data length L analyzed from the integrated value R to acquire the data.
2. The method for efficient downlink data transmission by an upper computer according to claim 1, wherein in step S3, before the upper computer copies the data to be transmitted, the upper computer reads the value of the DMA information amount register writable by the lower device, updates the counter REG _ FIFO, determines whether the REG _ FIFO is 0, and if the REG _ FIFO is 0, waits for a predetermined time, updates the counter REG _ FIFO again and determines that the data to be transmitted does not start to be copied until the REG _ FIFO is not 0.
3. The method as claimed in claim 2, wherein the upper computer and the lower layer device store the related information of data transmission in a circular queue manner, and calculate and determine whether the initially written data transmission request is completed in a manner of reading the counter for multiple times, so as to release the related resources of completed transmission in time when continuous data transmission is performed without interruption.
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