JP6364827B2 - Information processing apparatus, resource access method thereof, and resource access program - Google Patents

Description

  The present invention relates to a technology that enables a number of tasks executed by each processor core to access a specific resource in parallel in an information processing apparatus having a plurality of processor cores.

  2. Description of the Related Art In recent years, information processing apparatuses such as computers (hereinafter sometimes referred to as “multi-core systems”) having a plurality of processor cores (hereinafter simply referred to as “cores”), which are arithmetic processing devices, have become widespread.

  Processes and threads (hereinafter, sometimes collectively referred to as “tasks”) that operate in such a multi-core system have a main memory such as a memory in order to output various information related to the processing of the tasks at high speed. A device (hereinafter sometimes referred to as a “memory area”) may be used as a temporary output area. In this case, for example, various data output from the task to the memory area may be stored in a database system or a file system provided in a secondary storage device such as a hard disk by another task or the like.

  In such a multi-core system, when a multi-task operating system (OS) that can process a plurality of tasks in parallel operates, the scheduler of the OS has only one task per core at a specific moment. Control to execute. That is, one core is limited to not process more than one task at a particular moment.

  In the multi-core system as described above, a plurality of tasks may be executed simultaneously by different cores. Therefore, when accessing various resources shared by each task (hereinafter sometimes referred to as “resources”), exclusive control may be required for the resources.

  More specifically, for example, when multiple tasks output various types of information to a specific memory area, it is necessary to incorporate exclusive control into the task itself in consideration of the possibility of conflicting output processing of each task. There is.

  When exclusive control for shared resources is implemented, the resources related to other resources cannot be accessed while a specific task occupies the related resources, so the processing performance as a whole (hereinafter sometimes referred to as “throughput”) May decrease. In addition, processing overhead that occurs in connection with such exclusive control processing also causes a reduction in processing performance.

  More specifically, for example, when a large number of tasks run in parallel, each task outputs its operation log to a specific memory area. For example, multiple tasks output information to a specific small number of shared areas. In some cases, exclusive control may be required between tasks. This causes a reduction in the processing performance of the entire system.

  In order to avoid the degradation of processing performance associated with exclusive control as described above, for example, a method of preparing a dedicated memory area for each individual task is conceivable. However, in this case, the maximum size of information that can be output by each task must be estimated, and a memory area must be prepared based on the total size, which may require a huge amount of memory.

  In addition, when the size of the memory area that can be prepared is limited, if the memory area is divided for each task and allocated to each task, a memory area of a necessary size cannot be secured depending on the task. It may not be used effectively.

  That is, in a system in which different tasks are executed in parallel in a plurality of cores, a technique capable of efficiently processing access from each task to a resource is required.

  For example, the following patent documents are disclosed as techniques related to access to a shared resource such as a memory in an environment where a plurality of tasks as described above are executed.

  Patent Document 1 discloses a technique for enabling a dedicated memory area associated with each core to be used from another core in a multi-core processor having a plurality of cores.

  According to the technology disclosed in Patent Document 1, in a multi-core processor having a plurality of cores, the state of each core is monitored, and the associated memory associated with the core in the dormant state is used from another core Make it possible. Since the associated memory can be accessed at a higher speed than the external memory, according to the technique disclosed in Patent Document 1, it is possible to effectively use a memory area accessible at a high speed.

  Patent Document 2 discloses a technique in which a plurality of cores simultaneously access different cache memory areas in a multi-core processor.

  The technique disclosed in Patent Document 2 controls access from each core to an exclusive control target using a semaphore management table. Further, the technique disclosed in Patent Document 2 considers the priority assigned to each core during such exclusive control. According to the technique disclosed in Patent Document 2, access to an exclusive control target can be controlled based on a semaphore, and high priority processing can be performed with a short overhead.

  Patent Document 3 discloses a technique related to an exclusive control device for a shared memory.

  According to the technique disclosed in Patent Document 3, in a system having a plurality of processors and a shared memory, each processor sets an identification signal of the processor on the address signal line of the memory bus, thereby exclusive use of the memory. Win the right. The memory access controller recognizes the processor that has acquired the exclusive use right by monitoring the address signal line, and returns a retry response to an access request from another processor. Thereby, the technique disclosed in Patent Document 3 realizes exclusive control related to access from each processor to the shared memory.

  Patent Document 4 discloses a technique related to a multiprocessor system having a plurality of processors, a private memory prepared for each processor, and a shared memory accessible from all the processors. The technique disclosed in Patent Literature 4 implements a multitasking operating system in a local memory allocated for each processor. Then, the kernel part of the operating system is arranged in the private memory for each processor, and the task information part is arranged in the shared memory. According to the technique disclosed in Patent Document 4, since access to the kernel portion does not cause a memory access bus contention between processors, the throughput (processing performance) of the entire system can be improved.

JP 2009-037403 JP 2007-141155 A JP 2003-280980 A JP 2001-155001 A

  As described above, in a multi-core system in which a plurality of tasks are executed at the same time, there is a demand for a technique capable of suppressing a decrease in processing performance associated with exclusive control when accessing a shared resource such as a memory area. . In addition, it is desirable that such a technique can process access to the resource from a plurality of tasks in parallel and does not require a huge amount of resources.

  Here, the above-mentioned Patent Document 1 does not consider any exclusive control for the associated memory when a plurality of tasks (programs) are simultaneously executed in a plurality of cores.

  The above Patent Document 2 is premised on that only one task is assigned to each core. Further, when accessing a resource shared between cores, a normal exclusive control process is required.

  The above-mentioned Patent Document 3 is a mounting technology that suppresses an increase in circuit scale and improves the use efficiency of a bus, and requires exclusive control between processors when accessing a shared memory.

  Further, Patent Document 4 does not specifically mention the exclusive control in the case where a task executed in each processor shares a specific area on the local memory, for example. Since tasks are executed in parallel in each processor, it is expected that general exclusive control is required when simultaneously accessing a specific area on the local memory. For this reason, only the technique disclosed in each of the above-mentioned patent documents cannot sufficiently solve the above-described problem.

  The present invention has been made in view of the above circumstances. That is, the main object of the present invention is to provide an information processing apparatus or the like that allows a plurality of tasks to access a specific resource in parallel in a multi-core system having a plurality of processor cores.

In order to achieve the above object, an information processing apparatus according to the present invention has the following configuration. That is, the information processing apparatus according to the present invention includes a plurality of arithmetic processing means capable of executing one or more tasks, and information output from the task associated with the arithmetic processing means and executed by the arithmetic processing means. Notification is made based on the specific task among the one or more tasks, the dedicated memory area that is the first storage means to hold, the arithmetic processing assignment management means for assigning one or more of the tasks to the arithmetic processing unit, and The access request to the dedicated memory area is received, the occupancy of the arithmetic processing unit executing the specific task is requested to the arithmetic processing allocation management unit, and the processing unit associated with the arithmetic processing unit Resource access means for processing the access request to the dedicated memory area.

A resource access method in an information processing apparatus according to the present invention has the following configuration. That is, the resource access method in the information processing apparatus according to the present invention includes a plurality of arithmetic processing means capable of executing one or more tasks, and the task associated with the arithmetic processing means and executed by the arithmetic processing means. An information processing apparatus having a dedicated memory area that is a first storage unit that holds information to be output, to an arithmetic processing assignment management unit that allocates one or more tasks to the arithmetic processing unit. When an access request to the dedicated memory area notified based on the specific task among the tasks is received, the occupation processing unit executing the specific task is requested to be occupied, and the calculation is performed. The access request for the dedicated memory area associated with the processing means is processed.

  The object is also achieved by a computer program for realizing the communication control apparatus having the above-described configuration and the corresponding communication control method by a computer, and a computer-readable storage medium storing the computer program. Achieved.

  According to the present invention, in a multi-core system having a plurality of processor cores, a plurality of tasks can output arbitrary information in parallel to specific resources. More specifically, it is possible to provide an information processing apparatus or the like in which a plurality of tasks can access resources prepared for each processor core in parallel.

FIG. 1 is a block diagram illustrating a conceptual configuration of a multi-core system according to the first embodiment of the present invention. FIG. 2 is a diagram illustrating a conceptual configuration of the dedicated memory area according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating a conceptual configuration of the information holding area included in the dedicated memory area according to the first embodiment of the present invention. FIG. 4 is a block diagram illustrating a hardware configuration capable of realizing a multi-core system according to the first embodiment of the present invention. FIG. 5 is a flowchart illustrating a process of processing an information output request from a task in the multi-core system according to the first embodiment of the present invention. FIG. 6 is a flowchart illustrating a process of processing a file output request in the library in the multi-core system according to the first embodiment of the present invention. FIG. 7 is a flowchart illustrating the file output process in the multi-core system according to the first embodiment of the present invention. FIG. 8 is a block diagram conceptually illustrating the configuration of the information processing apparatus according to the second embodiment of the present invention. FIG. 9 is a block diagram illustrating a hardware configuration capable of realizing the information processing apparatus according to each embodiment of the present invention.

  Next, embodiments of the present invention will be described with reference to the drawings. The configurations described in the following embodiments are merely examples, and the technical scope of the present invention is not limited thereto.

<First Embodiment>
Hereinafter, the configuration of the multi-core system 100 that is the information processing apparatus according to the present embodiment will be described with reference to FIGS. 1 and 2.

  FIG. 1 is a diagram conceptually illustrating the configuration of a multi-core system 100 according to the present embodiment. As illustrated in FIG. 1, the multi-core system 100 includes a core 101 (“core 01” to “core 04” illustrated in FIG. 1) and a dedicated memory area 102 accessible from the core 101 (illustrated in FIG. 1). “Dedicated memory area 01” to “dedicated memory area 04”).

  In addition, the multi-core system 100 includes a plurality of tasks 103 executed in the core 101, a library 104 that provides an access function to the dedicated memory area 102 and the like for the task 101 and the like, and the dedicated memory area 102 And a file output unit 105 that outputs the held (stored) information to the file 106.

  Further, the multi-core system 100 has an OS (Operating System) that controls execution of the task 103 and the like. The OS includes a scheduler 107 that controls the execution order of each task 103 and the allocation of each task to the core 101. The scheduler 107 includes a core allocation management unit 108. Hereinafter, each component will be described.

  The core 101 is an arithmetic device such as a CPU (Central Processing Unit), and executes processing implemented in the task 103. The core 101 in the present embodiment may be a single CPU by itself, or may be an arithmetic processing unit that constitutes a part of a single CPU. In the specific example illustrated in FIG. 1, “core 01” to “core 04” are illustrated as the core 101. The multi-core system 101 in the present embodiment is not limited to this, and any number of cores 101 may be employed.

  In the multi-core system 100, only the task 103 to which the core 101 is assigned is set to the execution state, and the execution of the task 103 to which the core 101 is not assigned is interrupted. In this case, the processing of the task 103 is temporarily stopped, but the task 103 itself does not recognize that the processing is stopped.

  The dedicated memory area 102 is an area for holding various information output from a task 103 described later. A dedicated memory area 102 is provided for each core 101, and one dedicated memory area 102 is associated with one core 101. In the present embodiment, the access to the dedicated memory area 102 is limited to the task 103 executed in the core 101 associated with the dedicated memory area.

  That is, the task 103 executed in the other core 101 cannot access the dedicated memory area 102 associated with the specific core 101. However, only the dedicated memory area initialization process by the file output unit 105 to be described later can access all the dedicated memory areas 102 regardless of which core 101 the file output unit 105 is executing. The specific method for restricting access described above may employ a technique such as a well-known OS or a well-known memory controller, and will not be described in detail.

  The dedicated memory area 102 in this embodiment includes a management information area 201 and an information holding area 202 as exemplified in FIG. In the specific example illustrated in FIG. 2, the management information area 201 includes, as management information related to the dedicated memory area 102, an overall area size 201a, a file output flag 201b, a free area size 201c, a free area pointer 201d, Have

  The entire area size 201a is an area for holding the entire size capable of holding information in the dedicated memory area 102.

  The file output flag 201b holds information indicating whether or not the file output unit 105, which will be described later, is executing a process of outputting information held in the dedicated memory area 102 to a specific file 106.

  The empty area size 201c holds the size of the empty area 202b in the information holding area 202.

  The empty area pointer 201d holds information indicating the head position of the empty area 202b.

  The information holding area 202 is an area for holding information output from the task 103, and includes a used area 202a in which such information is written and an unused free area 202b.

  The used area 202a is an area in which various information output from the task 103 executed in the core 101 associated with the dedicated memory 102 is written. Depending on the execution status of the task 103, the used area 202a may not exist (information may not be output).

  As illustrated in FIG. 3, the information holding area 202 holds header information 301 and output information 302 from a task. In this embodiment, the header information 301 and the output information 302 from the task are written in the information holding area 202 by the library 104 described later. In the specific example illustrated in FIG. 3, the header information 301 includes an output time 301a, a task ID 301b, and a size 301c.

  The output time 301 a holds information indicating the time when the output information 302 output from the specific task 103 is written in the dedicated memory area 102.

  The task ID 301b holds identification information that can uniquely identify the task 103 in which the output information 302 is written. As such identification information, for example, a process ID or thread ID related to a task 103 to be described later, or a combination of these and a process name may be employed.

  The size 301c holds the size of the output information 302 from the task.

  The header information 301 is added by the library 104, which will be described later, when information designated by the task 103 is written to the dedicated memory area 102. The header information 301 is used to specify the task 103 that has output the information and the content of the output information.

  As described above, the task 103 is a process or thread executed in the multi-core system 100. What kind of processing each task 103 executes may be arbitrarily determined by a software program (computer program) or the like that implements the task 103.

  Note that the task 103 in this embodiment outputs various types of information to the dedicated memory area 102 via a library 104 described later. The content of information output by the task 103 may be determined as appropriate, and may include, for example, log information related to the processing of the task 103.

  The library 104 is a software program that provides a function of accessing the dedicated memory area 102 to the task 104, the file output unit 105 described later, and the like. More specifically, the library 104 provides a write / read function for the dedicated memory area 102, a function for initializing a specific area in the dedicated memory area 102, and the like.

  In response to an information output request from the task 103, the library 104 in this embodiment identifies the dedicated memory area 104 associated with the core 101 to which the task 103 is assigned, and writes information to the dedicated memory area 104. I do. Further, during the writing process, the core assignment management unit 108 to be described later is requested to exclusively use the core 101 assigned to the task 103. Further, it requests the file output unit 105 (to be described later) to output the information in the memory area to the file 106 or the like according to the usage status of the dedicated memory area 102. The library 104 according to the present embodiment may provide an interface that allows the task 103 to specify the contents of various information output by the task 103 and the output size.

  The library 104 in the present embodiment may be executed together with the task 103 in the core 101 in which the task task 103 using the library 104 is executed, for example. That is, the library 104 in the present embodiment may be executed by the core 101 as one unit with the task 103 by linking with the task 103 using the library 104, for example.

  Specific contents of each process in the task 103 and the library 104 will be described later.

  The file output unit 105 is a task that executes processing for saving various types of information written in the dedicated memory area 102, initialization processing for reusing the dedicated memory area 102, and the like. The file output unit 105 is called from the library 104 at an appropriate timing, and transfers various information written in the dedicated memory area 102 to the file 106 or the like. Further, the file output unit initializes the management information of the dedicated memory area 102. As a result, new information can be written into the dedicated memory area 102.

  The file 106 in this embodiment is a storage area provided by a file system or the like provided in a secondary storage device such as a hard disk (not shown). The file 106 in this embodiment holds (records) various information output by the file output unit 105.

  The file output unit 105 and the file 106 are not limited to the above. For example, the file 106 may be realized as a database record (not shown), and the file output unit 105 may output the database record. .

  The scheduler 107 is provided as a part of the multitasking OS that constitutes the multicore system 100, and performs scheduling for assigning the core 101 to the task 103 waiting in an executable state based on a predetermined criterion.

  Here, as a criterion for selecting the task 103 to be executed in the core 101, for example, a criterion such as a high priority and a short estimated remaining time until the completion of processing may be appropriately selected. In addition, as a criterion for selecting the core 101 that executes the task 103, for example, a criterion such as a balance of the usage rate (operating rate of each core) with respect to each core and the possibility of a cache hit may be appropriately selected. These criteria may be selected based on a predetermined policy defined for the multi-core system 100, for example.

  The scheduler 107 according to the present embodiment allocates the core 101 to a specific task 103 based on information on the assignable core 101 (assignable core information 109) managed by the core assignment management unit 108 described later. Note that the scheduler 107 in the present embodiment may have the same functions as those of a scheduler installed in a well-known multitask OS, in addition to the core allocation described above.

  The core assignment management unit 108 manages information on the cores 101 that can be assigned to the task 103 (assignable core information 109), and provides the information to the scheduler 107. In addition, the core allocation management unit 108 accepts a request from the library 104 to allocate the specific core 101 exclusively to the specific task 103 (hereinafter may be referred to as “occupation”). The core allocation management unit 108 controls whether or not each core 101 can be allocated to the task 103 based on the occupation request.

  Note that the multitasking OS in the present embodiment controls so that one core 101 executes only one task 103 at a specific moment, like the known multitasking OS. That is, one core is limited to not process more than one task at a particular moment.

  Note that the multitasking OS switches, for example, a task 103 executed in a specific core 101 at regular intervals (for example, by assigning one core 101 to a plurality of tasks 103 in a time division manner). It may be controlled so that one core can execute a plurality of tasks within a certain period. Note that the switching operation of the task 103 may employ a well-known technique, and thus detailed description thereof is omitted.

  A specific example of a hardware configuration capable of realizing the multi-core system 100 described above is illustrated in FIG.

  The multi-core processor 401 includes a plurality of cores 101 and an IO controller that controls input / output with respect to the cores 101.

  The primary storage device 402 includes a plurality of dedicated memory areas 102 associated with the core 101, a task 103 executed in each core, a general-purpose memory area accessible from the multitask OS, and a primary storage device. And a memory controller that controls output and data arrangement. The primary storage device 402 may be composed of, for example, a volatile RAM (Random Access Memory).

  The secondary storage device 403 is a non-volatile storage area configured by, for example, a hard disk or the like. For example, the secondary storage device 403 may store various files provided in the file system, a database, and the like. For example, in the present embodiment, the file 106 illustrated in FIG. 1 may be stored in the secondary storage device 403.

  The program storage area 404 is an area for storing software programs constituting the multi-core system 100 in the present embodiment. In the configuration illustrated in FIG. 4, the program storage area is described as an element different from the secondary storage device 403, but the program storage area 404 may be included in the secondary storage device 403. Further, the program storage area 404 may be configured by a ROM (Read Only Memory) or the like separately from the secondary storage device 403, for example.

  According to the multi-core system 100 configured as shown in FIG. 4, for example, the multi-task OS loads the task 103 and the library 104 stored in the program area 404 into the primary storage device 402, and loads the loaded task 103. When the core 101 in the multi-core processor 401 executes, various processes implemented in the task 103 are executed.

  Next, the operation of the multi-core system configured as described above will be described. In the following, an operation for outputting various types of information from the task 103 to the dedicated memory area 102 will be described with reference to flowcharts illustrated in FIGS.

  First, the operations of the task 103 and the library 104 will be described with reference to the flowchart illustrated in FIG.

  In the following description, a specific core 01 (hereinafter referred to as “core 01”) is assigned to a specific task 103 (hereinafter referred to as “task 01”), and the task 01 is assigned to the core 01. Assume that the state is being executed by.

  First, the task 01 requests the output of arbitrary information using the function provided by the library 104 (step S501). More specifically, the task 01 calls the information output interface provided by the library 104 by specifying the content of information to be output and its size. Hereinafter, such a request for outputting arbitrary information issued from the task 101 may be referred to as an “information output request”.

  The library 104 that has received the information output request from the task 01 requests the core allocation management unit 108 to occupy the core 01 so as not to deallocate the core 01 to the task 01 (step S502). After step S502, the task 01 can output various types of information to the dedicated memory area 102 (hereinafter referred to as “dedicated memory area 01”) associated with the occupied core 01.

  In the following, the library 104 confirms various information held in the management information area 201 in the dedicated memory area 01, and executes predetermined processing according to the confirmation result (steps S503 to S508). Hereinafter, each processing content is demonstrated.

  First, the library 104 checks whether the information held in the dedicated memory area 01 is being output to the file 106 by the file output unit 105 (step S503). More specifically, the library 104 checks whether the information held in the dedicated memory area 01 is being output to the file 106 by checking the file output flag 201c of the management information area 201 in the dedicated memory area 01. judge. In this case, for example, when the file output flag 201c is set to “ON”, the library 104 determines that the file is being output to a file, and when the file output flag 201c is set to “OFF”, the library 104 It may be determined that the output is not being performed.

  As a result of the determination, if the file is being output (YES in step S504), the process of outputting the information held in the dedicated memory area 01 to the file is being executed, so it is necessary to avoid access to the dedicated memory area 01. is there. That is, information related to the information output request of the task 01 cannot be written (output) to the dedicated memory 01.

  For this reason, the library 104 needs to write information output from the task 01 in a dedicated memory area 102 other than the dedicated memory area 01 (a dedicated memory area 102 associated with the core 101 other than the core 01).

  Therefore, in this case, the library 104 requests the core allocation management unit 108 to allocate and occupy the tasks 01 of the cores other than the core 01 (step S505). Further, the library 104 may notify the core allocation management unit 108 that the occupation of the core 01 executing the task 01 is to be released. Thereafter, when the core 101 other than the core 01 is assigned to the task 01 by the scheduler 107, the library 104 continues the processing from step S504.

  Next, as a result of the confirmation in step S503, when the file is not being output (NO in step S504), the library 104 confirms the size of the free area 202b in the dedicated memory area 102 (step S506). More specifically, the library 104 checks the size of the free area 202b by checking the free area size 201c in the dedicated memory area 01.

  As a result of the confirmation in step S506, if the size of the free area 202b in the dedicated memory area 01 is smaller than the sum of the size of the information requested by the task 01 and the size of the header information 301 (NO in step S507), The dedicated memory area 01 cannot provide a free area sufficient to hold information output by the task 01. In this case, the task 01 cannot write (output) information to the dedicated memory area 01.

  For this reason, the library 104 executes a file output request process (step S508) so that the information held in the dedicated memory area 01 is output to the file output unit 106.

  Hereinafter, the file output request process in step S508 will be described with reference to the flowchart illustrated in FIG.

  First, the library 104 sets the file output flag 201b in the dedicated memory area 01 (sets it to “ON”) so that other tasks 103 other than the file output unit 106 do not access the dedicated memory area 01 (step “ON”). S601).

  Next, the library 104 outputs the information held in the dedicated memory area 01 (more specifically, information held in the information holding area 202) to the file output unit 106 to a specific file 106. A request is made (step S602).

  When the library 104 executes step S602, the file output unit 106 executes processing for outputting the data held in the information holding area 202 in the dedicated memory area 01 to a file. Therefore, the task 01 cannot write (output) information to the dedicated memory area 01. For this reason, after step S508, the library 01 continues processing from step S505, and requests the assignment of the core 101 other than the core 01 and the occupation of the assigned core to the task 01. Thereafter, when the core 101 other than the core 01 is assigned to the task 01 by the scheduler 107, the library 104 executes the process again from step S504.

  Next, as a result of the confirmation in step S506, if the size of the free area 202b in the dedicated memory area 01 is sufficiently large (YES in step S507), the task 01 performs an information holding area in the dedicated memory area 01 via the library 104. Arbitrary information is written (output) in 202 (step S509).

  More specifically, the task 01 requests writing of arbitrary information through an interface provided by the library 104. The library 104 that has received such a request writes the information passed from the task 01 into the information holding area 202 of the dedicated memory area 01.

  At this time, the library 104 adds header information 301 to the information requested by the task 01 to be written (hereinafter sometimes referred to as “output information”). Then, the library 104 writes the header information and the output information from the task 01 at the position specified by the free area pointer 201d.

  Next, the library 104 updates the management information area 201 in the dedicated memory area 01 (step S510). More specifically, the library 104 updates the value of the free area size 201c and changes the position of the free area pointer 201d.

  Next, the library 104 checks the value of the free area size 201c in the updated dedicated memory area 01 (step S511). That is, as a result of writing the output information from the task 01, the library 104 checks how much area remains in the dedicated memory area 01 as the free area 202b.

  As a result of the confirmation in step S511, if the library 104 determines that the size of the free area is small based on a predetermined standard (NO in step S512), the library 104 performs file output request processing similarly to step S508. Is executed (step S514). By the file output request process, various information held in the dedicated memory area 01 is written to the file 106, so that the size of the free area 202b in the dedicated memory area 01 increases. After executing the process of step S514, the library 104 continues the process from step S513 below.

  Next, as a result of the confirmation in step S511, if the library 104 determines that the size of the free area is sufficiently large based on a predetermined standard (YES in step S512), the library 104 determines that the core allocation management unit 108 Is notified that the occupation of the core 01 is to be released (step S513). After execution of the processing in step S513, the core 01 can be used by other tasks 103 other than the task 01.

  In step S511, the criterion for determining whether the size of the free area 202b in the dedicated memory area 01 is sufficient may be appropriately selected according to the characteristics of the multi-core system 100, for example.

  Next, the operation of the core assignment management unit 108 will be described.

  The core assignment management unit 108 holds information on the cores 101 that can be assigned to each task 103 as assignable core information 109, and provides the information to the scheduler 107. It should be noted that how the core allocation management unit 108 specifically holds information on the assignable cores 101 may be selected as appropriate.

  The core assignment management unit 108 registers all the cores 101 that can be used in the multitask system 100 in the assignable core information 108 when an occupancy request for the core 101 is not received from a specific task 101 (library 104).

  When the core allocation management unit 108 receives a request (occupation request) to occupy a specific core 101 from the library 104 based on an information output request or the like from the specific task 101 (for example, steps S502 and S505 above) The information about the core 101 that is the target of the occupation request is deleted from the hitable core information 109.

  Since the scheduler 107 assigns the available core 101 to each task 103 based on the assignable core information 109, the core 101 deleted from the assignable core information 109 is not assigned to other tasks. In other words, when the core allocation management unit 108 and the scheduler 107 receive the occupancy request, the core 101 that is the target of the occupancy request is not the specific task 101 (library 104) that made the occupancy request. Control not to be assigned to a task.

  As a result, the specific task 101 that issued the information output request does not need explicit exclusive control, and exclusively uses the core 101 that is the target of the occupation request and the dedicated memory area 102 associated with the core. It is possible to use.

  When the core allocation management unit 108 receives an exclusive release request for the specific core 101 from the library 104 (for example, steps S505 and S513 described above), the core allocation management unit 108 allocates the specific core 101 specified in the exclusive release request. Register in the possible core information 109. As a result, the scheduler 107 can allocate the core 101 to another task 103.

  Next, processing of the file output unit 105 will be described with reference to a flowchart illustrated in FIG.

  For example, the file output unit 105 waits for a file output request from the library 104 (steps S508, S514 and the like illustrated in FIG. 5) (step S701). More specifically, the file output unit 105 may wait for such a file output request as a resident task in the multi-core system 100, for example.

  Next, the file output unit 105 checks whether a file output request has been received (step S702). If the file output request has not been received (NO in step S702), the file output unit 105 executes the standby process in step S701 again.

  On the other hand, when the file output request is received (YES in step S702), the dedicated memory area 102 (hereinafter referred to as “core 02”) associated with the specific core 101 (hereinafter referred to as “core 02”) designated in the file output request. The information held in “dedicated memory area 02” is read (step S703). More specifically, the management information area 201 and the information holding area 202 of the dedicated memory area 02 specified in the file output request are sequentially read.

  Next, the file output unit 105 outputs the information read in step S703 to the file 106 (step S704). Since a specific output (write) processing method for the file 106 may employ a known technique, a detailed description thereof will be omitted.

  Here, when the file output unit 105 executes the processing of steps S703 to S704, the file output flag in the dedicated memory area 02 is set to ON by the library 104 that has notified the file output request (FIG. 6). Step S601). For this reason, access to the dedicated memory area 02 does not compete with other tasks 101. That is, the file output unit 105 can access the dedicated memory area 02 without requiring explicit exclusive control.

  Next, after the output of the information held in the dedicated memory area 02 is completed, the file output unit 105 initializes the management information in the dedicated memory area 02 (step S705). More specifically, the file output unit 105 initializes the management information area 201 in the dedicated memory area 02 and sets the file output flag 201b to “OFF”. Further, the file output unit 105 may initialize the information holding area 202 together with the management information area 201.

  After the process in step S705, the file output unit 105 returns to step S701, continues the process, and waits for a further file output request.

  Since the file output unit 105 in this embodiment is realized as a kind of task 101, the processing of steps S 701 to S 705 is executed by the core 101 assigned to the file processing unit 105. The scheduler 107 may assign any available core 101 to the file output unit 105.

  In the present embodiment, a plurality of file output units 105 may be executed in parallel. In this case, for a plurality of dedicated memory areas 102, information held in the dedicated memory area 102 is output to a plurality of files 106 in parallel. Therefore, it is possible to increase the free capacity of the plurality of dedicated memory areas 102 in parallel, and it is possible to prepare the available dedicated memory areas 102 more quickly.

  As described above, in the multi-core system 100 according to the present embodiment, one core 101 can execute only one task 103 at a certain moment. Further, the specific dedicated memory area 102 can be accessed only by the task 103 executed in one specific core 101 associated with the specific dedicated memory area.

  For example, when a certain task 103 executes an information output request, a dedicated memory area associated with the specific core 101 is obtained by processing the information output request by occupying the specific core 101. 102 cannot be accessed. As a result, it is possible to avoid a race condition between a plurality of tasks 103.

  For this reason, according to the multi-core system 100 described above, it is not necessary to execute explicit exclusive control between the plurality of tasks 103, and information can be quickly output to a specific dedicated memory area 102.

  Also, each task 103 does not need to recognize which dedicated memory area 102 the information is output to. That is, when information cannot be output to a specific dedicated memory area 102 (for example, in the case of YES in step S504 illustrated in FIG. 5 or NO in step S507), the task itself is assigned to a different core 101. As a result, information can be output to different dedicated memory areas 102. That is, according to the described multi-core system 100, each task 103 can promptly execute the information output process without being affected by the usage status of the specific dedicated memory area 102 or the like.

  Further, according to the multi-core system 100 described above, the total storage capacity (size) that needs to be prepared as the dedicated memory area 102 is obtained by multiplying the maximum size of the output request from the task 103 by the total number of cores 101. Good. Since the total number of cores 101 is often smaller than the total number of tasks 103, the size of the memory to be prepared can be reduced as compared with the case where dedicated fishing areas are provided for all tasks 103.

  In addition, for example, in order to improve the performance of the entire multi-core system 100, even if the multi-core processor 401 is added, each task 103, library 104, etc. is corrected by preparing memory areas for the increased number of cores. The information output process can be executed without doing so. Further, in this case, even if the number of cores 101 increases, each task 103 does not require explicit exclusive control in the information output process, so that the information output process does not become a bottleneck of the entire multi-core system 100. .

  As described above, according to the multi-core system 100 of the present embodiment, a plurality of tasks 103 can output arbitrary information in parallel to the dedicated memory area 102, respectively.

  More specifically, by preparing a dedicated memory area 102 for each core 101, a plurality of tasks 103 can output arbitrary information in parallel to the dedicated memory area 102 for each core 101. . As a result, it is possible to provide an information processing apparatus (multi-core system 100) in which a plurality of tasks 103 can access a resource (dedicated memory area 102) prepared for each core 101 in parallel. is there.

<Second Embodiment>
Next, a second embodiment of the present invention will be described.

  FIG. 8 is a block diagram conceptually illustrating the configuration of the information processing apparatus 800 according to the present embodiment.

  The information processing apparatus 800 according to the present embodiment includes a plurality of arithmetic processing units 801 (such as “arithmetic unit 01” to “arithmetic unit 04” illustrated in FIG. 8) and a dedicated memory area 802 (“exclusive memory illustrated in FIG. Area 01 "to" dedicated memory area 04 "). Note that the number of arithmetic processing units 801 in the present embodiment may be appropriately selected according to the performance required for the information processing apparatus 800.

  In addition, the information processing apparatus 800 according to the present embodiment includes a plurality of tasks 803, a resource access unit 804, and an arithmetic processing assignment management unit 807.

  The arithmetic processing unit 801 is an arithmetic processing device that executes one or more tasks 803.

  The dedicated memory area 802 is a first storage unit that is associated with a specific arithmetic processing unit 801 and can hold various types of information output from the task 803 executed in the arithmetic processing unit 801.

  The task 803 is, for example, various software programs (computer programs) that are implemented so as to be executable in the arithmetic processing unit 801.

  The arithmetic processing allocation management unit 807 allocates one or more tasks 803 to a specific arithmetic processing unit 801. A task 803 to which a specific arithmetic processing device 801 is assigned is executed in the arithmetic scrivener device 801.

  The resource access unit 804 receives an access request to the dedicated memory area 802 notified by the specific task 803, and the operation processing unit 801 that is executing the specific task 803 with respect to the operation processing allocation management unit 807 And the access request for the dedicated memory area 802 associated with the arithmetic processing unit 801 is processed.

  In the present embodiment, the access request may be, for example, an information output request that requests that specific information be output from the specific task 803 to the dedicated memory area 802.

  In addition, the information processing apparatus 800 in the present embodiment may include a second storage output unit 805 and a second storage unit 806.

  In this case, the second storage output unit 805 may output various types of information held in the specific dedicated memory area 802 to the second storage unit 806 in response to a request from the resource access unit 804. In the present embodiment, the second storage unit 806 may be a storage device that can hold various types of information held in the dedicated memory area 802 such as a file or a database.

  In this case, the dedicated memory area 802 may accept only the access from the task 803 executed in the arithmetic processing unit 801 associated with the dedicated memory area 802 or the second storage output unit 805. .

  In the multi-core system 800 described above, only one specific core 801 associated with the specific dedicated memory area 102 is accessible to the specific dedicated memory area 102.

  For example, when a task 803 executes an information output request, the task 803 occupies a specific core 801, so that another task 801 accesses a dedicated memory area 802 associated with the specific core 801. I can't. Thereby, it is possible to avoid a race condition between a plurality of tasks 803.

  For this reason, according to the multi-core system 800 described above, it is not necessary to execute explicit exclusive control among a plurality of tasks 803, and information can be output to a specific dedicated memory area 802 quickly.

  As described above, according to the information processing apparatus 800 in this embodiment, a dedicated information output area (dedicated memory area 802) is prepared for each core 801, so that a plurality of tasks 803 do not perform exclusive control with each other in parallel. Thus, it is possible to output arbitrary information. Accordingly, it is possible to provide the information processing apparatus 800 that allows a plurality of tasks 803 to access a resource (dedicated memory area 802) prepared for each arithmetic processing apparatus 801 in parallel.

<Configuration of hardware and software program (computer program)>
Hereinafter, hardware and software programs capable of realizing the information processing apparatus in each of the above-described embodiments will be described.

  In the following description, the multi-core system 100 and the information processing apparatus 800 described in the above embodiments may be collectively referred to as “information processing apparatus or the like”.

  Each component such as the information processing apparatus described in each of the above embodiments may be configured by a dedicated hardware device that realizes each function. In this case, the components such as the information processing apparatus may be realized as hardware integrating all functions (such as an integrated circuit in which processing logic is mounted), or a combination of individual hardware realizing specific functions. You may comprise by.

  In addition, the components such as the information processing apparatus may be configured by hardware as illustrated in FIG. 9 and various software programs (computer programs) executed by the hardware. In the following description, the hardware illustrated in FIG. 9 may be simply referred to as information processing hardware.

  The arithmetic device 901 in FIG. 9 is an arithmetic processing device such as a general-purpose CPU (Central Processing Unit) or a microprocessor. The arithmetic device 901 may read various software programs stored in a nonvolatile storage device 903, which will be described later, into the storage device 902, and execute processing according to the software programs.

  In the specific example illustrated in FIG. 9, the arithmetic device 901 corresponds to, for example, the multi-core processor 401 and may include a core that is a plurality of arithmetic processing units.

  The storage device 902 is a memory device such as a RAM (Random Access Memory) that can be referred to from the arithmetic device 901, and stores software programs, various data, and the like. Note that the storage device 902 may be a volatile memory device.

  The storage device 902 corresponds to the primary storage device 402 and may provide a dedicated memory area (102, 802).

  The nonvolatile storage device 903 is a nonvolatile storage device such as a magnetic disk drive or a semiconductor storage device using a flash memory, and may record various software programs, data, and the like.

  The nonvolatile storage device 903 corresponds to the secondary storage device 403, and may store a file provided by a file system, a database, or the like. The nonvolatile storage device 903 may store various software programs (computer programs) as the program storage area 404.

  The network interface 906 is an interface device that can be connected to various communication networks. As the network interface 906, for example, a wired and wireless LAN (Local Area Network) connection interface device or the like may be employed.

  In each of the embodiments described above, for example, when the file 106 or the second storage unit 806 is provided by an external device connected by some communication network, each task (103, 803) is connected via the network interface 906. ) May be transmitted to the external device.

  The external storage device 904 is, for example, a device that processes reading and writing of data with respect to an external storage medium 905 described later.

  The external recording medium 905 is an arbitrary recording medium capable of recording data, such as an optical disk, a magneto-optical disk, and a semiconductor flash memory.

  The present invention described by taking the above-described embodiments as examples, for example, configures the information processing apparatus and the like by the information processing hardware illustrated in FIG. After the software program capable of realizing the function of the flowchart referred to in the above is supplied, the software program may be executed by the execution of the arithmetic device 901.

  In each embodiment described above, each unit (for example, core allocation management unit (108, 807), file output unit 105, second storage output unit 805, library 104, resource access unit 804, task (103) , 803) etc. can be realized as a software program executed by the hardware described above.

  These can also be realized as a software module, which is a function (processing) unit of a software program executed by the hardware described above. However, the division of each part shown in these drawings is a configuration for convenience of explanation, and various configurations can be assumed for mounting.

  For example, when each unit constituting the information processing apparatus or the like is realized as a software program, the software program is stored in the nonvolatile storage device 903, and when the arithmetic device 901 executes each process, These software programs may be read out to the storage device 902.

  In addition, various kinds of data may be transmitted between these software programs by an appropriate method such as shared memory or interprocess communication. With such a configuration, these software programs can be connected so as to communicate with each other.

  Further, each software program is recorded in the external storage medium 905, and the software program is stored in the nonvolatile memory 903 through the external storage device 904 as appropriate at the shipping stage or operation stage of the communication device or the like. You may comprise.

  Further, when the constituent elements such as the information processing apparatus in each of the above embodiments are realized as a software program, the information output to the file 106 and the second storage unit 806 described in each of the above embodiments has an appropriate data structure. Or the like, may be stored in the nonvolatile storage device 903. These pieces of information may be stored in the nonvolatile storage device 903 by storing them in an arbitrary database or the like.

  The method of supplying various software programs to each information processing apparatus is a method of installing in the apparatus using an appropriate jig at the manufacturing stage before shipment or the maintenance stage after shipment. A general procedure can be adopted at present, such as a method of downloading from the outside via a communication line such as the Internet. In such a case, the present invention can be understood to be constituted by a code constituting the software program or a computer-readable storage medium in which the code is recorded.

  In the above, this invention was demonstrated as an example applied to exemplary embodiment mentioned above. However, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to such embodiments. In such a case, a new embodiment to which such changes or improvements are added can also be included in the technical scope of the present invention. This is clear from the matters described in the claims.

  The present invention can be applied to an information processing system or the like in which a plurality of tasks operate in parallel and each task outputs information such as a processing result in parallel.

DESCRIPTION OF SYMBOLS 100 Multi-core system 101 Core 102 Dedicated memory area 103 Task 104 Library 105 File output part 106 File 107 Scheduler 108 Core allocation management part 109 Allocable core information 401 Multi-core processor 402 Primary storage device 403 Secondary storage device 404 Program storage area 800 Information Processing device 801 Arithmetic processing unit 802 Dedicated memory area 803 Task 804 Resource access unit 805 Second storage output unit 806 Second storage unit 807 Arithmetic processing allocation management unit 901 Arithmetic device 902 Storage device 903 Nonvolatile storage device 904 External storage device 905 External recording medium 906 Network interface

Claims (10)

A plurality of arithmetic processing means capable of executing one or more tasks;
A dedicated memory area which is a first storage means associated with the arithmetic processing means and holds information output from the task executed in the arithmetic processing means;
Arithmetic processing assignment managing means for assigning the task to the arithmetic processing means;
An access request to the dedicated memory area notified based on a specific task among one or more of the tasks is received, and the calculation processing means that is executing the specific task is assigned to the calculation processing allocation management means. An information processing apparatus comprising: resource access means for making a request and processing the access request for the dedicated memory area associated with the arithmetic processing means. The access request is a request for requesting output of arbitrary information from the task to the dedicated memory area.
The information processing apparatus according to claim 1. In response to an access request from the specific task to the dedicated memory area, the resource access unit requests the arithmetic processing allocation management unit to occupy the specific arithmetic processing unit that is executing the specific task. In case,
The arithmetic processing allocation management unit, in response to the request for the specific said arithmetic processing means, characterized in that it does not assign a process different from the task and the specific task,
The information processing apparatus according to claim 1 or 2. The resource access means is:
When an access request for the dedicated memory area from the specific task is received, if the dedicated memory area cannot provide a memory area of the size requested in the access request,
Requesting the arithmetic processing assignment management means to assign the specific task associated with the access request to the arithmetic processing means different from the arithmetic processing means executing the specific task. The information processing apparatus according to any one of claims 1 to 3. Second storage means capable of holding information held in the dedicated memory area;
In response to a request from the resource access means, the information stored in the dedicated memory area is output to the second storage means, and an area related to the output information is initialized in the dedicated memory area. And 2 memory output means,
The information processing apparatus according to any one of claims 1 to 4. The resource access means is:
When the access request to the dedicated memory area from the specific task is received, the second storage output unit executes a process of outputting the information held in the dedicated memory area to the second storage unit If
Requesting the arithmetic processing assignment management means to assign the specific task associated with the access request to the arithmetic processing means different from the arithmetic processing means executing the specific task. The information processing apparatus according to claim 5. The resource access means is:
When the size of the free area in the specific dedicated memory area is confirmed and it is determined that the size of the confirmed free area is small based on a predetermined criterion,
The second storage output unit is requested to output the information held in the specific dedicated memory area to the second storage unit,
The information processing apparatus according to claim 5. The dedicated memory area in the storage means is accessible only by the task executed in the arithmetic processing means associated with the dedicated memory area, or the second storage output means,
The information processing apparatus according to claim 5 . A plurality of arithmetic processing means capable of executing one or more tasks, and a first information associated with the arithmetic processing means and holding information output from the task executed in the arithmetic processing means
An information processing apparatus having a dedicated memory area as storage means,
When an access request to the dedicated memory area notified based on a specific task among the one or more tasks is received with respect to the arithmetic processing allocation management unit that allocates one or more tasks to the arithmetic processing unit Requesting the occupation of the arithmetic processing means executing the specific task,
Processing the access request for the dedicated memory area associated with the arithmetic processing means;
A resource access method in an information processing apparatus. A plurality of arithmetic processing means capable of executing one or more tasks, and a dedicated memory which is associated with the arithmetic processing means and is a first storage means for holding information output from the task executed in the arithmetic processing means A computer having a region,
When an access request to the dedicated memory area notified based on a specific task among the one or more tasks is received with respect to the arithmetic processing allocation management unit that allocates one or more tasks to the arithmetic processing unit And processing for requesting occupation of the arithmetic processing means executing the specific task,
Executing the access request to the dedicated memory area associated with the arithmetic processing means,
A resource access program in an information processing apparatus.

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