JP2007259648A - Charger for capacitor storage power supply - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform charging efficiently without feeding a current too much and without causing deficiency of power through simple circuitry. <P>SOLUTION: The charger for a capacitor storage power supply comprises a constant current control circuit 1 outputting a charging current I and an error amplification signal for controlling the charging current I based on a current reference value Vrefi, a power control circuit 2 outputting a charging power P and an error amplification signal for controlling the charging current I based on a power reference value Vrefp, a constant voltage control circuit 3 outputting a charging voltage Vc and an error amplification signal for controlling the charging current I based on a voltage reference value Vrefv, OR circuits D11-D31 outputting any one of error amplification signals while switching, and a control circuit 62 for generating a pulse width modulation signal based on an error amplification signal outputted from the OR circuit and controlling the charging current I by turning switch circuits SW1 and SW2 on/off wherein charging is performed for a capacitor storage power supply 7 for charging an electric double layer capacitor. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a capacitor storage power supply charging device that charges a capacitor storage power supply that stores power in an electric double layer capacitor.

  In a high-voltage, large-capacity storage power supply device configured by connecting a plurality of electric double layer capacitors in series, the terminal voltage varies greatly depending on the amount of charge / discharge. In such a capacitor storage power source, when performing constant voltage charging like a secondary battery, the efficiency is low, and a large charging current flows at the initial stage of charging, resulting in a problem of current resistance. Efficient charging is realized. In addition, in a power storage power source composed of an electric double layer capacitor, in order to solve the problem due to variation between capacitors connected in series, if a reference value is set and the terminal voltage (charging voltage) of each electric double layer capacitor exceeds the reference value A parallel monitor that bypasses the charging current and limits the terminal voltage of each electric double layer capacitor is connected.

The parallel monitor thus bypasses the charging current, thereby limiting the charging voltage to a predetermined value (full charging voltage within the withstand voltage range), and reducing the variation in charging voltage in each electric double layer capacitor. However, if the parallel monitors are sequentially bypassed as the charging voltage of each electric double layer capacitor increases, the power loss in the parallel monitors is proportional to the operating time and the number of bypassed parallel monitors. Becomes larger. Therefore, it is necessary to prevent the parallel monitor from performing a long-time bypass operation with a large current. In addition, when the charging voltage of the entire storage power supply device rises and exceeds a predetermined value due to constant current charging, the charging device reduces the useless power loss. It is also necessary to provide a power limiter function for switching to constant power charging so as to be electric power (see, for example, Non-Patent Document 1 and Patent Document 1).
Okamura Ikuo, “Electric Double Layer Capacitor and Power Storage System”, Nikkan Kogyo Shimbun, September 30, 2005, 3rd edition, first print, pages 138-139 Japanese Patent No. 3306325

  When a capacitor is charged with a constant current from 0V to fully charged, for example 3V, the power entering the capacitor (the product of voltage and current) is very small at the beginning and is proportional to the voltage as it approaches the end. Become bigger. If the maximum power that can be used, such as a household outlet, is determined to be 1.5 kW, for example, charging with a constant current will give you more power while the voltage is low, but depending on the capacity of the capacitor, the power will increase when the voltage increases. It ’s not enough. Therefore, when charging is performed at a low power type, the charging current is large at a low voltage, and the current is small as it approaches full charge. Will flow too much.

  Further, in order to reduce the power loss associated with the bypass operation of the parallel monitor, if it is attempted to reduce the current monitor upper limit value of the parallel monitor, the charging current must be reduced accordingly and the charging time becomes longer. If the variation in the charging voltage is constantly reduced, there arises a problem that the initialization operation of the electric double layer capacitor must be frequently performed. Therefore, adjustment of operation switching between constant current charging and constant power charging, a circuit configuration and control are complicated, and the entire apparatus is increased in cost.

  The present invention solves the above-mentioned problems, and it is possible to perform efficient charging without causing excessive current to flow and insufficient power with a simple circuit configuration, and further, reducing power loss and charging. It improves efficiency and enables high-speed charging.

  Therefore, the present invention provides a capacitor storage power supply charging device that charges a capacitor storage power supply that stores power in an electric double layer capacitor, and a switch circuit that turns on / off a charging current supplied from the charge power supply to the capacitor storage power supply. A current detection circuit for detecting the charging current; a voltage detection circuit for detecting a voltage of the capacitor storage power supply; and an error amplification for controlling the charging current based on a current value and a current reference value detected by the current detection circuit A constant current control circuit that outputs a signal; and a power that outputs an error amplification signal that controls the charging current based on a current value detected by the current detection circuit, a voltage value detected by the voltage detection circuit, and a power reference value A control circuit; and an error amplifier for controlling the charging current based on a voltage value detected by the voltage detection circuit and a voltage reference value A constant voltage control circuit that outputs a signal, a logical sum circuit that switches and outputs one of the error amplification signals output from the constant current control circuit, the power control circuit, and the constant voltage control circuit, and the logical sum And a control circuit that generates a pulse width modulation signal based on an error amplification signal output from the circuit to turn on / off the switch circuit and control the charging current.

  The OR circuit is a diode OR circuit, the constant current control circuit allows the current reference value to be switched between a plurality of reference values, and the constant current control circuit includes another capacitor. The charging device for the storage power supply is used as a master device, and the current value detected by the current detection circuit of the master device is input as the reference value. The capacitor storage power supply is connected to each of the plurality of electric double layer capacitors connected in series. A parallel monitor that bypasses a charging current with a full charge voltage during charging, wherein the constant current control circuit detects a bypass operation of the parallel monitor and switches the current reference value. The current value and the voltage value are multiplied by a power reference value and an error amplification signal is output, and the power control circuit determines whether the power reference value is And outputs an error amplification signal is compared with the value obtained by subtracting the voltage value the current value, the constant voltage control circuit is characterized in that the switchable said voltage reference value at a plurality of reference values.

  According to the present invention, any one of the error amplification signals output from the constant current control circuit, the power control circuit, and the constant voltage control circuit through the OR circuit is switched and output to generate a pulse width modulation signal, and the switch Since the charging current is controlled by turning on / off the circuit, the charging can be efficiently performed by efficiently following the capacitor voltage having a large fluctuation in the pulse width with a simple configuration. Switching to voltage charging can be performed smoothly. In addition, the switching point between constant current charging, constant power charging, and constant voltage charging can be changed flexibly by enabling switching with a plurality of reference values, and further, the reference value of the slave device as a master device and a slave device. Since the detection signal of the charging current of the master device can be introduced into the charging device, the charging current can be increased, so that more rapid charging is possible.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a main circuit of a charging device for a capacitor storage power source according to the present invention, and FIG. 2 is a diagram showing an embodiment of a signal processing circuit of the charging device for a capacitor storage power source according to the present invention. . In the figure, 1 is a constant current signal generating circuit, 2 is a constant power signal generating circuit, 3 is a constant voltage signal generating circuit, 5 is a charging power source, 6 is a charging device, 7 is a capacitor storage power source, 61 is a signal processing circuit, 62 Is a PWM signal generation circuit, 63 is an amplifier, 64 is an inverting amplifier, 71 is an electric double layer capacitor, AS11, AS12, AS21 and AS22 are analog switches, C1 and C2 are capacitors, D11, D21 and D31 are diodes, and L is a coil , R is a current detection resistor, SW1 is a main switch circuit, SW2 is a synchronous rectifier circuit, Vrefi1 and Vrefi2 are current reference value setting circuits, Vrefp is a power reference value setting circuit, Vrefv1 and Vrefv2 are charging voltage reference value setting circuits, I Is a charging current, Vc is a charging voltage, and Vi is an input voltage.

  The capacitor storage power supply charging device according to this embodiment shown in FIG. 1 charges and stores a capacitor storage power supply 7 in which a plurality of electric double layer capacitors 71 are connected in series from the charging power supply 5 through the charging device 6. Each of the plurality of electric double layer capacitors constituting the capacitor storage power source 7 may be connected in parallel with a so-called parallel monitor that bypasses the charging current when the charging voltage increases to a predetermined reference voltage, for example. The charging device 6 connects the choke coil L for charge control and the synchronous rectifier circuit SW2 in series between the charging power source 5 and the capacitor storage power source 7, and the main switch circuit SW1 is connected in parallel to these series connection points. In addition to connecting the capacitors C1 and C2 for smoothing in parallel on the input and output sides, a step-up type switching converter is constructed, and a current detection resistor R is inserted in series to detect the charging current I. Connected.

  The signal processing circuit 61 controls the charging current by turning on / off the main switch circuit SW1 and turning off / on the synchronous rectifier circuit SW2 in the opposite phase by the on / off control signal. For this purpose, the charging current I, the charging voltage Vc, and the input voltage Vi are detected, compared with various reference values set as control targets, and based on their error amplification signals, constant current charging, constant power charging, constant voltage An on / off control signal modulated in pulse width according to each charging mode such as charging is generated and output. Specifically, for example, as shown in FIG. 2, it has a constant current signal generation circuit 1, a constant power signal generation circuit 2, a constant voltage signal generation circuit 3, and a PWM signal generation circuit 62. In the circuits (1 to 3) for generating each error amplification signal, various reference values set by the current reference value setting circuit Vrefi1 or Vrefi2, the constant power reference value setting circuit Vrefp, or the constant voltage reference value setting circuit Vrefv1 or Vrefv2. And the detection signal of the charging current I and the charging voltage Vc, and the control target signal obtained by calculating these are output, and an error amplification signal is output, and one of the error amplification signals is an OR logic circuit comprising diodes D11, D21, and D31 Is switched and selected and input to the PWM signal generation circuit 62, and a pulse width modulated on / off control signal (PWM signal) is generated from the PWM signal generation circuit 62 to the main switch circuit SW 1 through the amplifier 63 and the inverting amplifier 64. To turn on / off signals to the synchronous rectifier circuit SW2.

  In the embodiment shown in FIG. 2, each of the constant current signal generation circuits 1 can be selected and changed by switching connection to one of a plurality of current reference value setting circuits Vrefi1 or Vrefi2 by analog switches AS11 and AS12. 3, the analog switches AS31 and AS32 are connected to one of a plurality of constant voltage reference value setting circuits Vrefv1 or Vrefv2 so that the reference value can be selected and changed.

  Here, the current reference values Vrefi1 and Vrefi2 are switched by connecting the parallel monitor to the electric double layer capacitor 71 in parallel, and reducing the current monitor upper limit value of the parallel monitor relative to the current limit value of the electric double layer capacitor 71. In the case where the parallel monitor is bypassed, the condition (full charge signal: F signal) is performed. In this case, the analog switch AS11 is turned on by the selection signal refi1 and the analog switch AS12 is turned off by the selection signal refi2 until the parallel monitor performs a bypass operation, and a large charge corresponding to the current withstand current upper limit value of the electric double layer capacitor 71 is obtained. When the parallel monitor is quickly charged and the bypass operation of the parallel monitor is detected, the analog switch AS11 is turned off by the selection signal refi1 and the analog switch AS12 is turned on by the selection signal refi2, thereby reducing the parallel monitor's current withstand current upper limit value or less. Switch to charge current. By switching the current reference value in this way, the capacity of the parallel monitor can be reduced, and the loss of power due to the bypass operation after full charge can be reduced.

  Further, when a plurality of charging devices are operated in parallel, when the charging current of each charging device is made the same, the detected value of the charging current from the master charging device is set as the current reference value of the slave charging device. In this case, in one master charging device, the analog switch AS11 is turned on by the selection signal refi1, the analog switch AS12 is turned off by the selection signal refi2, and in the other slave charging devices, the analog switch AS11 is turned off by the selection signal refi1, The analog switch AS12 is turned on by the selection signal refi2, and the detected value of the charging current taken out from the master charging device is connected as the current reference value setting circuit Vrefi2. In this way, a plurality of charging devices are used and are not operated independently, but one of them is set as a master charging device and the other as a slave charging device, and the charging current output from the master charging device is used as it is as a current reference value. As a result, the synchronous control can be performed, the charging current can be increased as a whole, and more rapid charging is possible.

  The constant voltage reference value setting circuits Vrefv1 and Vrefv2 are switched by an external signal (refv1, refv2) such as an output signal of a rated voltage switch. The electric double layer capacitor 71 has an empirical rule that, when the rated voltage is 5V and the voltage is lowered by 0.2V, the life is 1.5 times longer. Therefore, for example, in the normal use mode, the analog switch AS31 is turned on by the selection signal refv1 to select the constant voltage reference value Vrefv1, and in the longevity use mode, the analog switch AS32 is turned on by the selection signal refv2 to set the constant voltage reference value Vrefv2. select.

  FIG. 3 is a diagram illustrating an embodiment of a constant voltage signal generation circuit and a constant power signal generation circuit, FIG. 4 is a diagram illustrating transition of a control mode of constant current-constant power-constant voltage, and FIG. It is a figure which shows embodiment of the switching signal generation circuit by operation | movement. In the figure, 11 and 21 are operational amplifiers, 72 is a parallel monitor, 73 is an OR gate, AS12 is an analog switch, C21, C22, Cr1, and Cr2 are capacitors, R11, R21, Rr1, and Rr2 are resistors, and Rrv11, Rrv12, and Rrv2 are Indicates a variable resistor.

  In FIG. 3, the constant current signal generating circuit 1 inputs a detection signal of the charging current I to the inverting input terminal − of the operational amplifier 11, inputs the current reference value Vrefi to the non-inverting input terminal +, and And an output terminal, a series circuit of a capacitor C11 and a resistor R11 is connected to form an error amplifier circuit. Similarly, the constant power signal generation circuit 2 inputs the detection signal (current × voltage calculation signal) of the charging power P to the inverting input terminal − of the operational amplifier 21 and the power reference value Vrefp to the non-inverting input terminal +. An error amplifier circuit is configured by connecting a series circuit of a capacitor C21 and a resistor R21 between the inverting input terminal − and the output terminal. The constant voltage signal generation circuit 3 is omitted because it can adopt the same configuration as the constant current signal generation circuit 1.

  Each of the reference value setting circuits described above can be constituted by various known circuits. However, with a current reference value, the bias power source + V stabilized as shown in FIG. 2 is divided between the fixed resistor Rr1 and the variable resistor Rrv1. The voltage is divided by the circuit, the current reference value Vrefi is taken out from the voltage dividing connection point, and adjusted to a predetermined voltage by the variable resistor Rrv1. The capacitor Cr1 is connected in parallel to the variable resistor Rrv1 as a noise countermeasure. Further, the variable resistor Rrv2 is connected in parallel with the variable resistor Rrv1 via the analog switch AS12, and the current reference value is switched by turning on / off the analog switch AS12 by the selection signal refi2. Here, when the analog switch AS12 is turned off, the analog switch AS11 of the embodiment shown in FIG. 2 is turned on, the analog switch AS12 is turned off, and when the analog switch AS12 is turned on, the analog switch AS11 of the embodiment shown in FIG. It is possible to correspond to a circuit in which the analog switch AS12 is turned on. Of course, each of Vrefi1 and Vrefi2 of the embodiment shown in FIG. 2 may be configured by a voltage dividing circuit of the fixed resistor Rr1 and variable resistor Rrv1 of the embodiment shown in FIG.

  In FIG. 3, a constant current signal generation circuit 1 takes out a voltage drop between terminals of a current detection resistor R inserted and connected in series with a charging device as a detection signal of a charging current I, and inputs this as a control object, Compared with the current reference value Vrefi set by the current reference value setting circuit as a reference value, the error amplification circuit outputs the error amplification signal. Therefore, the error amplification signal output from the constant current signal generation circuit 1 has a larger output value if the input charging current I to be controlled is smaller than the current reference value Vrefi, and the charging current I is larger than the current reference value Vrefi. The output value becomes smaller. When this error amplification signal is input, the PWM signal generation circuit 62 increases the charging current I when the charging current I is smaller than the current reference value Vrefi, and conversely when the charging current I is larger than the current reference value Vrefi. Since the pulse width (duty ratio) is controlled according to the magnitude of the input error amplification signal so that I is small, as a result, the charging current is controlled so that the charging current I becomes constant based on the current reference value Vrefi. The constant current charging control mode CC is executed.

  Similarly, the constant power signal generation circuit 2 inputs the charging power P as a control target, compares it with the power reference value Vrefp set by the power reference value setting circuit as a reference value of the comparator, and calculates the error amplification signal. It consists of an error amplification circuit that outputs. Therefore, the error amplification signal output from the constant power signal generation circuit 2 has a larger output value if the input charging power P to be controlled is smaller than the power reference value Vrefp, and the charging power P is larger than the power reference value Vrefp. The output value becomes smaller. When this error amplification signal is input, the PWM signal generation circuit 62 increases the charging current I when the charging power P is smaller than the power reference value Vrefp, and conversely when the charging power P is larger than the power reference value Vrefp. Since the pulse width (duty ratio) is controlled in accordance with the magnitude of the input error amplification signal so that I becomes small, as a result, the charging current I is set so that the charging power P becomes constant based on the power reference value Vrefp. The control mode CP of constant power charging to be controlled is executed.

  The diodes D11, D21, and D31 are respectively input to the PWM signal generation circuit 62 from the constant current signal generation circuit 1, the constant power signal generation circuit 2, and the constant voltage signal generation circuit 3 that output error amplification signals with opposite polarities. Since they are connected, the smallest error amplification signal among the error amplification signals output from the constant current signal generation circuit 1, constant power signal generation circuit 2, and constant voltage signal generation circuit 3 is input to the PWM signal generation circuit 62. OR logic circuit is configured.

  The charging mode switching control performed by the OR logic circuit will be further described. First, in the initial stage of starting charging, the constant current charging control mode CC is executed while the diode D11 is on and the diodes D21 and D31 are off. Is done. That is, when the charging voltage Vc of the capacitor storage power supply 7 is small in the initial stage and the PWM signal generating circuit 62 is executing the constant current charging control mode CC based on the error amplification signal output from the constant current signal generating circuit 1. Since the constant power signal generation circuit 2 and the constant voltage signal generation circuit 3 are both smaller than the reference value to be compared, even if a large value error amplification signal is output, the charging current I is Since the charging voltage Vc is not increased and the error amplification signal is stuck to the upper limit value, the diodes D21 and D31 are biased in the reverse direction and turned off.

  Next, when the constant voltage charging is continued, the charging voltage Vc of the capacitor storage power source 7 increases, the charging power P increases, and the charging power P becomes larger than the power reference value Vrefp in the constant power signal generating circuit 2. The error amplification signal output from the power signal generation circuit 2 is smaller than the error amplification signal output from the constant current signal generation circuit 1. From this point, the diode D11 connected to the output of the constant current signal generation circuit 1 is turned off, the diode D21 connected to the output of the constant power signal generation circuit 2 is turned on, and the charging power of the capacitor storage power source 7 is switched on. A constant power charging control mode CP is executed in which the charging current I is controlled so that P does not exceed the power reference value Vrefp.

  Furthermore, if the constant power charging is continued, the charging voltage Vc of the capacitor storage power supply 7 increases and becomes larger than the voltage reference value Vrefv in the constant voltage signal generating circuit 3, an error output from the constant voltage signal generating circuit 3. The amplified signal becomes smaller than the error amplified signal output from the constant power signal generating circuit 2, and the diode D21 connected to the output of the current diminishing signal generating circuit 2 is turned off and connected to the output of the constant voltage signal generating circuit 3. The switched diode D31 is turned on, and the constant voltage charging control mode CV is executed in which the charging current is controlled so that the charging voltage Vc is smaller than the voltage reference value Vrefv.

  As described above, according to the charging device 6 of the present embodiment, the charging current I is detected and compared with the predetermined current reference value Vrefi set by the current reference value setting circuit as shown in FIG. When the capacitor storage power supply 7 is charged to a predetermined voltage (constant current charging: CC), the charging power P is calculated and compared with a predetermined power reference value Vrefp set by the power reference value setting circuit. When the electric power P is kept constant (constant current charging: CP) and the capacitor storage power supply 7 is charged to the fully charged voltage, the charging voltage Vc is compared with a predetermined voltage reference value Vrefv set by the voltage reference value setting circuit, The main switch circuit SW1 and the synchronous rectifier circuit SW2 are controlled by PWM (Pulse Width Modulation: pulse width modulation) by switching between the control modes so that the charging voltage Vc becomes constant (constant voltage charging: CV). FIG. 4 (a) shows the state of transition in this constant current-constant power-constant voltage charging control mode.

  Further, in the constant current signal generating circuit 1, charging is performed with a large charging current close to the current withstand upper limit value of the electric double layer capacitor 71 as the current reference value Vrefi1, and the charging current is monitored in parallel by the detection signal F of the bypass operation of the parallel monitor. FIG. 4B shows an example of a type that switches to a current reference value Vrefi2 that is equal to or less than the current withstand current upper limit value. In this case, as shown in FIG. 5, the detection signal F of the bypass operation of the parallel monitor 72 of each electric double layer capacitor 71 is taken out through the OR gate 73, and when any one of the parallel monitors is bypassed, the current reference value Vrefi2 is switched. Can be. Further, in the constant voltage signal generating circuit 3, an example of a type in which the rated voltage (Vfu) of the capacitor storage power supply is changed by switching the voltage reference value Vrefv in consideration of the life of the electric double layer capacitor is shown in FIG. (C).

  FIG. 6 is a diagram showing an embodiment of a synchronous control system in which a master charging device and a slave charging device are operated in parallel. The analog switches AS1a to AS3a and AS1b to AS3b are selectively turned on / off by a master / slave setting signal. Then, the embodiment is configured to be set in the master charging device or the slave charging device and operated in parallel. In the embodiment shown in FIG. 6, when the analog switches AS1a and AS3a of the charging device A are turned on by the master setting signal, the charging device A becomes the master charging device and the constant current signal generation circuit 1a sets the voltage reference value Vrefia. The charging current Ia is input and controlled, and the detection signal of the charging current Ia is used as a reference value for the slave charging device, so that it is output to a common reference value line (broken line) through the analog switch AS3a. On the other hand, when the analog switch AS2b of the charging device B is turned on by the slave setting signal, the charging device B becomes a slave charging device, and the constant current signal generating circuit 1b is connected to the common reference value line (broken line) through the analog switch AS2b. The charging current Ib of the master charging device is input as a reference value to control the charging current Ib.

  FIG. 7 is a diagram showing another embodiment of the constant power signal generating circuit, wherein 22 is a multiplication circuit, 23 is an operational amplifier, R22 and R23 are resistors, and Voff-set is an offset value setting circuit. As shown in FIG. 7A, the constant power signal generation circuit 2 multiplies the charging current I by the charging voltage Vc of the capacitor storage power source by the multiplication circuit 22 to obtain the charging power P, which is used as the power reference value Vrefip. A configuration that outputs an error amplification signal is common. However, in a large-capacity capacitor storage power supply, it can be several tens to several hundreds A, several hundreds to several kV, and the voltage varies in a wide range from near 0 V to a full charge voltage. There are problems such as high cost and adjustment. As a result, the cost of the apparatus increases as the cost of the parts increases. Therefore, as an embodiment of the constant power signal generation circuit, as shown in FIG. 7B, a simple configuration in which the charging current is gradually decreased in inverse proportion to the increase of the charging voltage may be employed.

  A simplified constant power signal generation circuit 2 shown in FIG. 7B is a current diminishing signal generation circuit, and is a current reference value that decreases the charging current I in inverse proportion to the increase in the charging voltage Vc of the capacitor storage power source 7. Vref (vi) is generated, the current reference value Vref (vi) is compared with the charging current I to be controlled, and an error amplification signal is output. The current reference value Vref (vi) is obtained by inputting a detection signal of the charging voltage Vc of the capacitor storage power supply 7 to the inverting input terminal − of the operational amplifier 23 via the resistor R22 and supplying the offset value Voff− to the non-inverting input terminal +. An output shown in FIG. 7C is generated from a subtracting circuit configured by inputting set and connecting a resistor R23 between the inverting input terminal − and the output terminal. According to this subtraction circuit, a current reference value Vref (vi) of Voff-set + (Voff-set−Vc) R23 / R22 (where R23 = R22 is 2Voff-set−Vc) is taken out and Voff− When set is set to a value that matches Vst in FIG. 2B, when the charging voltage Vc of the capacitor storage power supply 7 increases to Voff-set, the reference values of the constant current signal generation circuit 1 and the current diminishing signal generation circuit 2 are set. Since the values are equal to each other, the setting is switched from here to the current decreasing control mode. Further, in this subtraction circuit, by changing the ratio of R23 and R22, the gradient of the current reference value Vref (vi) is changed as shown in VI and (VI) ′ of FIG. Further, as shown in FIG. 7 (d), switching from constant current charging to constant power charging (current decreasing charging), constant power charging (current decreasing charging) by the bypass operation signals F and F 'of the parallel monitor. May be switched to constant current charging with a small current.

  When charging, even if the charging voltage of each electric double layer capacitor is charged unevenly, if there is a parallel monitor, it bypasses sequentially from the parallel monitor of the electric double layer capacitor charged to a predetermined reference voltage By operating, the charging current is bypassed and the charging voltage is limited to a predetermined reference voltage. Therefore, finally, when the full charge voltage of the electric double layer capacitor is set as a predetermined reference voltage, each electric double layer capacitor can be evenly charged to the full charge voltage.

  When a parallel monitor of an electric double layer capacitor charged to a predetermined reference voltage bypasses the charging current, the parallel monitor uses a power that is the product of the predetermined reference voltage and the charging current, that is, the voltage and current at the time of bypass. Is consumed. As a result, the longer the operation time of the parallel monitor and the greater the number, the greater the power loss and heat loss of the capacitor storage power supply 7. As a result, the parallel monitor has to be increased in capacity and structurally large in order to increase heat dissipation efficiency, and waste of power and waste of space are large, and it is difficult to realize downsizing of the capacitor storage power source 7. Therefore, as in the charging device 6 according to the present embodiment, the initial stage in which the parallel monitor of any of the plurality of electric double layer capacitors performs a bypass operation is determined based on the charging voltage of the capacitor storage power supply 7, and the increase in the charging voltage is reversed. The charging current is decreased in proportion, or the charging current is limited to the upper limit of the withstand current of the parallel monitor according to the bypass operation of the parallel monitor as shown in FIGS. 4 (b) and 7 (d). By performing an appropriate control, the capacity and size can be reduced.

  FIG. 8 is a diagram showing another embodiment of the main circuit of the charging device for capacitor storage power source according to the present invention, wherein 61 ′ is a signal processing circuit, C1 ′ and C2 ′ are capacitors, L ′ is a coil, R ′ Denotes a current detection resistor, and SW1 'and SW2' denote switch circuits.

  In the charging device shown in FIG. 8, a switching circuit SW1 ′ for charging control and a choke coil L ′ are connected in series between a charging power source 5 and a capacitor storage power source 7, and a synchronous rectifier circuit is connected in parallel to these series connection points. SW2 'is connected and capacitors C1' and C2 'are connected in parallel on the input side and output side, and the switch circuit SW1' is turned on / off by the PWM signal, and the synchronous rectifier circuit SW2 'is turned on in the opposite phase. A step-down switching converter is provided that supplies the charging current to the capacitor storage power source 7 by turning it off / on. In the embodiment shown in FIGS. 1 and 8, the synchronous rectification circuits SW2 and SW2 ′ may be replaced with diodes (flywheel diodes).

  FIG. 9 is a diagram showing an embodiment of a circuit for limiting the operation of the synchronous rectifier circuit in the output circuit for the on / off control signal, and FIG. 10 is an implementation of the circuit for preventing simultaneous on in the output circuit for the on / off control signal. It is a figure which shows a form. In the figure, 63, 65 and 66 are amplifiers, 64 is an inverting amplifier, Cp1 to Cp4 are capacitors, Dp1 to Dp3 are diodes, Qp1 and Qp2 are transistors, and Rp1 to Rp8 are resistors.

  In the on / off control of the main switch circuit SW1, the duty ratio is reduced when the charging current is narrowed down. In the embodiment shown in FIG. 9, a diode is connected in parallel with a polarity that releases energy stored in the choke coil L with respect to the synchronous rectifier circuit SW2, and when the duty ratio is small, regardless of whether the main switch circuit SW1 is on or off, By maintaining the synchronous rectifier circuit SW2 in an off state, the charging current is prevented from flowing back through the synchronous rectifier circuit at a light load. Here, a diode Dp1, a resistor Rp1, and a capacitor Cp1 are connected in series, and a resistor Rp2 is connected in parallel to the capacitor Cp1, thereby forming an on / off control signal rectifying and smoothing circuit. Then, this rectified and smoothed output is applied between the base and emitter of the transistor Qp1, and when the pulse duty ratio, that is, the ON pulse width is larger than a predetermined value, the transistor Qp1 is turned ON. Is reduced so that the transistor Qp1 is turned off, and the base bias of the transistor Qp2 is controlled by the collector output of the transistor Qp1 to short-circuit the output of the inverting amplifier 64 that turns on and off the synchronous rectifier circuit SW2. It has. According to the present embodiment, only when the current is small, the synchronous rectifier circuit SW2 is turned off to release the energy accumulated in the choke coil L through the diode, and the large current flows with the synchronous rectifier circuit SW2 turned on. Therefore, the loss in the diode can be reduced.

  Further, in order to prevent the main switch circuit SW1 and the synchronous rectifier circuit SW2 from being turned on at the same time, for example, as shown in FIG. A circuit may be provided. In FIG. 10A, the resistor Rp6 and the capacitor Cp3 realize a delay Δt when the drive pulse of the main switch circuit SW1 rises (on), and similarly, the resistor Rp8 and the capacitor Cp4 rises of the drive pulse of the synchronous rectifier circuit SW2. This is a circuit that realizes a delay Δt at the time (ON time), and is connected in parallel with a diode Dp2 and a resistor Rp8 having a polarity opposite to the output direction of the drive pulse signal of the main switch circuit SW1 connected in parallel with the resistor Rp6. The diode Dp3 having a polarity opposite to the output direction of the drive pulse signal of the synchronous rectifier circuit SW2 is a circuit for preventing a delay Δt from occurring at the falling edge of each pulse. The parallel circuit of the resistor Rp7 and the capacitor Cp2 connected to the output of the inverting amplifier circuit is intended to remove noise. By connecting these circuits, a PWM signal is inputted and a pulse signal outputted to the main switch circuit SW1 through the amplifiers 63 and 65, and a pulse signal outputted to the synchronous rectification circuit SW2 through the inverting amplifiers 64 and 66 are shown in FIG. As shown in FIG. 10B, only the rising edge is delayed, and the main switch circuit SW1 and the synchronous rectifier circuit SW2 can be prevented from being turned on simultaneously. In FIG. 10B, at t7 and t8, since the pulse width is smaller than the predetermined value, the transistor Qp2 shown in FIG. 9 is turned on.

It is a figure which shows embodiment of the main circuit of the charging device for capacitor electrical storage power supplies which concerns on this invention. It is a figure which shows embodiment of the signal processing circuit of the charging device for capacitor electrical storage power supplies which concerns on this invention. It is a figure which shows embodiment of a constant voltage signal generation circuit and a constant power signal generation circuit. It is a figure explaining the transition of the control mode of constant current-constant power-constant voltage. It is a figure which shows embodiment of the switching signal generation circuit by the bypass operation of a parallel monitor. It is a figure which shows embodiment of the synchronous control system operated in parallel as a master charging device and a slave charging device. It is a figure which shows other embodiment of a constant power signal generation circuit. It is a figure which shows other embodiment of the main circuit of the charging device for capacitor electrical storage power supplies which concerns on this invention. It is a figure which shows embodiment of the circuit which restrict | limits operation | movement of the synchronous rectifier circuit in the output circuit of an on / off control signal. It is a figure which shows embodiment of the circuit which prevents simultaneous ON in the output circuit of an on / off control signal.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Constant current signal generation circuit, 2 ... Constant power signal generation circuit, 3 ... Constant voltage signal generation circuit, 5 ... Charge power supply, 6 ... Charging apparatus, 7 ... Capacitor electrical storage power supply, 61 ... Signal processing circuit, 62 ... PWM signal Generator circuit 63 ... Amplifier 64 ... Inverting amplifier 71Electric double layer capacitor AS11, AS12, AS21, AS22 ... Analog switch C1, C2 ... Capacitor D11, D21, D31 ... Diode, L ... Coil, R ... Current detection resistor, SW1 ... main switch circuit, SW2 ... synchronous rectifier circuit, Vrefi1, Vrefi2 ... current reference value setting circuit, Vrefp ... power reference value setting circuit, Vrefv1, Vrefv2 ... charging voltage reference value setting circuit, I ... charging current , Vc: charging voltage, Vi: input voltage

Claims (8)

In a charging device for a capacitor storage power source that charges a capacitor storage power source that stores power in an electric double layer capacitor,
A switch circuit for turning on / off a charging current supplied from the charging power source to the capacitor storage power source;
A current detection circuit for detecting the charging current;
A voltage detection circuit for detecting a voltage of the capacitor storage power supply;
A constant current control circuit that outputs an error amplification signal for controlling the charging current based on a current value detected by the current detection circuit and a current reference value;
A power control circuit that outputs an error amplification signal for controlling the charging current based on a current value detected by the current detection circuit, a voltage value detected by the voltage detection circuit, and a power reference value;
A constant voltage control circuit that outputs an error amplification signal for controlling the charging current based on a voltage value and a voltage reference value detected by the voltage detection circuit;
An OR circuit that switches and outputs any one of the error amplification signals output from the constant current control circuit, the power control circuit, and the constant voltage control circuit;
And a control circuit for generating a pulse width modulation signal based on an error amplification signal output from the OR circuit and turning the switch circuit on and off to control the charging current. Charging device. 2. The charging device for a capacitor storage power source according to claim 1, wherein the OR circuit is a diode OR circuit. 2. The charging device for a capacitor storage power source according to claim 1, wherein the constant current control circuit is capable of switching the current reference value between a plurality of reference values. The said constant current control circuit inputs the electric current value detected by the electric current detection circuit of the said master apparatus as said reference value by using the charging device for another capacitor electrical storage power supply as a master apparatus. The charging apparatus for capacitor electrical storage power supply of description. The capacitor storage power supply has a parallel monitor that bypasses a charging current at a full charge voltage when charging each of a plurality of electric double layer capacitors connected in series, and the constant current control circuit performs a bypass operation of the parallel monitor. 5. The charging device for a capacitor storage power source according to claim 3, wherein the current reference value is detected and switched. 2. The charging device for a capacitor storage power supply according to claim 1, wherein the power control circuit compares a value obtained by multiplying the current value and the voltage value with a power reference value and outputs an error amplification signal. 2. The charging device for a capacitor storage power supply according to claim 1, wherein the power control circuit compares the current value with a value obtained by subtracting a voltage value from the power reference value, and outputs an error amplification signal. 2. The charging device for a capacitor storage power source according to claim 1, wherein the constant voltage control circuit is capable of switching the voltage reference value with a plurality of reference values.

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