JP2007259615A - Charger or discharger for capacitor storage power supply - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress useless power loss due to leakage current during stoppage of charge or discharge. <P>SOLUTION: In the charger or discharger for a capacitor storage power supply comprising a main switch circuit SW1 turning on/off according to an on/off control signal and a choke coil L, and arranged to perform charge or discharge for the capacitor storage power supply 7 which stores power in an electric double layer capacitor, signal interruption circuits TS1-TS3 are inserted in series into a signal line connected with a circuit performing charge or discharge for the capacitor storage power supply 7 and detecting a current or a voltage at the time of charge or discharge, and the signal line is interrupted by the signal interruption circuit by judging stoppage state of charge or discharge. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention is directed to charging or discharging a capacitor storage power source that is configured to charge or discharge a capacitor storage power source that has a main switch circuit that is turned on / off according to an on / off control signal and a choke coil and that is stored in an electric double layer capacitor. The present invention relates to a discharge device.

  In a high-voltage and large-capacity storage power supply apparatus configured by connecting a plurality of electric double layer capacitors in series, the terminal voltage of the storage power supply varies in proportion to the square root of the storage amount of the capacitor. Therefore, in such a storage power supply charging or discharging device, PWM (Pulse Width Modulation) control is used to efficiently follow a terminal voltage having a large fluctuation, and a desired charging / discharging is performed by changing the pulse width. Control (for example, switching between constant current control CC, constant power control CP, and constant voltage control CV) is realized.

Also, in a switching power supply device that turns on and off the main switch circuit to store energy in the choke coil and release the energy stored through the rectifier diode, the ratio of loss due to the rectifier diode increases when a low-voltage DC output is obtained. Therefore, the loss is reduced by using a synchronous rectification circuit (switch circuit) that turns off / on in a phase opposite to that of the main switch circuit instead of the rectifier diode. Also in the charging / discharging device of the capacitor storage power source that performs PWM control, it is possible to improve the charging / discharging efficiency by using the synchronous rectification circuit.
(For example, refer nonpatent literature 1 and patent literature 1).
Okamura Ikuo, “Electric Double Layer Capacitor and Power Storage System”, Nikkan Kogyo Shimbun, September 30, 2005, 3rd edition, first edition, pages 135-137 JP-A-7-87668

  However, in the capacitor power storage power source, in contrast to being capable of rapid charging, a large current flows even during discharge, and rapidly accumulated energy is released, so in a charging or discharging device that performs charging or discharging, It is important to take measures against leakage current that wastes energy. That is, when a large current flows for charging a capacitor storage power supply or for a necessary discharge to a load, there is no problem with the original purpose itself, but a circuit in which a leakage current flows when charging or discharging stops Therefore, energy that cannot be ignored is released according to the impedance of the circuit, and there is a problem that even if the charge / discharge efficiency is increased, the overall utilization efficiency of the capacitor power storage power source is deteriorated.

  The present invention solves the above-described problem, and is intended to suppress useless power loss due to leakage current when charging or discharging is stopped.

  For this purpose, the present invention is for a capacitor storage power supply configured to charge or discharge a capacitor storage power supply that has a choke coil and a main switch circuit that is turned on / off according to an on / off control signal. In the charging or discharging device, a signal cut-off circuit is inserted in series and connected to a signal line that detects a current or voltage at the time of charging or discharging and is connected to a circuit that charges or discharges the capacitor storage power source, It is characterized in that the signal line is cut off by the signal cut-off circuit by determining the discharge stop state.

  The charging or discharging stop state is determined from a voltage of a circuit that performs the charging or discharging on the side opposite to the connection side of the capacitor storage power source with respect to the main switch circuit and the choke coil, A detection element for detecting a current during discharge is connected to a line opposite to the common line, and the signal cut-off circuit is inserted in series with the signal line of the signal line opposite to the common line. The charging or discharging stop state is determined from a charging or discharging stop signal, and the signal cutoff circuit is a semiconductor switch.

  According to the present invention, since the signal line for detecting the current or voltage at the time of charging or discharging is cut off by the signal cut-off circuit by judging the stop state of charging or discharging, useless leakage from the stored capacitor storage power supply through the signal line. The power loss due to the current can be eliminated, and the charge / discharge efficiency of the capacitor storage power supply can be increased. In addition, the determination of whether the charging or discharging is stopped can be realized with a simple circuit configuration by determining whether or not a voltage is applied to the disconnection state of the charging power source that performs charging or discharging or the off state of the main switch circuit. it can.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a charging device for a capacitor storage power source according to the present invention, and FIG. 2 is a diagram showing an embodiment of a signal processing circuit of the charging device for a capacitor storage power source according to the present invention. The discharging device will be described with reference to the charging device because the charging power source in the charging device has substantially the same configuration only by replacing the capacitor power storage power source and the capacitor power storage power source with the load. In the figure, 1 is a constant current signal generating circuit, 2 is a constant power signal generating circuit, 3 is a constant voltage signal generating circuit, 5 is a charging power supply, 6 is a charging device, 7 is a capacitor storage power supply, 60 is a leakage current cutoff circuit, 61 is a control circuit, 62 is a PWM signal generation circuit, 63 is an amplifier, 64 is an inverting amplifier, 71 is an electric double layer capacitor, AS11, AS12, AS21 and AS22 are analog switches, C1 and C2 are capacitors, D11, D21 and D31 Is a diode, L is a coil, R is a current detection resistor, SW1 is a main switch circuit, SW2 is a synchronous rectifier circuit, TS1 to TS3 are signal cutoff switches, Vrefi1 and Vrefi2 are current reference value setting circuits, and Vrefp is a power reference value setting. Circuits Vrefv1 and Vrefv2 are charging voltage reference value setting circuits, I is a charging current, Vc is a charging voltage, and Vi is an input voltage.

  The capacitor storage power supply charging device according to this embodiment shown in FIG. 1 charges and stores a capacitor storage power supply 7 in which a plurality of electric double layer capacitors 71 are connected in series from the charging power supply 5 through the charging device 6. The charging device 6 connects a choke coil L for charge control and a synchronous rectifier circuit SW2 in series between the charging power source 5 and the capacitor storage power source 7, and connects the main switch circuit SW1 in parallel to these series connection points. In addition, a capacitor C1 and C2 for smoothing are connected in parallel on the input side and the output side to constitute a boost type switching converter that boosts the voltage by the on / off control duty of the main switch circuit SW1, and the charging current I is detected. Therefore, the current detection resistor R is inserted and connected in series.

  The signal processing circuit 61 controls the charging current by turning on / off the main switch circuit SW1 and turning off / on the synchronous rectifier circuit SW2 in the opposite phase by the on / off control signal. Therefore, the charging current I and the charging voltage Vc are detected, compared with various reference values set as control targets, and based on their error amplification signals, constant current charging, constant power charging, constant voltage charging, etc. An on / off control signal modulated in pulse width according to the charging mode is generated and output. Specifically, for example, as shown in FIG. 2, it has a constant current signal generation circuit 1, a constant power signal generation circuit 2, a constant voltage signal generation circuit 3, and a PWM signal generation circuit 62. In the circuits (1 to 3) for generating each error amplification signal, various reference values set by the current reference value setting circuit Vrefi1 or Vrefi2, the constant power reference value setting circuit Vrefp, the constant voltage reference value setting circuit Vrefv1 or Vrefv2. Is compared with the detection signal of the charging current I and the charging voltage Vc, and the signal to be controlled (for example, the charging power P obtained by multiplying I and Vc), and an error amplification signal is output. The diodes D11, D21, and D31 constitute an OR logic circuit. One of the error amplification signals is switched and selected and input to the PWM signal generation circuit 62, and pulse width modulation is performed from the PWM signal generation circuit 62. An on / off control signal (PWM signal) is generated. This PWM signal is output as a signal to be turned on / off through the amplifier 63 to the main switch circuit SW1 and through the inverting amplifier 64 to the synchronous rectifier circuit SW2.

  In the capacitor storage power supply 7 which is charged to the full charge voltage and is in a stopped state, if there is a circuit through which a leakage current flows, the stored power is discharged gradually over time, resulting in heat and unnecessary loss. For example, even when a 30W class charging device is connected to a capacitor module with a full charge voltage of 60V, a leakage current of about 40mA is actually generated, and the charge / discharge efficiency is improved by constant current charging or synchronous rectification circuit. However, the electric power charged and stored can be wasted. In order to cut off such a leakage current, simply thinking, it seems to be sufficient to cut off the current from the capacitor at its original “A”. However, in reality, the capacitor has a higher output density than the secondary battery, that is, the charge / discharge speed is fast, so that the current that flows is large, and if a switch with a very large forward current is not used, the switch breaks. Arise. On the other hand, when the leakage current was analyzed in the charging device, it was found that the largest amount of current leaked through the signal line connected to the signal processing circuit 61. This is a signal line for detecting the charging current I used in the constant current signal generating circuit 1, the constant power signal generating circuit 2, and the constant voltage signal generating circuit 3 as shown in FIG. It is a signal line.

  The leakage current interruption circuit 60 detects the input voltage Vi to determine whether it is in a charging operation state or a charging stop state. When it is determined that the charging is in a stopping state, the leakage current interruption circuit 60 operates the signal interruption circuit. The signal line of the signal processing circuit 61 that detects the signal is cut off. That is, it is determined whether or not the charging power source for charging is disconnected, and whether or not the charging is stopped is determined by whether or not the input voltage Vi is applied or whether there is a predetermined voltage. At this time, the signal line of the signal processing circuit 61 is cut off. The signal line is connected from the signal processing circuit 61 to a circuit that charges the capacitor storage power source 7. For example, the signal line is connected to the output terminal side to detect the charging voltage Vc of the capacitor storage power source 7. These are signal lines that are connected to both ends to detect the charging current I, and signal cut-off switches TS1 to TS3 are inserted in series as signal cut-off circuits for cutting off the signals. The signal cutoff switches TS1 to TS3 are semiconductor elements such as FETs and NPN (PNP) transistors, for example.

  In FIG. 2, a constant current signal generating circuit 1 takes out a voltage drop between terminals of a current detection resistor R inserted and connected in series with a charging device as a detection signal of a charging current I, and inputs this as a control object, Compared with the current reference value Vrefi set by the current reference value setting circuit as a reference value, the error amplification circuit outputs the error amplification signal. Therefore, the error amplification signal output from the constant current signal generation circuit 1 has a larger output value if the input charging current I to be controlled is smaller than the current reference value Vrefi, and the charging current I is larger than the current reference value Vrefi. The output value becomes smaller. When this error amplification signal is input, the PWM signal generation circuit 62 increases the charging current I when the charging current I is smaller than the current reference value Vrefi, and conversely when the charging current I is larger than the current reference value Vrefi. Since the pulse width (duty ratio) is controlled according to the magnitude of the input error amplification signal so that I is small, as a result, the charging current is controlled so that the charging current I becomes constant based on the current reference value Vrefi. The constant current charging control mode CC is executed.

  Similarly, the constant power signal generation circuit 2 inputs the charging power P as a control target, compares it with the power reference value Vrefp set by the power reference value setting circuit as a reference value of the comparator, and calculates the error amplification signal. It consists of an error amplification circuit that outputs. Therefore, the error amplification signal output from the constant power signal generation circuit 2 has a larger output value if the input charging power P to be controlled is smaller than the power reference value Vrefp, and the charging power P is larger than the power reference value Vrefp. The output value becomes smaller. When this error amplification signal is input, the PWM signal generation circuit 62 increases the charging current I when the charging power P is smaller than the power reference value Vrefp, and conversely when the charging power P is larger than the power reference value Vrefp. Since the pulse width (duty ratio) is controlled in accordance with the magnitude of the input error amplification signal so that I becomes small, as a result, the charging current I is set so that the charging power P becomes constant based on the power reference value Vrefp. The control mode CP of constant power charging to be controlled is executed.

  The diodes D11, D21, and D31 are respectively input to the PWM signal generation circuit 62 from the constant current signal generation circuit 1, the constant power signal generation circuit 2, and the constant voltage signal generation circuit 3 that output error amplification signals with opposite polarities. Since they are connected, the smallest error amplification signal among the error amplification signals output from the constant current signal generation circuit 1, constant power signal generation circuit 2, and constant voltage signal generation circuit 3 is input to the PWM signal generation circuit 62. OR logic circuit is configured.

  The charging mode switching control performed by the OR logic circuit will be further described. First, in the initial stage of starting charging, the constant current charging control mode CC is executed while the diode D11 is on and the diodes D21 and D31 are off. Is done. That is, when the charging voltage Vc of the capacitor storage power supply 7 is small in the initial stage and the PWM signal generating circuit 62 is executing the constant current charging control mode CC based on the error amplification signal output from the constant current signal generating circuit 1. Since the constant power signal generation circuit 2 and the constant voltage signal generation circuit 3 are both smaller than the reference value to be compared, even if a large value error amplification signal is output, the charging current I is Since the charging voltage Vc is not increased and the error amplification signal is stuck to the upper limit value, the diodes D21 and D31 are biased in the reverse direction and turned off.

  Next, when the constant voltage charging is continued, the charging voltage Vc of the capacitor storage power source 7 increases, the charging power P increases, and the charging power P becomes larger than the power reference value Vrefp in the constant power signal generating circuit 2. The error amplification signal output from the power signal generation circuit 2 is smaller than the error amplification signal output from the constant current signal generation circuit 1. From this point, the diode D11 connected to the output of the constant current signal generation circuit 1 is turned off, the diode D21 connected to the output of the constant power signal generation circuit 2 is turned on, and the charging power of the capacitor storage power source 7 is switched on. A constant power charging control mode CP is executed in which the charging current I is controlled so that P does not exceed the power reference value Vrefp.

  Furthermore, when the constant power charging is continued, the charging voltage Vc of the capacitor storage power supply 7 increases and becomes larger than the voltage reference value Vrefvc in the constant voltage signal generating circuit 3, and an error output from the constant voltage signal generating circuit 3 The amplified signal becomes smaller than the error amplified signal output from the constant power signal generating circuit 2, and the diode D21 connected to the output of the current diminishing signal generating circuit 2 is turned off and connected to the output of the constant voltage signal generating circuit 3. The controlled diode C31 is turned on, and the constant voltage charging control mode CV is executed in which the charging current is controlled so as to make the charging voltage Vc smaller than the voltage reference value Vrefvc.

  Thus, according to the charging device 6 of the present embodiment, the charging current I is detected and compared with the predetermined current reference value Vrefi set by the current reference value setting circuit, and the charging current I is made constant (constant current charging). : CC), when the capacitor storage power source 7 is charged to a predetermined voltage, the charging power P is calculated and compared with a predetermined power reference value Vrefp set by the power reference value setting circuit, and the charging power P is made constant ( When the capacitor storage power supply 7 is charged to the full charge voltage, the charge voltage Vc is compared with a predetermined voltage reference value Vrefvc set by the voltage reference value setting circuit, and the charge voltage Vc is kept constant. As described above (constant voltage charging: CV), switching between the control modes is performed to control the main switch circuit SW1 and the synchronous rectifier circuit SW2 by PWM (Pulse Width Modulation).

  Further, in the embodiment shown in FIG. 2, each of the constant current signal generation circuits 1 can be selected and changed by switching and connecting to one of a plurality of current reference value setting circuits Vrefi1 or Vrefi2 by analog switches AS11 and AS12. The generation circuit 3 is switched and connected to one of a plurality of constant voltage reference value setting circuits Vrefv1 or Vrefv2 by analog switches AS31 and AS32 so that the reference value can be selected and changed.

  Here, the current reference values Vrefi1 and Vrefi2 are switched by connecting the parallel monitor to the electric double layer capacitor 71 in parallel, and reducing the current monitor upper limit value of the parallel monitor relative to the current limit value of the electric double layer capacitor 71. In the case where the parallel monitor is bypassed, the condition (full charge signal: F signal) is performed. In this case, the analog switch AS11 is turned on by the selection signal refi1 and the analog switch AS12 is turned off by the selection signal refi2 until the parallel monitor performs a bypass operation, and a large charge corresponding to the current withstand current upper limit value of the electric double layer capacitor 71 is obtained. When the parallel monitor is quickly charged and the bypass operation of the parallel monitor is detected, the analog switch AS11 is turned off by the selection signal refi1 and the analog switch AS12 is turned on by the selection signal refi2, thereby reducing the parallel monitor's current withstand current upper limit value or less. Switch to charge current. By switching the current reference value in this way, the capacity of the parallel monitor can be reduced, and the loss of power due to the bypass operation after full charge can be reduced.

  Further, when a plurality of charging devices are operated in parallel, when the charging current of each charging device is made the same, the detected value of the charging current from the master charging device is set as the current reference value of the slave charging device. In this case, in one master charging device, the analog switch AS11 is turned on by the selection signal refi1, the analog switch AS12 is turned off by the selection signal refi2, and in the other slave charging devices, the analog switch AS11 is turned off by the selection signal refi1, The analog switch AS12 is turned on by the selection signal refi2, and the detected value of the charging current taken out from the master charging device is connected as the current reference value setting circuit Vrefi2. In this way, a plurality of charging devices are used and are not operated independently, but one of them is set as a master charging device and the other as a slave charging device, and the charging current output from the master charging device is used as it is as a current reference value. As a result, the synchronous control can be performed, the charging current can be increased as a whole, and more rapid charging is possible.

  The constant voltage reference value setting circuits Vrefv1 and Vrefv2 are switched by an external signal (refv1, refv2) such as an output signal of a rated voltage switch. The electric double layer capacitor 71 has an empirical rule that, when the rated voltage is 5V and the voltage is lowered by 0.2V, the life is 1.5 times longer. Therefore, for example, in the normal use mode, the analog switch AS31 is turned on by the selection signal refv1 to select the constant voltage reference value Vrefv1, and in the longevity use mode, the analog switch AS32 is turned on by the selection signal refv2 to set the constant voltage reference value Vrefv2. select.

  FIG. 3 is a diagram showing an embodiment of a capacitor storage power source discharge device according to the present invention, in which 60 ′ is a leakage current cutoff circuit, 61 ′ is a signal processing circuit, C1 ′ and C2 ′ are capacitors, and L ′ is a coil. , R ′ are current detection resistors, SW1 ′ and SW2 ′ are switch circuits, and TS1 ′ to TS3 ′ are signal cutoff switches.

  In the discharge device shown in FIG. 3, a switch circuit SW1 ′ for discharge control and a choke coil L ′ are connected in series between a capacitor storage power source 7 and a load 9, and a synchronous rectifier circuit SW2 is connected in parallel to these series connection points. ′, And capacitors C1 ′ and C2 ′ are connected in parallel to the input side and the output side, and the switch circuit SW1 ′ is turned on / off by the PWM signal, and the synchronous rectifier circuit SW2 ′ is turned off in the opposite phase to that. A step-down switching converter that turns on and supplies a discharge current (load current) to the load is provided, and a current detection resistor R ′ is inserted and connected in series to detect the discharge current Id.

  The leakage current cut-off circuit 60 'detects the load voltage Vl to determine whether it is in a discharge operation state or a discharge stop state. The signal of the signal processing circuit 61 'that detects the voltage and load voltage is cut off. That is, it is determined whether the main switch circuit that performs discharge is in an off state or a discharge stop state based on whether the load voltage Vl is output or whether there is a predetermined voltage, and when the load voltage Vl is not output and the discharge is stopped, The signal line of the signal processing circuit 61 'is cut off. The signal line is connected to a circuit that discharges the capacitor storage power source 7 from the signal processing circuit 61 ′. For example, the signal line is connected to the input terminal side and connected to the output terminal side to detect the charging voltage Vc of the capacitor storage power source 7. A signal line for detecting the load voltage Vl and a signal line for detecting the discharge current Id connected to both ends of the current detection resistor R ′, and the signal cut-off switches TS1 ′ to TS3 ′ are connected to the signal lines. It is inserted and connected in series as a signal cut-off circuit to cut off.

  1 and 3, the charging device can be a discharging device and the discharging device can be a charging device, but it goes without saying that the signal processing circuit is different from charging or discharging. That is, in the case of the charging device, the charging current is controlled (CC, CP, CV mode charging control) according to the predetermined charging specifications as shown in the embodiment of FIG. The discharge current is controlled according to the power supply specifications. In the embodiments of FIGS. 1 and 8, the synchronous rectifier circuits SW2 and SW2 ′ may be replaced with diodes (flywheel diodes). Further, even if a detection element (current detection resistor R) for detecting a current during charging or discharging is connected to a common line as in the embodiment shown in FIG. 1, charging or discharging is performed as in the embodiment shown in FIG. A detection element (current detection resistor R ′) for detecting the current at the time may be connected to a line opposite to the common line. In this way, the leakage current cutoff circuit is not considered for the common line, and the circuit design can be simplified.

  In the embodiment shown in FIG. 1, the charging or discharging is stopped in the state in which the switch circuit SW1 is off, and in the embodiment shown in FIG. 3, the switch circuit SW1 ′ is in the off state. Therefore, the determination can be made from the voltage of the circuit that charges or discharges the main switch circuits SW1 and SW1 ′ and the choke coils L and L ′ on the side opposite to the connection side of the capacitor storage power source 7. That is, if this voltage is zero, the switch circuit SW1 ′ is in an off state, and it is possible to determine whether the charging or discharging is stopped regardless of the voltage of the capacitor storage power source.

  In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. For example, in the above embodiment, the charging or discharging stop state is determined from the voltage of the circuit that performs charging or discharging on the side opposite to the connection side of the capacitor storage power source for the main switch circuit and the choke coil. Alternatively, the determination may be made based on a stop switch for charging or discharging or a stop signal for controlling the stop. Also, depending on whether the charge or discharge current is detected and below a certain value, if the charge or discharge current is below a certain value, the charging or discharging stop state is determined and the signal is cut off by the leakage current interruption circuit You may comprise as follows. Further, the signal cut-off switches TS1 to TS3 made of semiconductor switch elements are inserted and connected in series as signal cut-off circuits for cutting off the signal to the signal line, but the signal line is connected by a contact such as a relay operating at a voltage higher than the set value. You may comprise so that connection / blocking may be performed.

It is a figure which shows embodiment of the main circuit of the charging device for capacitor electrical storage power supplies which concerns on this invention. It is a figure which shows embodiment of the signal processing circuit of the charging device for capacitor electrical storage power supplies which concerns on this invention. It is a figure which shows other embodiment of the main circuit of the charging device for capacitor electrical storage power supplies which concerns on this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Constant current signal generation circuit, 2 ... Constant power signal generation circuit, 3 ... Constant voltage signal generation circuit, 5 ... Charge power supply, 6 ... Charging apparatus, 7 ... Capacitor storage power supply, 60 ... Leakage current interruption circuit, 61 ... Control Circuit, 62 ... PWM signal generating circuit, 63 ... Amplifier, 64 ... Inverting amplifier, 71 ... Electric double layer capacitor, AS11, AS12, AS21, AS22 ... Analog switch, C1, C2 ... Capacitor, D11, D21, D31 ... Diode, L ... Coil, R ... Current detection resistor, SW1 ... Main switch circuit, SW2 ... Synchronous rectifier circuit, TS1-TS3 ... Signal cutoff switch, Vrefi1, Vrefi2 ... Current reference value setting circuit, Vrefp ... Power reference value setting circuit, Vrefv1 , Vrefv2 ... charging voltage reference value setting circuit, I ... charging current, Vc ... charging voltage, Vi ... input voltage

Claims (5)

In a capacitor storage power supply charging or discharging device configured to charge or discharge a capacitor storage power supply that has a choke coil and a main switch circuit that is turned on / off according to an on / off control signal,
Connected to a circuit that charges or discharges the capacitor storage power source and connects a signal cut-off circuit in series to a signal line that detects current or voltage at the time of charging or discharging, and determines whether charging or discharging is stopped Then, the charging / discharging device for a capacitor storage power source is configured to block the signal line by the signal blocking circuit. The charge or discharge stop state is determined from a voltage of a circuit that performs the charge or discharge on the side opposite to the connection side of the capacitor storage power source with respect to the main switch circuit and the choke coil. The charging or discharging device for capacitor power storage according to any one of the above. A detection element for detecting a current during charging or discharging is connected to a line opposite to the common line, and the signal cutoff circuit is connected in series to a signal line of the signal line opposite to the common line. The charging / discharging device for a capacitor storage power source according to claim 2, wherein the charging / discharging device is inserted into the capacitor and connected. The charging or discharging device for a capacitor storage power source according to claim 1, wherein the stop state of the charging or discharging is determined from a charging or discharging stop signal. 2. The charging / discharging device for a capacitor storage power source according to claim 1, wherein the signal cutoff circuit is a semiconductor switch.

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