JP2007251104A - Method of manufacturing film transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a film transistor including a plasma CVD process which can form a high-quality silicon layer receiving less damage by plasma. <P>SOLUTION: Since at least one of a source electrode 4 or a drain electrode 5 and a dope silicon layer 6 are electrically connected with a conductive substrate 2, and the conductive substrate 2 is grounded when forming a silicon layer 7 by a plasma CVD method, it is difficult to accumulate electrons on the conductive substrate 2. Therefore, a high-quality silicon layer 7 which is less damaged by plasma due to a collision of positive ions can be formed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a thin film transistor having a forward staggered structure.

As a method of manufacturing a thin film transistor having a forward stagger type structure, a source electrode and a drain electrode are formed on a substrate, and an N-type or P-type doped silicon layer is formed on the electrodes to make ohmic contact. And a step of depositing and patterning a silicon layer serving as an active layer thereon, a step of depositing a gate insulating layer, and a step of depositing a gate electrode are known (Patent Document 1). And 2).

JP-A-5-95117 (page 3, FIG. 1) Japanese Patent Laid-Open No. 11-26772 (page 3, FIG. 1)

As a substrate used in these manufacturing methods, an insulating substrate is used. For this reason,
When silicon layer is deposited by plasma CVD (Chemical Vapor Deposition) method,
Electrons that easily follow the electric field accumulate on the substrate, and plasma damage occurs due to the collision of positive ions with the silicon layer on the substrate. Therefore, the quality of the silicon layer is deteriorated due to plasma damage.
An object of the present invention is to provide a method of manufacturing a thin film transistor including a plasma CVD process capable of forming a high-quality silicon layer with little plasma damage.

The thin film transistor manufacturing method of the present invention is a method of manufacturing a thin film transistor including a conductive substrate, wherein a base insulating layer forming step of forming a base insulating layer on the conductive substrate, and a contact hole in the base insulating layer Forming a contact hole, forming a contact hole to electrically connect at least one of a source electrode and a drain electrode of the thin film transistor to the conductive substrate through the contact hole, and a doped silicon layer. A doped silicon layer forming step for forming on the source electrode, the drain electrode, and the base insulating layer, and plasma for forming a silicon layer on the doped silicon layer by plasma CVD while grounding the conductive substrate Etch CVD process, the doped silicon layer and the silicon layer Characterized in that it comprises a device separation step of isolation and grayed.

According to the present invention, when the silicon layer is formed by the plasma CVD method, at least one of the source electrode or the drain electrode, the doped silicon layer and the conductive substrate are electrically joined, and the conductive substrate is grounded. Therefore, it is difficult for electrons to accumulate on the conductive substrate. Therefore, a high-quality silicon layer with little plasma damage due to positive ion collision is formed.

In this invention, it is preferable to include the doped silicon layer etching process of removing the said doped silicon layer of the channel region of the said thin-film transistor by an etching after the said doped silicon layer formation process.
In the present invention, since only the doped silicon layer in the channel region is etched, the portions other than the narrow channel region are electrically connected to the conductive substrate through either the source electrode or the drain electrode, and thus more efficient. Thus, a silicon layer with little plasma damage due to the collision of positive ions is formed.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings.
FIG. 1 is a schematic cross-sectional view of a thin film transistor 1 according to this embodiment.
The thin film transistor 1 has a forward staggered structure.
The thin film transistor 1 includes a conductive substrate 2, a base insulating layer 3, a source electrode 4, and a drain electrode 5.
A doped silicon layer 61 in the source region, a doped silicon layer 62 in the drain region, a silicon layer 71, a gate insulating layer 8, and a gate electrode 9. Further, in FIG.
0 is also described.

A base insulating layer 3 is formed on the conductive substrate 2. A contact hole 11 is formed in the base insulating layer 3.
In the contact hole 11, a bonding electrode 51 is formed extending from the drain electrode 5, and these are electrically connected to the conductive substrate 2. In the present embodiment, the drain electrode 5 is electrically connected to the conductive substrate 2, but the source electrode 4 may be connected.
That is, whether the electrode side on which the bonding electrode 51 is formed functions as the source electrode 4 or the drain electrode 5 is determined as follows, so that either the source electrode 4 or the drain electrode 5 is determined depending on the operating state. A part of the contact hole 11 is formed.
If the thin film transistor 1 is operated while the conductive substrate 2 is grounded, the thin film transistor 1 functions as the drain electrode 5, and if the conductive substrate 2 is operated with the positive potential, it functions as the source electrode 4.

The source electrode 4 and the drain electrode 5 are formed so as to sandwich the channel region 15, and in order to make ohmic contact, a part of these electrodes includes a doped silicon layer 61 in the source region and a doped silicon layer 62 in the drain region. Is formed. And silicon layer 7
1 is formed over the doped silicon layer 61 in the source region and the doped silicon layer 62 in the drain region so as to straddle the channel region 15 of the thin film transistor 1.

The gate insulating layer 8 includes a source electrode 4, a drain electrode 5, and a doped silicon layer 6 in the source region.
1 and the doped silicon layer 62 and the silicon layer 71 in the drain region. A gate electrode 9 is formed on the gate insulating layer 8 on the channel region 15.

The capacity holding unit 10 includes a lower electrode 12, a gate insulating layer 8, and an upper electrode 13 formed on the gate insulating layer 8.
The lower electrode 12 is formed extending from the bonding electrode 51 formed in the contact hole 11. A gate insulating layer 8 is formed on the lower electrode 12, and an upper electrode 13 is formed thereon.
Is formed.

FIG. 2 is a flowchart showing a method for manufacturing the thin film transistor 1 according to this embodiment.
The manufacturing method of the thin film transistor 1 includes a base insulating layer forming step (S1), a contact hole forming step (S2), a contact step (S3), a doped silicon layer forming step (S4), a doped silicon layer etching step (S5), and plasma CVD. Step (S6) and element isolation step (S7)
).

FIG. 3 is a schematic cross-sectional view in each step of the method for manufacturing the thin film transistor 1.
FIG. 3A shows a base insulating layer forming step (S1).
In FIG. 3A, the base insulating layer 3 is formed on the conductive substrate 2.
As the material of the conductive substrate 2, stainless steel or the like can be used.
The base insulating layer 3 can be formed by a CVD method, a sputtering method, or the like. As a material for the base insulating layer 3, an insulating silicon material such as silicon oxide, silicon nitride, or silicon nitride oxide, or a ceramic material such as aluminum oxide can be used. Further, an insulating film obtained by annealing the conductive substrate 2 in an oxidizing atmosphere or performing anodizing treatment is used as the base insulating layer 3.
Can be used as In particular, when the conductive substrate 2 is stainless steel, a passive film of chromium oxide formed on the surface thereof can be used as the base insulating layer 3.

FIG. 3B shows a contact hole forming step (S2).
In FIG. 3B, a contact hole 11 is formed in the base insulating layer 3.
A part of the base insulating layer 3 is removed by etching or the like until the conductive substrate 2 is exposed, and a contact hole 11 is opened.

FIG. 3C shows the contact step (S3).
3C, at least one of the source electrode 4 and the drain electrode 5 of the thin film transistor 1 is extended to form a bonding electrode 51 in the contact hole 11 and electrically connected to the conductive substrate 2 through the contact hole 11. Join. In the present embodiment, the drain electrode 5 and the lower electrode 12 of the capacity holding unit 10 are formed integrally with the bonding electrode 51 at the same time, and the bonding electrode 5
1 is formed so as to be electrically bonded to the conductive substrate 2 through the contact hole 11.
The drain electrode 5, the lower electrode 12 of the capacity holding unit 10, the bonding electrode 51 and the source electrode 4
Deposits a metal material such as indium tin oxide, molybdenum, or copper by sputtering or the like. These deposited metal materials are patterned to obtain the respective electrodes.

When stainless steel is used for the conductive substrate 2, the following processing may be performed when the bonding electrode 51 is formed. This is because a passive film is formed in the atmosphere on the surface of the conductive substrate 2 where the contact hole 11 is opened, which may cause contact failure.
Specifically, immediately before forming the metal material, for example, by sputtering, the surface of the conductive substrate 2 is exposed to plasma in a vacuum and the passive film is removed to deal with the problem. Can do.

FIG. 3D shows a doped silicon layer forming step (S4).
In FIG. 3D, a doped silicon layer 6 is formed on the conductive substrate 2.
A doped silicon layer 6 containing a large amount of phosphorus or boron, which will later become a source / drain region of the thin film transistor 1, is formed.
The doped silicon layer 6 is generally deposited by mixing silane and phosphine or diborane and directly depositing by plasma CVD, but after depositing an intrinsic silicon layer, phosphorus or boron is ion-implanted by silicon implantation. The doped silicon layer 6 may be formed. Further, a liquid silicon material mixed with polysilane, cyclopentasilane, or the like may be deposited by applying a solution prepared by mixing yellow phosphorus, decaborane, or the like by spin coating and annealing.

FIG. 3E shows a doped silicon layer etching step (S5).
In FIG. 3E, the doped silicon layer 6 in the channel region 15 of the thin film transistor 1 is removed by etching.
As a result, the region other than the very narrow region of the channel region 15 is electrically connected to the conductive substrate 2 via either the source electrode 4 or the drain electrode 5.

FIG. 3F shows a plasma CVD process (S6).
In FIG. 3F, the silicon layer 7 is formed by the plasma CVD method while the conductive substrate 2 is grounded. In this embodiment, an amorphous silicon layer is formed.
Specifically, the silicon layer 7 is deposited to approximately 50 nm by flowing monosilane as a source gas at 100 sccm and performing a treatment at a deposition temperature of 430 ° C. for 60 seconds. At this time, the electrode of the plasma CVD apparatus is joined to the conductive substrate 2 and the electrode of the plasma CVD apparatus is grounded. As a result, the substrate surface other than the extremely narrow region of the channel region 15 is grounded via the conductive substrate 2 and either the source electrode 4 or the drain electrode 5.

FIG. 3G shows the element isolation step (S7).
In FIG. 3G, the doped silicon layer 6 and the silicon layer 7 are etched to separate the elements.
Regions other than the silicon layer 7 to be the source, drain region, and channel region 15 are etched, and element isolation and source / drain regions are formed.
Specifically, CF ₄ gas and O ₂ gas are mixed at a ratio of 1: 1 and introduced into the chamber while the inside of the chamber is maintained at 10 Pa, and the doped silicon layer 6 and the silicon layer are applied at a power of 750 W by remote plasma. Etching 7 is performed.
In this embodiment, dry etching is used. However, wet etching using nitric acid or hydrofluoric acid may be used.

FIG. 3H shows a process for forming the gate insulating layer 8.
In FIG. 3H, the gate insulating layer 8 is formed.
Tetraethoxysilane gas (TEOS) and O ₂ gas are introduced into the deposition chamber of the gate insulating layer 8 at a flow ratio of 1:50, and the pressure in the deposition chamber is adjusted to 175 Pa. When the gas pressure in the room becomes stable, RF discharge is started and film formation of the gate insulating layer 8 is started. The RF power is 1.3 kW.
Film formation was performed at a film formation speed of 100 (nm / min). Thereby, the gate insulating layer 8 was formed to a thickness of about 100 nm.

FIG. 3I shows a process of forming the gate electrode 9 and the storage capacitor upper electrode 13.
In FIG. 3I, a thin film to be the gate electrode 9 and the upper electrode 13 of the capacity holding unit 10 is deposited by a PVD method, a CVD method, or the like.
Usually, since the gate electrode 9 and the gate wiring are made of the same material and in the same process, it is desirable that this material has a low electric resistance. In this embodiment, a tantalum thin film having a thickness of 600 nm is formed by sputtering. The substrate temperature when forming the tantalum thin film is 180 ° C., and an argon gas containing 6.7% nitrogen gas is used as the sputtering gas. The tantalum thin film thus formed has an α structure in crystal structure and a specific resistance of about 40 μΩcm. The tantalum thin film after film formation is patterned to form the gate electrode 9 and the upper electrode 13, thereby completing the thin film transistor 1 having a forward staggered structure.

According to such an embodiment, there are the following effects.
(1) When the silicon layer 7 is formed by plasma CVD, at least one of the source electrode 4 or the drain electrode 5 and the doped silicon layer 6 and the conductive substrate 2 are electrically joined, and the conductive substrate 2 is Since it is grounded, it is difficult to accumulate electrons on the conductive substrate 2.
Therefore, it is possible to form a high-quality silicon layer 7 with less plasma damage due to positive ion collisions.

(2) Since only the doped silicon layer 6 in the channel region 15 is etched, except for the narrow channel region 15, it is electrically connected to the conductive substrate 2 through either the source electrode 4 or the drain electrode 5. Thus, the silicon layer 7 with less plasma damage due to positive ion collision can be formed more efficiently.

It should be noted that the present invention is not limited to the above-described embodiments, and modifications, improvements, and the like within the scope that can achieve the object of the present invention are included in the present invention.
For example, although a high quality amorphous silicon layer is deposited as the silicon layer 7, a high quality polysilicon layer may be deposited directly. Further, the polysilicon layer may be formed by crystallizing this high quality amorphous silicon layer.
Crystallization depends on the quality of the amorphous silicon layer that is the precursor layer. Therefore,
Since a high-quality and dense amorphous silicon layer can be formed according to the present invention, a crystallized polysilicon layer can form a higher-quality film than a polysilicon layer formed by a conventional technique.

A thin film transistor 1 having a staggered structure prepared according to the present invention is, for example, an organic EL (El
ectroluminescence) can be used for the display pixel element 20. When used for the pixel element 20 for an organic EL display, for example, the configuration shown in FIGS.
FIG. 4 is a schematic cross-sectional view of the pixel element 20 for an organic EL display. After the process shown in FIG. 3, the interlayer insulating film 21 is formed, the contact hole 22 is opened at the position of the source electrode 4 of the interlayer insulating film 21, and the pixel electrode 23 is formed so as to be electrically connected to the source electrode 4. By doing so, the pixel element 20 for organic EL displays is obtained.
The display panel 100 shown in FIG. 5 can be constituted by the obtained organic EL display pixel element 20 and the organic EL and the counter electrode (not shown).

FIG. 5 is a schematic diagram showing the entire display panel 100.
According to the thin film transistor 1 having a staggered structure prepared according to the present invention, the conductive substrate 2
Since one of the source electrode 4 and the drain electrode 5 is electrically connected to the conductive substrate 2, the conductive substrate 2 can be used as a supply source of the power supply 30.
Normally, power is directly supplied from a single wiring 31, but in such a case, a voltage drop occurs at both ends and the center of the pixel, and the voltage supplied to the pixel element 20 for organic EL display is not uniform. Sex was occurring. On the other hand, as shown in FIG. 5, if the power supply 30 is supplied from several places on the back surface of the conductive substrate 2, the problem can be overcome more reliably.

FIG. 6 shows the most basic configuration when the power supply 30 is connected to the conductive substrate 2. The current control transistor DR (corresponding to the thin film transistor 1), the data write transistor SW 1, the data erase transistor SW 2, It comprises a holding capacitor Cs (corresponding to the capacitor holding unit 10) and an organic EL 25.
A characteristic point of this configuration is that a portion Vsub for supplying power to the organic EL 25 through the current control transistor DR is connected to the conductive substrate 2. SW1 by SEL
Data is written from the DATA line to the DR gate during the period when is selected.
25 emits light. During the period when SW2 is selected by ERS, the DR gate potential is V
Since it is maintained at sub and the source-gate potential of DR becomes 0 V, DR is turned off (lights off). In the configuration of FIG. 6, the source electrode of DR, which is a P-type transistor, is connected to Vsub. Such a configuration is best because the source potential of the transistor is always stabilized at the substrate potential.
FIG. 7 shows the best configuration in the case where the type of the DR transistor is changed to the N type with respect to FIG. In this configuration, the power source 30 is connected to the counter electrode of the organic EL 25.

FIG. 8 shows an electronic device using the display panel 100.
FIG. 8A shows a perspective view of the portable computer 80.
The portable computer 80 includes an operation unit 82 and a display unit 83, and the display unit 83 is provided with a display panel 100.
FIG. 8B shows a perspective view of the mobile phone 90.
The portable telephone 90 includes an operation button 91 and a display panel 100.

The best method for carrying out the present invention has been disclosed in the above description, but the present invention is not limited to this. That is, although the present invention has been mainly described with reference to specific embodiments, the materials, shapes, and quantities used for the above-described embodiments can be used without departing from the scope of the technical idea and object of the present invention. Various other modifications can be made by those skilled in the art.
Therefore, the description limited to the materials disclosed above is exemplary for easy understanding of the present invention, and does not limit the present invention.
Descriptions excluding some or all of the limitations are included in the present invention.

1 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention. The flowchart which shows the manufacturing method of a thin-film transistor. FIG. 6 is a schematic cross-sectional view illustrating a method for manufacturing a thin film transistor. The schematic sectional drawing of the pixel element for organic EL displays using the thin-film transistor which concerns on this invention. The schematic diagram which showed the whole display panel using the pixel element for organic EL displays. The circuit block diagram at the time of using an electroconductive board | substrate as a power supply. The best circuit block diagram at the time of replacing the type of DR transistor with N type. (A) is a perspective view of the portable computer using the thin-film transistor according to the present invention, and (b) is a perspective view of the portable phone.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Thin-film transistor, 2 ... Conductive substrate, 3 ... Base insulating layer, 4 ... Source electrode, 5 ... Drain electrode, 6 ... Dope silicon layer, 7 ... Silicon layer, 11 ... Contact hole, 15 ... Channel area | region.

Claims (2)

A method of manufacturing a thin film transistor provided with a conductive substrate,
A base insulating layer forming step of forming a base insulating layer on the conductive substrate;
A contact hole forming step of forming a contact hole in the base insulating layer;
A contact step of forming at least one of a source electrode and a drain electrode of the thin film transistor so as to be electrically bonded to the conductive substrate through the contact hole;
A doped silicon layer forming step of forming a doped silicon layer on the source electrode, the drain electrode, and the base insulating layer;
A plasma CVD step of forming a silicon layer on the doped silicon layer by a plasma CVD method while grounding the conductive substrate;
A method of manufacturing a thin film transistor, comprising: an element isolation step of isolating elements by etching the doped silicon layer and the silicon layer. In the manufacturing method of the thin-film transistor of Claim 1,
After the doped silicon layer forming step,
A method of manufacturing a thin film transistor, comprising: a doped silicon layer etching step of removing the doped silicon layer in a channel region of the thin film transistor by etching.

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