JP2007242925A - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device or the like capable of manufacturing the silicon carbide semiconductor device, in which a high concentration well region and a low concentration well region are formed so as to be located in a line in the view of section while a source region is formed in the high concentration well region at a low cost. <P>SOLUTION: A drift layer 2 is formed on a silicon carbide semiconductor substrate 1. The high concentration well region 3b is formed in the surface of the drift layer 2. Further, the low concentration well region 3a is formed in the surface of the drift layer 2, and neighbored to the high concentration well region 3b in the view of section while being lower in an impurity concentration than that in the high concentration well region 3b and a channel. Further, a source region 5 is formed in the upper surface of the high concentration well region 3b. Further, a JTE (junction termination extension) or a guard ring (high breakdown voltage retainable region 4) is formed on the outer periphery of an element. Furthermore, the low concentration well region 3a and the high breakdown voltage retainable region 4 are provided with the same impurity distribution. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device, and in particular, a silicon carbide semiconductor device and silicon carbide in which two well regions having different concentrations are formed on the surface of the drift layer The present invention relates to a method for manufacturing a semiconductor device.

  As a next generation high breakdown voltage low loss switching element, a vertical high breakdown voltage silicon carbide field effect transistor is expected. For example, as shown in Patent Document 1, this element includes a high concentration well region, a source region formed in the high concentration well region, a low concentration in the vicinity of the substrate surface of the drift layer existing on the silicon carbide substrate. A concentration well region and a JFET region existing under a gate electrode sandwiched between a pair of low concentration well regions are provided.

  Further, as a feature of Patent Document 1, a structure is disclosed in which a high-concentration well region and a low-concentration well region are formed side by side in the substrate lateral direction, and a channel region exists in the low-concentration well region.

JP 2004-146465 A

  However, since the silicon carbide semiconductor device of Patent Document 1 does not have a high-concentration well region in the channel region, there is a problem that leakage current increases when the device itself is downsized.

  Therefore, an object of the present invention is to provide a silicon carbide semiconductor device capable of suppressing leakage current even if the device itself is downsized, and a method for manufacturing the silicon carbide semiconductor device.

  In order to achieve the above object, a silicon carbide semiconductor device according to claim 1 according to the present invention is formed on a silicon carbide semiconductor substrate having a first conductivity type and on the silicon carbide semiconductor substrate. A drift layer having one conductivity type; a first well region having a second conductivity type formed in a channel region on a surface of the drift layer; and a channel region on a surface of the drift layer. A second well region having a second conductivity type, wherein the first well region is adjacent to the second well region, and the impurity concentration of the first well region is the second well region. This is lower than the impurity concentration in the well region.

  According to a fourth aspect of the present invention, there is provided a silicon carbide semiconductor device manufacturing method comprising: (A) forming a drift layer having the first conductivity type on a silicon carbide semiconductor substrate having the first conductivity type; B) forming a first well region having a predetermined impurity concentration of the second conductivity type on the surface of the drift layer; and (C) adjoining the first well region on the surface of the drift layer. Thus, the method includes a step of forming a second well region of a second conductivity type and having an impurity concentration higher than that of the first well region.

  Since the silicon carbide semiconductor device according to claim 1 of the present invention is configured as described above, it is possible to suppress the leakage current even if the device itself is downsized.

  Moreover, since the manufacturing method of the silicon carbide semiconductor device of Claim 4 was made into the above processes, manufacturing the silicon carbide semiconductor device which can suppress a leakage current even if the apparatus itself is reduced in size. Is possible.

  Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.

<Embodiment 1>
FIG. 1 is a cross-sectional view showing a configuration of a silicon carbide field effect transistor (hereinafter referred to as a silicon carbide semiconductor device) formed as a result of the manufacturing method according to the present embodiment.

  As shown in FIG. 1, drift layer 2 having a first conductivity type is formed on a first main surface of silicon carbide semiconductor substrate 1 having a first conductivity type. In addition, the surface of the drift layer 2 has a second conductivity type and a relatively high impurity concentration (that is, a higher impurity concentration than a low-concentration well region 3a (first well region) described later). A concentration well region 3b (second well region) is formed.

  A low concentration well region 3a is formed in the surface of the drift layer 2 adjacent to the high concentration well region 3b in a cross-sectional view. Here, the low concentration well region 3a has a lower impurity concentration than the high concentration well region 3b. A channel is formed in the low concentration well region 3a. The low concentration well region has the second conductivity type.

  A source region 5 having the first conductivity type is formed in the upper surface of the predetermined high concentration well region 3b. Here, a well contact region 6 is formed between the two source regions 5 in a cross-sectional view.

  Further, as shown in FIG. 1, a high concentration well region 3b is formed between the end portion of the source region 5 and the low concentration well region 3a in a cross-sectional view. As can be seen from this configuration, the channel is formed in the vicinity of the upper surface of the low concentration well region 3a and the high concentration well region 3b. As will be described later, when the source region 5 and the low concentration well region 3a are directly connected in a cross-sectional view, the channel is formed only near the upper surface of the low concentration well region 3a.

  In addition, a JTE (Junction Termination Extension) or a guard ring (hereinafter collectively referred to as a high breakdown voltage holdable region 4) is formed in the upper surface of the drift layer 2 as a region for holding a high breakdown voltage. Here, the high breakdown voltage holdable region 4 has the second conductivity type. Further, the high withstand voltage maintaining region 4 is formed so as to surround the element at the outer peripheral portion (peripheral portion) of the element (that is, the silicon carbide semiconductor device).

  Here, as a result of performing the manufacturing method described below, the low concentration well region 3a and the high breakdown voltage holdable region 4 have substantially the same impurity distribution. More specifically, the impurity distribution in the depth direction of the low-concentration well region 3a is substantially the same as the impurity distribution in the depth direction of the high breakdown voltage holdable region 4.

  A field stopper region 7 is also formed in the surface of the drift layer 2. A gate insulating film 8 is formed on the upper surface of the drift layer 2. Here, a part of the gate insulating film is opened, and the well contact region 6 and a part of the source region 5 are exposed from the opening.

  A gate electrode 9 having a desired shape is formed on the gate insulating film 8. Here, the gate electrode 9 is formed over a part of the source electrode, the high concentration well region 3b, the low concentration well region 3a, and the JFET region 2a in plan view.

  Here, the JFET region 2a is formed adjacent to the low concentration well region 3a in a sectional view. The JFET region 2a is formed below the gate electrode 9 with the gate insulating film 8 interposed therebetween. The conductivity type of the impurity distributed in the JFET region 2a is the first conductivity type. That is, the JFET region 2a has the first conductivity type.

  An interlayer insulating film 14 is formed on the gate insulating film 8 so as to cover the gate electrode 9. Here, the interlayer insulating film 14 has an opening, and the well contact region 6 and a part of the source region 5 are exposed from the opening. A source electrode 11 is formed at the bottom of the opening so as to be in contact with the upper surface of the well contact region 6 and a part of the upper surface of the source region 5. A drain electrode 10 is formed on the second main surface of silicon carbide semiconductor substrate 1.

  Next, a method for manufacturing the silicon carbide semiconductor device according to the present embodiment will be described.

  First, referring to FIG. 2, drift layer 2 made of silicon carbide having the first conductivity type is formed on silicon carbide semiconductor substrate 1 having the first conductivity type by an epitaxial crystal growth method or the like.

The thickness of the drift layer 2 may be 5 to 50 μm, and the impurity concentration of the first conductivity type may be 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ . By doing so, a vertical field effect transistor having a breakdown voltage of several hundreds V to 3 kV or more can be realized. More preferably, the thickness of the drift layer 2 is 10 to 20 μm, and the impurity concentration of the first conductivity type is 1 × 10 ^{15 to} 5 × 10 ¹⁶ cm ⁻³ .

Moreover, it is desirable for the first conductivity type silicon carbide semiconductor substrate 1 to exhibit n-type conductivity, and any plane orientation or polytype may be used. Furthermore, it is desirable that the impurity concentration of the first conductivity type (here, n-type) is doped by 1 × 10 ¹⁸ cm ⁻³ or more.

  On the other hand, silicon carbide semiconductor substrate 1 in which drift layer 2 is formed in advance may be used instead of the method shown in the first embodiment.

  Although different from FIG. 2, after the drift layer 2 is formed, a drift layer having the first conductivity type (hereinafter referred to as the second drift layer 2 c) is continuously formed by an epitaxial crystal growth method or the like. (See FIG. 3).

  The thickness of the second drift layer 2c may be 0.3 to 1.0 μm, and the impurity concentration of the first conductivity type may be higher than that of the drift layer 2 (in this case, the finished product). The impurity concentration of the JFET region 2a is higher than the impurity concentration of the drift layer 2). By setting in this way, the resistance in the JFET region 2a of the manufactured field effect transistor is reduced.

  In the second drift layer 2c, the first conductivity type impurity may be uniformly present, the vicinity of the interface with the drift layer 2 may be higher in concentration, It may be composed of two or more layers having different impurity concentrations of one conductivity type.

  When the second drift layer 2c is formed, photolithography and dry or wet etching may be performed on the second drift layer 2c existing on the outer periphery of the element. In other words, the second drift layer 2c in the part may be removed by this process. Then, in the surface of the drift layer 2 existing below the removed region, a high breakdown voltage holdable region 4 having a second conductivity type described later is formed.

  By doing so, the impurity concentration distribution of the high withstand voltage holdable region 4 having the second conductivity type can be determined (set) without being influenced by the impurity concentration of the second drift layer 2c having a relatively high concentration. .

  Now, let us return to the description of the manufacturing method using FIG.

  Next, a low-concentration well region 3a having the second conductivity type is formed in a predetermined region within the surface of the drift layer 2 by photolithography and ion implantation (which can be understood as first ion implantation) with reference to FIG. And the high withstand voltage holdable region 4 having the second conductivity type are formed in the same process.

The depth of the low-concentration well region 3a and the depth of the high withstand voltage holdable region 4 do not exceed the depth of the drift layer 2, and these depths may be, for example, 0.4 to 1.5 μm. The impurity concentration of the second conductivity type is set to exceed the impurity concentration of the first conductivity type in the drift layer 2, for example, 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ (preferably 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ , more preferably 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ⁻³ ).

  As described above, a channel is formed in the vicinity of the surface of the low concentration well region 3a having the second conductivity type. Further, since the low concentration well region 3a and the high breakdown voltage holdable region 4 are formed in the same process, the impurity distribution (impurity concentration distribution) of the low concentration well region 3a and the impurity distribution (high breakdown voltage holdable region 4) ( Impurity concentration distribution) is almost the same.

  Here, the low concentration well region 3a may be formed over a relatively wide area as shown in FIG. 2, or divided into a relatively narrow range as shown in FIG. The well region 3a may be formed.

  Next, as shown in FIG. 5, the high-concentration well region 3b having the second conductivity type, the well contact region by photolithography and ion implantation (including second ion implantation and third ion implantation). 6. Source region 5 and field stopper region 7 having the first conductivity type are formed in desired regions, respectively.

  A high concentration well region 3b is formed by performing ion implantation processing (second ion implantation processing) on a predetermined portion of the low concentration well region 3a. Here, as described above, the high-concentration well region 3b has the second conductivity type. The impurity concentration of the high concentration well region 3b is higher than the impurity concentration of the low concentration well region 3a.

  Further, the source region 5 having the first conductivity type is formed by performing ion implantation processing (third ion implantation processing) on a predetermined portion of the high concentration well region 3b.

  As can be seen from FIG. 5, when viewed in plan, the high concentration well region 3b is included in the formation region of the low concentration well region 3a.

  The depth of the high-concentration well region 3b does not exceed the depth of the drift layer 2, and the depth of the high-concentration well region 3b may be 0.4 to 2.0 μm, for example. It is desirable that the depth of the high concentration well region 3b exceeds the depth of the low concentration well region 3a.

Further, the impurity concentration of the second conductivity type exceeds the impurity concentration of the second conductivity type in the low-concentration well region 3a, and may be, for example, 2 × 10 ¹⁷ to 2 × 10 ¹⁹ cm ⁻³ . The impurity concentration of the second conductivity type may be distributed so that the impurity concentration decreases toward the substrate surface side.

  Here, when the low concentration well region 3a is formed in the mode shown in FIG. 4, the high concentration well region 3b may be formed as shown by the dotted line in FIG. Here, in FIG. 4, the low concentration well region 3a and the high concentration well region 3b may be formed to overlap each other by about 50 nm to 5 μm.

Further, the depth of the source region 5 should not exceed the depth of the high concentration well region 3b, and the depth may be, for example, 10 nm to 0.5 μm. The impurity concentration of the first conductivity type in the source region 5 exceeds the impurity concentration of the second conductivity type in the high-concentration well region 3b, for example, 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ^−3. It ’s fine.

  Furthermore, the source region 5 is preferably formed so as to be included in the high concentration well region 3b as shown in FIG. That is, as described above, it is desirable that the high concentration well region 3b be formed between the end portion of the source region 5 and the low concentration well region 3a in the cross-sectional view of FIG.

  As described above, when the high-concentration well region 3b is formed between the end portion of the source region 5 and the low-concentration well region 3a, the channel is formed from the end portion of the source region 5 to the high-concentration well region 3b. It is formed over each surface portion of the well region 3b and the low concentration well region 3a. In this case, for example, when fabricating an element having a fine channel length, the width of the low concentration well region 3a in the cross-sectional view of FIG. 5 is (more specifically, the width of the low concentration well region 3a near the surface is ), 0.1 to 2.0 μm (more preferably 0.3 to 1.0 μm). Further, the width of the high concentration well region 3b existing between the source region 5 and the low concentration well region 3a in the cross-sectional view of FIG. 5 (more specifically, the width of the high concentration well region 3b in the vicinity of the surface is ), 1.0 um or less (more preferably 0.5 um or less).

  After completion of the process described with reference to FIG. 5, the substrate shown in FIG. 5 is subsequently cleaned. And after performing the said washing | cleaning, it heat-processes with respect to the said board | substrate using a heat processing apparatus. Here, the heat treatment is performed at a temperature of about 1400 to 1800 ° C., for example, for about 30 seconds to 1 hour, for example. As a result of the heat treatment, the ions implanted in the above ion implantation steps are electrically activated.

  After the heat treatment, formation of a gate insulating film 8 made of silicon oxide, silicon oxynitride, metal oxide film, metal nitride film, etc., formation of a gate electrode 9 made of polycrystalline silicon or a refractory metal, oxidation based on ordinary methods After forming the interlayer insulating film 14 made of silicon or silicon nitride, forming the source electrode 11 and drain electrode 10 made of nickel, titanium, or aluminum silicide, etc., the protective film is formed as shown in FIG. A silicon carbide semiconductor device is completed.

  In the process up to the completion of the silicon carbide semiconductor device, a process of forming epitaxial channel region 12 may be added before gate insulating film 8 is formed. Thereby, a silicon carbide semiconductor device having the structure shown in FIG. 6 (that is, a structure in which epitaxial channel region 12 is separately provided in the structure of FIG. 1) is formed.

  Here, epitaxial channel region 12 is made of silicon carbide of the first or second conductivity type. The film thickness of the epitaxial channel region 12 is about 10 to 1000 nm. In a cross-sectional view, the epitaxial channel region 12 is formed over a part of the source region 5, over the high concentration well region 3b, over the low concentration well region 3a, and over the JFET region 2a.

  In addition, as described with reference to FIG. 3, when second drift layer 2c is formed, the silicon carbide semiconductor device has a configuration as shown in FIGS. Here, FIG. 7 shows a case where the configuration of the second drift layer 2c is added to the configuration of FIG. FIG. 8 shows a case where the configuration of the second drift layer 2c is added to the configuration of FIG.

  As can be seen from FIGS. 7 and 8, the JFET region 2a is formed adjacent to the low-concentration well region in a cross-sectional view, and exists below the gate electrode 9 through the gate insulating film 8 and the like. 7 and 8, the impurity concentration of the JFET region 2 a (which can be grasped as the second drift layer 2 c) is higher than the impurity concentration of the drift layer 2.

  As described above, in the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, low concentration well region 3a and high withstand voltage holdable region 4 are formed in the same process. Therefore, the low concentration well region 3a and the high withstand voltage holdable region 4 can be efficiently formed in one process. Therefore, the manufacturing cost can be reduced by the method according to the present embodiment, compared with the case where the low-concentration well region 3a and the high withstand voltage holdable region 4 are formed separately.

  Since the low concentration well region 3a and the high breakdown voltage holdable region 4 are formed in the same process, the impurity distribution (impurity concentration distribution) of the low concentration well region 3a and the impurity distribution (high breakdown voltage holdable region 4) ( Impurity concentration distribution) is substantially the same (more specifically, the distribution in the depth direction is substantially the same).

  In the silicon carbide semiconductor device according to the present embodiment, as shown in FIG. 1, a high concentration well region 3b is formed between the source region 5 and the low concentration well region 3a in a cross-sectional view. . Therefore, even if the silicon carbide semiconductor device is shortened, leakage current is suppressed, so that the short channel effect can be suppressed.

  In the above description, the impurity concentration distribution of the low concentration well region 3a and the impurity concentration distribution of the high breakdown voltage holdable region 4 are substantially the same (referred to as the first configuration), and the source region 5 is low in cross section. The silicon carbide semiconductor device including the configuration (referred to as the second configuration) in which the high concentration well region 3b is formed between the concentration well region 3a has been described. However, a silicon carbide semiconductor device having the following configuration may be used.

  That is, the first configuration and the configuration in which the end of the source region 5 is in direct contact with the low-concentration well region 3a in a cross-sectional view (that is, the high-concentration well region 3b between the region 5 and the region 3a in the cross-sectional view). A structure in which is not formed). In this case, only the effect of reducing the manufacturing cost is exhibited among the above-described effects. In the case of this configuration, the channel is formed over the range from the end of the source region 5 to the JFET region 2a through the surface of the low-concentration well region 3a. In this case, a silicon carbide semiconductor device with a low ON threshold can be provided.

  On the other hand, the structure in which the impurity concentration distribution in the low concentration well region 3a and the impurity concentration distribution in the high withstand voltage holdable region 4 are different (that is, the region 3a and the region 4 are formed separately and separately) And a silicon carbide semiconductor device including the second configuration. In this case, only the short channel effect can be suppressed among the effects described above.

  Furthermore, the following effects are also exhibited in common with the silicon carbide semiconductor devices having the above-described configurations.

  That is, since the low concentration well region 3a is formed in the region where the channel is formed, the channel mobility is increased as compared with the case where the channel is formed only in the high concentration well region 3b that maintains a high breakdown voltage. Therefore, the silicon carbide semiconductor device having each configuration described above can reduce the on-resistance.

  The low concentration well region 3a has a low concentration in the depth direction. Therefore, the number of implanted ions that pass through the channel portion is small. Thereby, it is possible to suppress implantation damage (occurrence of implantation defects) in the portion that becomes the channel. Therefore, increase in channel mobility, generation of defects in the gate insulating film 8 formed thereon and defects at the MOS interface can be suppressed.

  Further, since the impurity concentration of the low-concentration well region 3a adjacent to the JFET region 2a is low, the spread of the depletion layer to the JFET region 2a can be suppressed. Therefore, the JFET resistance can be reduced.

  7 and 8, the impurity concentration of the JFET region 2 a (which can be grasped as the second drift layer 2 c) is higher than the impurity concentration of the drift layer 2. Therefore, the resistance in the JFET region 2a can be further reduced.

<Embodiment 2>
The present embodiment can be applied to a method for manufacturing a silicon carbide semiconductor device related to each configuration described in the first embodiment (excluding a configuration in which low-concentration well region 3a and source region 5 are in contact with each other in a cross-sectional view). .

  The manufacturing method according to the present embodiment relates to a method capable of precisely controlling the channel length dimension formed in the high concentration well region 3b in the method according to the first embodiment. Hereinafter, the manufacturing method according to the present embodiment will be described.

  First, each process demonstrated using FIG. 2 is implemented. Here, as also mentioned in the silicon carbide semiconductor device of another configuration example of the first embodiment, the low concentration well region 3a and the high breakdown voltage holdable region 4 may be formed in separate steps.

  Next, a mask material (which can be grasped as a first film) 20 a patterned into a predetermined shape is formed on the drift layer 2. Here, the mask material 20a may be a photoresist, but may preferably be composed of any of polycrystalline silicon, amorphous silicon, silicon oxide, and silicon nitride.

  Next, an ion implantation process (which can be grasped as a second ion implantation process) is performed using the mask material 20a as a mask. Here, in the ion implantation process, aluminum (Al) ions, boron (B) ions, or the like is implanted. By the ion implantation process, as shown in FIG. 9, a high concentration well region 3 b is formed in a predetermined region in the surface of the drift layer 2.

  Next, a predetermined film (which can be grasped as a second film) 21 is formed on the drift layer 2 so as to cover the mask material 20a (FIG. 10). As the predetermined film 21, a film made of any of photoresist, polycrystalline silicon, amorphous silicon, silicon oxide, and silicon nitride can be employed. Moreover, as a method for forming the predetermined film 21, for example, a coating method, a chemical vapor deposition method, or the like can be employed.

  After the predetermined film 21 is formed, the predetermined film 21 is subjected to an anisotropic etching process such as reactive ion etching. Thus, as shown in FIG. 11, sidewalls 21a are formed on the sidewalls of the mask material 20a in a self-aligning manner. Here, the thickest portion of the sidewall 21a has a thickness corresponding to the thickness of the predetermined film (which can be grasped as the second film) 21 at the time of film formation.

  Next, referring to FIG. 12, a mask material 20d such as a photoresist is formed in a region where a channel is not required to be formed outside the element formation region. Thereafter, as shown in FIG. 12, an impurity ion implantation process (which can be understood as a third ion implantation process) is performed using the mask material 20a on which the sidewalls 21a are formed and the mask material 20d as a mask. Here, the implanted impurity ions have the first conductivity type. As the impurity ions, for example, n-type nitrogen (N) ions or phosphorus (P) ions can be employed.

By the ion implantation process, the source region 5 is formed as shown in FIG. The depth of the source region 5 does not exceed the depth of the high-concentration well region 3b, and the depth may be, for example, 10 nm to 0.5 μm. The impurity concentration of the first conductivity type in the source region 5 exceeds the impurity concentration of the second conductivity type in the high-concentration well region 3b, for example, 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ^−3. I just need it.

  Here, the width of the high concentration well region 3b (width L in FIG. 13) existing between the formed source electrode 5 and the low concentration well region 3a in a cross-sectional view is the thickest of the sidewalls 21a. Corresponds to the film thickness at the location. That is, the width of the high-concentration well region 3b (width L in FIG. 13) corresponds to the film thickness when the predetermined film (which can be grasped as the second film) 21 is formed.

  Note that the length of the width L in FIG. 13 may be 10 nm to 1 μm (more preferably 10 to 500 nm).

After forming the source region 5, next, a well contact region having the second conductivity type and a field stopper region having the first conductivity type are formed by photolithography and ion implantation. Here, the depth of the well contact region does not exceed the source region 5 and does not exceed the high concentration well region 3b. Further, the impurity concentration of the second conductivity type exceeds the impurity concentration of the first conductivity type in the source region 5, and may be, for example, 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ .

  The steps after the heat treatment for activating the implanted ions are the same as those in the first embodiment. Therefore, detailed description here is omitted.

  As described above, the silicon carbide semiconductor device manufacturing method according to the present embodiment uses the mask material (which can be grasped as the first film) 20a as a mask to perform ion implantation processing (second ion implantation treatment and grasping). The high-concentration well region 3b is formed. Thereafter, a side wall 21a is formed on the side surface of the mask material 20a in a self-aligned manner, and the mask material 20a on which the side wall 21a is formed is used as a mask. ) Is performed to form the source region 5.

  Therefore, the length of the channel formed in the vicinity of the surface of the high concentration well region 3b can be precisely controlled in a self-aligning manner. As described above, the length of the channel (width L in FIG. 13) substantially corresponds to the film thickness of the sidewall 21a (that is, the film thickness when a predetermined film is formed). Further, as can be seen from the above process, the sidewall 21 can be formed with a symmetrical thickness in any direction. Therefore, the length of the channel formed in the vicinity of the surface of the high-concentration well region 3b is the same in any direction.

  The impurity concentration of the second conductivity type is higher in the vicinity of the surface of the high concentration well region 3b than in the vicinity of the surface of the low concentration well region 3a. Therefore, the high concentration well region 3b is more susceptible to impurity scattering, and the channel mobility is reduced. Therefore, the channel length in the high-concentration well region 3b is preferably short from the viewpoint of channel mobility.

  However, when the channel length in the high-concentration well region 3b is reduced, the short channel effect appears and the leakage current when the device is off increases. Therefore, in order to suppress a depletion layer extending from the source region 5 to the channel region, it is desirable that the channel length formed in the high concentration well region 3b has an appropriate length (that is, as described above, as shown in FIG. The length of the width L may be 10 nm to 1 μm (more preferably 10 to 500 nm).

  By adopting the manufacturing method according to the present embodiment, the length of the channel formed near the surface of the high-concentration well region 3b can be precisely controlled.

  By adopting the manufacturing method according to the present embodiment, the source region 5 is not in direct contact with the low concentration well region 3a. Therefore, as described in the first embodiment, the short channel effect can be suppressed, which is advantageous for shortening the channel length of the element.

  As described above, the low-concentration well region 3a and the high withstand voltage holdable region 4 may be formed in the same process or in different processes as in the first embodiment. If the low-concentration well region 3a and the high withstand voltage holdable region 4 are formed in the same process, the manufacturing cost can be reduced as compared with the case where they are formed separately as described in the first embodiment. .

<Embodiment 3>
The present embodiment can be applied to a method for manufacturing a silicon carbide semiconductor device according to each configuration described in the first embodiment.

  The manufacturing method according to the present embodiment relates to a method capable of precisely controlling the channel length dimension formed in the low concentration well region 3a in the method according to the first embodiment. Hereinafter, the manufacturing method according to the present embodiment will be described.

  First, as described in the first embodiment, drift layer 2 is formed on the first main surface of silicon carbide semiconductor substrate 1. Here, silicon carbide semiconductor substrate 1 on which a drift layer is formed in advance may be prepared. As shown in the first embodiment, the second drift layer 2c having the first conductivity type may be formed (see FIG. 3).

  Next, as shown in FIG. 14, polycrystalline silicon or amorphous silicon (hereinafter referred to as a mask material 30 a) having a predetermined pattern shape is formed on the drift layer 2. Here, the mask material 30a having a predetermined pattern shape is formed by performing the photolithography process.

  Next, using the mask material 30a as a mask, an ion implantation process for implanting second conductivity type impurity ions (which can be grasped as the first ion implantation process) is performed. Here, in the ion implantation process, aluminum (Al) ions, boron (B) ions, or the like, which are p-type impurity ions, are implanted. By the ion implantation process, as shown in FIG. 14, the low concentration well region 3 a and the high breakdown voltage holdable region 4 are formed in a predetermined region in the surface of the drift layer 2 in the same process.

  Here, as shown in FIG. 14, the low concentration well region 3a and the high withstand voltage holdable region 4 may be formed in the same process, and the low concentration well region 3a and the high withstand voltage holdable region 4 May be formed separately. What is common to both cases is that the mask material 20a is for forming the low-concentration well region 3a.

  Now, after the formation of the low concentration well region 3a, the mask material 30a is subjected to thermal oxidation treatment. As shown in FIG. 15, the side surface and the upper surface of the mask material 30a are oxidized by the thermal oxidation treatment, and an oxide film 30b such as silicon oxide (including the inside of each surface) is formed on each surface in a self-aligned manner. Is done.

  Here, the said thermal oxidation process is performed in the temperature range (for example, 800-1000 degreeC) in which silicon carbide is hardly oxidized.

  Next, a photoresist 30c is formed above the region where the high breakdown voltage holdable region 4 is formed. In the ion implantation process (which can be grasped as the second ion implantation process) that is performed when the high-concentration well region 3b described later is formed, the formation of the photoresist 30c causes the high breakdown voltage holdable region 4 to Ion implantation is not performed.

  Next, a composite mask composed of the mask material 30a and the oxide film 30b (that is, a mask made of polycrystalline silicon or amorphous silicon on which the oxide film 30b is formed. The volume of the composite mask is self-aligned. And a mask material 30c such as a photoresist as a mask, and an ion implantation process for implanting second conductivity type impurity ions (second ion implantation). Can be understood as processing).

  Here, in the ion implantation process, aluminum (Al) ions, boron (B) ions, or the like, which are p-type impurity ions, are implanted. By the ion implantation process, as shown in FIG. 15, a high concentration well region 3b is formed in a predetermined region within the surface of the drift layer 2 (that is, partially overlapping with the low concentration well region 3a). The

  As a result of the formation of the high concentration well region 3b, the low concentration well region 3a exists on both sides of the high concentration well region 3b in a cross-sectional view. Here, the cross-sectional width of the low-concentration well region 3a (which can be grasped as the channel length formed in the low-concentration well region 3a) is 10 nm to 1.0 μm (preferably 10 to 500 nm). good.

  Next, sidewalls 21a are formed on the side surfaces of the composite mask composed of mask material 30a and oxide film 30b by the same method as in the second embodiment (FIG. 16). Then, referring to FIG. 16, a mask material 30d such as a photoresist is formed in a region where the channel does not need to be formed outside the element formation region.

  Thereafter, as in the second embodiment, impurity ion implantation processing (third ion implantation processing) is performed using the composite mask (mask material 30a + oxide film 30b) on which the sidewalls 21a are formed and the mask material 30d as masks. Can be grasped). Here, the implanted impurity ions have the first conductivity type. As the impurity ions, for example, n-type nitrogen (N) ions or phosphorus (P) ions can be employed.

  By the ion implantation process, the source region 5 is formed as in the second embodiment (FIG. 16). Here, in a cross-sectional view, the width of the high concentration well region 3b formed between the source region 5 and the low concentration well region 3a (that is, the channel length formed in the high concentration well region 3b) is 10 nm to 1 μm. (More preferably, it may be 10 to 500 nm).

  After the source region 5 is formed, a well contact region having the second conductivity type and a field stopper region having the first conductivity type are formed by photolithography and ion implantation, as in the second embodiment.

  The steps after the heat treatment for activating the implanted ions are the same as those in the first embodiment. Therefore, detailed description here is omitted.

  As described above, the method for manufacturing the silicon carbide semiconductor device according to the present embodiment uses the mask material 30a made of polycrystalline silicon or amorphous silicon as a mask, and performs ion implantation processing (first ion implantation processing and The low concentration well region 3a is formed. Thereafter, a thermal oxidation process is performed on the mask material 30a to form an oxide film 30b, and the mask material 30a on which the oxide film 30b is formed is used as a mask (that is, the composite mask is used as a mask). The high concentration well region 3b is formed by performing an ion implantation process (which can be grasped as a second ion implantation process).

  Therefore, the length of the channel formed near the surface of the low concentration well region 3a can be precisely controlled in a self-aligning manner. Here, the length of the channel is precisely formed in a desired dimension by time control from the oxidation rate of the mask material 30a.

  Here, as can be seen from the above steps, the oxide film 30b can be formed with a symmetrical volume in any direction with respect to the mask material 30a. Therefore, the length of the channel formed in the vicinity of the surface of the low-concentration well region 3a is the same in any direction.

  By adopting the manufacturing method according to the present embodiment, the end portion of the source region 5 is not in direct contact with the low concentration well region 3a. Therefore, as described in the first embodiment, the short channel effect can be suppressed, which is advantageous for shortening the channel length of the element.

  Here, like the second embodiment, the method of forming the high concentration well region 3b between the source region 5 and the low concentration well region 3a in the cross-sectional view is mentioned above. However, for example, when manufacturing a silicon carbide semiconductor device having a structure in which source region 5 and low-concentration well region 3a are in contact with each other, the step of forming sidewall 21a may be omitted. However, this is not advantageous for shortening the channel length of the device.

  Further, as described above, the low-concentration well region 3a and the high withstand voltage holdable region 4 may be formed in the same process or in different processes as in the first embodiment. If the low-concentration well region 3a and the high withstand voltage holdable region 4 are formed in the same process, the manufacturing cost can be reduced as compared with the case where they are formed separately as described in the first embodiment. .

<Embodiment 4>
The present embodiment can be applied to a method for manufacturing a silicon carbide semiconductor device according to each configuration described in the first embodiment.

  Similar to the manufacturing method according to the third embodiment, the manufacturing method according to the present embodiment relates to a method capable of precisely controlling the dimension of the channel length formed in the low-concentration well region 3a.

  In the manufacturing method according to the third embodiment, ion implantation processing for forming the low-concentration well region 3a is performed using the mask material 30a made of polycrystalline silicon or amorphous silicon as a mask. Thereafter, the mask material 30a was thermally oxidized to form an oxide film 30b on the mask material 30a, and a composite mask was formed in a self-aligning manner. Then, ion implantation processing for forming the high concentration well region 3b was performed using the composite mask.

  On the other hand, in the manufacturing method according to the fourth embodiment, ion implantation processing for forming the low concentration well region 3a is performed using a mask such as a photoresist. After that, the method described in Embodiment 2 is learned, and sidewalls are formed in a self-aligned manner on the side surfaces of a mask such as a photoresist. Then, ion implantation processing for forming the high-concentration well region 3b is performed using the mask on which the sidewall is formed.

  Hereinafter, the manufacturing method according to the present embodiment will be described.

  First, as described in the first embodiment, drift layer 2 is formed on the first main surface of silicon carbide semiconductor substrate 1. Here, silicon carbide semiconductor substrate 1 on which a drift layer is formed in advance may be prepared. As shown in the first embodiment, the second drift layer 2c having the first conductivity type may be formed (see FIG. 3).

  Next, as shown in FIG. 17, a mask material (which can be grasped as a first film) 40 a patterned into a predetermined shape is formed on the drift layer 2. Here, the mask material 40a may be a photoresist, but may preferably be composed of any of polycrystalline silicon, amorphous silicon, silicon oxide, and silicon nitride.

  Next, using the mask material 40a as a mask, an ion implantation process (which can be grasped as the first ion implantation process) for implanting impurity ions of the second conductivity type is performed. Here, in the ion implantation process, aluminum (Al) ions, boron (B) ions, or the like, which are p-type impurity ions, are implanted.

  By the ion implantation process, as shown in FIG. 17, a low concentration well region 3 a is formed in a predetermined region in the surface of the drift layer 2. In FIG. 17, the high breakdown voltage holdable region 4 is formed in the same process as the low concentration well region 3a. However, both regions 3a and 4 may be formed in separate steps.

  Next, a predetermined film (which can be grasped as a second film) is formed on the drift layer 2 so as to cover the mask material 40a (not shown). As the predetermined film, a film made of any of photoresist, polycrystalline silicon, amorphous silicon, silicon oxide, and silicon nitride can be employed. Further, as a method for forming the predetermined film, for example, a coating method, a chemical vapor deposition method, or the like can be employed.

  After the predetermined film is formed, an anisotropic etching process such as reactive ion etching is performed on the predetermined film. As a result, as shown in FIG. 18, sidewalls 41a are formed in a self-aligned manner on the sidewalls of the mask material 40a. Here, the thickest portion of the sidewall 41a has a thickness corresponding to the thickness of the predetermined film (which can be grasped as the second film).

  Next, referring to FIG. 18, a mask material 44 such as a photoresist is formed in a region outside the element formation region where a channel need not be formed. Thereafter, as shown in FIG. 18, ion implantation processing (second ions) for implanting impurity ions of the second conductivity type using the mask material 40 a formed with the sidewall 41 a and the mask material 44 as a mask. Implement the injection process.

  Here, in the ion implantation process, aluminum (Al) ions, boron (B) ions, or the like, which are p-type impurity ions, are implanted. By the ion implantation process, as shown in FIG. 18, a high concentration well region 3b is formed in a predetermined region in the surface of the drift layer 2 (that is, partially overlapping with the low concentration well region 3a). The

  In addition, the width of the low concentration well region 3a in a cross-sectional view as a result of forming the high concentration well 3b corresponds to the thickness of the thickest portion of the sidewall 41a. That is, the width of the low-concentration well region 3a corresponds to the film thickness when the predetermined film (which can be grasped as the second film) is formed.

  Thereafter, if the source region 5 is formed so that the high concentration well region exists between the source region 5 and the low concentration well region 3a in a cross-sectional view, the method according to the second embodiment is performed. .

  Further, since the process after the formation of the source region 5 is the same as that in the third embodiment, the description thereof is omitted here.

  As described above, the method for manufacturing the silicon carbide semiconductor device according to the present embodiment is low by performing the ion implantation process (can be grasped as the first ion implantation process) using the mask material 40a as a mask. A concentration well region 3a is formed. Thereafter, a side wall 41a is formed in a self-aligned manner with respect to the side surface of the mask material 40a, and the mask material 40a on which the side wall 41a is formed is used as a mask to perform ion implantation processing (second ion implantation processing). The high-concentration well region 3b is formed.

  Therefore, the length of the channel formed near the surface of the low concentration well region 3a can be precisely controlled in a self-aligning manner. Here, the length of the channel corresponds to the film thickness when the predetermined film (which can be grasped as the second film) is formed.

  Here, as can be seen from the above steps, the sidewall 41a can be formed symmetrically in any direction with respect to the mask material 40a. Therefore, the length of the channel formed in the vicinity of the surface of the low-concentration well region 3a is the same in any direction.

  By adopting the manufacturing method according to the present embodiment, the end portion of the source region 5 is not in direct contact with the low concentration well region 3a. Therefore, as described in the first embodiment, the short channel effect can be suppressed, which is advantageous for shortening the channel length of the element.

  Here, like the second embodiment, the method of forming the high concentration well region 3b between the source region 5 and the low concentration well region 3a in the cross-sectional view is mentioned above. However, for example, when manufacturing a silicon carbide semiconductor device having a structure in which source region 5 and low-concentration well region 3a are in contact with each other, the step of forming sidewall 21a may be omitted. However, this is not advantageous for shortening the channel length of the device.

  Further, as described above, the low-concentration well region 3a and the high withstand voltage holdable region 4 may be formed in the same process or in different processes as in the first embodiment. If both the regions 3a and 4 are formed in the same process, the manufacturing cost can be reduced as compared with the case where they are formed separately as described in the first embodiment.

  7 and 8, when the high concentration well region 3b is formed between the source region 5 and the low concentration well region 3a in a cross-sectional view, the impurity concentration of the JFET region 2a is equal to the drift layer 2 in FIG. The structure in the case where the impurity concentration is higher than the above is shown.

  However, as shown in FIGS. 19 and 20, the end of the source region 5 and the low-concentration well region 3 a are in direct contact with each other in a cross-sectional view, and the impurity concentration of the JFET region 2 a is less than that of the drift layer 2. It is also possible to adopt a configuration in the case where the concentration is higher than the concentration. FIG. 19 shows a configuration in which an epitaxial channel region is not formed, and FIG. 20 shows a configuration in which an epitaxial channel region is formed.

  Further, the shape, configuration and the like of the high withstand voltage holdable region 4 are not limited to those described in the above embodiments. For example, in each of the above embodiments, the number of the high withstand voltage holdable regions 4 in the cross-sectional view is three. However, the number may be singular or less than 3 or greater than 3.

  The combination of the first conductivity type and the second conductivity type in the above description may be n-type and p-type, or vice versa. When the first conductivity type is n-type, an n-channel field effect transistor is realized, and when the first conductivity type is p-type, a p-channel field effect transistor is realized.

1 is a cross sectional view showing a configuration of a main part of a silicon carbide semiconductor device according to a first embodiment. 9 is a process cross-sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 9 is a process cross-sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 9 is a process cross-sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 9 is a process cross-sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. FIG. 8 is a cross sectional view showing another configuration of the silicon carbide semiconductor device according to the first embodiment. FIG. 8 is a cross sectional view showing another configuration of the silicon carbide semiconductor device according to the first embodiment. FIG. 8 is a cross sectional view showing another configuration of the silicon carbide semiconductor device according to the first embodiment. 9 is a process cross-sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment. FIG. 9 is a process cross-sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment. FIG. 9 is a process cross-sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment. FIG. 9 is a process cross-sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment. FIG. It is an expanded sectional view for demonstrating the width | variety of the high concentration well area | region in a cross sectional view. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the third embodiment. FIG. 11 is a process cross-sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the third embodiment. FIG. 11 is a process cross-sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the third embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the fourth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the fourth embodiment. It is sectional drawing which shows the other structure of the silicon carbide semiconductor device concerning this invention. It is sectional drawing which shows the other structure of the silicon carbide semiconductor device concerning this invention.

Explanation of symbols

1 silicon carbide semiconductor substrate, 2 drift layer, 2a JFET region, 2c second drift layer, 3a low concentration well region, 3b high concentration well region, 4 high breakdown voltage holdable region (JTE or guard ring), 5 source region, 6 well contact region, 7 field stopper region, 8 gate insulating film, 9 gate electrode, 10 drain electrode, 11 source electrode, 12 epitaxial channel region, 14 interlayer insulating film, 20a, 40a mask material (first film), 21 Predetermined film (second film), 21a, 41a sidewall, 30a mask material (polycrystalline silicon or amorphous silicon), 30b oxide film, 20d, 30c, 30d, 44 mask material (photoresist).

Claims (9)

A silicon carbide semiconductor substrate having a first conductivity type;
A drift layer of a first conductivity type formed on the silicon carbide semiconductor substrate;
A first well region of a second conductivity type formed in a channel region on the surface of the drift layer;
A second well region of a second conductivity type formed in a channel region on the surface of the drift layer,
The first carbide region is adjacent to the second well region, and the impurity concentration of the first well region is lower than the impurity concentration of the second well region. Semiconductor device. 2. The silicon carbide semiconductor device according to claim 1, further comprising a source region having a first conductivity type, which is formed at a predetermined position on the surface of the second well region. A high withstand voltage holding region that is a second conductivity type and is formed on the surface of the drift layer at the periphery of the silicon carbide semiconductor device so as to surround the silicon carbide semiconductor device itself,
3. The silicon carbide semiconductor device according to claim 1, wherein the high withstand voltage holdable region has substantially the same impurity concentration as the first well region. 4. (A) forming a drift layer having the first conductivity type on a silicon carbide semiconductor substrate having the first conductivity type;
(B) forming a first well region having a predetermined impurity concentration of the second conductivity type on the surface of the drift layer;
(C) forming a second well region of the second conductivity type and having an impurity concentration higher than that of the first well region so as to be adjacent to the first well region on the surface of the drift layer; A method of manufacturing a silicon carbide semiconductor device comprising the steps. (D) The manufacturing method of the silicon carbide semiconductor device of Claim 4 further equipped with the process of forming the source region which becomes a 1st conductivity type in the predetermined location of the surface of the said 2nd well region. 6. The high withstand voltage holdable region of the second conductivity type is formed in the peripheral part of the silicon carbide semiconductor device by the step (C) so as to surround the silicon carbide semiconductor device itself. The manufacturing method of the silicon carbide semiconductor device of description. After the step (B)
(E) forming a first film having a predetermined shape on the drift layer,
7. The method for manufacturing a silicon carbide semiconductor device according to claim 4, wherein in the step (C), the second well region is formed using the first film as a mask. 8. After the step (A),
(F) forming a second film having a predetermined shape on the drift layer;
After the step (B)
(G) a step of thermally oxidizing the second film,
The step (B) uses the second film as a mask to form the first well region,
7. The silicon carbide semiconductor device according to claim 4, wherein in the step (C), the second well region is formed using the thermally oxidized second film as a mask. 8. Production method. After the step (A),
(F) forming a second film having a predetermined shape on the drift layer;
After the step (B)
(H) forming a third film on the second film and on the drift layer;
(I) a step of anisotropically etching the third film,
The step (B) uses the second film as a mask to form the first well region,
7. The silicon carbide semiconductor according to claim 4, wherein in the step (C), the second well region is formed using the anisotropic-etched third film as a mask. 8. Device manufacturing method.

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