JP2004006598A - Insulated gate semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power MOSFET which is high in speed and is most primarily characterized by having the capability of suppressing switching noise. <P>SOLUTION: For example, the power MOSFET comprises a plurality of p base layers 12 which are selectively formed on the surface of an n<SP>-</SP>drift layer 11, an n<SP>+</SP>source layer 13 formed on the surface of each p base layer 12, an n<SP>+</SP>drain layer 15 formed on the rear face side of the n<SP>-</SP>drift layer 11, drain electrode 21 connected to the n<SP>+</SP>drain layer 15, a plurality of source electrodes 22 connected to the p base layers 12 and to the n<SP>+</SP>source layer 13, a gate electrode 24 formed between the source electrodes 22 via a gate insulation film 23, and a p layer 14 which is selectively formed on the surface of the n<SP>-</SP>drift layer 11 below the gate electrode 24 while being connected to one of the p base layers 12 and having a lower impurity concentration than the p base layer has. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an insulated gate semiconductor device used for power control, and more particularly to a MOS gate element such as a switching power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor).
[0002]
[Prior art]
To reduce the size of a power supply circuit such as a switching power supply, it is effective to increase the switching frequency. That is, it is effective to reduce passive elements such as inductance and capacitance in the power supply circuit. However, when the switching frequency is increased, switching loss of a switching element such as a MOSFET or an IGBT increases. An increase in switching loss causes a decrease in power supply efficiency. Therefore, in order to reduce the size of the power supply circuit, it is essential to reduce the switching loss by increasing the speed of the switching element.
[0003]
[Problems to be solved by the invention]
At present, in MOS gate elements such as MOSFETs and IGBTs used as switching elements, the gate length is reduced. Thereby, the facing area between the gate electrode and the drain electrode is reduced. Thus, the speed of the MOS gate element is increased by reducing the gate-drain capacitance.
[0004]
However, if the capacitance between the gate and the drain is reduced for speeding up, resonance occurs between the parasitic inductance included in the wiring and the switching element capacitance. This causes high-frequency noise (switching noise) during switching. In order to suppress such switching noise, soft switching must be performed. Alternatively, it is necessary to provide a filter circuit or devise a gate drive circuit. Thus, the suppression of the switching noise has been accompanied by an increase in cost.
[0005]
As described above, in the related art, although higher speed can be achieved by reducing the gate-drain capacitance, it is necessary to suppress switching noise.For this purpose, soft switching is performed or an external circuit such as a filter circuit is used. There was a problem that must be done.
[0006]
Therefore, an object of the present invention is to provide an insulated gate semiconductor device that can suppress switching noise at a high speed without using an external circuit.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, in the insulated gate semiconductor device of the present invention, a first semiconductor layer of the first conductivity type and a surface portion of the first semiconductor layer of the first conductivity type are selected. A plurality of second conductive type second semiconductor layers, and at least one first conductive type second semiconductor layer formed on a surface of the plurality of second conductive type second semiconductor layers, respectively. A third semiconductor layer; a plurality of first main electrodes respectively connected to the plurality of second semiconductor layers of the second conductivity type and the at least one third semiconductor layer of the first conductivity type; A fourth semiconductor layer formed on the back surface side of the first semiconductor layer of one conductivity type; a second main electrode connected to the fourth semiconductor layer; Semiconductor layer, the at least one third semiconductor layer of the first conductivity type, and the first semiconductor layer of the first conductivity type. A control electrode formed on each surface of the semiconductor layer with a gate insulating film interposed therebetween; and a control electrode provided on the first semiconductor layer of the first conductivity type, wherein the plurality of second semiconductor layers of the second conductivity type are provided. At least one of the plurality of second conductive type fifth semiconductor layers having an impurity concentration lower than that of the plurality of second conductive type second semiconductor layers is provided.
[0008]
Further, in the insulated gate semiconductor device of the present invention, the first semiconductor layer of the first conductivity type and the plurality of semiconductor layers selectively formed on the surface of the first semiconductor layer of the first conductivity type are provided. A second semiconductor layer of a second conductivity type, at least one third semiconductor layer of the first conductivity type formed on a surface of each of the plurality of second semiconductor layers of the second conductivity type; A plurality of first main electrodes respectively connected to a plurality of second conductive type second semiconductor layers and the at least one first conductive type third semiconductor layer; and a first conductive type first semiconductor electrode. A fourth semiconductor layer formed on the back side of the semiconductor layer, a second main electrode connected to the fourth semiconductor layer, the plurality of second conductive second semiconductor layers, Three third semiconductor layers of the first conductivity type, and on each surface of the first semiconductor layer of the first conductivity type. A control electrode formed via a gate insulating film, and the control electrode provided on the first semiconductor layer of the first conductivity type and connected to at least one of the plurality of second semiconductor layers of the second conductivity type. And at least one fifth semiconductor layer of the second conductivity type having an impurity concentration lower than that of the second semiconductor layers of the second conductivity type, when a voltage is applied to the second main electrode. The capacitance between the control electrode and the second main electrode is configured to decrease at a low voltage and to be constant or increase at a high voltage.
[0009]
Further, in the insulated gate semiconductor device of the present invention, the first semiconductor layer of the first conductivity type and the plurality of semiconductor layers selectively formed on the surface of the first semiconductor layer of the first conductivity type are provided. A second semiconductor layer of a second conductivity type, at least one third semiconductor layer of the first conductivity type formed on a surface of each of the plurality of second semiconductor layers of the second conductivity type; A plurality of first main electrodes respectively connected to a plurality of second conductive type second semiconductor layers and the at least one first conductive type third semiconductor layer; and a first conductive type first semiconductor electrode. A fourth semiconductor layer formed on the back side of the semiconductor layer, a second main electrode connected to the fourth semiconductor layer, the plurality of second conductive second semiconductor layers, Three third semiconductor layers of the first conductivity type, and on each surface of the first semiconductor layer of the first conductivity type. A control electrode formed via a gate insulating film, and the control electrode provided on the first semiconductor layer of the first conductivity type and connected to at least one of the plurality of second semiconductor layers of the second conductivity type. At least one fifth semiconductor layer of the second conductivity type having an impurity concentration lower than that of the second semiconductor layers of the second conductivity type, and a voltage applied to the second main electrode is rated. When the voltage is １ ／ to ／ of the voltage, the capacitance between the control electrode and the second main electrode starts increasing.
[0010]
Further, in the insulated gate semiconductor device of the present invention, the first semiconductor layer of the first conductivity type and the plurality of semiconductor layers selectively formed on the surface of the first semiconductor layer of the first conductivity type are provided. A second semiconductor layer of a second conductivity type, at least one third semiconductor layer of the first conductivity type formed on a surface of each of the plurality of second semiconductor layers of the second conductivity type; A plurality of first main electrodes respectively connected to a plurality of second conductive type second semiconductor layers and the at least one first conductive type third semiconductor layer; and a first conductive type first semiconductor electrode. A fourth semiconductor layer formed on the back side of the semiconductor layer, a second main electrode connected to the fourth semiconductor layer, the plurality of second conductive second semiconductor layers, Three third semiconductor layers of the first conductivity type, and on each surface of the first semiconductor layer of the first conductivity type. A control electrode formed via a gate insulating film, and the control electrode provided on the first semiconductor layer of the first conductivity type and connected to at least one of the plurality of second semiconductor layers of the second conductivity type. At least one fifth semiconductor layer of the second conductivity type having an impurity concentration lower than that of the second semiconductor layers of the second conductivity type, and a voltage applied to the second main electrode is rated. When the voltage is ３ to ／ of the voltage, the at least one fifth semiconductor layer of the second conductivity type is configured to be completely depleted.
[0011]
Further, in the insulated gate semiconductor device of the present invention, a plurality of second conductive type second semiconductor layers selectively formed on a surface portion of the first conductive type first semiconductor layer; At least one third semiconductor layer of the first conductivity type formed on the surface portion of each of the plurality of second semiconductor layers of the second conductivity type, the plurality of second semiconductor layers of the second conductivity type, and A first cell including at least a plurality of first main electrodes connected to at least one third semiconductor layer of the first conductivity type, and a surface portion of the first semiconductor layer of the first conductivity type. A plurality of second conductive type second semiconductor layers, and the plurality of second conductive type second semiconductor layers provided between adjacent second conductive type second semiconductor layers. Cell including at least a fifth semiconductor layer of a second conductivity type having a lower impurity concentration than Characterized by comprising a.
[0012]
Further, in the insulated gate semiconductor device of the present invention, a plurality of second conductive type second semiconductor layers selectively formed on a surface portion of the first conductive type first semiconductor layer; At least one third semiconductor layer of the first conductivity type formed on the surface portion of each of the plurality of second semiconductor layers of the second conductivity type, the plurality of second semiconductor layers of the second conductivity type, and A first cell including at least a plurality of first main electrodes connected to at least one third semiconductor layer of the first conductivity type, and a surface portion of the first semiconductor layer of the first conductivity type. A plurality of second conductive type second semiconductor layers, and the plurality of second conductive type second semiconductor layers provided between adjacent second conductive type second semiconductor layers. Cell including at least a fifth semiconductor layer of a second conductivity type having a lower impurity concentration than Wherein the first semiconductor layer of the first conductivity type is provided with a low-resistance layer of the first conductivity type having a higher impurity concentration than the first semiconductor layer of the first conductivity type; A seventh semiconductor layer of the first conductivity type having an impurity concentration lower than that of the low resistance layer of the first conductivity type is provided between adjacent second semiconductor layers of the second conductivity type in one cell. It is characterized by having.
[0013]
Further, in the insulated gate semiconductor device of the present invention, a first semiconductor layer of a first conductivity type and a first semiconductor layer of the first conductivity type provided on the first semiconductor layer of the first conductivity type are provided. A first conductivity type low resistance layer having a higher impurity concentration than the first semiconductor layer; and a plurality of second conductivity type second resistance layers selectively formed on the surface of the first conductivity type low resistance layer. A semiconductor layer, at least one third semiconductor layer of the first conductivity type formed on a surface portion of each of the plurality of second conductivity type second semiconductor layers, and a plurality of second semiconductor layers of the second conductivity type; A plurality of first main electrodes respectively connected to the second semiconductor layer and the at least one third semiconductor layer of the first conductivity type; and a plurality of first main electrodes formed on the back surface side of the first semiconductor layer of the first conductivity type. A fourth semiconductor layer, a second main electrode connected to the fourth semiconductor layer, and the plurality of second conductive layers. A control electrode formed on each surface of the second semiconductor layer, the at least one third semiconductor layer of the first conductivity type, and the low resistance layer of the first conductivity type via a gate insulating film And lower than the plurality of second conductive type second semiconductor layers provided on the first conductive type low resistance layer and connected to the adjacent second conductive type second semiconductor layers, respectively. A plurality of fifth semiconductor layers of the second conductivity type having an impurity concentration, and an impurity lower than the low resistance layer of the first conductivity type between the plurality of fifth semiconductor layers of the second conductivity type. A seventh semiconductor layer of a first conductivity type having a concentration is provided.
[0014]
Further, in the insulated gate semiconductor device of the present invention, the first semiconductor layer of the first conductivity type and the first semiconductor layer of the first conductivity type provided on the first semiconductor layer of the first conductivity type are provided. A first conductivity type low resistance layer having a higher impurity concentration than the first semiconductor layer; and a plurality of second conductivity type second resistance layers selectively formed on the surface of the first conductivity type low resistance layer. A semiconductor layer, at least one third semiconductor layer of the first conductivity type formed on a surface portion of each of the plurality of second conductivity type second semiconductor layers, and a plurality of second semiconductor layers of the second conductivity type; A plurality of first main electrodes respectively connected to the second semiconductor layer and the at least one third semiconductor layer of the first conductivity type; and a plurality of first main electrodes formed on the back surface side of the first semiconductor layer of the first conductivity type. A fourth semiconductor layer, a second main electrode connected to the fourth semiconductor layer, and the plurality of second conductive layers. A control formed on each surface of the second semiconductor layer of the first type, the at least one third semiconductor layer of the first conductivity type, and the low-resistance layer of the first conductivity type via a gate insulating film An electrode and the plurality of second conductivity type second semiconductor layers provided on the first conductivity type low resistance layer and connected to the plurality of adjacent second conductivity type second semiconductor layers, respectively; And a plurality of fifth semiconductor layers of the second conductivity type having lower impurity concentrations.
[0015]
According to the insulated gate semiconductor device of the present invention, the fifth semiconductor layer of the second conductivity type can be depleted at the time of turn-off by applying a high voltage to some extent. As a result, it is possible to suppress the voltage jump at the time of turn-off without deteriorating the high-speed operation.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each embodiment, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described.
[0017]
(1st Embodiment)
FIG. 1 shows a configuration example of a vertical power MOSFET according to the first embodiment of the present invention.
[0018]
In FIG. 1, an n-drift layer 11 as a first semiconductor layer has an n-low resistance layer 11a provided on one surface (surface) by diffusion. A plurality of p base layers 12 as second semiconductor layers are selectively formed on the surface of the n low resistance layer 11a by diffusion. Each p base layer 12 is arranged in a stripe shape in a first direction orthogonal to the front of the element. A plurality of n + source layers 13 as third semiconductor layers are selectively formed on the surface of each p base layer 12 by diffusion.
[0019]
A p-type layer 14 as a fifth semiconductor layer is selectively formed on the surface of the n-type low-resistance layer 11a between two adjacent p-type base layers 12 by diffusion. In the case of the present embodiment, the p-layers 14 are arranged in stripes in the first direction along the p-base layer 12. Then, it is connected to one of the two adjacent p base layers 12. The p layer 14 is formed with a lower impurity concentration than the p base layer 12.
[0020]
On the other surface (back surface) of the n- drift layer 11, an n + drain layer 15 as a fourth semiconductor layer is formed. A drain electrode 21 as a second main electrode is connected to the entire surface of the n + drain layer 15.
[0021]
On the other hand, a source electrode 22 as a first main electrode is formed on each of the p base layers 12, including a part of the n + source layer 13. Each source electrode 22 is arranged in a stripe shape in the first direction. Further, a gate electrode 24 as a control electrode is formed between the source electrodes 22 via a gate insulating film (for example, a silicon (Si) oxide film) 23. In other words, the gate electrode 24 having the planar structure is formed from the n + source layer 13 in one p base layer 12 through the n low resistance layer 11a and the p layer 14 to the other p base layer 12. It is formed on a region reaching the n + source layer 13. The gate insulating film 23 has a thickness of about 0.1 μm.
[0022]
Here, as a substrate used for forming the n − drift layer 11 and the n + drain layer 15, for example, a substrate obtained by forming an n − layer on a low-resistance Si substrate by epitaxial growth is used. Alternatively, a substrate in which an n + layer is formed on a Si substrate by diffusion can be used.
[0023]
As described above, the p layer (hereinafter, also referred to as a gate lower p layer) 14 is disposed between the adjacent p base layers 12 and below the gate electrode 24 and on the surface of the n low resistance layer 11a. Then, the p layer 14 is formed with a lower impurity concentration than the p base layer 12. The p layer 14 is depleted when a high voltage is applied. Thus, high-speed and low-noise switching characteristics of the MOSFET are realized.
[0024]
That is, the MOSFET of the structure according to the present embodiment (hereinafter, simply referred to as the structure of the present embodiment) utilizes the characteristic that the capacitance between the gate and the drain is increased in accordance with the drain voltage, and the switching characteristic of high speed and low noise To achieve.
[0025]
FIG. 2 shows the dependence of the gate-drain capacitance on the source-drain voltage in the MOSFET of the present embodiment in comparison with a MOSFET (not shown) of a conventional structure.
[0026]
As shown by the broken line in FIG. 2, in the case of the MOSFET (B) having the conventional structure, the gate-drain capacitance continues to decrease in proportion to the source-drain voltage.
[0027]
On the other hand, as shown by the solid line in FIG. 2, the gate-drain capacitance of the MOSFET (A) of the present embodiment increases as the source-drain voltage increases.
[0028]
That is, if the source-drain voltage is low, the gate-drain capacitance gradually decreases. As the source-drain voltage increases, the gate-drain capacitance increases. This is because the lower gate p-layer 14 is depleted due to an increase in the source-drain voltage (high drain voltage), thereby increasing the apparent gate length as well as the apparent gate length. This is because the area facing the drain electrode 21 has increased.
[0029]
Here, the switching speed of the MOSFET increases as the gate-drain capacitance decreases. However, if the MOSFET has a small capacitance at the time when it is completely turned off, the jump-up voltage at the time of turn-off becomes large. It is desirable that the MOSFET has a small capacitance at the time of starting to turn off, that is, a low capacitance when the drain voltage is low, and has a large capacitance at the time of ending the turning off, that is, a high drain voltage.
[0030]
In the case of the MOSFET (B) having the conventional structure, the smaller the distance between the p base layers, the smaller the facing area between the gate electrode and the drain electrode. That is, the gate-drain capacitance is reduced. When a drain voltage is applied, a depletion layer from the p base layer extends. For this reason, the gate-drain capacitance is further reduced. Therefore, in order to realize high-speed and low-noise switching, a gate drive circuit is required. In addition, complicated control such as gradually reducing the gate current is required.
[0031]
As described above, the MOSFET (A) having the structure of the present embodiment utilizes the characteristic that the gate-drain capacitance increases in accordance with the drain voltage. That is, at the time when the MOSFET starts to be turned off, the space between the p base layers 12 is narrowed by the non-depletion of the p layer 14 under the gate due to the low drain voltage. Thus, the facing area between the gate electrode 24 and the drain electrode 21 is reduced, so that the gate-drain capacitance is reduced. Thereby, high-speed switching characteristics are ensured. On the other hand, at the end of turning off, the gap between the apparent p base layers 12 is increased by depletion of the gate lower p layer 14 due to the high drain voltage. In this way, the facing area between the gate electrode 24 and the drain electrode 21 is increased to increase the gate-drain capacitance. Thereby, the surge of the drain voltage is suppressed, and the switching noise is reduced. Thus, high-speed and low-noise switching characteristics are realized without requiring external circuits or complicated control.
[0032]
FIG. 3 shows a waveform of a drain voltage (Vds) and a waveform of a drain current (Id) at the time of turn-off in the MOSFET having the structure of the present embodiment, respectively, in comparison with a MOSFET having a conventional structure.
[0033]
In the case of the MOSFET (B) having the conventional structure, as described above, the switching characteristics are speeded up by shortening the gate length. In addition, as shown by a broken line in FIG. 3, the jump-up voltage (drain voltage Vds) at the time of OFF increases in proportion thereto. The drain voltage Vds oscillates greatly thereafter, and is not easily stabilized.
[0034]
On the other hand, the MOSFET (A) of the present embodiment structure has a small gate-drain capacitance at a low drain voltage and a large gate-drain capacitance at a high drain voltage. As a result, while maintaining the high-speed operation, for example, as shown by a solid line in FIG. 3, the jumping voltage is less than half of the conventional case, and the switching characteristics are such that the oscillation of the drain voltage Vds is suppressed.
[0035]
In the case of the MOSFET having the structure of the present embodiment described above, for example, as shown in FIG. 1, the p-layer 14 under the gate is provided only in one of the two adjacent p-base layers 12. However, the present invention is not limited to this. For example, as shown in FIG. 4, a configuration in which a gate lower p layer 14 is provided on each of two adjacent p base layers 12 may be employed.
[0036]
Further, the p-layer 14 under the gate is not limited to the case where it is formed shallower than the p-base layer 12. That is, the p-layer 14 under the gate may be depleted at a high drain voltage in operation. Therefore, the junction depth of the p-layer 14 under the gate may be the same as that of the p-base layer 12 or may be deeper than the p-base layer 12. However, if the gate lower p-layer 14 is formed shallow, the effective area of the opposing gate electrode 24 and drain electrode 21 when completely depleted increases. For this reason, the change in the gate-drain capacitance with respect to the increase in the drain voltage becomes large, and a great effect can be obtained in reducing noise. For this reason, it is desirable that the gate lower p layer 14 is shallower than the p base layer 12.
[0037]
Further, in the MOSFET having the structure of this embodiment shown in FIG. 1, the n low resistance layer 11a is provided to reduce the resistance between the adjacent p base layers 12. That is, the n low resistance layer 11a is formed deeper than the p base layer 12. Thereby, the spreading resistance from the narrow JFET (Junction FET) region sandwiched between the p base layers 12 to the wide n− drift layer 11 can be suppressed. In order to reduce the on-resistance, the n low resistance layer 11a may be shallower than the p base layer 12.
[0038]
Thus, the n low resistance layer 11a does not directly affect the switching characteristics of high speed and low noise. Therefore, for example, as shown in FIG. 5, it is possible to omit the formation of the n low resistance layer (the same applies to the MOSFET having the structure of the present embodiment shown in FIG. 4).
[0039]
When attention is paid not only to the high speed but also to the on-resistance, the gate capacitance representing the high speed is usually proportional to the area, and the on-resistance is inversely proportional to the area. For this reason, there is a trade-off between high speed and low on-resistance. However, in the MOSFET having the structure of the present embodiment, it is possible to greatly increase the speed simply by slightly increasing the channel resistance and the resistance of the JFET region. For this reason, the trade-off relationship between high speed and low on-resistance is improved. Thus, it is possible to easily lower the on-resistance while maintaining the switching speed.
[0040]
Normally, a switching element whose rated voltage (element breakdown voltage) is 1.5 to 3 times the power supply voltage is selected. Therefore, it is desirable that the capacitance between the gate and the drain be large with respect to a voltage about the power supply voltage. That is, the switching element desirably has such characteristics that its gate-drain capacitance starts to increase at a voltage of 1/3 to 2/3 of the rated voltage.
[0041]
If the gate lower p-layer 14 is completely depleted, the facing area between the gate electrode 24 and the drain electrode 21 increases greatly, and the gate-drain capacitance increases. Therefore, it is desirable that the p-layer 14 under the gate be completely depleted by a voltage of 1/3 to 2/3 of the rated voltage.
[0042]
When the gate lower p-layer 14 is completely depleted, the gate-drain capacitance increases (see FIG. 2). However, even when the capacitance between the gate and the drain does not increase, that is, when the decrease in the capacitance is eliminated and the capacitance becomes constant, or when the decrease in the capacitance is suppressed to a small value, compared to the MOSFET having the conventional structure, The off-state capacitance increases. Therefore, since switching noise is suppressed, the p-layer 14 under the gate may not be completely depleted but may be partially depleted.
[0043]
FIG. 6 shows a turn-off waveform of the MOSFET (A) having the structure of the present embodiment in comparison with that of the MOSFET (B) having the conventional structure.
[0044]
In a state of a low drain voltage, the capacitance between the gate and the drain is reduced by the p layer 14. Therefore, high-speed switching characteristics are obtained. On the other hand, when the drain voltage is high, the p-layer 14 is depleted. This increases the apparent gate length and increases the gate-drain capacitance. Therefore, the jump voltage can be suppressed.
[0045]
As is clear from FIG. 6, the switching characteristic becomes faster as the area of the depleted p layer 14 between the p base layers 12 under the gate electrode 24 is increased.
[0046]
FIG. 7 shows a change in the turn-off loss (Eoff) when the area of the p-layer 14 under the gate is changed in the MOSFET having the structure of the present embodiment. The abscissa indicates the ratio of the depleted p layer 14 to the area between the p base layers 12 under the gate electrode 24. The vertical axis is the turn-off loss with an inductive load.
[0047]
As shown in FIG. 7, it is estimated that setting the value of the area ratio to 30% or more is effective for increasing the speed, and that the turn-off loss becomes smaller than that of a MOSFET having a conventional structure (about 1.35 mJ). Accordingly, it is desirable that the area ratio be a value larger than this value (30%).
[0048]
FIG. 8 shows a change in the turn-off loss when the net dose (effective dose) of the p-layer 14 under the gate is changed in the MOSFET having the structure of the present embodiment.
[0049]
The net dose is not the amount of impurities actually implanted. It is an impurity amount (concentration) corresponding to the number of carriers present in the portion of the p layer 14, and is an impurity amount obtained by subtracting an n-type impurity amount existing between the p base layers 12 from the p-type impurity amount.
[0050]
If the net dose is small, the p-layer 14 is completely depleted at a low voltage, so that the effect of increasing the speed is small. When the net dose exceeds a certain level, the p layer 14 does not become depleted when a high voltage is applied, and the capacitance does not increase. In this case, although the speed can be increased, the turn-off loss is constant, so that the switching noise increases as in the case of the normal speed increase. Thus, the net dose of the p-layer 14 is 1 to 3.2 × 10 ¹² cm ^-2 It is desirable to be less than about.
[0051]
When actually manufacturing the MOSFET, the dopants of the n low resistance layer 11a and the p layer 14 under the gate are phosphorus (P) and boron (B). In this case, due to the difference in the diffusion constant, the n low resistance layer 11a and the p layer 14 under the gate can be formed by simultaneous diffusion.
[0052]
Since the high-concentration n low resistance layer 11a and the p layer 14 overlap, the net dose differs from the amount of impurities actually implanted. As shown in FIG. 8, the amount of impurities to be ion-implanted may be adjusted so that the net dose becomes the optimum amount of impurities.
[0053]
FIG. 9 shows the relationship between the distance Lj between the adjacent p base layers 12 and the maximum net dose Np0 of the gate lower p layer 14 effective for reducing noise in the MOSFET having the structure of the present embodiment. Here, the case where the depth Xj of the p base layer 12 is 4 μm is shown.
[0054]
The maximum net dose Np0 is the maximum net dose at which the gate lower p-layer 14 is depleted when a high voltage is applied. If it is larger than this, the p-layer 14 under the gate will not be depleted, and the gate capacitance will not increase. Therefore, noise increases. Accordingly, it is desirable that the net dose of the p-layer 14 under the gate be suppressed to the maximum net dose Np0 or less.
[0055]
As shown in FIG. 9, the maximum net dose Np0 is substantially proportional to the distance Lj between the p base layers 12. Thus, the ratio (Np0 / Lj) between the maximum net dose Np0 and the distance Lj between the p base layers 12 is 2 × 10 ^Fifteen cm ^-3 It is desirable to make the following.
[0056]
In addition, when the depth of the p base layer 12 is increased, the drain voltage is less likely to be applied to the p layer 14 under the gate, and it is difficult to be depleted. Therefore, the maximum net dose Np0 is inversely proportional to the depth Xj of the p base layer 12.
[0057]
As shown in FIG. 9, when the depth Xj of the p base layer 12 is 4 μm, the ratio (Np0 / (Lj · Xj) of the maximum net dose Np0 to the product of the depth Xj of the p base layer 12 and the interval Lj )) Is 5 × 10 ¹⁸ cm ^-4 It is desirable to make the following.
[0058]
(Second embodiment)
FIG. 10 shows a configuration example of a power MOSFET according to the second embodiment of the present invention. The same parts as those of the MOSFET shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. Here, only different portions will be described. FIG. 10 shows an example in which the formation of the n low resistance layer is omitted.
[0059]
In FIG. 10, the p-layer 14A as the fifth semiconductor layer has a structure embedded in the n-drift layer 11, respectively. That is, in the case of the present embodiment, the two p layers 14 </ b> A are arranged below the respective p base layers 12. The two p layers 14A are connected to two adjacent p base layers 12, respectively. The p-layers 14A are arranged in stripes in the first direction along the p-base layer 12, respectively. Each of the p layers 14A has a lower impurity concentration than each of the p base layers 12.
[0060]
In the MOSFET of the present embodiment, for example, similarly to the MOSFET of the structure shown in FIG. 1, the p-layer 14A is depleted by applying a high drain voltage. Then, the facing area between the gate electrode 24 and the drain electrode 21 is increased, so that the gate-drain capacitance is increased. Thereby, high-speed and low-noise switching characteristics can be realized.
[0061]
As described above, if the p-layer 14A exists between the gate electrode 24 and the drain electrode 21, substantially the same effects as those of the first embodiment can be obtained. Therefore, the p-layer depleted by the high drain voltage does not necessarily have to be formed on the surface of the n- drift layer (or n-low resistance layer).
[0062]
In the case of the MOSFET having the structure of the present embodiment, the manufacturing process is slightly more complicated than that of the MOSFET having the structure shown in FIG. In other words, the manufacturing process is complicated because the p-layer 14A is formed inside the n-drift layer 11. However, the point where the electric field is concentrated when a high voltage is applied becomes closer to the bottom of the p base layer 12. Accordingly, the breakdown strength is improved as compared with the MOSFET having the structure shown in FIG.
[0063]
(Third embodiment)
FIG. 11 shows a configuration example of a power MOSFET according to the third embodiment of the present invention. The same parts as those of the MOSFET shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. Here, only different portions will be described. FIG. 11 shows an example in which the formation of the n low resistance layer is omitted.
[0064]
In FIG. 11, a gate electrode 24a as a control electrode is buried in the surface of n-drift layer 11 via gate insulating film 23a. That is, in the case of the present embodiment, the gate electrode (trench gate) 24a having a trench structure is provided in a stripe shape between two adjacent p base layers 12. A p-layer 14B as a fifth semiconductor layer is formed around the trench gate 24a. The p layer 14B is connected to at least one of the p base layers 12. The p layer 14B is formed to have a lower impurity concentration than each of the p base layers 12.
[0065]
In the MOSFET of this embodiment having such a trench gate 24a, the p layer 14B remains without being depleted at a low drain voltage. Therefore, the gate-drain capacitance is small, and high-speed switching becomes possible. On the other hand, when a high drain voltage is applied, p layer 14B is depleted. As a result, the apparent gate area increases, and the gate-drain capacitance increases. Therefore, the noise is low, and substantially the same effect as that of the MOSFET having the planar type gate electrode shown in FIG. 1, that is, high-speed and low-noise switching characteristics can be realized.
[0066]
Further, in the case of the MOSFET having the structure of the present embodiment, the ratio of the number of trench gates 24a surrounded by the p layer 14B and the area ratio of the p layer 14B to the trench gate 24a can be changed. Thus, in the MOSFET having the configuration shown in FIG. 1, the same effect as when the area ratio of the p-layer is changed can be obtained.
[0067]
Further, for example, as shown in FIG. 12, p layer 14B 'may be formed so as to surround one side wall and the bottom of trench gate 24a. That is, the p layer 14B 'can be formed except for a part of the side wall of the trench gate 24a. In this case, since there is no need to create a channel through which current does not completely flow, low on-resistance can be achieved.
[0068]
(Fourth embodiment)
FIG. 13 shows a configuration example of a power MOSFET according to the fourth embodiment of the present invention. The same parts as those of the MOSFET shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. Here, only different portions will be described. FIG. 13 shows an example in which an n low resistance layer is formed.
[0069]
In FIG. 13, a gate electrode 24b as a control electrode has a split gate structure. In the case of the present embodiment, two p-layers 14 under the gate as a fifth semiconductor layer are formed on the surface of the n-low resistance layer 11a. The two gate lower p-layers 14 are connected to each of the adjacent p base layers 12. The p layer 14 has a lower impurity concentration than each of the p base layers 12.
[0070]
Normally, by using a split gate structure as the gate structure, the switching characteristics can be speeded up by reducing the gate capacitance. Therefore, when the p-layer 14 under the gate is formed, it is possible to further realize high-speed switching characteristics.
[0071]
In the process of manufacturing the MOSFET having the structure of the present embodiment, the gate electrode 24b may be formed (divided) after the formation of the p-layer 14 under the gate. Alternatively, the gate electrode 24b is formed after forming the gate lower p layer 14 on the entire surface of the n low resistance layer 11a. Then, using the gate electrode 24b as a mask, the n low resistance layer 11a may be formed (the p layer 14 is divided).
[0072]
Further, the gate structure is not limited to the gate electrode 24b having the split gate structure. For example, as shown in FIG. 14, a gate electrode (control electrode) 24c having a terrace gate structure can be used. In this case, substantially the same result as in the case of the split gate structure described above can be obtained.
[0073]
(Fifth embodiment)
FIG. 15 shows a configuration example of a power MOSFET according to the fifth embodiment of the present invention. The same parts as those of the MOSFET shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. Here, only different portions will be described. FIG. 15 shows an example in which an n low resistance layer is formed.
[0074]
In FIG. 15, a plurality of p base layers 12 as second semiconductor layers are formed in a stripe shape in a first direction orthogonal to the front of the device. On the other hand, the plurality of gate lower p-layers 14 as fifth semiconductor layers are formed in a stripe shape in a second direction orthogonal to the respective p base layers 12.
[0075]
According to the MOSFET having the structure according to the present embodiment, not only effects similar to those of the MOSFET having the structure shown in FIG. 1 can be obtained, but also other effects can be expected. For example, the depleted p-layer 14 can be formed without the influence of misalignment.
[0076]
(Sixth embodiment)
FIG. 16 shows a configuration example of a power MOSFET according to the sixth embodiment of the present invention. The same parts as those of the MOSFET shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. Here, only different portions will be described. FIG. 16 shows an example in which an n low resistance layer is formed.
[0077]
In FIG. 16, a plurality of p base layers 12a as second semiconductor layers are arranged in a lattice shape (or staggered shape) on the surface of the n low resistance layer 11a. Each of the plurality of gate lower p-layers 14a as the fifth semiconductor layer is disposed in a rectangular shape between four adjacent p-base layers 12a.
[0078]
The plurality of n + source layers 13a as the third semiconductor layers are formed in a ring shape on the surface of each of the p base layers 12a. A rectangular source electrode 22a as a first main electrode is provided at a portion corresponding to each of the p base layer 12a and the n + source layer 13a. The gate electrode 24d as a control electrode is provided at a portion other than the source electrodes 22a via a gate insulating film 23d.
[0079]
With the MOSFET having the structure according to the present embodiment, substantially the same effects as those of the MOSFET having the configuration shown in FIG. 1 can be obtained. Moreover, since the electric field at the corners of each p base layer 12a is further reduced, it is possible to suppress a decrease in breakdown voltage.
[0080]
Further, as shown in FIG. 16, for example, the interval Wp between the adjacent gate lower p layers 14a is made smaller than the interval Wj between the adjacent p base layers 12a. This is equivalent to reducing the area of the p base layer 12a. This alleviates the electric field at the junction between p base layer 12a and n low resistance layer 11a. Therefore, it is possible to suppress a decrease in breakdown voltage. Such an effect is similarly obtained in a structure in which each p base layer 12 is formed in a stripe shape as shown in FIG.
[0081]
FIG. 17 shows an example in which the arrangement of the gate lower p-layer 14a and the n-low resistance layer 11a is reversed in the power MOSFET having the configuration shown in FIG.
[0082]
That is, the plurality of p base layers 12a as the second semiconductor layers are arranged in a lattice shape (or a staggered shape) on the surface of the n low resistance layer 11a. The plurality of gate lower p-layers 14a as fifth semiconductor layers are each disposed in a rectangular shape between two adjacent p-base layers 12a.
[0083]
With such a configuration, substantially the same effects as those of the MOSFET shown in FIG. 16 can be obtained.
[0084]
FIG. 18 shows an example in which the p-layer under the gate is arranged in a stripe pattern in the power MOSFET having the configuration shown in FIG.
[0085]
That is, the plurality of p base layers 12a as the second semiconductor layers are arranged in a lattice shape (or a staggered shape) on the surface of the n low resistance layer 11a. The plurality of gate lower p-layers 14b as fifth semiconductor layers are each arranged in a stripe shape between adjacent p base layers 12a.
[0086]
With such a configuration, substantially the same effects as those of the MOSFET shown in FIG. 16 can be obtained.
[0087]
FIGS. 19 to 21 show still another configuration example of the power MOSFET according to the sixth embodiment.
[0088]
FIG. 19 shows an example of an arrangement pattern of the p-layer under the gate when the p-base layers are arranged in a lattice shape (or a staggered shape). In this case, a plurality of gate lower p-layers 14c as a fifth semiconductor layer may be arranged in a staggered manner so as to surround some of the p-base layers 12a as the second semiconductor layers.
[0089]
FIG. 20 shows another example of the arrangement pattern of the p-layer under the gate when the p-base layers are arranged in a lattice (or staggered). In this case, a plurality of gate lower p-layers 14c as fifth semiconductor layers can be arranged in a unidirectional stripe so as to surround some of the p-base layers 12a as second semiconductor layers. is there.
[0090]
FIG. 21 shows still another example of the arrangement pattern of the p-layer under the gate when the p-base layers are arranged in a lattice shape (or staggered shape). In this case, a plurality of gate-underlying p-layers 14c as fifth semiconductor layers may be arranged in a bidirectional stripe shape so as to surround some of the p-base layers 12a as second semiconductor layers. is there.
[0091]
As shown in FIGS. 19 to 21, the MOSFET having the structure of the present embodiment can be easily realized regardless of the configuration.
[0092]
(Seventh embodiment)
FIG. 22 shows an example in which the seventh embodiment of the present invention is applied to an IGBT. The same parts as those of the MOSFET shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. Here, only different portions will be described. FIG. 22 shows an example in which the formation of the n low resistance layer is omitted.
[0093]
In FIG. 22, the IGBT (non-punch-through type structure) of the structure of this embodiment has substantially the same structure as the MOSFET in which the formation of the n low resistance layer shown in FIG. 5 is omitted.
[0094]
That is, in the n-drift layer 11 as the first semiconductor layer, a plurality of p base layers 12 as the second semiconductor layer are selectively formed on one surface (surface) by diffusion. Each p base layer 12 is arranged in a stripe shape in a first direction from the front to the back of the drawing. At least one n + source layer 13 as a third semiconductor layer is selectively formed on the surface of each p base layer 12 by diffusion.
[0095]
A p-layer 14 as a fifth semiconductor layer is selectively formed on the surface of the n-drift layer 11 between two adjacent p-base layers 12 by diffusion. In the case of the present embodiment, the p-layers 14 are arranged in stripes in the first direction along the p-base layer 12. Then, it is connected to one of the two adjacent p base layers 12. The p layer 14 is formed with a lower impurity concentration than the p base layer 12.
[0096]
On the other surface (back surface) of the n- drift layer 11, a p + drain layer 31 as a fourth semiconductor layer is formed. The drain electrode 21 as a second main electrode is connected to the entire surface of the p + drain layer 31.
[0097]
On the other hand, a source electrode 22 as a first main electrode is formed on each of the p base layers 12, including a part of the n + source layer 13. Each source electrode 22 is arranged in a stripe shape in the first direction. Further, a gate electrode 24 as a control electrode is formed between the source electrodes 22 with a gate insulating film 23 interposed therebetween. That is, the gate electrode 24 having the planar structure is formed from the n + source layer 13 in the one p base layer 12 through the n − drift layer 11 and the p layer 14 and then into the other p base layer 12. It is formed on a region reaching n + source layer 13. The gate insulating film 23 has a thickness of about 0.1 μm.
[0098]
As described above, in the IGBT having the structure of the present embodiment, the portion of the n + drain layer 15 in the MOSFET is constituted by the p + drain layer 31. Thereby, it is configured to operate as an IGBT.
[0099]
Generally, in the case of a MOS gate element, the switching characteristics are almost uniquely determined by the capacitance determined by the MOS gate structure. Therefore, the MOS gate structure of the present embodiment is also effective for the IGBT.
[0100]
The IGBT is not limited to the non-punch-through type structure, but can be similarly applied to a punch-through type IGBT as shown in FIG. 23, for example. In the case of a punch-through type IGBT, an n + buffer layer 32 as a sixth semiconductor layer is provided between the n− drift layer 11 and the p + drain layer 31.
[0101]
FIG. 24 shows still another configuration example of the IGBT according to the seventh embodiment of the present invention. Note that the same portions as those of the IGBT shown in FIG. 23 are denoted by the same reference numerals, and detailed description thereof will be omitted. Here, only different portions will be described. FIG. 24 shows an example in which an n low resistance layer is formed. Further, this is an example of a case where the present invention is applied to an IGBT having a punch-through structure.
[0102]
As shown in FIG. 24, some IGBTs have dummy cells (second cells) 41 in which part of the source contact (source electrode 22A) is thinned out. By thinning the source contacts, the conductivity modulation of the n- drift layer 11 can be enhanced.
[0103]
In the IGBT having such a configuration, in the dummy cell 41, a p-layer 14d under the gate as a fifth semiconductor layer is formed. At this time, the p layer 14d is formed so as to completely cover the surface of the n low resistance layer 11a. On the other hand, in the normal cell (first cell) 42 in which the source contact (source electrode 22) is formed on both sides as usual, the p-layer 14d under the gate is not formed. Thus, when the drain voltage is low, the gate-drain capacitance is small, and high-speed switching is possible. When the drain voltage is high, the gate-drain capacitance is increased and low switching noise can be obtained.
[0104]
The IGBT of the present embodiment structure is not limited to the planar type MOS gate structure as shown in FIGS. 22 to 24, and may be similarly applied to a trench type MOS gate structure. It is possible.
[0105]
(Eighth embodiment)
FIG. 25 shows a configuration example of a power MOSFET according to the eighth embodiment of the present invention. The same parts as those of the IGBT shown in FIG. 24 are denoted by the same reference numerals, and detailed description thereof will be omitted. Here, only different portions will be described. FIG. 25 shows an example in which an n low resistance layer is formed.
[0106]
As shown in FIG. 25, this MOSFET has a MOS cell (second cell) 51 having a gate lower p-layer 14d as a fifth semiconductor layer, and a MOS cell having no gate lower p-layer 14d. (First cell) 52 is provided. The gate lower p layer 14d is formed, for example, so as to completely cover the surface of the n low resistance layer 11a.
[0107]
In the case of the MOSFET having the structure of the present embodiment, the density (number) of the MOS cells 51 including the p-layer 14d under the gate is changed. By doing so, the same effect as when the area ratio of the p-layer 14d under the gate is changed can be obtained. That is, the ratio of the number of cells 51 to the number of cells 51 and 52 of the entire device corresponds to the area ratio of the p-layer 14 under the gate shown in FIG.
[0108]
Further, as compared with the IGBT in which the source contacts are thinned out (see FIG. 24), the manufacturing process can be simplified, which is advantageous in manufacturing.
[0109]
Here, the gate electrode 24 in the MOS cell 52 in which the gate lower p layer is not inserted has a split gate structure, and the gate electrode 24 in the MOS cell 51 in which the gate lower p layer 14d is inserted has a normal structure. Then, when the voltage is low, the capacitance is determined by the gate area of the MOS cell 52, so that the gate-drain capacitance is small and the speed is increased. On the other hand, when the voltage is high, the area of the gate electrode 24 of the MOS cell 51 is large, and low noise can be achieved.
[0110]
It is not necessary to form the p-layer 14d under the gate so as to completely cover the surface of the n-low resistance layer 11a. The same effect can be obtained when the surface of the n-low resistance layer 11a is partially covered with the p-layer 14d under the gate. In this case as well, it is important to design the device by the ratio of the gate area of the entire device to the area under the gate (for example, the surface area of the n low resistance layer 11a). It is also desirable that the net dose be a value as shown in FIG.
[0111]
Furthermore, the present invention is not limited to MOSFETs, but can be similarly applied to an IGBT having a punch-through structure (or an IGBT having a non-punch-through structure (not shown)) as shown in FIG.
[0112]
(Ninth embodiment)
FIG. 27 shows a configuration example of a power MOSFET according to the ninth embodiment of the present invention. The same portions as those of the MOSFET shown in FIG. 25 are denoted by the same reference numerals, and detailed description thereof will be omitted. Here, only different portions will be described.
[0113]
In the case of the MOSFET having the structure of the present embodiment, for example, as shown in FIG. 27, a MOS cell (first cell) 51a having a p-layer 14d under the gate as a fifth semiconductor layer is used as a third semiconductor layer. The structure does not include the n + source layer 13.
[0114]
In the MOSFET having such a structure, the breakdown strength can be increased. That is, even when a voltage is applied to the gate electrode 24, the MOS cell 51a including the gate lower p layer 14d does not operate because there is no path for electrons to flow. That is, the MOS cell 51a has only a role of increasing the gate-drain capacitance when the drain voltage is high. Therefore, removing the n + source layer 13 does not affect the on-resistance.
[0115]
Also, since there is no n + source layer 13, no parasitic bipolar transistor exists in the MOS cell 51a. Therefore, even if avalanche breakdown occurs when a high voltage is applied, the generated holes can be quickly discharged. Thereby, high-speed and low-noise switching characteristics can be realized, and the avalanche withstand capability is improved.
[0116]
In the MOSFET shown in FIG. 27, the gate lengths of the MOS cell 52 and the MOS cell 51a are the same. On the other hand, as shown in FIG. 28, for example, the gate length of gate electrode 24B of MOS cell 51b is increased, and the gate length of gate electrode 24A of MOS cell 52a is reduced. By doing so, the effect on high-speed and low switching noise is enhanced.
[0117]
That is, at a low voltage, only the gate capacitance of the MOS cell 52a becomes the gate capacitance of the entire device. Therefore, the speed can be increased by shortening the gate length of the MOS cell 52a. At the time of high voltage, the p-layer 14d under the gate is depleted. Therefore, the gate capacitance of MOS cell 51b is added to the gate capacitance of MOS cell 52a. Thus, by increasing the gate length of the MOS cell 51b, it is possible to increase the amount of increase in gate capacitance, and as a result, switching noise can be greatly reduced.
[0118]
(Tenth embodiment)
Here, the impurity amount of the p-layer under the gate will be described in more detail. Here, the MOSFET having the configuration shown in FIG. 1 will be described as an example.
[0119]
In the MOSFET according to the first embodiment, the gate-drain capacitance changes due to the depletion of the p-layer 14 under the gate. This is effective for increasing the speed and reducing noise of the MOSFET. For this reason, the p-type layer 14 under the gate needs to have such an impurity amount as to be depleted when a high drain voltage is applied. When the impurity amount is set to a certain level or more, the p-layer 14 under the gate is not depleted, and the effect of increasing the speed and reducing the noise cannot be obtained. As described above, the impurity amount of the p-layer 14 under the gate has a maximum value which is a limit for depletion.
[0120]
The maximum impurity amount of the p-layer 14 under the gate is determined by the degree of depletion of the p-layer 14 under the gate. The degree of depletion depends on the magnitude of the electric field applied to the p-layer 14 under the gate. That is, the maximum impurity amount of the p-layer 14 under the gate depends on the size of each part of the MOSFET and the concentration of each part. Specifically, it depends on the dimensions of the p layer 14 under the gate, the distance (distance) between the p base layers 12, the concentration of the n low resistance layer 11a, the depth of the p base layer 12, and the like. Therefore, when designing the impurity amount of the p-layer 14 under the gate, it is important to consider the dimensions of each part and the concentration of each part of the MOSFET. The n-low resistance layer 11a is formed with a higher impurity concentration than the n- drift layer 11.
[0121]
In the case of the MOSFET shown in FIG. 1, the p layer 14 under the gate is formed on the same surface as the n low resistance layer 11a. Therefore, the impurity amount of the p-layer 14 under the gate needs to be discussed in terms of the net dose. The net dose is an amount obtained by subtracting the n-type impurity amount from the p-type impurity amount corresponding to the hole amount.
[0122]
In the following description, the impurity amount of the gate lower p layer 14 indicates the net dose of the gate lower p layer 14. Further, as a unit of the impurity amount, a concentration per area (cm) obtained by integrating the impurity concentration in the depth direction. ^-2 ) Is used.
[0123]
FIG. 29 shows the relationship between the dimension (area ratio Ap) of the p-layer 14 under the gate and the maximum net dose Np0 of the p-layer 14 under the gate in the MOSFET having the structure of the first embodiment. However, here, the dose (Nn) of the n low-resistance layer 11a is set to 4 × 10 ¹² cm ^-2 , P base layer 12 is set to 6 μm.
[0124]
The area ratio Ap (= Ap1 / (Ap1 + Ap2)) of the gate lower p layer 14 is a ratio of the area (Ap1) of the gate lower p layer 14 to the area (Ap1 + Ap2) between the p base layers 12. As shown in FIG. 1, when the gate electrode 24, the p-base layer 12, the n + source layer 13, and the p-layer 14 under the gate are respectively formed in a stripe shape, the area between the p-base layers 12 is p-base. It is substantially proportional to the distance Lj between the layers 12. Similarly, the area of the p-layer 14 under the gate is substantially proportional to the length Lgp of the p-layer 14 under the gate. Thus, the area ratio Ap of the p-layer 14 under the gate can be represented by the ratio (Ap = Lgp / Lj) of the distance Lj between the p-base layers 12 and the length Lgp of the p-layer 14 under the gate.
[0125]
As shown in FIG. 29, the maximum net dose Np0 of the p-layer 14 under the gate is substantially proportional to the reciprocal of the area ratio Ap of the p-layer 14 under the gate. Even if the area of the gate lower p layer 14 changes, the total net dose Np of the gate lower p layer 14 that can be depleted does not change much. The net dose Np is the amount of impurities per area. Therefore, as the area of the p-layer 14 under the gate increases, the net dose Np decreases.
[0126]
The relationship between the reciprocal (1 / Ap) of the area ratio Ap of the gate lower p-layer 14 and the maximum net dose Np0 is expressed by the following equation (1).
[0127]
Np0 = 9 × 10 ¹¹ /Ap+1.2×10 ¹² cm ^-2 … (1)
Accordingly, it is desirable that the net dose Np of the p-layer 14 under the gate be smaller than the maximum net dose Np0.
[0128]
The relationship between the net dose Np of the gate lower p layer 14 and the distance Lj between the p base layers 12 is substantially proportional, for example, as shown in FIG. This is because when the distance Lj between the p base layers 12 is reduced, the lines of electric force from the drain are cut off by the p base layers 12. This makes it difficult for the p-layer 14 under the gate to be depleted, and the maximum net dose Np0 decreases.
[0129]
When the above equation (1) is modified by this proportional relation, the following equation (2) is obtained.
[0130]
Np0 / Lj = 1.7 × 10 ^Fifteen / Ap + 2 × 10 ^Fifteen cm ^-3 … (2)
Accordingly, it is desirable that the net dose Np of the p-layer 14 under the gate be smaller than the maximum net dose Np0.
[0131]
FIG. 30 shows the relationship between the depth Xj of the p base layer 12 and the maximum net dose Np0 of the p-layer 14 under the gate in the MOSFET having the structure of the first embodiment. However, here, the dose (Nn) of the n low-resistance layer 11a is set to 4 × 10 ¹² cm ^-2 The case where the area ratio (Ap) of the p layer 14 under the gate is 50% and the interval (Lj) between the p base layers 12 is 2 μm is shown.
[0132]
As shown in FIG. 30, the maximum net dose Np0 of the p layer 14 under the gate is substantially inversely proportional to the depth Xj of the p base layer 12. That is, the maximum net dose Np0 of the p-layer 14 under the gate is substantially proportional to the reciprocal of the depth Xj of the p-base layer 12. This is because when the depth Xj of the p base layer 12 is increased, the lines of electric force from the drain are cut off by the p base layer 12. This makes it difficult for the p-layer 14 under the gate to be depleted, and the maximum net dose Np0 decreases.
[0133]
When the above equation (1) is modified by the inverse proportional relation, the following equation (3) is obtained.
[0134]
Np0 · Xj = 3.6 × 10 ⁸ /Ap+4.8×10 ⁸ cm ^-1 … (3)
Accordingly, it is desirable that the net dose Np of the p-layer 14 under the gate be smaller than the maximum net dose Np0.
[0135]
As shown in FIG. 9, the maximum net dose Np0 of the p layer 14 under the gate is substantially proportional to the distance Lj between the p base layers 12. Therefore, when the above equation (3) is modified by this proportional relationship, the following equation (4) is obtained.
[0136]
Np0 · Xj / Lj = 6 × 10 ¹¹ / Ap + 8 × 10 ¹¹ cm ^-2 … (4)
Accordingly, it is desirable that the net dose Np of the p-layer 14 under the gate be smaller than the maximum net dose Np0.
[0137]
FIG. 31 shows the relationship between the dose Nn of the n-low resistance layer 11a and the maximum net dose Np0 of the p-layer 14 under the gate in the MOSFET having the structure of the first embodiment. However, here, the case where the area ratio (Ap) of the p layer 14 under the gate is 50% and the interval (Lj) between the p base layers 12 is 6 μm is shown.
[0138]
As shown in FIG. 31, the maximum net dose Np0 of the p layer 14 under the gate is substantially proportional to the dose Nn of the n low resistance layer 11a. The concentration of the n low resistance layer 11a increases. Then, since the gate lower p-layer 14 is easily depleted, the maximum net dose Np0 increases.
[0139]
The relationship between the dose Nn of the n-low resistance layer 11a and the maximum net dose Np0 is expressed by the following first-order approximation formula (5).
[0140]
Np0 = 0.37Nn + 1.6 × 10 ¹² cm ^-2 … (5)
When this equation (5) is further transformed into a form including the area ratio Ap of the p-layer 14 under the gate together with the above equation (1), the following equation (6) is obtained.
[0141]
Np0 = 8.4 × 10 ¹¹ /Ap+0.34Nn+0.015Nn/Ap-1.2×10 ¹¹ cm ^-2 … (6)
Accordingly, it is desirable that the net dose Np of the p-layer 14 under the gate be smaller than the maximum net dose Np0.
[0142]
As shown in FIG. 9, the maximum net dose Np0 of the p layer 14 under the gate is substantially proportional to the distance Lj between the p base layers 12. According to this relationship, when the above equation (6) is modified, the following equation (7) is obtained.
[0143]
Np / Lj = 1.4 × 10 ^Fifteen / Ap + 570Nn + 25Nn / Ap-2 × 10 ¹⁴ cm ^-3 … (7)
Accordingly, it is desirable that the net dose Np of the p-layer 14 under the gate be smaller than the maximum net dose Np0.
[0144]
As shown in FIG. 30, the maximum net dose Np0 of the p layer 14 under the gate is substantially inversely proportional to the depth Xj of the p base layer 12. According to this relationship, when the above equation (7) is modified, the following equation (8) is obtained.
[0145]
Np · Xj / Lj = 5.6 × 10 ¹¹ /Ap+0.228Nn+0.01Nn/Ap-8×10 ¹⁰ cm ^-2 … (8)
Accordingly, it is desirable that the net dose Np of the p-layer 14 under the gate be smaller than the maximum net dose Np0.
[0146]
On the other hand, if the net dose Np of the gate lower p layer 14 is small and the gate lower p layer 14 is completely depleted by a low drain voltage, the effect of inserting the gate lower p layer 14 cannot be obtained. That is, if the net dose Np of the p-layer 14 under the gate is too small, as shown in FIG. 8, the switching loss becomes equivalent to that of the conventional MOSFET. Therefore, the net dose amount Np of the p-layer 14 under the gate needs to be an impurity amount that is depleted when a certain high drain voltage is applied. As described above, the impurity amount of the p-layer 14 under the gate has a minimum value suitable for depletion.
[0147]
Assuming that the minimum net dose of the gate lower p-layer 14 is an impurity amount that causes a switching loss equivalent to that of the conventional MOSFET, the minimum net dose of the gate lower p-layer 14 is １ ／ to 1/1 of the maximum net dose. It is about 3 (for example, see FIG. 8).
[0148]
The minimum net dose of the p-layer 14 under the gate is determined by the degree of depletion of the p-layer 14 under the gate, similarly to the case of the maximum net dose. That is, the minimum net dose of the p-layer 14 under the gate depends on the size of each part of the MOSFET and the concentration of each part. From this, it is important to design the impurity amount of the p-layer 14 under the gate in consideration of the dimensions of each part and the concentration of each part of the MOSFET.
[0149]
FIG. 32 shows the relationship between the dimension (area ratio Ap) of the p-layer 14 below the gate and the minimum net dose Np_min of the p-layer 14 below the gate in the MOSFET having the structure of the first embodiment. However, here, the dose (Nn) of the n low-resistance layer 11a is set to 4 × 10 ¹² cm ^-2 , P base layer 12 is set to 6 μm.
[0150]
As shown in FIG. 32, the minimum net dose Np_min of the p-layer 14 under the gate is substantially proportional to the reciprocal of the area ratio Ap of the p-layer 14 under the gate. Similarly to the case of the maximum net dose Np0, the relationship of the minimum net dose Np_min to the reciprocal (1 / Ap) of the area ratio Ap of the gate-underlying p-layer 14 is represented by the following first-order approximation formula (9). become.
[0151]
Np_min = 2.5 × 10 ¹¹ /Ap+5.3×10 ¹¹ cm ^-2 … (9)
Therefore, it is desirable that the net dose Np of the p-layer 14 under the gate is larger than the minimum net dose Np_min.
[0152]
FIG. 33 shows the relationship between the distance Lj between the p base layers 12 and the minimum net dose Np_min of the p-layer 14 under the gate in the MOSFET having the structure of the first embodiment. However, here, the dose (Nn) of the n low-resistance layer 11a is set to 4 × 10 ¹² cm ^-2 The case where the area ratio Ap of the p-layer 14 under the gate is 50% is shown.
[0153]
As in the case of the maximum net dose Np0 described above, the minimum net dose Np_min of the p-layer 14 under the gate is substantially proportional to the distance Lj between the p base layers 12. When the above equation (9) is modified by this proportional relationship, the following equation (10) is obtained.
[0154]
Np_min / Lj = 4.2 × 10 ¹⁴ /Ap+8.8×10 ¹⁴ cm ^-3 … (10)
Therefore, it is desirable that the net dose Np of the p-layer 14 under the gate is larger than the minimum net dose Np_min.
[0155]
FIG. 34 shows the relationship between the depth Xj of the p base layer 12 and the minimum net dose Np_min of the p-layer 14 under the gate in the MOSFET having the structure of the first embodiment. However, here, the dose (Nn) of the n low-resistance layer 11a is set to 4 × 10 ¹² cm ^-2 The case where the area ratio Ap of the p layer 14 under the gate is 50% and the interval Lj between the p base layers 12 is 2 μm is shown.
[0156]
As in the case of the maximum net dose Np0 described above, the minimum net dose Np_min of the p layer 14 under the gate is almost inversely proportional to the depth Xj of the p base layer 12 (the reciprocal of the depth Xj of the p base layer 12). Almost proportional). When the above equation (9) is modified by the inverse proportional relation, the following equation (11) is obtained.
[0157]
Np_min · Xj = 1 × 10 ⁸ /Ap+2.1×10 ⁸ cm ^-1 … (11)
Therefore, it is desirable that the net dose Np of the p-layer 14 under the gate is larger than the minimum net dose Np_min.
[0158]
As shown in FIG. 33, the minimum net dose Np_min of the p-layer 14 under the gate is substantially proportional to the distance Lj between the p-base layers 12. According to this relationship, when the above equation (11) is modified, the following equation (12) is obtained.
[0159]
Np_min · Xj / Lj = 1.7 × 10 ¹¹ /Ap+3.5×10 ¹¹ cm ^-2 … (12)
Accordingly, it is desirable that the net dose Np of the p-layer 14 under the gate is larger than the minimum net dose Np0.
[0160]
FIG. 35 shows the relationship between the dose Nn of the n-low resistance layer 11a and the minimum net dose Np_min of the p-layer 14 under the gate in the MOSFET of the first embodiment. Here, the case where the depth Xj of the p base layer 12 is 4 μm, the area ratio Ap of the p layer 14 under the gate is 50%, and the interval Lj between the p base layers 12 is 6 μm is shown.
[0161]
As shown in FIG. 35, the minimum net dose Np_min of the p layer 14 under the gate is substantially proportional to the dose Nn of the n low resistance layer 11a. The concentration of the n low resistance layer 11a increases. Then, since the gate lower p-layer 14 is easily depleted, the minimum net dose Np_min increases.
[0162]
When the relationship between the dose Nn of the n-low resistance layer 11a and the minimum net dose Np_min is expressed by a first-order approximation, the following expression (13) is obtained.
[0163]
Np_min = 0.2Nn + 3.4 × 10 ¹¹ cm ^-2 … (13)
When this equation (13) is further transformed into a form including the area ratio Ap of the p-layer 14 under the gate together with the above equation (9), the following equation (14) is obtained.
[0164]
Np_min = -4 × 10 ¹⁰ /Ap+0.0375Nn+0.075Nn/Ap+4×10 ¹¹ cm ^-2 … (14)
Therefore, it is desirable that the net dose Np of the p-layer 14 under the gate is larger than the minimum net dose Np_min.
[0165]
As shown in FIG. 33, the minimum net dose Np_min of the p-layer 14 under the gate is substantially proportional to the distance Lj between the p-base layers 12. According to this relationship, when the above equation (14) is modified, the following equation (15) is obtained.
[0166]
Np / Lj = -6.7 × 10 ¹³ /Ap+62.5Nn+125Nn/Ap+6.7×10 ¹⁴ cm ^-3 … (15)
Therefore, it is desirable that the net dose Np of the p-layer 14 under the gate is larger than the minimum net dose Np_min.
[0167]
As shown in FIG. 34, the minimum net dose Np_min of the p layer 14 under the gate is substantially inversely proportional to the depth Xj of the p base layer 12. According to this relationship, when the above equation (15) is modified, the following equation (16) is obtained.
[0168]
Np · Xj / Lj = −2.7 × 10 ¹⁰ /Ap+0.025Nn+0.05Nn/Ap+2.7×10 ¹¹ cm ^-2 … (16)
Therefore, it is desirable that the net dose Np of the p-layer 14 under the gate is larger than the minimum net dose Np_min.
[0169]
(Eleventh embodiment)
FIG. 36 shows a configuration example of a power MOSFET according to an eleventh embodiment of the present invention. The same portions as those of the MOSFET shown in FIG. 18 are denoted by the same reference numerals, and detailed description thereof will be omitted. Here, only different portions will be described.
[0170]
FIG. 36 shows an example in which, in the power MOSFET having the configuration shown in FIG. 18, the gate electrode 24d is configured using the first gate electrode 24A and the second gate electrode 24B having different gate lengths. .
[0171]
That is, the plurality of p base layers 12a as the second semiconductor layers are arranged in a lattice shape (or a staggered shape) on the surface of the n low resistance layer 11a. The gate electrode 24d as a control electrode includes at least one first gate electrode (second control electrode) 24A and at least one second gate electrode (first control electrode) 24B arranged in a lattice. Is configured. First gate electrode 24A has, for example, first gate length (second electrode length) Lg2. The second gate electrode 24B has, for example, a second gate length (first electrode length) Lg1 longer than the first gate length Lg2 of the first gate electrode 24A. The plurality of gate lower p-layers 14b as fifth semiconductor layers are arranged in stripes only between the adjacent p-base layers 12a, at portions corresponding to the second gate electrodes 24B. Have been.
[0172]
The gate-drain capacitance when a low drain voltage is applied is determined by the capacitance of the portion where the gate length is short. In this case, the capacitance between the gate and the drain is small, and high-speed operation is possible.
[0173]
On the other hand, the gate-drain capacitance when a high drain voltage is applied greatly increases. This is because the p-layer 14b under the gate in a portion where the gate length is long is depleted, thereby reducing noise.
[0174]
The power MOSFET having the configuration shown in FIG. 36 can be formed by changing the area of the p-layer under the gate.
[0175]
As shown in FIG. 37, for example, some of the gate lower p-layers 14b-1 are selectively formed in a portion between the adjacent p base layers 12a corresponding to the second gate electrode 24B. To Thus, by changing the area of the p-layer 14b-1 under the gate, it is possible to easily adjust the change in the gate-drain capacitance.
[0176]
At this time, the distance Ljp between the adjacent gate lower p-layers 14b-1 is set to be substantially the same as the distance Lj between the p base layers 12a (Ljp to Lj) corresponding to the first gate electrode 24A. By doing so, it is possible to suppress a decrease in breakdown voltage due to an increase in the interval Ljx between the p base layers 12a corresponding to the second gate electrode 24B.
[0177]
FIG. 38 shows an example in which a part of the gate electrode 24d has a split gate structure in the power MOSFET having the configuration shown in FIG.
[0178]
That is, among the gate electrodes 24d as control electrodes, the first gate electrode 24A-1 having a short gate length has a split gate structure. Thereby, the capacitance between the gate and the drain when a low drain voltage is applied, which is determined by the capacitance of the portion where the gate length is short, can be further reduced, and the speed can be further increased.
[0179]
In addition, not limited to the split gate structure, for example, a terrace gate structure as shown in FIG. 14 can be adopted. Even when the first gate electrode having a short gate length has the terrace gate structure, the same effect as in the case of the split gate structure can be obtained.
[0180]
FIG. 39 shows an example in which the n + source layer 13a is selectively formed in the power MOSFET having the configuration shown in FIG.
[0181]
That is, the n + source layer 13a as the third semiconductor layer is formed only on the surface of the p base layer 12a as the second semiconductor layer corresponding to the first gate electrode 24A having a short gate length. That is, the n + source layer 13a is not formed on the surface of the p base layer 12a corresponding to the second gate electrode 24B having the longer gate length among the gate electrodes 24d as the control electrodes.
[0182]
In a portion where the gate length is long, even when a voltage is applied to the gate electrode 24d and an inversion channel is formed, almost no current flows. This is because the channel path of the long gate length is long and the resistance is high. Therefore, even if there is no n + source layer 13a on the surface of p base layer 12a corresponding to second gate electrode 24B, the on-resistance of the element does not increase.
[0183]
In addition, the area of the n + source layer 13a can be reduced. By doing so, the operation of the parasitic bipolar transistor can be suppressed, and the safe operation area of the element can be increased.
[0184]
Also in the MOSFET having this configuration, a high speed operation is achieved by adopting a split gate structure as shown in FIG. 38 or a terrace gate structure as shown in FIG. 14 for the first gate electrode 24A having a short gate length. Is possible.
[0185]
(Twelfth embodiment)
FIG. 40 shows a configuration example of a power MOSFET according to a twelfth embodiment of the present invention. 1A is a plan view, and FIG. 1B is a cross-sectional view. Further, the same portions as those of the MOSFET shown in FIG. 28 are denoted by the same reference numerals, and detailed description thereof will be omitted. Here, only different portions will be described.
[0186]
FIG. 40 shows an example of the power MOSFET having the configuration shown in FIG. 28, in which the p-layer 14d under the first gate electrode 24A having the gate length Lg2 can be formed in a self-aligned manner. Here, a case where the first and second gate electrodes 24A and 24B are formed in a stripe shape is shown.
[0187]
That is, the MOS cell 52a 'as the first cell includes the second gate electrode (first control electrode) 24B having the gate length Lg1. In the MOS cell 52a ', an n + source layer 13 as a third semiconductor layer is formed on the surface of a p base layer 12 as a second semiconductor layer. Then, between the p base layers 12, a low concentration n layer 11b as a seventh semiconductor layer is provided. This low concentration n layer 11b is provided with an impurity concentration lower than that of the n low resistance layer 11a.
[0188]
On the other hand, the MOS cell 51b as a second cell includes a first gate electrode (second control electrode) 24A having a gate length Lg2 having a shorter gate length than the second gate electrode 24B. In the MOS cell 51b, the n + source layer 13 is formed on the surface of the p base layer 12. Further, between the p base layers 12, a gate lower p layer 14d as a fifth semiconductor layer is provided.
[0189]
As described above, in a MOSFET in which two types of MOS cells 51b and 52a 'having the gate electrodes 24A and 24B having different gate lengths Lg2 and Lg1 are mixed, the p-layer 14d under the gate can be formed by self-alignment. .
[0190]
FIG. 41 shows a manufacturing process of the MOSFET having the configuration shown in FIG.
[0191]
First, ion implantation and diffusion are performed on a substrate having an n− drift layer 11 and an n + drain layer 15 (see FIG. 3A). Then, an n-low resistance layer 11a is formed on the surface of the n- drift layer 11 (see FIG. 3B).
[0192]
Next, a p-type dopant such as boron is ion-implanted into the surface of the n low-resistance layer 11a and annealed. Thus, a low-concentration n-layer 11b is formed on the surface of the n-low-resistance layer 11a (see FIG. 3C).
[0193]
Next, the first and second gate electrodes 24A and 24B are patterned on the surface of the low-concentration n-layer 11b via the gate insulating film 23 (see FIG. 3D). Thereafter, the p base layer 12 is formed by ion implantation and diffusion (see FIG. 3E).
[0194]
At this time, the low-concentration n-layer 11b exists immediately below the first and second gate electrodes 24A and 24B. For this reason, the same effect can be obtained as when the lateral diffusion of the dopant in the p base layer 12 is increased. That is, the dopant of the p base layer 12 extends in the lateral direction only near the surface of the n low resistance layer 11a. The dopant of the p base layer 12 extends substantially equally from both sides of each of the gate electrodes 24A and 24B. Therefore, if the gate length is short, the p base layer 12 is completely p-layered by the dopant of the p base layer 12. As a result, the gate lower p layer 14d can be selectively formed only under the first gate electrode 24A having a shorter gate length.
[0195]
If the gate length is long, the space between the p base layers 12 is not completely formed into a p layer. That is, the gate lower p-layer 14d is not formed sufficiently below the second gate electrode 24B having a longer gate length. As described above, the p-layer 14d under the gate can be formed by self-alignment only under the first gate electrode 24A, and the lithography process for forming the p-layer 14d under the gate can be reduced.
[0196]
In the case where the gate lower p layer 14d is formed by lateral diffusion from the p base layer 12, the distance between the p base layers 12 of the MOS cells 51b is smaller in order to completely form the p layer between the p base layers 12. Is desirable. Conversely, in the MOS cell 52a ', it is desirable that the distance between the p base layers 12 is wide. In order to surely form the two MOS cells 51b and 52a 'having different patterns, it is desirable to change the interval between the p base layers 12 at least twice.
[0197]
In the case of a MOSFET formed by such a process, the gate-drain capacitance when a low drain voltage is applied is determined by the capacitance of the MOS cell 52a 'having the low-concentration n-layer 11b. Further, the gate-drain capacitance when a high drain voltage is applied increases due to the capacitance of the MOS cell 51b having the p-layer 14d under the gate added to the capacitance of the MOS cell 52a '. This realizes low noise.
[0198]
Further, in the MOSFET having such a configuration, the ratio of the MOS cell 51b to the number of cells of the entire device or the area of the p-layer 14d under the gate to the area under the gate of the entire device (for example, the surface area of the low concentration n-layer 11b) Increase the percentage. By doing so, the increase in gate-drain capacitance when a high drain voltage is applied can be increased. As a result, the effect of reducing noise can be further improved. Incidentally, the ratio of the MOS cell 51b or the ratio of the area of the p-layer 14d under the gate is desirably 30% or more.
[0199]
It is not necessary to provide the lower gate p layer 14d provided in the MOS cell 51b so as to completely cover the area under the gate electrode 24A. As long as the depleted p-layer is formed, the gate-drain capacitance increases due to the increase in the drain voltage. Therefore, substantially the same effect as the case where the space between the p base layers 12 is completely formed into a p layer, that is, an effect of reducing noise can be obtained.
[0200]
The net dose of the p-layer 14d under the gate is desirably set to the value described above.
[0201]
Further, in the power MOSFET having the configuration shown in FIG. 40, it is also possible to selectively form n + source layer 13.
[0202]
That is, in the case of the power MOSFETs shown in FIGS. 42A and 42B, the n + source layer 13 as the third semiconductor layer is, for example, a second semiconductor corresponding to the second gate electrode 24B having a long gate length. It is formed only on the surface of p base layer 12 as a layer. That is, the n + source layer 13 is not formed on the surface of the p base layer 12 corresponding to the first gate electrode 24A having the short gate length. 1A is a plan view, and FIG. 1B is a cross-sectional view.
[0203]
In the MOS cell 51b, the area under the first gate electrode 24A is completely covered by the p-layer 14d under the gate. Therefore, no current flows through MOS cell 51b. Therefore, even if the n + source layer 13 is not provided on the surface of the p base layer 12 corresponding to the first gate electrode 24A, the on resistance of the device is not affected.
[0204]
In addition, the operation of the parasitic bipolar transistor can be suppressed, so that the safe operation area of the element can be increased.
[0205]
FIG. 43 shows another configuration example of the power MOSFET according to the twelfth embodiment of the present invention. Here, an example is shown in which, in a power MOSFET in which the p-layer under the gate can be formed in a self-aligned manner, first and second gate electrodes 24A and 24B having different gate lengths are formed in a lattice shape.
[0206]
That is, the plurality of p base layers 12a as the second semiconductor layers are arranged in a lattice shape (or a staggered shape) on the surface of the n low resistance layer 11a. Further, an n + source layer 13a as a third semiconductor layer is formed on the surface of the p base layer 12a. The gate electrode 24d as a control electrode includes at least one first gate electrode (second control electrode) 24A and at least one second gate electrode (first control electrode) 24B arranged in a lattice. Is configured. First gate electrode 24A has, for example, first gate length (second electrode length) Lg2. The second gate electrode 24B has, for example, a second gate length (first electrode length) Lg1 longer than the first gate length Lg2 of the first gate electrode 24A.
[0207]
The plurality of gate lower p-layers 14d as the fifth semiconductor layers are formed by self-alignment only between the adjacent p base layers 12a and only at portions corresponding to the first gate electrodes 24A. . Further, a low-concentration n-layer 11b as a seventh semiconductor layer is formed between adjacent p-base layers 12a at a portion corresponding to the second gate electrode 24B.
[0208]
Even in such a configuration, the p-layer 14d under the gate can be formed by self-alignment. Therefore, cost reduction is possible.
[0209]
FIG. 44 shows an example in which the n + source layer 13a is selectively formed in the power MOSFET having the configuration shown in FIG.
[0210]
That is, the n + source layer 13a as the third semiconductor layer is formed only on the surface of the p base layer 12a as the second semiconductor layer corresponding to the second gate electrode 24B having a long gate length. That is, the n + source layer 13a is not formed on the surface of the p base layer 12a corresponding to the first gate electrode 24A having a short gate length among the gate electrodes 24d as the control electrodes.
[0211]
In the portion of the first gate electrode 24A, the space between the p base layers 12a is completely covered by the gate lower p layer 14d. Therefore, no current flows through this portion. Therefore, even if there is no n + source layer 13a on the surface of p base layer 12a corresponding to first gate electrode 24A, there is no effect on the on-resistance of the device.
[0212]
In addition, the operation of the parasitic bipolar transistor can be suppressed, so that the safe operation area of the element can be increased.
[0213]
FIG. 45 shows another example of the power MOSFET according to the twelfth embodiment in which gate electrodes are arranged in stripes. 2A is a plan view showing a gate pattern, FIG. 2B is a cross-sectional view taken along line 45B-45B of FIG. 2A, and FIG. 2C is FIG. It is sectional drawing which follows the 45C-45C line of FIG.
[0214]
In the case of this example, the plurality of gate electrodes 24e as control electrodes are each provided in a stripe shape. The plurality of gate electrodes 24e each include at least one first gate electrode unit (second control electrode unit) 24A ′ having a first gate length (second electrode length) Lg2, and It is configured to include at least one second gate electrode portion (first control electrode portion) 24B 'having a second gate length (first electrode length) Lg1 longer than one gate length Lg2. .
[0215]
FIG. 46 shows another example of the power MOSFET according to the twelfth embodiment in which gate electrodes are arranged in a lattice. 2A is a plan view showing a gate pattern, FIG. 2B is a cross-sectional view taken along line 46B-46B of FIG. 2A, and FIG. 2C is FIG. It is sectional drawing which follows the 46C-46C line.
[0216]
In the case of this example, the plurality of gate electrodes 24f as the control electrodes each include at least one first gate electrode unit (second control electrode unit) having a first gate length (second electrode length) Lg2. 24A 'and at least one second gate electrode portion (first control electrode portion) 24B' having a second gate length (first electrode length) Lg1 longer than the first gate length Lg2. Including. The plurality of gate electrodes 24f are configured by assembling the first gate electrode portions 24A 'with each other in a lattice shape.
[0219]
FIG. 47 shows still another example in which the gate electrodes are arranged in a grid in the power MOSFET according to the twelfth embodiment. 2A is a plan view showing a gate pattern, FIG. 2B is a cross-sectional view taken along line 47B-47B of FIG. 2A, and FIG. 2C is FIG. FIG. 47 is a sectional view taken along the line 47C-47C of FIG.
[0218]
In the case of this example, the plurality of gate electrodes 24g as the control electrodes each include at least one first gate electrode unit (second control electrode unit) having a first gate length (second electrode length) Lg2. 24A 'and at least one second gate electrode portion (first control electrode portion) 24B' having a second gate length (first electrode length) Lg1 longer than the first gate length Lg2. Including. The plurality of gate electrodes 24g have a configuration in which the first gate electrode portions 24A 'are mutually assembled in a lattice.
[0219]
As shown in FIGS. 45 to 47, the gate length of each of the gate electrodes 24e, 24f, and 24g is locally changed. In such a case, the area of the gate lower p-layer 14d can be freely changed in any case by changing the ratio of the gate width of the first gate electrode portion 24A 'having a short gate length. It is.
[0220]
In each of the power MOSFETs shown in FIGS. 45 to 47, as in the case of the power MOSFETs shown in FIGS. 42 and 44, the p-base corresponding to the first gate electrode portion 24A 'having a short gate length is used. The formation of the n + source layer 13 on the surface of the layer 12 may be omitted.
[0221]
(Thirteenth embodiment)
FIG. 48 shows a configuration example of a power MOSFET according to the thirteenth embodiment of the present invention. The same portions as those of the MOSFET shown in FIG. 40 are denoted by the same reference numerals, and detailed description thereof will be omitted. Here, only different portions will be described.
[0222]
FIG. 48 shows an example of a power MOSFET in which the gate lower p layer can be formed in a self-aligned manner, in which the gate lower p layer 14d is formed below the second gate electrode 24B having a somewhat longer gate length. Is shown in
[0223]
That is, the plurality of p base layers 12 as the second semiconductor layers are selectively arranged on the surface of the n low resistance layer 11a. Further, an n + source layer 13 as a third semiconductor layer is formed on the surface of the p base layer 12. Further, a low-concentration n-layer 11b as a seventh semiconductor layer is provided on the surface of the n-low-resistance layer 11a between adjacent p-base layers 12.
[0224]
Among the control electrodes, for example, the gate electrode 24B has a somewhat long gate length (for example, Lg1).
[0225]
In the case of this example, the plurality of p-layers 14d under the gate as the fifth semiconductor layer are each formed between adjacent p-base layers 12 by self-alignment (lateral diffusion of p-type dopant). Each of the gate lower p layers 14 d is connected to each of the p base layers 12. Each of the gate lower p-layers 14d is formed so as not to completely cover between the adjacent p base layers 12.
[0226]
As described above, in a MOSFET in which the p-layer under the gate can be formed by self-alignment, for example, as shown in FIG. It is possible to form the p layer 14d so as not to cover. As a result, the gate lower p-layer 14d increases the gate-drain capacitance due to an increase in the drain voltage. Therefore, substantially the same effect as the case where the space between the p base layers 12 is completely formed into a p layer, that is, an effect of reducing noise can be obtained.
[0227]
When the dose of the p-type dopant is increased, it becomes easier to form the p-layer 14d under the gate. However, in this case, the specific resistance of the low-concentration n-layer 11b is increased, and the on-resistance is increased.
[0228]
Therefore, it is necessary to optimally design the dose of the dopant for forming the p-layer 14d under the gate and the low-concentration n-layer 11b and the gate length of the gate electrode 24B (the interval between the p-base layers 12). That is, in order to suppress an increase in on-resistance, the interval between the p base layers 12 is set to be as large as the depth of the p base layers 12. Further, it is desirable that the interval between the gate lower p-layers 14d is about half of that.
[0229]
Note that, as shown in the present embodiment, a MOSFET which can form a p-layer 14d so as not to completely cover between the p-base layers 12 under the gate electrode 24B having a somewhat longer gate length is shown in FIG. The present invention can also be applied to MOSFETs other than the MOSFET shown in FIG. For example, the present invention can be similarly applied to the MOSFET in which the formation of the n + source layer 13 on the surface portion of the p base layer 12 corresponding to the first gate electrode 24A having a short gate length is omitted as shown in FIG. .
[0230]
As shown in FIGS. 43 and 44, in a MOSFET having a configuration in which the p base layers 12a are arranged in a lattice pattern, for example, the p layer 14d is provided between the p base layer 12a under the gate electrode 24A having a short gate length. Can be formed so as to completely cover the p base layer 12a under the gate electrode 24B having a long gate length.
[0231]
Furthermore, the twelfth embodiment is not limited to the MOSFET in which two types of MOS cells having different gate lengths of the gate electrodes are mixed, as shown, but includes, for example, only one type of MOS cell having a somewhat longer gate length. It is also applicable to MOSFETs.
[0232]
(14th embodiment)
FIG. 49 shows a configuration example of a power MOSFET according to a fourteenth embodiment of the present invention. The same parts as those of the MOSFET shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. Here, only different portions will be described.
[0233]
In FIG. 49, a plurality of p base layers 12a as second semiconductor layers are arranged in a lattice shape (or a staggered shape) on the surface of the n low resistance layer 11a. The plurality of gate lower p-layers 14a as fifth semiconductor layers are respectively arranged between four adjacent p-base layers 12a.
[0234]
The plurality of n + source layers 13a as the third semiconductor layers are formed in a ring shape on the surface of each of the p base layers 12a. A rectangular source electrode 22a as a first main electrode is provided at a portion corresponding to each of the p base layer 12a and the n + source layer 13a.
[0235]
The gate electrode 24h as a control electrode is provided in a lattice shape at a portion other than the source electrodes 22a. The gate electrode 24h has a split gate structure in which openings 24ha are provided in portions not corresponding to the gate lower p layer 14a, that is, portions corresponding to the n low resistance layer 11a between the gate lower p layers 14a. It is configured.
[0236]
According to the MOSFET having the structure of the present embodiment, it is possible to reduce the gate-drain capacitance when a low drain voltage is applied. Thereby, the speed can be increased.
[0237]
In the MOSFET having this configuration, a similar effect can be expected by adopting not only the split gate structure but also a terrace gate structure for the gate electrode as shown in FIG. 14, for example.
[0238]
(Fifteenth embodiment)
FIG. 50 shows a configuration example of a power MOSFET according to a fifteenth embodiment of the present invention. The same parts as those of the MOSFET shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. Here, only different portions will be described.
[0239]
In FIG. 50, a plurality of p base layers 12a as second semiconductor layers are arranged in a lattice (or staggered) on the surface of n low resistance layer 11a. The plurality of gate lower p-layers 14a as fifth semiconductor layers are respectively arranged between four adjacent p-base layers 12a.
[0240]
Further, a plurality of n + source layers 13a as third semiconductor layers are selectively formed on the surface of each of the p base layers 12a. For example, the n + source layer 13a is provided only on the surface of the p base layer 12a except for the portions corresponding to the respective gate lower p layers 14a. That is, the n + source layer 13a is not formed in a portion of the surface of the p base layer 12a corresponding to the p layer 14a under the gate.
[0241]
A rectangular source electrode 22a as a first main electrode is provided at a portion corresponding to each of the p base layer 12a and the n + source layer 13a. Further, the gate electrode 24i as a control electrode is provided in a lattice shape at a portion other than the source electrodes 22a.
[0242]
According to such a MOSFET having the structure of the present embodiment, it is possible to suppress the operation of the parasitic bipolar transistor without changing the on-resistance. Thereby, the safe operation area of the element can be increased.
[0243]
In the MOSFET having this configuration, a split gate structure as shown in FIG. 49 (or a terrace gate structure as shown in FIG. 14) can be employed for the gate electrode 24i. In that case, it is possible to realize a MOSFET which is high speed and has a large safe operation area of the element.
[0244]
(Sixteenth embodiment)
FIG. 51 shows a configuration example of a power MOSFET according to a sixteenth embodiment of the present invention. The same portions as those of the MOSFET shown in FIG. 49 are denoted by the same reference numerals, and detailed description thereof will be omitted. Here, only different portions will be described.
[0245]
FIG. 51 shows an example in which the p-layer under the gate is connected to each other in the MOSFET having the configuration shown in FIG.
[0246]
That is, the plurality of p base layers 12a as the second semiconductor layers are arranged in a lattice shape (or a staggered shape) on the surface of the n low resistance layer 11a. The plurality of gate lower p-layers 14a 'as fifth semiconductor layers are respectively arranged between four adjacent p-base layers 12a. The plurality of p-layers 14a 'under the gate are locally disposed between two adjacent p-base layers 12a, respectively. The plurality of n + source layers 13a as the third semiconductor layers are formed in a ring shape on the surface of each of the p base layers 12a.
[0247]
A rectangular source electrode 22a as a first main electrode is provided at a portion corresponding to each of the p base layer 12a and the n + source layer 13a. Further, the gate electrode 24i as a control electrode is provided in a lattice shape at a portion other than the source electrodes 22a.
[0248]
With such a configuration, the MOSFET of the present embodiment can form the p-layer 14a 'under the gate without crushing the MOS channel. As a result, it is possible to suppress an increase in on-resistance.
[0249]
As a MOSFET having this configuration, for example, as shown in FIG. 52, a MOSFET having a structure in which gate electrodes are arranged in a stripe shape can be similarly applied.
[0250]
That is, the plurality of p base layers 12 as the second semiconductor layers are arranged in a stripe shape on the surface of the n low resistance layer 11a. The p-layer 14 'under the gate as the fifth semiconductor layer is disposed between two adjacent p-base layers 12, respectively. Further, the gate lower p-layers 14 ′ arranged between two adjacent p base layers 12 are locally connected to the respective two adjacent p base layers 12. At least one n + source layer 13 as a third semiconductor layer is formed in a stripe shape on the surface of each of the p base layers 12.
[0251]
A stripe-shaped source electrode 22 as a first main electrode is provided at a portion corresponding to each of the p base layer 12 and the n + source layer 13. Further, the gate electrode 24 as a control electrode is provided in a stripe shape via a gate insulating film 23 at a portion other than the source electrodes 22.
[0252]
Also in the MOSFET having such a structure, the area of the p-layer 14 'under the gate connected to the MOS channel can be reduced, and the decrease in the effective gate width of the MOS channel can be suppressed. As a result, an increase in on-resistance can be suppressed.
[0253]
In addition, as the MOSFET having the configuration according to the present embodiment described above, for example, as described in the eleventh and twelfth embodiments, the present invention can be similarly applied to MOSFETs each having a gate electrode having a different gate length.
[0254]
In each of the above embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type has been described. The present invention is not limited to this, and in any of the embodiments, the first conductivity type can be p-type and the second conductivity type can be n-type.
[0255]
In each embodiment, the case where Si is used has been described. However, the present invention is not limited to this, and can be applied to a compound semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or aluminum nitride (AlN), or an element using diamond.
[0256]
Furthermore, each embodiment is not limited to the case where the present invention is applied to a MOSFET having a super junction structure or a vertical switching element. For example, the present invention can be similarly applied to a MOS or MIS gate element such as a lateral MOSFET or IGBT.
[0257]
In addition, the present invention is not limited to the above (each) embodiment, and can be variously modified in an implementation stage without departing from the gist thereof. Furthermore, the (each) embodiment includes various stages of the invention, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some components are deleted from all the components shown in the (each) embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and When (at least one of) the effects described in the effect column is obtained, a configuration from which the constituent requirements are deleted can be extracted as an invention.
[0258]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to provide an insulated gate semiconductor device capable of suppressing switching noise at high speed without using an external circuit.
[Brief description of the drawings]
FIG. 1 is a perspective view showing a configuration example of a vertical power MOSFET according to a first embodiment of the present invention, with a part thereof cut away.
FIG. 2 is a characteristic diagram showing the dependency of the gate-drain capacitance on the source-drain voltage in the MOSFET shown in FIG. 1 in comparison with a MOSFET having a conventional structure.
FIG. 3 is a characteristic diagram showing a drain voltage waveform and a drain current waveform at the time of turn-off in the MOSFET shown in FIG. 1 in comparison with a MOSFET having a conventional structure.
FIG. 4 is a perspective view showing another configuration example of the vertical power MOSFET according to the first embodiment of the present invention, with a part thereof being cut away;
FIG. 5 is an exemplary perspective view showing a further configuration example of the vertical power MOSFET according to the first embodiment of the present invention, with a part thereof cut away;
FIG. 6 is a characteristic diagram showing a turn-off waveform of the MOSFET according to the first embodiment of the present invention in comparison with a MOSFET having a conventional structure.
FIG. 7 is a characteristic diagram showing a change in turn-off loss when the area of the p-layer under the gate is changed in the MOSFET according to the first embodiment of the present invention.
FIG. 8 is a characteristic diagram showing a change in turn-off loss when the net dose of the p-layer under the gate is changed in the MOSFET according to the first embodiment of the present invention.
FIG. 9 is a characteristic diagram showing a relationship between an interval between p base layers and a maximum net dose of a p layer under a gate in the MOSFET according to the first embodiment of the present invention.
FIG. 10 is a sectional view of a main part showing a configuration example of a power MOSFET according to a second embodiment of the present invention;
FIG. 11 is a sectional view of a main part showing a configuration example of a power MOSFET according to a third embodiment of the present invention.
FIG. 12 is a sectional view of a main part showing another configuration example of the power MOSFET according to the third embodiment of the present invention.
FIG. 13 is a sectional view of a main part showing a configuration example of a power MOSFET according to a fourth embodiment of the present invention.
FIG. 14 is a sectional view of a main part showing another configuration example of the power MOSFET according to the fourth embodiment of the present invention.
FIG. 15 is an exemplary perspective view of a configuration example of a power MOSFET according to a fifth embodiment of the present invention, with a part thereof cut away;
FIG. 16 is a perspective view showing a configuration example of a power MOSFET according to a sixth embodiment of the present invention, with a part thereof cut away.
FIG. 17 is a perspective view showing another configuration example of the power MOSFET according to the sixth embodiment of the present invention, with a part thereof cut away.
FIG. 18 is a perspective view showing still another configuration example of the power MOSFET according to the sixth embodiment of the present invention, with a part thereof being cut away.
FIG. 19 is a plan view showing an example of an arrangement pattern of a p-layer under a gate in a power MOSFET according to a sixth embodiment of the present invention.
FIG. 20 is a plan view showing another example of the arrangement pattern of the p-layer below the gate in the power MOSFET according to the sixth embodiment of the present invention.
FIG. 21 is a plan view showing still another example of the arrangement pattern of the p-layer under the gate in the power MOSFET according to the sixth embodiment of the present invention.
FIG. 22 is a cross-sectional view of a main part showing an example when applied to an IGBT according to a seventh embodiment of the present invention.
FIG. 23 is a sectional view of a main part showing another configuration example of the IGBT according to the seventh embodiment of the present invention;
FIG. 24 is a sectional view of a main part showing still another configuration example of the IGBT according to the seventh embodiment of the present invention;
FIG. 25 is a sectional view of a main part showing a configuration example of a power MOSFET according to an eighth embodiment of the present invention;
FIG. 26 is a cross-sectional view of a main part showing an example in which the invention is applied to an IGBT according to the eighth embodiment of the present invention.
FIG. 27 is a sectional view of a main part showing a configuration example of a power MOSFET according to a ninth embodiment of the present invention;
FIG. 28 is a sectional view of a main part showing another configuration example of the power MOSFET according to the ninth embodiment of the present invention;
FIG. 29 is a characteristic diagram showing a relationship between the area ratio of the p-layer under the gate and the maximum net dose of the p-layer under the gate in the MOSFET having the configuration shown in FIG. 1 according to the tenth embodiment of the present invention;
30 is a characteristic diagram showing a relationship between the depth of a p base layer and the maximum net dose of a p layer under a gate in the MOSFET having the configuration shown in FIG. 1;
FIG. 31 is a characteristic diagram showing a relationship between a dose of an n low resistance layer and a maximum net dose of a p layer under a gate in the MOSFET having the configuration shown in FIG. 1;
FIG. 32 is a characteristic diagram showing the relationship between the area ratio of the p-layer under the gate and the minimum net dose of the p-layer under the gate in the MOSFET having the configuration shown in FIG. 1;
FIG. 33 is a characteristic diagram showing the relationship between the distance between the p base layers and the minimum net dose of the p layer under the gate in the MOSFET having the configuration shown in FIG. 1;
FIG. 34 is a characteristic diagram showing a relationship between the depth of the p base layer and the minimum net dose of the p layer under the gate in the MOSFET having the configuration shown in FIG. 1;
FIG. 35 is a characteristic diagram showing a relationship between a dose of an n low resistance layer and a minimum net dose of a p layer under a gate in the MOSFET having the configuration shown in FIG. 1;
FIG. 36 is a plan view showing a configuration example of a power MOSFET according to an eleventh embodiment of the present invention, with a part of a gate electrode being cut away.
FIG. 37 is a plan view showing another configuration example of the power MOSFET according to the eleventh embodiment of the present invention, with a part of a gate electrode being cut away.
FIG. 38 is a plan view showing still another configuration example of the power MOSFET according to the eleventh embodiment of the present invention, with a part of a gate electrode being cut away.
FIG. 39 is a plan view showing still another configuration example of the power MOSFET according to the eleventh embodiment of the present invention, with a part of a gate electrode being cut away.
FIG. 40 is a configuration diagram showing an example of a power MOSFET according to a twelfth embodiment of the present invention.
FIG. 41 is a process cross-sectional view shown for explaining the manufacturing process of the power MOSFET shown in FIG. 40;
FIG. 42 is a configuration diagram showing another example of the power MOSFET according to the twelfth embodiment of the present invention.
FIG. 43 is a plan view showing still another configuration example of the power MOSFET according to the twelfth embodiment of the present invention, with a part of a gate electrode being cut away.
FIG. 44 is a plan view showing still another configuration example of the power MOSFET according to the twelfth embodiment of the present invention, with a part of a gate electrode being cut away.
FIG. 45 is a configuration diagram showing another example of the power MOSFET according to the twelfth embodiment of the present invention in which gate electrodes are arranged in a stripe shape.
FIG. 46 is a configuration diagram showing another example in the case where gate electrodes are arranged in a grid in the power MOSFET according to the twelfth embodiment of the present invention.
FIG. 47 is a configuration diagram showing still another example in the case where gate electrodes are arranged in a lattice in the power MOSFET according to the twelfth embodiment of the present invention.
FIG. 48 is a sectional view showing a configuration example of a power MOSFET according to a thirteenth embodiment of the present invention;
FIG. 49 is a plan view showing a configuration example of a power MOSFET according to a fourteenth embodiment of the present invention, with a part of a gate electrode being cut away.
FIG. 50 is a plan view showing a configuration example of a power MOSFET according to a fifteenth embodiment of the present invention, with a part of a gate electrode cut away.
FIG. 51 is a plan view showing a configuration example of a power MOSFET according to a sixteenth embodiment of the present invention, with a part of a gate electrode being cut away;
FIG. 52 is a perspective view showing another configuration example of the power MOSFET according to the sixteenth embodiment of the present invention, with a part thereof cut away;
[Explanation of symbols]
11 ... n-drift layer
11a ... n low resistance layer
11b: Low concentration n-layer
12, 12a ... p base layer
13, 13a... N + source layer
14, 14 ', 14a, 14a', 14b, 14b-1, 14c, 14d ... p layer (p layer under gate)
14A, 14B, 14B '... p layer
15 ... n + drain layer
21 ... Drain electrode
22, 22a, 22A ... source electrode
23, 23a, 23d ... gate insulating film
24, 24d, 24e, 24f, 24g, 24h, 24i, 24A, 24A-1, 24B ... gate electrode (planar gate structure)
24ha ... opening
24A ': First gate electrode portion
24B ': second gate electrode portion
24a: Gate electrode (trench gate structure)
24b gate electrode (split gate structure)
24c gate electrode (terrace gate structure)
31 ... p + drain layer
32 ... n + buffer layer
41 ... Dummy cell
42 ... Normal cell
51, 51a, 51b ... MOS cell (with p-layer)
52, 52a, 52a '... MOS cell (without p layer)
Id: drain current
Vds: drain voltage
Eoff: Turn-off loss
Lg1... Second gate length
Lg2: First gate length

Claims (75)

A first semiconductor layer of a first conductivity type;
A plurality of second conductivity type second semiconductor layers selectively formed on a surface portion of the first conductivity type first semiconductor layer;
At least one third semiconductor layer of the first conductivity type formed on a surface portion of each of the plurality of second semiconductor layers of the second conductivity type;
A plurality of first main electrodes respectively connected to the plurality of second conductive type second semiconductor layers and the at least one first conductive type third semiconductor layer;
A fourth semiconductor layer formed on the back surface side of the first semiconductor layer of the first conductivity type;
A second main electrode connected to the fourth semiconductor layer;
Gate insulation is provided on each of the surfaces of the plurality of second semiconductor layers of the second conductivity type, the at least one third semiconductor layer of the first conductivity type, and the first semiconductor layer of the first conductivity type. A control electrode formed through the membrane,
A plurality of second conductive type second semiconductor layers provided on the first conductive type first semiconductor layer and connected to at least one of the plurality of second conductive type second semiconductor layers; And at least one fifth semiconductor layer of the second conductivity type having a low impurity concentration. The at least one fifth semiconductor layer of the second conductivity type may be provided on a surface portion of the first semiconductor layer of the first conductivity type between the plurality of second semiconductor layers of the second conductivity type. The insulated gate semiconductor device according to claim 1, wherein: The plurality of second semiconductor layers of the second conductivity type are arranged in a stripe shape,
The insulation according to claim 2, wherein the at least one fifth semiconductor layer of the second conductivity type is provided along a first direction along the second semiconductor layer of the second conductivity type. Gate type semiconductor device. The plurality of second semiconductor layers of the second conductivity type are arranged in a stripe shape,
The at least one fifth semiconductor layer of the second conductivity type is provided along a second direction orthogonal to a first direction along the second semiconductor layer of the second conductivity type. The insulated gate semiconductor device according to claim 2. The insulated gate semiconductor device according to claim 1, wherein the at least one fifth semiconductor layer of the second conductivity type is embedded in the first semiconductor layer of the first conductivity type. The insulated gate semiconductor device according to claim 1, wherein the control electrode has a planar structure. The insulated gate semiconductor device according to claim 6, wherein the control electrode has a split gate structure. The insulated gate semiconductor device according to claim 6, wherein the control electrode has a terrace gate structure. The insulated gate semiconductor device according to claim 1, wherein the control electrode has a trench structure. The control electrode has a trench type structure,
The insulated gate semiconductor device according to claim 9, wherein the at least one fifth semiconductor layer of the second conductivity type is provided along a bottom surface and at least one side surface of the control electrode. The plurality of second semiconductor layers of the second conductivity type are arranged in a lattice,
The insulated gate type according to claim 1, wherein the at least one fifth semiconductor layer of the second conductivity type is provided in a rectangular shape between the second semiconductor layers of the second conductivity type. Semiconductor device. The insulated gate semiconductor device according to claim 11, wherein the at least one fifth semiconductor layer of the second conductivity type is provided between two adjacent second semiconductor layers of the second conductivity type. . The insulated gate semiconductor device according to claim 11, wherein the at least one fifth semiconductor layer of the second conductivity type is provided between four adjacent second semiconductor layers of the second conductivity type. . 14. The insulated gate semiconductor according to claim 13, wherein an interval between adjacent second semiconductor layers of the second conductivity type is smaller than an interval between adjacent second semiconductor layers of the second conductivity type. apparatus. The plurality of second semiconductor layers of the second conductivity type are arranged in a lattice,
The insulated gate semiconductor device according to claim 1, wherein the at least one fifth semiconductor layer of the second conductivity type is provided in a stripe shape between the second semiconductor layers of the second conductivity type. . The plurality of second semiconductor layers of the second conductivity type are arranged in a lattice,
The insulated gate according to claim 1, wherein the at least one fifth semiconductor layer of the second conductivity type is provided so as to surround some of the second semiconductor layers of the second conductivity type. Type semiconductor device. 17. The insulated gate semiconductor device according to claim 16, wherein the at least one fifth semiconductor layer of the second conductivity type is provided in a staggered manner. 17. The insulated gate semiconductor device according to claim 16, wherein the at least one fifth semiconductor layer of the second conductivity type is provided in a stripe shape. The insulated gate semiconductor device according to claim 18, wherein the at least one fifth semiconductor layer of the second conductivity type is provided in one direction. 19. The insulated gate semiconductor device according to claim 18, wherein the at least one fifth semiconductor layer of the second conductivity type is provided in two directions. The insulated gate semiconductor device according to claim 1, wherein the fourth semiconductor layer is formed of a first conductivity type semiconductor layer. 2. The insulated gate semiconductor device according to claim 1, wherein said fourth semiconductor layer comprises a second conductivity type semiconductor layer. The first conductive type sixth semiconductor layer is further provided between the fourth semiconductor layer and the (first) first conductive type first semiconductor layer. 23. The insulated gate semiconductor device according to 22. The at least one fifth semiconductor layer of the second conductivity type has a surface area of 30% of the surface area of the first semiconductor layer of the first conductivity type between the adjacent second semiconductor layers of the second conductivity type. %. The insulated gate semiconductor device according to claim 1, wherein The at least one fifth semiconductor layer of the second conductivity type has an effective impurity amount of:
1 × 10 ¹² to 3.2 × 10 ¹² cm ⁻²
2. The insulated gate semiconductor device according to claim 1, wherein The ratio of the effective impurity amount (Np) of the at least one fifth semiconductor layer of the second conductivity type to the distance (Lj) between adjacent second semiconductor layers of the second conductivity type is:
Np / Lj <2 × 10 ¹⁵ cm ⁻³
2. The insulated gate semiconductor device according to claim 1, wherein The product of the effective impurity amount (Np) of the at least one fifth semiconductor layer of the second conductivity type, the distance (Lj) between adjacent second semiconductor layers of the second conductivity type, and the junction depth (Xj) thereof. And the ratio
Np / (Lj · Xj) <5 × 10 ¹⁸ cm ⁻⁴
2. The insulated gate semiconductor device according to claim 1, wherein A first semiconductor layer of a first conductivity type;
A plurality of second conductivity type second semiconductor layers selectively formed on a surface portion of the first conductivity type first semiconductor layer;
At least one third semiconductor layer of the first conductivity type formed on a surface portion of each of the plurality of second semiconductor layers of the second conductivity type;
A plurality of first main electrodes respectively connected to the plurality of second conductive type second semiconductor layers and the at least one first conductive type third semiconductor layer;
A fourth semiconductor layer formed on the back surface side of the first semiconductor layer of the first conductivity type;
A second main electrode connected to the fourth semiconductor layer;
Gate insulation is provided on each of the surfaces of the plurality of second semiconductor layers of the second conductivity type, the at least one third semiconductor layer of the first conductivity type, and the first semiconductor layer of the first conductivity type. A control electrode formed through the membrane,
A plurality of second conductive type second semiconductor layers provided on the first conductive type first semiconductor layer and connected to at least one of the plurality of second conductive type second semiconductor layers; At least one fifth semiconductor layer of the second conductivity type having a low impurity concentration,
When a voltage is applied to the second main electrode, the capacitance between the control electrode and the second main electrode is configured to decrease at a low voltage and to be constant or increase at a high voltage. An insulated gate semiconductor device comprising: A first semiconductor layer of a first conductivity type;
A plurality of second conductivity type second semiconductor layers selectively formed on a surface portion of the first conductivity type first semiconductor layer;
At least one third semiconductor layer of the first conductivity type formed on a surface portion of each of the plurality of second semiconductor layers of the second conductivity type;
A plurality of first main electrodes respectively connected to the plurality of second conductive type second semiconductor layers and the at least one first conductive type third semiconductor layer;
A fourth semiconductor layer formed on the back surface side of the first semiconductor layer of the first conductivity type;
A second main electrode connected to the fourth semiconductor layer;
Gate insulation is provided on each of the surfaces of the plurality of second semiconductor layers of the second conductivity type, the at least one third semiconductor layer of the first conductivity type, and the first semiconductor layer of the first conductivity type. A control electrode formed through the membrane,
A plurality of second conductive type second semiconductor layers provided on the first conductive type first semiconductor layer and connected to at least one of the plurality of second conductive type second semiconductor layers; At least one fifth semiconductor layer of the second conductivity type having a low impurity concentration,
When the voltage applied to the second main electrode is 1/3 to 2/3 of the rated voltage, the capacity between the control electrode and the second main electrode starts to increase. An insulated gate semiconductor device, characterized in that: A first semiconductor layer of a first conductivity type;
A plurality of second conductivity type second semiconductor layers selectively formed on a surface portion of the first conductivity type first semiconductor layer;
At least one third semiconductor layer of the first conductivity type formed on a surface portion of each of the plurality of second semiconductor layers of the second conductivity type;
A plurality of first main electrodes respectively connected to the plurality of second conductive type second semiconductor layers and the at least one first conductive type third semiconductor layer;
A fourth semiconductor layer formed on the back surface side of the first semiconductor layer of the first conductivity type;
A second main electrode connected to the fourth semiconductor layer;
Gate insulation is provided on each of the surfaces of the plurality of second semiconductor layers of the second conductivity type, the at least one third semiconductor layer of the first conductivity type, and the first semiconductor layer of the first conductivity type. A control electrode formed through the membrane,
A plurality of second conductive type second semiconductor layers provided on the first conductive type first semiconductor layer and connected to at least one of the plurality of second conductive type second semiconductor layers; At least one fifth semiconductor layer of the second conductivity type having a low impurity concentration,
When the voltage applied to the second main electrode is 1/3 to 2/3 of the rated voltage, the at least one fifth semiconductor layer of the second conductivity type is completely depleted. An insulated gate semiconductor device. A plurality of second conductivity type second semiconductor layers selectively formed on a surface portion of the first conductivity type first semiconductor layer, and a plurality of second conductivity type second semiconductor layers; Connected to at least one third semiconductor layer of the first conductivity type respectively formed on the plurality of second semiconductor layers of the second conductivity type and the at least one third semiconductor layer of the first conductivity type. A first cell including at least a plurality of first main electrodes,
A plurality of second conductivity type second semiconductor layers selectively formed on a surface portion of the first conductivity type first semiconductor layer, and a plurality of second conductivity type second semiconductor layers provided between adjacent second conductivity type second semiconductor layers. A second cell including at least a plurality of second conductive type fifth semiconductor layers having a lower impurity concentration than the plurality of second conductive type second semiconductor layers. Insulated gate semiconductor device. The second cell is provided between adjacent second semiconductor layers of the second conductivity type and completely covers a surface portion of the first semiconductor layer of the first conductivity type. 32. The insulated gate semiconductor device according to claim 31, further comprising a conductive fifth semiconductor layer. The second cell further includes a first main electrode connected to the plurality of second conductive type second semiconductor layers, or a surface portion of the plurality of second conductive type second semiconductor layers. At least one third semiconductor layer of the first conductivity type respectively formed on the plurality of second semiconductor layers of the second conductivity type and the at least one third semiconductor layer of the first conductivity type. 32. The insulated gate semiconductor device according to claim 31, further comprising: a first main electrode connected thereto. The control electrode length of the second cell or the distance between adjacent second conductive type second semiconductor layers is equal to the control electrode length of the first cell or the adjacent second conductive type second semiconductor layer. 32. The insulated gate semiconductor device according to claim 31, wherein the distance is wider than the interval of. The semiconductor device further includes a first conductive type low resistance layer provided between the adjacent second conductive type second semiconductor layers with a higher impurity concentration than the first conductive type first semiconductor layer. ,
The effective impurity amount (Np) of the at least one fifth semiconductor layer of the second conductivity type; the surface area (Ap1) of the at least one fifth semiconductor layer of the second conductivity type; The relationship between the surface area (Ap2) of the resistive layer and the ratio (Ap = Ap1 / (Ap1 + Ap2)) to the sum (Ap1 + Ap2) of the surface area (Ap1) of the at least one fifth semiconductor layer of the second conductivity type is as follows:
0 <Np <9 × 10 ¹¹ /Ap+1.2×10 ¹² cm ⁻²
2. The insulated gate semiconductor device according to claim 1, wherein The effective impurity amount (Np) of the at least one fifth semiconductor layer of the second conductivity type; the surface area (Ap1) of the at least one fifth semiconductor layer of the second conductivity type; The relationship between the surface area (Ap2) of the resistive layer and the ratio (Ap = Ap1 / (Ap1 + Ap2)) to the sum (Ap1 + Ap2) of the surface area (Ap1) of the at least one fifth semiconductor layer of the second conductivity type is as follows:
Np> 2.5 × 10 ¹¹ /Ap+5.3×10 ¹¹ cm ⁻²
36. The insulated gate semiconductor device according to claim 35, wherein: The semiconductor device further includes a first conductive type low resistance layer provided between the adjacent second conductive type second semiconductor layers with a higher impurity concentration than the first conductive type first semiconductor layer. ,
The effective impurity amount (Np) of the at least one fifth semiconductor layer of the second conductivity type; the surface area (Ap1) of the at least one fifth semiconductor layer of the second conductivity type; The ratio (Ap = Ap1 / (Ap1 + Ap2)) between the surface area (Ap2) of the resistance layer and the sum (Ap1 + Ap2) of the surface area (Ap1) of the fifth semiconductor layer of the at least one second conductivity type, and The relationship with the distance (Lj) between the two conductive type second semiconductor layers is as follows:
0 <Np <Np / Lj <1.7 × 10 ¹⁵ / Ap + 2 × 10 ¹⁵ cm ⁻³
2. The insulated gate semiconductor device according to claim 1, wherein The effective impurity amount (Np) of the at least one fifth semiconductor layer of the second conductivity type; the surface area (Ap1) of the at least one fifth semiconductor layer of the second conductivity type; The ratio (Ap = Ap1 / (Ap1 + Ap2)) between the surface area (Ap2) of the resistance layer and the sum (Ap1 + Ap2) of the surface area (Ap1) of the fifth semiconductor layer of the at least one second conductivity type, and The relationship with the distance (Lj) between the two conductive type second semiconductor layers is as follows:
Np / Lj> 4.2 × 10 ¹⁴ /Ap+8.8×10 ¹⁴ cm ⁻³
The insulated gate semiconductor device according to claim 37, wherein: The semiconductor device further includes a first conductive type low resistance layer provided between the adjacent second conductive type second semiconductor layers with a higher impurity concentration than the first conductive type first semiconductor layer. ,
The effective impurity amount (Np) of the at least one fifth semiconductor layer of the second conductivity type; the surface area (Ap1) of the at least one fifth semiconductor layer of the second conductivity type; The ratio (Ap = Ap1 / (Ap1 + Ap2)) between the surface area (Ap2) of the resistance layer and the sum (Ap1 + Ap2) of the surface area (Ap1) of the fifth semiconductor layer of the at least one second conductivity type, and The relationship with the junction depth (Xj) of the two-conductivity-type second semiconductor layer is as follows:
0 <Np <Np.Xj <3.6 × 10 ⁸ /Ap+4.8×10 ⁸ cm ⁻¹
2. The insulated gate semiconductor device according to claim 1, wherein The effective impurity amount (Np) of the at least one fifth semiconductor layer of the second conductivity type; the surface area (Ap1) of the at least one fifth semiconductor layer of the second conductivity type; The ratio (Ap = Ap1 / (Ap1 + Ap2)) between the surface area (Ap2) of the resistance layer and the sum (Ap1 + Ap2) of the surface area (Ap1) of the fifth semiconductor layer of the at least one second conductivity type, and The relationship with the junction depth (Xj) of the two-conductivity-type second semiconductor layer is as follows:
Np · Xj> 1 × 10 ⁸ /Ap+2.1×10 ⁸ cm ⁻¹
40. The insulated gate semiconductor device according to claim 39, wherein: The semiconductor device further includes a first conductive type low resistance layer provided between the adjacent second conductive type second semiconductor layers with a higher impurity concentration than the first conductive type first semiconductor layer. ,
The effective impurity amount (Np) of the at least one fifth semiconductor layer of the second conductivity type; the surface area (Ap1) of the at least one fifth semiconductor layer of the second conductivity type; The ratio (Ap = Ap1 / (Ap1 + Ap2)) between the surface area (Ap2) of the resistance layer and the sum (Ap1 + Ap2) of the surface area (Ap1) of the fifth semiconductor layer of the at least one second conductivity type, and The relationship between the distance (Lj) between the two semiconductor layers of the two conductivity type and the junction depth (Xj) between the adjacent second semiconductor layers of the second conductivity type is as follows:
0 <Np <Np.Xj / Lj <6 × 10 ¹¹ / Ap + 8 × 10 ¹¹ cm ⁻²
2. The insulated gate semiconductor device according to claim 1, wherein The effective impurity amount (Np) of the at least one fifth semiconductor layer of the second conductivity type; the surface area (Ap1) of the at least one fifth semiconductor layer of the second conductivity type; The ratio (Ap = Ap1 / (Ap1 + Ap2)) between the surface area (Ap2) of the resistance layer and the sum (Ap1 + Ap2) of the surface area (Ap1) of the fifth semiconductor layer of the at least one second conductivity type, and The relationship between the distance (Lj) between the two semiconductor layers of the two conductivity type and the junction depth (Xj) between the adjacent second semiconductor layers of the second conductivity type is as follows:
Np.Xj / Lj> 1.7 × 10 ¹¹ /Ap+3.5×10 ¹¹ cm ⁻²
42. The insulated gate semiconductor device according to claim 41, wherein: The semiconductor device further includes a first conductive type low resistance layer provided between the adjacent second conductive type second semiconductor layers with a higher impurity concentration than the first conductive type first semiconductor layer. ,
The effective impurity amount (Np) of the at least one fifth semiconductor layer of the second conductivity type; the effective impurity amount (Nn) of the low resistance layer of the first conductivity type; The sum (Ap1 + Ap2) of the surface area (Ap1) of the fifth semiconductor layer, the surface area (Ap2) of the low resistance layer of the first conductivity type, and the surface area (Ap1) of the at least one fifth semiconductor layer of the second conductivity type. With the ratio (Ap = Ap1 / (Ap1 + Ap2))
0 <Np <Np <8.4 × 10 ¹¹ /Ap+0.34 Nn + 0.015 Nn / Ap−1.2 × 10 ¹¹ cm ⁻²
2. The insulated gate semiconductor device according to claim 1, wherein The effective impurity amount (Np) of the at least one fifth semiconductor layer of the second conductivity type; the effective impurity amount (Nn) of the low resistance layer of the first conductivity type; The sum (Ap1 + Ap2) of the surface area (Ap1) of the fifth semiconductor layer, the surface area (Ap2) of the low resistance layer of the first conductivity type, and the surface area (Ap1) of the at least one fifth semiconductor layer of the second conductivity type. With the ratio (Ap = Ap1 / (Ap1 + Ap2))
Np> −4 × 10 ¹⁰ /Ap+0.0375 Nn + 0.075 Nn / Ap + 4 × 10 ¹¹ cm ⁻²
44. The insulated gate semiconductor device according to claim 43, wherein: The semiconductor device further includes a first conductive type low resistance layer provided between the adjacent second conductive type second semiconductor layers with a higher impurity concentration than the first conductive type first semiconductor layer. ,
The effective impurity amount (Np) of the at least one fifth semiconductor layer of the second conductivity type; the effective impurity amount (Nn) of the low resistance layer of the first conductivity type; The sum (Ap1 + Ap2) of the surface area (Ap1) of the fifth semiconductor layer, the surface area (Ap2) of the low resistance layer of the first conductivity type, and the surface area (Ap1) of the at least one fifth semiconductor layer of the second conductivity type. The relationship between the ratio (Ap = Ap1 / (Ap1 + Ap2)) and the distance (Lj) between adjacent second semiconductor layers of the second conductivity type is as follows:
0 <Np <Np / Lj <1.4 × 10 ¹⁵ / Ap + 570 Nn + 25 Nn / Ap−2 × 10 ¹⁴ cm ⁻³
2. The insulated gate semiconductor device according to claim 1, wherein The effective impurity amount (Np) of the at least one fifth semiconductor layer of the second conductivity type; the effective impurity amount (Nn) of the low resistance layer of the first conductivity type; The sum (Ap1 + Ap2) of the surface area (Ap1) of the fifth semiconductor layer, the surface area (Ap2) of the low resistance layer of the first conductivity type, and the surface area (Ap1) of the at least one fifth semiconductor layer of the second conductivity type. The relationship between the ratio (Ap = Ap1 / (Ap1 + Ap2)) and the distance (Lj) between adjacent second semiconductor layers of the second conductivity type is as follows:
Np / Lj> −6.7 × 10 ¹³ /Ap+62.5 Nn + 125 Nn / Ap + 6.7 × 10 ¹⁴ cm ⁻³
The insulated gate semiconductor device according to claim 45, wherein: The semiconductor device further includes a first conductive type low resistance layer provided between the adjacent second conductive type second semiconductor layers with a higher impurity concentration than the first conductive type first semiconductor layer. ,
The effective impurity amount (Np) of the at least one fifth semiconductor layer of the second conductivity type; the effective impurity amount (Nn) of the low resistance layer of the first conductivity type; The sum (Ap1 + Ap2) of the surface area (Ap1) of the fifth semiconductor layer, the surface area (Ap2) of the low resistance layer of the first conductivity type, and the surface area (Ap1) of the at least one fifth semiconductor layer of the second conductivity type. (Ap = Ap1 / (Ap1 + Ap2)), the distance (Lj) between adjacent second semiconductor layers of the second conductivity type, and the junction depth of adjacent second semiconductor layers of the second conductivity type. The relationship with (Xj) is
0 <Np <Np.Xj / Lj <5.6 × 10 ¹¹ /Ap+0.228 Nn + 0.01 Nn / Ap− ⁸ × 10 ¹⁰ cm ⁻²
2. The insulated gate semiconductor device according to claim 1, wherein The effective impurity amount (Np) of the at least one fifth semiconductor layer of the second conductivity type; the effective impurity amount (Nn) of the low resistance layer of the first conductivity type; The sum (Ap1 + Ap2) of the surface area (Ap1) of the fifth semiconductor layer, the surface area (Ap2) of the low resistance layer of the first conductivity type, and the surface area (Ap1) of the at least one fifth semiconductor layer of the second conductivity type. (Ap = Ap1 / (Ap1 + Ap2)), the distance (Lj) between adjacent second semiconductor layers of the second conductivity type, and the junction depth of adjacent second semiconductor layers of the second conductivity type. The relationship with (Xj) is
Np · Xj / Lj> −2.7 × 10 ¹⁰ /Ap+0.025Nn+0.05Nn/Ap+2.7×10 ¹¹ cm ⁻²
48. The insulated gate semiconductor device according to claim 47, wherein: The plurality of second semiconductor layers of the second conductivity type are arranged in a lattice,
2. The insulated gate semiconductor device according to claim 1, wherein the control electrode is provided between the plurality of second conductivity type second semiconductor layers. 3. 50. The control electrode of claim 49, wherein the control electrodes include at least one first control electrode having a first electrode length and at least one second control electrode having a second electrode length. Insulated gate type semiconductor device. The control electrode includes at least one first control electrode having a first electrode length, and at least one second control electrode having a second electrode length;
Only between the plurality of second conductive type second semiconductor layers corresponding to at least one first control electrode having the first electrode length, the at least one second conductive type fifth semiconductor layer is provided. 2. The insulated gate semiconductor device according to claim 1, wherein a semiconductor layer is provided. The insulated gate semiconductor device according to claim 51, wherein a first electrode length of the first control electrode is longer than a second electrode length of the second control electrode. 52. The method of claim 51, wherein the at least one fifth semiconductor layer of the second conductivity type is selectively provided between the corresponding plurality of second semiconductor layers of the second conductivity type. Insulated gate type semiconductor device. The insulated gate semiconductor device according to claim 50, wherein at least one second control electrode having the second electrode length among the control electrodes has a split gate structure or a terrace gate structure. The control electrode includes at least one first control electrode having a first electrode length, and at least one second control electrode having a second electrode length;
The at least one second conductive type fifth semiconductor layer is provided only between the plurality of second conductive type second semiconductor layers corresponding to at least one first control electrode having the first electrode length. A semiconductor layer of
The at least one third conductive type third semiconductor layer is provided only on surface portions of the plurality of second conductive type second semiconductor layers corresponding to at least one second control electrode having the second electrode length. 2. The insulated gate semiconductor device according to claim 1, wherein a semiconductor layer is provided. The control electrode includes at least one first control electrode having a first electrode length, and at least one second control electrode having a second electrode length;
The at least one fifth conductive type fifth semiconductor layer is provided only between the plurality of second conductive type second semiconductor layers corresponding to at least one second control electrode having the second electrode length. 2. The insulated gate semiconductor device according to claim 1, wherein a semiconductor layer is provided. The semiconductor device further includes a first conductive type low resistance layer provided between the adjacent second conductive type second semiconductor layers with a higher impurity concentration than the first conductive type first semiconductor layer. ,
The control electrode includes at least one first control electrode having a first electrode length, and at least one second control electrode having a second electrode length;
The at least one fifth conductive type fifth semiconductor layer is provided only between the plurality of second conductive type second semiconductor layers corresponding to at least one second control electrode having the second electrode length. A semiconductor layer of
Between the plurality of second-conductivity-type second semiconductor layers corresponding to at least one first control electrode having the first electrode length, a distance between the plurality of second-conductivity-type second semiconductor layers is lower than that of the first-conductivity-type low-resistance layer. 56. The insulated gate semiconductor device according to claim 55, wherein a seventh semiconductor layer of a first conductivity type having a low impurity concentration is provided. The control electrode includes at least one first control electrode having a first electrode length, and at least one second control electrode having a second electrode length;
The at least one fifth conductive type fifth semiconductor layer is provided only between the plurality of second conductive type second semiconductor layers corresponding to at least one second control electrode having the second electrode length. A semiconductor layer of
The at least one third conductive type third semiconductor layer is provided only on surface portions of the plurality of second conductive type second semiconductor layers corresponding to at least one first control electrode having the first electrode length. 56. The insulated gate semiconductor device according to claim 55, wherein a semiconductor layer is provided. The control electrode is characterized in that at least one first control electrode having the first electrode length and at least one second control electrode having the second electrode length are provided in a stripe shape. 51. The insulated gate semiconductor device according to claim 50. The control electrode is characterized in that at least one first control electrode having the first electrode length and at least one second control electrode having the second electrode length are provided in a grid pattern. 51. The insulated gate semiconductor device according to claim 50. The control electrode includes a plurality of control electrodes including at least one first control electrode unit having a first electrode length and at least one second control electrode unit having a second electrode length. 50. The insulated gate semiconductor device according to claim 49, wherein: 62. The insulated gate semiconductor device according to claim 61, wherein the plurality of control electrodes are provided in a stripe shape. 62. The insulated gate semiconductor device according to claim 61, wherein the plurality of control electrodes are provided in a lattice shape. The plurality of control electrodes include at least one first control electrode unit having a first electrode length, and at least one second control electrode unit having a second electrode length,
64. The insulated gate semiconductor device according to claim 63, wherein at least one second control electrode unit having the second electrode length is assembled in a lattice shape. A plurality of second conductivity type second semiconductor layers selectively formed on a surface portion of the first conductivity type first semiconductor layer, and a plurality of second conductivity type second semiconductor layers; Connected to at least one third semiconductor layer of the first conductivity type respectively formed on the plurality of second semiconductor layers of the second conductivity type and the at least one third semiconductor layer of the first conductivity type. A first cell including at least a plurality of first main electrodes,
A plurality of second conductivity type second semiconductor layers selectively formed on a surface portion of the first conductivity type first semiconductor layer, and a plurality of second conductivity type second semiconductor layers provided between adjacent second conductivity type second semiconductor layers. A second cell including at least a second conductive type fifth semiconductor layer having a lower impurity concentration than the plurality of second conductive type second semiconductor layers.
The first conductive type first semiconductor layer is provided with a first conductive type low resistance layer having a higher impurity concentration than the first conductive type first semiconductor layer,
Between the adjacent second semiconductor layers of the second conductivity type of the first cell, a seventh semiconductor layer of the first conductivity type having a lower impurity concentration than the low resistance layer of the first conductivity type is provided. An insulated gate semiconductor device, which is provided. The control electrode length of the second cell or the distance between adjacent second conductive type second semiconductor layers is equal to the control electrode length of the first cell or the adjacent second conductive type second semiconductor layer. 66. The insulated gate semiconductor device according to claim 65, wherein the distance is smaller than the interval of. The first cell further includes a fifth of the second conductivity type having an impurity concentration lower than that of the second semiconductor layer of the second conductivity type between the adjacent second semiconductor layers of the second conductivity type. 67. The insulated gate semiconductor device according to claim 66, wherein a semiconductor layer is provided. The second cell further includes a first main electrode connected to the plurality of second conductive type second semiconductor layers, or a surface portion of the plurality of second conductive type second semiconductor layers. At least one third semiconductor layer of the first conductivity type respectively formed on the plurality of second semiconductor layers of the second conductivity type and the at least one third semiconductor layer of the first conductivity type. 66. The insulated gate semiconductor device according to claim 65, further comprising: a first main electrode connected thereto. A first semiconductor layer of a first conductivity type;
A first conductivity type low-resistance layer provided on the first conductivity type first semiconductor layer and having a higher impurity concentration than the first conductivity type first semiconductor layer;
A plurality of second conductive type second semiconductor layers selectively formed on the surface of the first conductive type low resistance layer;
At least one third semiconductor layer of the first conductivity type formed on a surface portion of each of the plurality of second semiconductor layers of the second conductivity type;
A plurality of first main electrodes respectively connected to the plurality of second conductive type second semiconductor layers and the at least one first conductive type third semiconductor layer;
A fourth semiconductor layer formed on the back surface side of the first semiconductor layer of the first conductivity type;
A second main electrode connected to the fourth semiconductor layer;
A gate insulating film is formed on each surface of the plurality of second semiconductor layers of the second conductivity type, the at least one third semiconductor layer of the first conductivity type, and the surface of the low resistance layer of the first conductivity type. A control electrode formed through
A lower impurity concentration than the plurality of second conductive type second semiconductor layers, which is provided on the first conductive type low resistance layer and is connected to the adjacent second conductive type second semiconductor layers, respectively. And a plurality of fifth semiconductor layers of the second conductivity type having:
A seventh semiconductor layer of the first conductivity type having a lower impurity concentration than the low resistance layer of the first conductivity type is provided between the plurality of fifth semiconductor layers of the second conductivity type. Insulated gate type semiconductor device. A first semiconductor layer of a first conductivity type;
A first conductivity type low-resistance layer provided on the first conductivity type first semiconductor layer and having a higher impurity concentration than the first conductivity type first semiconductor layer;
A plurality of second conductive type second semiconductor layers selectively formed on the surface of the first conductive type low resistance layer;
At least one third semiconductor layer of the first conductivity type formed on a surface portion of each of the plurality of second semiconductor layers of the second conductivity type;
A plurality of first main electrodes respectively connected to the plurality of second conductive type second semiconductor layers and the at least one first conductive type third semiconductor layer;
A fourth semiconductor layer formed on the back surface side of the first semiconductor layer of the first conductivity type;
A second main electrode connected to the fourth semiconductor layer;
A gate insulating film is formed on each surface of the plurality of second semiconductor layers of the second conductivity type, the at least one third semiconductor layer of the first conductivity type, and the surface of the low resistance layer of the first conductivity type. A control electrode formed through
Lower than the plurality of second conductive type second semiconductor layers provided on the first conductive type low resistance layer and connected to the plurality of adjacent second conductive type second semiconductor layers, respectively. An insulated gate semiconductor device, comprising: a plurality of second conductivity type fifth semiconductor layers having an impurity concentration. The plurality of second semiconductor layers of the second conductivity type are arranged in a lattice,
71. The insulated gate semiconductor according to claim 70, wherein the plurality of fifth semiconductor layers of the second conductivity type are respectively provided between four adjacent second semiconductor layers of the second conductivity type. apparatus. 72. The insulated gate semiconductor device according to claim 71, wherein each of the plurality of fifth semiconductor layers of the second conductivity type is locally connected. The at least one first conductive type is provided only on a surface portion of the plurality of second conductive type second semiconductor layers except for a portion to which the plurality of second conductive type fifth semiconductor layers are connected. 71. The insulated gate semiconductor device according to claim 70, wherein a third semiconductor layer is provided. 71. The insulated gate semiconductor according to claim 70, wherein the control electrodes are arranged in a lattice pattern, and a portion corresponding to the low resistance layer of the first conductivity type has a split gate structure or a terrace gate structure. apparatus. The plurality of second semiconductor layers of the second conductivity type are arranged in a stripe shape,
71. The insulated gate type according to claim 70, wherein the plurality of second conductive type fifth semiconductor layers are locally connected to the plurality of second conductive type second semiconductor layers. Semiconductor device.

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