JP2007230173A - Pulse width modulating device and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate a pixel clock capable of correcting an error or nonlinear error of a scanning speed with high accuracy and to perform high resolution pulse width modulation with high reproducibility of gradation based on the pixel clock. <P>SOLUTION: This pulse width modulating device is equipped with a data converting means 301 that converts density data designating a density of a dot of image data to pulse width data by a unit of a phase difference T/P according to a predetermined conversion rule depending on a frequency of a pixel clock, an edge time computing means 304 for computing rising time and falling time of a pulse width modulation signal according to the pulse width data based on rising time of the pixel clock, and pulse width modulation signal output means 305 and 306 for generating the pulse width modulation signal according to the rising time and the falling time of the pulse width modulation signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a pulse width modulation device and an image forming apparatus.

  FIG. 26 is a diagram showing a general schematic configuration of an image forming apparatus such as a laser printer or a digital copying machine. In FIG. 26, the laser light emitted from the semiconductor laser unit 1009 is scanned by a rotating polygon mirror 1003 to form a light spot on a photoconductor 1001 that is a medium to be scanned through a scanning lens 1002, and the photoconductor 1001 is exposed to form an electrostatic latent image. At this time, the photodetector 1004 detects the scanning beam for each line.

  The phase synchronization circuit 1006 receives the clock from the clock generation circuit 1005, generates an image clock (pixel clock) synchronized in phase for each line based on the output signal of the photo detector 1004, and outputs the image processing unit. 1007 and the laser driving circuit 1008. Further, the semiconductor laser unit 1009 controls the light emission time of the semiconductor laser according to the image data generated by the image processing unit 1007 and the image clock whose phase is set for each line by the phase synchronization circuit 1006, thereby Controls the formation of an electrostatic latent image on 1001.

  In such a scanning optical system, unevenness in scanning speed fluctuates the image and causes deterioration in image quality. In particular, in a color image, the main scanning dot position shift of each color occurs, resulting in color shift, resulting in deterioration of color reproducibility and resolution. Therefore, in order to obtain high quality image quality, it is essential to correct the scanning speed unevenness.

  The scanning speed unevenness (error) is roughly classified as follows. The main factors are described for each.

(1) An error for each surface (each scanning line) of the polygon mirror (hereinafter, referred to as an error for each surface as appropriate).
Factors that cause such scanning speed unevenness include variations in the distance from the rotation axis of the deflecting and reflecting surface of a deflector such as a polygon mirror (that is, eccentricity of the polygon mirror) and surface accuracy of each surface of the polygon mirror. is there. This type of error is an error having a periodicity of several lines (for example, the number of lines corresponding to the number of polygon mirror surfaces).

(2) Error due to scanning average speed fluctuation.
The average scanning speed is the average of the scanning speeds of each surface of the polygon mirror. The causes of such scanning speed unevenness include fluctuations in the rotation speed of the polygon mirror and various environmental fluctuations such as temperature, humidity, and vibration. Due to fluctuations in the scanning optical system. In addition, the oscillation speed of the semiconductor laser, which is a light source, changes due to temperature fluctuations, etc., so that the scanning speed varies due to chromatic aberration of the scanning optical system. This type of error is a relatively gradual variation.

(3) Error for each light source.
For example, scanning speed unevenness occurs in a multi-beam optical system that includes a plurality of light sources such as a semiconductor laser array and simultaneously scans a plurality of light beams with a common scanning optical system. The main factor is the difference in the oscillation wavelength of each light source, and the scanning speed fluctuates due to the chromatic aberration of the scanning optical system. Since the fluctuation of the oscillation wavelength differs for each light source, the error (2) described above may differ for each light source. In addition, the scanning speed of a plurality of beams varies depending on the assembly accuracy of a plurality of light sources.

(4) Error for each scanning optical system.
In the case of an image forming apparatus that includes a plurality of photoconductors / scanning optical systems and is compatible with multiple colors, a difference in scanning speed between the scanning optical systems greatly affects image quality. The main factors include manufacturing accuracy and assembly accuracy of each component of the scanning optical system, deformation due to changes over time, and the like. Moreover, since the light source is also different, the error (3) described above also occurs. This error is different from the scanning average speed itself, and the above errors (1) and (2) occur individually. Some image forming apparatuses commonly use some units of the scanning optical system. However, since the optical paths from the respective light sources to the scanned medium (photosensitive member) are different, this is also included in (4). .

  As a method for correcting these scanning speed errors, there is a method of changing the frequency of the pixel clock in accordance with the scanning speed, as disclosed in Patent Document 1, for example. This is to control the frequency of the oscillator that generates the pixel clock (so-called PLL (Phase Locked Loop) control) so that the count of the pixel clock from the start to the end of the scan becomes a predetermined value.

  However, the conventional pixel clock frequency control method has the following problems. That is, since the frequency of the reference clock for phase comparison is one line frequency, it is very low (several thousand to several tens of thousands) with respect to the oscillating pixel clock, and sufficient PLL open loop gain cannot be secured. Therefore, sufficient control accuracy cannot be obtained. Also, it is vulnerable to disturbances, and the clock frequency fluctuates, so that a highly accurate clock cannot be generated. Furthermore, when the error for each surface is corrected as in Patent Document 1, the control voltage of the VCO that is the oscillator is changed for each scan, so that it takes time until the clock frequency oscillates stably. End up.

  As another method for correcting an error in scanning speed, for example, as disclosed in Patent Document 2, there is a method of performing phase control of a pixel clock based on a generated high frequency clock. This controls the phase of the pixel clock so that the count number of the high-frequency clock from the start to the end of scanning becomes a predetermined value. Since this high-frequency clock can be generated with a high-accuracy clock such as a crystal oscillator as a reference clock, a high-accuracy clock is obtained, and the phase control of the pixel clock is performed based on this clock, so the control accuracy of the pixel clock is also good. Things can be generated.

  However, since the error of the scanning speed is corrected by appropriately performing the phase control of the pixel clock, it is necessary to generate phase control data for this one scanning line, and further, local by the phase change of the pixel clock. In order to reduce the deviation, that is, to generate a highly accurate pixel clock, it is necessary to perform phase control with high resolution, and therefore phase control data increases. Therefore, it is not easy to generate this phase control data at high speed and with high accuracy. In addition, when applied to a device that corrects errors for each surface, it is necessary to generate phase control data for each surface, and in order to perform highly accurate correction, it is necessary to generate and store a large amount of phase control data. It was not easy to realize. Further, the scanning speed fluctuates during scanning of one line due to the accuracy error and assembly error of each unit of the scanning optical system.

(5) Non-linearity error.
FIG. 27A is a diagram showing an example of the nonlinear error of the scanning speed in one line. Here, the horizontal axis x is the position of the scanning line, and the vertical axis is the scanning speed V (x) with respect to the position x. A one-dot chain line Vavg is an average value of the scanning speed in one line. When such scanning speed fluctuation occurs, the deviation Δ from the ideal value scanned at a constant speed is as shown in FIG. This means a dot position shift and causes image degradation. In FIG. 27, when scanning from the position X2 to the direction X1, the deviation Δ from the ideal value is as indicated by a dotted line. Therefore, particularly when scanning is performed bidirectionally in such a scanning optical system that causes asymmetric positional deviation with respect to the scanning center, color misregistration increases and image degradation becomes serious. Furthermore, the error amount and distribution of this non-linearity error may vary from surface to surface depending on the surface accuracy of each surface of the polygon mirror. In addition, this error is different for each scanning optical system.

As a method for correcting such a scanning speed non-linearity error, for example, as disclosed in Patent Document 3, there is a method of correcting by correcting the frequency of the pixel clock corresponding to the position in the scanning line. However, since the generation of the center frequency of the pixel clock is the same as in the prior art, the accurate clock cannot be generated as described above, and sufficient correction cannot be made.
JP 2001-183600 A JP 2004-262101 A JP 2000-152001 A

  The present invention has been made in view of the above problems, and generates a pixel clock capable of correcting a scanning speed error and a non-linearity error caused by various factors with high accuracy, and gradation reproducibility based on the pixel clock. An object of the present invention is to provide a pulse width modulation apparatus and an image forming apparatus capable of performing high-resolution and high-resolution pulse width modulation.

  In order to achieve the above object, the invention according to claim 1 is a pulse width modulation device for generating a pulse width modulation signal obtained by performing pulse width modulation according to image data based on a pixel clock generated by a pixel clock generation device. The pixel clock generator includes a multi-phase clock generator for generating a multi-phase clock having a phase number P and a phase difference of T / P by a period T, and first and second synchronization signals to be input. Comparing means for detecting a time interval, comparing the detected time interval with a target value, and outputting an error from the target value, and calculating a set value of the pixel clock frequency according to the error output from the comparing means A frequency calculation means for outputting a frequency instruction signal indicating the pixel clock frequency according to the set value of the calculated pixel clock frequency, and a phase difference T / P of the multiphase clock Counting means for calculating the rise time and fall time of the pixel clock by counting the number of the unit times according to the frequency instruction signal, and the counting means based on the multiphase clock. Pixel clock output means for generating a pixel clock according to a rise time and a fall time of the pixel clock, and the pulse width modulation device converts density data indicating the density of dots of the image data to a frequency of the pixel clock. In accordance with the pulse width data based on the rise time of the pixel clock calculated by the counting means and data conversion means for converting the pulse width data in units of the phase difference T / P according to a predetermined conversion rule according to Edge for calculating rise time and fall time of the pulse width modulation signal And a pulse width modulation signal output means for generating a pulse width modulation signal according to the rise time and fall time of the pulse width modulation signal with the multiphase clock as a reference. .

  According to a second aspect of the present invention, in the pulse width modulation device according to the first aspect, the image data includes phase data indicating a dot phase, and the edge time calculating means is the counting means. The rise time and fall time of the pulse width modulation signal are calculated according to the pulse width data and the phase data based on the rise time of the pixel clock calculated by the above.

  According to a third aspect of the present invention, in the pulse width modulation device according to the first or second aspect, the data conversion means sets the predetermined value when the density data is full density as the conversion rule. It converts the pixel clock control target value Mtarget in units of phase difference T / P to generate a full density signal indicating full density, and the edge time calculation means In consideration of this, the rise time and fall time of the pulse width modulation signal are calculated.

  According to a fourth aspect of the present invention, there is provided the pulse width modulation device according to any one of the first to third aspects, wherein the pulse width modulation device and the predetermined conversion rule in the data conversion unit are used. A pulse width data correction unit that corrects the pulse width data to data corresponding to the frequency of the pixel clock at the time of conversion according to a difference in frequency of the pixel clock at the time of conversion; The rising time and falling time of the pulse width modulation signal are calculated according to the pulse width data corrected by the pulse width data correcting means.

  According to a fifth aspect of the present invention, in the pulse width modulation device according to the fourth aspect, the frequency calculation means of the pixel clock generation device divides a period between the first and second synchronization signals into a plurality of periods. Corresponding to a region, frequency modulation data generating means for generating frequency modulation data that is difference data from the set value of the pixel clock frequency, and adding the set value of the pixel clock frequency and the frequency modulated data, Frequency modulation means for outputting a frequency instruction signal for instructing the pixel clock frequency according to the added value, and the pulse width data correction means corrects data according to the frequency modulation data.

  According to a sixth aspect of the present invention, a pixel is formed by driving a light source with a pulse width modulation signal generated by a pulse width modulation device and scanning a light beam output from the light source onto a scanned medium to form an image. In the apparatus, the pulse width modulation device includes a multiphase clock generating means for generating a multiphase clock having a number of phases P, the phases of which are shifted by a phase difference T / P with a period T, and first and second input A comparison unit that detects a time interval of the synchronization signal, compares the detected time interval with a target value, and outputs an error from the target value, and a set value of the pixel clock frequency according to the error output from the comparison unit Frequency calculation means for outputting a frequency instruction signal for indicating the pixel clock frequency in accordance with the calculated set value of the pixel clock frequency, and the phase difference T / P of the multiphase clock as a unit time, Counting means for calculating the rise time and fall time of the pixel clock by counting the number of unit times according to the frequency instruction signal, and density data for instructing the dot density of the image data according to the frequency of the pixel clock. Data conversion means for converting to pulse width data in units of the phase difference T / P according to a predetermined conversion rule, and the pulse width modulation according to the pulse width data based on the rise time of the pixel clock calculated by the counting means Edge time calculation means for calculating the rise time and fall time of the signal, and pulse width modulation for generating a pulse width modulation signal according to the rise time and fall time of the pulse width modulation signal with the multiphase clock as a reference And a signal output means.

  According to a seventh aspect of the present invention, pixel formation is performed in which a light source is driven by a pulse width modulation signal generated by a pulse width modulation device, and a light beam output from the light source is scanned onto a scanned medium to form an image. In the apparatus, the pulse width modulation device includes a multiphase clock generating means for generating a multiphase clock having a number of phases P, the phases of which are shifted by a phase difference T / P with a period T, and first and second input Comparing means for detecting the time interval of the synchronization signal, comparing the detected time interval value with the target value, and outputting an error from the target value, and setting the pixel clock frequency according to the error output from the comparing means A frequency calculation unit that calculates a value and outputs a frequency instruction signal that indicates the pixel clock frequency according to the set value of the calculated pixel clock frequency, and a period between the first and second synchronization signals is divided into a plurality of periods The frequency modulation data generating means for generating the frequency modulation data that is the difference data from the set value of the pixel clock frequency, and the set value of the pixel clock frequency and the frequency modulated data are added to correspond to each other region, Frequency modulation means for outputting a frequency instruction signal for instructing a pixel clock frequency according to the added value, and a phase difference T / P of the multiphase clock as a unit time, and counting the number of unit times according to the frequency instruction signal. The phase difference T / P is calculated in accordance with a conversion rule determined in advance according to the frequency of the pixel clock. Data conversion means for converting the pulse width data as a unit; and the pulse width data according to the frequency modulation data. Based on the rise time of the pixel clock calculated by the counting means and the pulse width data correction means for correcting the data, the rise time and fall time of the pulse width modulation signal are calculated according to the corrected pulse width data. Characterized in that it comprises edge time calculation means and pulse width modulation signal output means for generating a pulse width modulation signal according to the rise time and fall time of the pulse width modulation signal with the multiphase clock as a reference. Yes.

  According to an eighth aspect of the present invention, in the image forming apparatus according to the sixth or seventh aspect, the data conversion means uses the density data generated during image formation and the density of the formed image as a conversion rule. It is characterized by having a conversion rule for correcting the nonlinear characteristic.

As described above, according to the first to eighth aspects of the present invention, the pixel clock is generated on the basis of the multiphase clocks (VCLK0 to VCLK15) generated with high accuracy, and matched with the variation of the scanning time. Since the pixel clock frequency is controlled, it is possible to generate a pixel clock that can correct this error with high accuracy even if the scanning average speed fluctuates. Since the control is performed, it is possible to generate a pixel clock that can be accurately corrected even if there is a scanning speed error for each surface. Further, since the pixel clock frequency is modulated so as to correct the non-linearity error of the scanning speed, a more accurate pixel clock can be generated, and the pixel clock that has corrected the scanning speed error with high precision is used as a reference. By generating the pulse width modulation signal, a high-quality image can be obtained. Further, even if the pulse width modulation resolution is improved, the circuit does not become complicated and can be realized with a simple configuration without increasing the circuit scale, so that modulation data subjected to pulse width modulation with high resolution can be generated. Further, even if the pixel clock frequency correction corresponding to the non-linearity error of the scanning speed is performed, the correction corresponding to the frequency variation of the pixel clock is performed, so that it is faithful to the desired density data regardless of the non-linear error of the scanning speed. An image with a smooth gradation can be obtained. Further, since the generation of the pixel clock and the generation of the pulse width modulation data can be accurately controlled in units of the phase difference Tv of the multiphase clock (VCLK0 to 15), it is not necessary to increase the oscillation frequency of the multiphase clock. Can be easily designed and current consumption can be reduced. Furthermore, since one of the multiphase clocks is operated with the clock GCLK further divided, the operating frequency is further lowered, and the current consumption can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  First, a basic embodiment for correcting the aforementioned errors (1) to (4), which is the basis of the present invention, will be described.

(First embodiment)
FIG. 1 is a diagram showing the overall configuration of a first embodiment of an image forming apparatus according to the present invention. In this image forming apparatus, laser light from a semiconductor laser 101 as a light source is shaped through a collimator lens 102 and a cylinder lens 103 and then incident on a polygon mirror 104 as a deflector, thereby having periodicity. Then, the light is reflected from the polygon mirror 104 so as to scan the photoconductor 105. The reflected laser light irradiates the photoconductor 105 through the fθ lens 106, the mirror 110, and the toroidal lens 107 to form a light spot. Thereby, an image (electrostatic latent image) corresponding to the output of the semiconductor laser 101 is formed on the photoconductor 105.

  Photodetectors PD1 (108) and PD2 (109) are arranged at both ends of the mirror 110, and the start and end of scanning are detected. That is, the laser beam reflected by the polygon mirror 104 is incident on the PD1 before scanning the photosensitive member 105 for one line, and is incident on the PD2 after scanning. Each of the photodetectors PD1 and PD2 converts the incident laser light into a first synchronization signal SPSYNC and a second synchronization signal EPSYNC, respectively, and supplies them to the pixel clock generation unit 111. The pixel clock generation unit 111 measures a time interval during which the laser beam is scanned between PD1 and PD2 from the two synchronization signals SPSYNC and EPSYNC so that a predetermined number of clocks fit in the time interval. The pixel clock PCLK having the frequency determined in (1) is generated and supplied to the image processing unit 112 and the laser modulation data generation unit 113. The configuration of the pixel clock generation unit 111 will be described later. The first synchronization signal SPSYNC which is an output signal of the photodetector PD1 is also given to the image processing unit 112 as a line synchronization signal. The image processing unit 112 generates image data based on the pixel clock PCLK. The modulation data generation unit 113 generates modulation data from the input image data with the pixel clock PCLK as a reference, and drives the semiconductor laser 101 via the laser driving unit 114.

  Next, the details of the pixel clock generation unit 111 in the above-described image forming apparatus will be described.

  FIG. 2 is a diagram illustrating a first configuration example of the pixel clock generation unit according to the present invention. In the pixel clock generation unit of FIG. 2, the high frequency clock generation unit 1 generates a multiplied high frequency clock VCLK based on the reference clock RefCLK, and is configured by a general PLL (Phase Locked Loop) circuit. By using, for example, an accurate crystal oscillator output as the input reference clock RefCLK, an accurate high frequency clock VCLK can be obtained. A pixel clock PCLK is generated based on the high-frequency clock VCLK. That is, the frequency divider 4 generates a pixel clock PCLK obtained by dividing the high frequency clock VCLK by M. This is composed of an M-ary counter, for example, and outputs a count value countM. Here, if counting is started at the rising edge of the synchronization signal SPSYNC, a pixel clock that is phase-synchronized with the scanning start time can be generated. Further, the frequency division ratio M is changed according to the pixel clock frequency instruction signal Mnow from the frequency calculation unit 7. Thus, since the pixel clock PCLK is generated by dividing the high-frequency clock VCLK oscillated stably and with high precision, the pixel clock frequency can be changed instantaneously and stably by changing the division ratio. It becomes possible to do. Therefore, even if the frequency for each line is changed, the transition can be made instantaneously.

  The first edge detector 2 detects the rising edge of the first synchronization signal SPSYNC with reference to the high frequency clock VCLK, and outputs a detection pulse SPpls synchronized with the pixel clock PCLK when the rising edge of the synchronization signal SPSYNC is detected. .

  The second edge detector 3 detects the rising edge of the second synchronization signal EPSYNC with reference to the high frequency clock VCLK, and outputs a detection pulse EPpls and a count value EPm.

  The comparison unit 5 detects the time Tline between the two synchronization signals SPSYNC and EPSYNC, and the difference between the reference time predetermined according to the writing frequency and the distance between the two photodetectors PD1 and PD2 and the measured time Tline. Is calculated as the error Lerr of the line. That is, the difference between the appropriate scanning time (reference time) and the scanning time Tline of the line is the scanning speed error.

  The error Lerr may be calculated by counting on the basis of the high frequency clock VCLK. However, the high frequency clock VCLK has a very high frequency and the number of bits to be counted becomes very large. It is disadvantageous. Therefore, in the present invention, the time Tline is counted using the pixel clock PCLK as a reference, compared with the reference value RefN, and finally converted as an error Lerr of the line based on the high-frequency clock.

  The filter 6 is a digital filter that filters the line error Lerr and outputs the error data Err. For example, the error 6 Err is averaged by the errors Lerr for the latest plural lines to obtain the error data Err.

The frequency calculation unit 7 calculates an appropriate pixel clock frequency according to the error data Err, converts it to a pixel clock frequency instruction signal Mnow, and outputs it. When the high frequency clock cycle is Tv, the pixel clock cycle is Tp, and scanning is performed with the pixel clock frequency set to Tp = KTv, an error Err from the target value Tp ′ (Tp ′ = K′Tv) is input. . Therefore, since RefN · Tp ′ = RefN · Tp + Err · Tv,
K ′ = K + Err / RefN (Formula 1)
If K ′ is set as follows, the pixel clock frequency can be controlled to the target value.

  That is, the digital PLL control is performed by the frequency divider 4, the comparison unit 5, the filter 6, and the frequency calculation unit 7. The characteristics of the filter 6 determine the PLL control characteristics, and the filter characteristics are determined so that the control system becomes stable. Further, the loop gain may be changed as K ′ = K + α · Err / RefN.

  Further, since the frequency division ratio M of the frequency divider 4 is a natural number, the rounding error can be reduced by converting the set value K of the pixel clock frequency into the pixel clock frequency instruction signal Mnow as follows. An accurate pixel clock can be obtained. For example, normally, a value obtained by rounding the set value K to a whole number is rounded to an integer, M is set as Mnow = M, and Mnow = M + 1 or M−1 once per C clock cycle, so that K = (M ± 1 / C), and rounding errors can be reduced. In addition, since the rounding error can be equally distributed, the local deviation of the pixel clock can be suppressed. In this case, the M value and the C value may be controlled. Detailed description will be given later.

  FIG. 3 is a timing chart showing an example of signals in the pixel clock generation unit of FIG. FIG. 4 is a diagram illustrating a detailed configuration example of the comparison unit 5. The operation of the comparison unit 5 will be described in detail with reference to FIGS.

  In FIG. 3, (a) SPSYNC is a first synchronization signal indicating the start of scanning and is input to the first edge detector 2. (B) EPSYNC is a second synchronization signal indicating the end of scanning, and is input to the second edge detector 3. (C) VCLK indicates the rising edge of the high-frequency clock generated by the high-frequency clock generator 1. (D) countM is a count value counted by the frequency divider 4 on the basis of the high-frequency clock VCLK. (E) PCLK is a pixel clock that rises when (d) countM is 0. (F-1) SPpls and (f-2) EPpls are pulses synchronized with PCLK indicating the rise of (a) SPSYNC and (b) EPSYNC, respectively. (G-2) EPm is the value of (d) countM at the rise of (b) EPSYNC. (H) is the value of the counter in the comparison unit 5 that counts on the basis of the pixel clock PCLK, and is reset to 0 at (f-1) SPpls, and the count is stopped at (f-2) EPpls.

In the comparison unit 5 of FIG. 4, the counter 11 is a counter that counts based on the pixel clock PCLK, is reset to 0 by SPpls, and stops counting at EPpls. The subtracter 12 subtracts the reference count value RefN from the value countN (n in FIG. 3) of the counter 11 after the count is stopped, and outputs a subtraction result diffN. The error calculator 13 performs the following calculation and outputs an error Lerr with the high-frequency clock VCLK cycle Tv as a unit.
Lerr = diffN · K + EPm
Here, diffN = n−RefN, EPm = m2, Tp = K · Tv, Tp: the period of PCLK.

If the distance between the two photodetectors PD1 and PD2 is not an integral multiple of the dot width, that is, if the reference time is not an integral multiple of the target pixel clock period, the fraction is converted into the number of cycles of the high-frequency clock VCLK. Is input to the error calculation unit 13 as RefM, and Lerr = diffN · K + EPm−RefM
As a result, the pixel clock frequency can be controlled more accurately.

  FIG. 5 is a diagram illustrating a detailed configuration example of the frequency calculation unit 7. Here, it is assumed that the polygon mirror has a six-surface configuration, and the pixel clock frequency is controlled for each surface in order to correct an error for each surface.

The calculation unit 16 calculates the next set values NextM, NextC, NextR from the current set values M, C, R and the error data Err, and performs this calculation for each plane according to the calculation plane instruction signal CalcNo. . As described above, the relationship of M, C, and R is Tp = (M ± 1 / C) Tv, and C = RefN / R. From these formulas and (Formula 1),
Abbreviated as NextM = M ′, NextR = R ′, RefN = Nr,
M ′ + R ′ / Nr = M + R / Nr + Err / Nr, C ′ = Nr / R ′
Therefore, the calculation is performed according to the following procedure.

(1) Calculate R + Err (= TmpR).
(2) If TmpR> Nr / 2, M ′ = M + 1 and R ′ = TmpR−Nr. If TmpR <−Nr / 2, M ′ = M−1 and R ′ = TmpR + Nr. In other cases, M ′ = M and R ′ = TmpR.
(3) The quotient of Nr ÷ R ′ is C ′. If R ′ = 0, C ′ = 0.

  The register 17 is a data holding unit for holding the M value obtained by the above calculation, and the value to be held is a value of F0M to F5M for each surface of the polygon mirror. Further, the corresponding register value is updated to NextM according to the update signal Renew. Here, * indicates that the polygon mirror has surface numbers 0 to 5, and F * indicates a value corresponding to the surface number of the polygon mirror (the same applies hereinafter). Note that the surface number indicates a relative relationship, and the corresponding value is automatically controlled, so it is not necessary to match the actual surface.

  Similarly, the register 18 is a data holding unit that holds the currently set C value, and the register 19 is a data holding unit that holds the currently set R value. The corresponding register values are updated to NextC and NextR, respectively, according to the update signal Renew.

  The selection unit 20 selects and outputs a corresponding M value from F0M to F5M according to the surface selection signal FNo. Similarly, the selection unit 21 selectively outputs a corresponding C value among F0C to F5C according to the surface selection signal FNo. Csign represents the sign of the C value.

  The counter 23 counts the C value with reference to PCLK. The counted C value is from 0 to C-1. When the count value is C-1, +1 is output if Csign indicates positive, -1 is output if negative, and 0 is output otherwise. When C = 0, 0 is always output.

  The adder 22 adds M output from the selector 20 and the value output from the counter 23, and outputs the result as a pixel clock frequency instruction signal Mnow. Therefore, the M value is converted to +1 or −1 once every C cycle of PCLK, and the average period of the pixel clock is (M ± 1 / C) Tv.

  The calculation control unit 15 controls the above-described calculation, and generates and outputs a calculation surface instruction signal CalcNo, an update signal Renew, and a surface selection signal FNo. The output of these signals will be described with the following flowchart.

  FIG. 6 is a flowchart for explaining a procedure by which the arithmetic control unit outputs a signal. In FIG. 6, first, at Step 1, the arithmetic control unit 15 performs initialization with FNo = 0 and CalcNo = 0. Next, in Step 2, it waits until the scanning of one line is completed. That is, it waits until the end of scanning is detected by EPpls. Note that the waiting time includes a grace period until the calculation of the error data Err is finalized.

  Next, in Step 3, the calculation control unit 15 performs the above-described calculation corresponding to the current CalcNo. In Step 4, the update signal Renew corresponding to the current CalcNo is activated, and the value of each register is updated to the Next value. In Step 5, CalcNo is incremented. When CalcNo = 5, the value returns to 0. In Step 6, the process branches according to a lock flag Lock indicating whether or not the pixel clock frequency control is locked. Here, the lock flag Lock is determined, for example, between predetermined lines (for example, 6 lines), and the error Lerr (or error data Err) is within a predetermined range (a range of variations in inter-surface error, desired control accuracy, etc.). If it is within a range of ± 2M, for example, it is a signal that is considered to be locked, and this signal generator may be provided in the filter 6, for example. Alternatively, a predetermined time (designated by the number of lines or the like) may be determined in advance from the start of control based on control responsiveness, and the Lock signal may be activated when this time has elapsed.

  In Step 7, if the determination result in Step 6 is No (that is, if it is not yet locked), it is determined whether the calculation is performed on all surfaces and the set value is updated. If all six planes have been calculated, FNo = CalcNo, and the process moves to Step 8. If not, the process returns to Step 2 to perform another surface calculation.

  In Step 8, FNo is incremented (in the case of 5, it returns to 0), and FNo is substituted for CalcNo (value after increment). As a result, the M and C values to be converted into the pixel clock frequency instruction signal Mnow are changed to the set values for the next line. The operations up to this point are performed until the next line starts scanning (SPSYNC is detected). Thereafter, the process returns to Step 2 and the above routine is repeated.

  If the arithmetic control unit 15 controls in this way, the control is performed so that the error Err is reduced on all surfaces until the clock frequency of each surface falls within the predetermined error. After being within the predetermined error, control is performed for each surface individually, so that the error between the surfaces is reduced, and highly accurate clock frequency control can be performed.

  FIG. 7 is a diagram illustrating an example of the state of the pull-in process by the above-described control method, where the horizontal axis represents time and the vertical axis represents line error Lerr. Black circles are errors corresponding to the 0th surface, and errors on other surfaces are indicated by x. A dotted line indicates an average value of errors for six surfaces.

FIG. 8 is a diagram illustrating another detailed configuration example of the frequency calculation unit 7. Also in the configuration example of FIG. 8, the calculation control unit 15 controls the calculation here in the same manner as that of FIG. 5. The calculation unit 25 calculates the next set values NextM and NextF from the current set values M and F and the error data Err, and performs this calculation for each surface in accordance with the calculation surface instruction signal CalcNo. In the configuration example of FIG. 8, the set value K of the pixel clock frequency is converted into the pixel clock frequency instruction signal Mnow as follows. That is, the integer part of the set value K is set to M, and the decimal part is rounded to a value F of a digit (binary notation). Then, by setting Mnow = M + 1 F times in 2 ^ a (= Na) cycle, K = (M + F / Na) is set. Here, since the rounding error due to the set value is the maximum Nref / Na, it is only necessary to determine the number of digits a in the decimal part so that it falls within the desired error tolerance. Further, in order to suppress local frequency deviation, the F cycles of +1 are distributed evenly. This function is performed by the conversion unit 31 (details of the operation will be described later). Therefore, according to (Expression 1) and the relational expression of K, it is written as NextF = F ′,
K ′ + F ′ / Na = M + F / Na + Err / Nr
Therefore, the calculation is performed according to the following procedure.

  (1) Calculate F + Err / Nr * Na (= TmpF). Since Na is 2 ^ a, * Na only needs to take the upper a bits of the multiplicand (Err / Nr), and Nr is fixed during this frequency control, so the reciprocal of Nr is calculated in advance. If this is multiplied by Err, the calculation can be performed easily.

  (2) If TmpF> Na, M ′ = M + 1 and F ′ = TmpF−Na. If TmpF <0, M ′ = M−1 and F ′ = TmpF + Na.

  As in the case of FIG. 5, the register 26 is a data holding unit that holds the M value obtained by the above calculation. The register 27 is a data holding unit that similarly holds the F value. These retained values are retained corresponding to F0 to F5 for each surface of the polygon mirror. Then, the corresponding register values are updated to NextC and NextR, respectively, according to the update signal Renew.

  The selection unit 28 selectively outputs a corresponding M value from F0M to F5M in accordance with the surface selection signal FNo. Similarly, the selection unit 29 selectively outputs a corresponding C value from F0F to F5F in accordance with the surface selection signal FNo.

  The counter 30 is an a-bit counter that counts based on PCLK, and outputs the count value countA. In accordance with the count value countA, the conversion unit 31 outputs a signal UP with “1” for the F cycle and “0” for the remaining Na-F cycles during the Na (= 2 ^ a) cycle. The generation of the UP signal is set to 1 when Arev is smaller than F when countA [0: a-1] obtained by reversing the bit arrangement of the count value countA [a-1: 0] is Arev. (UP = (Arev <F)), “1” is generated F times evenly during the Na cycle.

  The addition unit 32 adds M output from the selection unit 28 and UP output from the conversion unit 31 and outputs the result as a pixel clock frequency instruction signal Mnow. Therefore, the conversion is made so that the M value is incremented by 1 in the Na cycle of PCLK, and the average period of the pixel clock is (M + F / Na) Tv.

  As described above, the pixel clock frequency is controlled by detecting the phase error Lerr for each line and performing digital PLL control so that the phase error becomes 0. The filter 6 is a digital filter placed in the control loop, and the control band can be set by changing the filter characteristics. An example of filter setting is shown below.

  FIG. 9 is a diagram for explaining an example of setting filter characteristics. First, the loop gain of the DPLL control system excluding the loop filter is as shown in FIG. Here, fs is the sampling frequency, that is, here the line frequency. The control system can be stabilized by inserting a lag reed filter having the characteristics as shown in (b) into the control system to obtain the loop gain shown in (c).

When τ1 = 1 / 2πf1 and τ2 = 1 / 2πf2, the transfer function H (s) of the loop filter is as follows.
H (s) = (1 + τ2s) / (1 + τ1s)
If the above equation is converted into a z-transform form by bilinear transformation (s = 2 / T · (1-z ^ -1) / (1 + z ^ -1)) and further normalized as T = 1, the loop filter The transfer function H (z) is as follows:
H (z) = (b0 + b1z ^ -1) / (1 + a1z ^ -1)
Here, a1 = (1-2τ1) / (1 + 2τ1), b0 = (1 + 2τ2) / (1 + 2τ1), b1 = (1-2τ2) / (1 + 2τ1)

  FIG. 10 is a diagram showing a detailed configuration example of the filter 6 that realizes the above transfer function H (z). The filter 6 is a first-order IIR type filter. The adders 40 and 45 add the respective inputs, and the multipliers 42, 43, and 44 respectively multiply the inputs by the coefficients −a1, b1, and b0. The delay element 41 delays the intermediate variable w every sample (that is, every line). If a line error Lerr is input to the filter 6, error data Err is obtained.

  If means for changing each coefficient of the multipliers 42, 43, and 44 is provided, the filter characteristics can be dynamically changed. For example, the filter characteristics may be changed according to the above-described Lock signal.

  Note that the filter characteristics and configuration of this example are examples, and the present invention can be applied to filters having other configurations. Since the digital filter is a known technique, the illustration of other configurations is omitted.

  Next, a preferable modulation method of the modulation data generation unit 113 that modulates according to image data based on the pixel clock PCLK generated by the pixel clock generation unit 111 of FIG. 2 will be described.

  FIG. 11 is a diagram for explaining the operation of the modulation data generation unit 113. Here, it is assumed that modulation data MData is generated by performing 8-value pulse width modulation according to the image data PData. In FIG. 11, (a) VCLK indicates the rising edge of the high-frequency clock (cycle Tv), (b) countM is the count value counted by the frequency divider 4, and now Mnow = 16 is set. . (C) PCLK is a pixel clock, and the period is 16 Tv here. (D) PData is image data input in synchronization with PCLK, and modulates the pulse width Tw of modulation data (e) MData to be output according to this value Dm.

  The modulation data MData is generated with reference to the high frequency clock VCLK. If Dm ≠ 0, it is set to “H” when countM = 0. Further, when countM = Dm / Nm · Mnow (Nm is the number of gradations, here 8), it is set to “L”. Alternatively, if countM = (Nm−Dm) / Nm · Mnow, “H” is set, and if Dm ≠ 8, if countM = 0, “L” is set. Can be generated. Further, these two generation modes may be switched so that each dot can be changed.

  In the above description, the mode in which the pixel clock frequency is controlled in accordance with the variation of the scanning time between the two points of scanning start and end has been described. However, if the scanning speed in one line is substantially constant, one line Control may be performed in accordance with fluctuations in scanning time between any two of the points.

  As described above, according to the first configuration example of the pixel clock generation unit, the pixel clock is generated based on the high-frequency clock VCLK generated with high accuracy, and the pixel clock frequency is controlled in accordance with the variation of the scanning time. As a result, a pixel clock that can correct this error with high accuracy can be generated even if the scanning average speed fluctuates. Furthermore, since the pixel clock frequency is controlled corresponding to each surface of the polygon mirror, a pixel clock that can be corrected with high accuracy can be generated even if there is a scanning speed error for each surface. Further, when this pixel clock generation unit is applied to an image forming apparatus, an image is formed on the basis of a pixel clock in which a scanning speed error is corrected with high accuracy, so that a high quality image can be obtained.

  FIG. 12 is a diagram showing a second configuration example of the pixel clock generation unit according to the present invention. In the pixel clock generation unit 118 of FIG. 12, the high frequency clock generation unit 51 multiplies based on the reference clock RefCLK to generate a multiphase clock with equal phase differences. In the second configuration example, 16-phase multiphase clocks VCLK0 to VCLK15 are generated. Also, an internal operation clock GCLK obtained by dividing one of the multiphase clocks by Q (Q = 4 in this case) is generated and supplied to each unit of the pixel clock generation unit 118 (not shown).

  FIG. 13 is a diagram illustrating the timing of each clock generated by the high-frequency clock generation unit 51. Signals (a-0) to (a-15) in FIG. 13 are clocks of the multiphase clocks VCLK0 to VCLK15, and have a phase difference of equal intervals, and this time interval is Tv. . The signal (b) GCLK is a clock obtained by dividing (a-0) VCLK0 by four. The pixel clock generation unit 118 of FIG. 12 basically operates using this clock GCLK as an operation clock, and the periods obtained by dividing GCLK into four are sequentially called QT0, QT1, QT2, and QT3, and the rising edges of the multiphase clocks VCLK0 to 15 The time corresponding to each is referred to as PH0 to PH15, and the time information QP in GCLK is expressed by the period QT and the phase PH.

  Here, the time information QP is 64 values of 0 to 63, and in the second configuration example, the pixel clock PCLK is generated with reference to the phase difference Tv of the multiphase clock at equal intervals. That is, the control operation of the pixel clock frequency is performed by calculating the time information QP (QT, PH) based on the operation clock GCLK.

  Returning to FIG. 12, the first edge detection unit 52 detects the rising edge of the first synchronization signal SPSYNC based on the multiphase clocks VCLK0 to VCLK15, and detects the rising edge of the synchronization signal SPSYNC and detects the detection pulse synchronized with the clock GCLK. The time information SPqp indicating the SPpls, the rising period QT, and the phase PH is output.

  Similarly, the second edge detection unit 53 detects the rising edge of the second synchronization signal EPSYNC with reference to the multiphase clocks VCLK0 to VCLK15, and detects the rising edge of the synchronization signal EPSYNC and detects the detection pulse EPpls synchronized with the clock GCLK. Time information EPqp indicating the period QT and the phase PH at the time of rising is output.

  The counting unit 54 counts time according to the pixel clock frequency instruction signal Mnow from the frequency calculation unit 57, and generates a Set signal (consisting of a SETpls signal synchronized with GCLK and time information SETqp) every time it reaches Mnow. A time corresponding to Mnow / 2 is counted from the signal, and an Rst signal (consisting of an RSTpls signal synchronized with GCLK and time information RSTqp) is generated. The time unit for counting is the phase difference Tv between the multiphase clocks VCLK0 to VCLK15.

  The pixel clock output unit 58 generates and outputs a pixel clock PCLK by switching between “H” and “L” in accordance with the Set signal and the Rst signal supplied from the counting unit 58. Details of the configuration and operation will be described later.

  The comparison unit 55 detects the time Tline between the two synchronization signals SPSYNC and EPSYNC, and calculates the difference between the reference time predetermined according to the writing frequency and the distance between the two photodetectors PD1 and PD2 and the measured time Tline. Calculated as the error Lerr of the line. That is, the difference between the appropriate scanning time (reference time) and the scanning time Tline of the line is the scanning speed error. Here, the number of SETpls input during the period from the input of SPpls to the input of EPpls is counted, this value is compared with the reference value RefN, and the error of the line is calculated from the time information of each pulse. It is converted as Lerr. The unit of this error is the phase difference Tv.

  The filter 56 is a digital filter that filters the line error Lerr and outputs error data Err. The frequency calculator 57 calculates an appropriate pixel clock frequency according to the error data Err, converts it to a pixel clock frequency instruction signal Mnow, and outputs it.

  When the pixel clock cycle is Tp and scanning is performed with the pixel clock frequency set to Tp = KTv, an error Err with the target value Tp ′ (Tp ′ = K′Tv) is input. Therefore, the pixel clock frequency can be controlled to the target value by setting K ′ obtained by (Equation 1) as described above.

  The filter 56 and the frequency calculation unit 57 perform the same functions as those of the filter 6 and the frequency calculation unit 7 in FIG.

  Next, each part of the second configuration example of the pixel clock generation unit will be described. FIG. 14 is a diagram illustrating a configuration example of the high-frequency clock generation unit 51. The high-frequency clock generation unit 51 generates multiphase clocks VCLK0 to VCLK15 and an internal operation clock GCLK from the reference clock RefCLK.

  The voltage controlled oscillator VCO 63 is configured by a ring oscillator to which eight stages of differential buffers 64a to 64h are connected, and generates 16-phase clocks VCLK0 to VCLK15. The frequency divider 60 divides one of the multiphase clocks (here, VCLK8) by Nv.

  The phase frequency comparator PFD 61 performs phase comparison between the reference clock RefCLK and the output of the frequency divider 60, and drives an internal charge pump based on this phase difference information. The low pass filter LPF 62 smoothes the charge pump output and supplies the control voltage Vc to the VCO 63.

  The differential buffers 64a to 64h in the VCO 63 change in delay amount according to the control voltage Vc, and phase synchronization control is performed. For example, when a 100 MHz clock is supplied as the reference clock RefCLK and the frequency division ratio Nv is 20, the multiphase clocks VCLK0 to VCLK15 can generate clocks having a phase difference of equal intervals at 2 GHz. Further, the frequency divider 65 divides one of the multiphase clocks VCLK0 to VCLK0 to 15 (here, VCLK0) by Q (Q = 4 here) to generate the clock GCLK. Note that the number of phases of the multiphase clock that can be applied is not limited to 16 in this example, but a power of 2 is most desirable from the viewpoint of simplicity of calculation. Similarly, the frequency division ratio Q for generating GCLK is most preferably a power of 2.

  FIG. 15 is a diagram illustrating a configuration example of the counting unit 54. FIG. 16 is a diagram illustrating a configuration example of the pixel clock output unit 58. Further, FIG. 17 is a diagram illustrating an example of the timing of each signal of the counting unit 54 and the pixel clock output unit 58. A detailed configuration and operation for generating the pixel clock PCLK in accordance with the pixel clock frequency instruction signal Mnow will be described with reference to these drawings.

  In FIG. 15, each unit operates in synchronization with the clock GCLK. The SET time calculation unit 70 adds the pixel clock frequency instruction signal Mnow to the current PCLK rise time information, and calculates set time information nextS representing the next PCLK rise time. The update of this calculation is performed by the pSet signal. To do. A quotient obtained by dividing the set time information nextS by 64 is represented by nextSc, and the remainder is represented by nextSqp. That is, nextSc = nextS [MSB: 6], nextSqp = nextS [5: 0].

  Since the generation of PCLK is started in phase synchronization with the rise of SPSYNC (more precisely, after a predetermined signal processing time, here 2 GCLK), the first PCLK rise time information is SPqp.

  Similarly, the RST time calculation unit 71 adds 1/2 of the pixel clock frequency instruction signal Mnow to the current PCLK rise time information, and calculates reset time information nextR representing the next PCLK fall time. Yes, this calculation is updated by the pSet signal. Further, it is assumed that nextRc = nextR [MSB: 6] and nextRqp = nextR [5: 0]. Note that Mnow / 2 is added in order to make the duty of PCLK approximately 50%, and when 50% duty is not required, a value that can simplify this calculation may be added.

  The counter 72 counts nextSc cycles based on the clock GCLK, and generates a pSet signal. When the pSet signal is “H”, the counter is cleared to “1”, and when the count value matches nextSc, the pSet signal is set to “H”.

  The F / F 73 is a flip-flop that generates a SETpls signal by delaying the pSet signal and the SPpls signal by 1 GCLK. The F / F 74 is a flip-flop that generates the SETqp signal by enabling the pSet signal and latching nextSqp, and enabling SPpls and latching SPqp. The SETpls signal designates the rise of PCLK in units of GCLK, and designates rise time information in the GCLK cycle by the SETqp signal synchronized therewith. These are called Set signals and are supplied to the pixel clock output unit 58.

  The counter 75 counts the nextRc cycle with reference to the clock GCLK, and generates an RSTpls signal. When SETpls is “H”, the counter is cleared to “1”, and when the count value matches nextRc, the RSTpls signal is set to “H”. The F / F 76 is a flip-flop that enables SETpls, latches nextRqp, and generates an RSTqp signal. This RSTpls signal designates the fall of PCLK in units of GCLK, and the RSTqp signal designates fall time information within the GCLK cycle. These are called Rst signals and supplied to the pixel clock output unit 58.

  Note that the SETqp signal and the RSTqp signal only need to be valid when the SETpls and RSTpls signals are “H”, respectively. Therefore, the control timing of each unit is not limited to this configuration example.

  In FIG. 16, a delay unit 77 outputs a pulse S obtained by delaying SETpls supplied from the counting unit 54 according to time information SETqp with reference to the multiphase clocks VCLK0 to VCLK15. A clock GCLK is also input to specify the period QT. Alternatively, a period signal QT indicating a period may be input. In this case, the high-frequency clock generation unit 51 generates the QT signal. That is, the pulse S is a pulse obtained by delaying SETpls by SETqp · Tv.

  Similarly, the delay unit 78 outputs a pulse R obtained by delaying the RSTpls supplied from the counting unit 54 according to the time information RSTqp on the basis of the multiphase clocks VCLK0 to VCLK. The pulse is delayed by Tv. The SR-F / F 79 is a Set-Reset flip-flop that outputs a pixel clock PCLK that is set “H” at the rising edge of the pulse S and reset “L” at the rising edge of the pulse R.

  In FIG. 17, (a) is GCLK. When the first edge detection unit 52 detects the rising edge of the first synchronization signal (b) SPSYNC, the next GCLK1 cycle becomes “H” (c−1), and the SPpls signal is output. Also output (c-2) SPqp signal (in this example, 10) indicating at which time it started.

  (D) Mnow is a pixel clock frequency instruction signal supplied from the frequency calculation unit 57, and is input as illustrated. (E-1) nextS represents the rise time of the next PCLK calculated by the SET time calculation unit 70. At first, since PCLK rises in synchronization with the rise of SPSYNC, the next rise of PCLK is after SPqp + Mnow = 250 Tv. Here, the numerical value before the comma on the right side represents nextSc, and the numerical value after the comma represents nextSqp. The next nextS is nextSqp + Mnow = 298.

  (E-2) nextR represents the fall time of the next PCLK calculated by the RST time calculation unit 71. First, the value obtained by adding Mnow / 2 to the rising edge of SPSYNC (= 130) is the falling time of PCLK. Like (e-1) nextS, the numerical value before the comma on the right side is nextRc, and the numerical value after the comma is represents nextRqp.

  (F) pSet is a pulse output 1 GCLK before SETpls in order to update the SETqp signal, and becomes “H” when the count value of the counter 72 coincides with nextSc. In addition, the circled number shown in the figure represents the count value of nextSc.

  (G-1) SETpls is a pulse obtained by delaying the SPpls and pSet signals by 1 GCLK, and specifies the rising edge of PCLK in units of GCLK. (G-2) SETqp is PCLK rise time information indicating the delay value of SETpls, and (f) is updated to the value of (e-1) nextSqp when pSet is “H”. (H-1) RSTpls is a pulse in which the falling edge of PCLK is designated in GCLK units, and becomes “H” when the count value of the counter 75 coincides with nextRc. (H-2) RSTqp is PCLK fall time information indicating a delay value of RSTpls.

  (I-1) S is a pulse obtained by delaying (g-1) SETpls by the corresponding value (g-2) SETqp, and the unit of the delay value is the phase difference Tv of the multiphase clocks VCLK0 to VCLK15. . Similarly, (i-2) R is a pulse obtained by delaying (h-1) RSTpls by the corresponding value of (h-2) RSTqp. (J) PCLK is a pixel clock generated as (i-1) “H” at the rise of S and (i-2) “L” at the rise of R.

  FIG. 18 is a diagram illustrating a detailed configuration example of the comparison unit 55. FIG. 19 is a diagram showing an example of the timing of each signal. The detailed operation of the comparison unit 55 will be described with reference to FIGS.

  In FIG. 19, (a) is GCLK. (B-1) is SPSYNC, and (b-2) is EPSYNC. The time interval between the rises of these two signals is the scanning time Tline of the line. (C-1) is SPpls, and (c-2) is EPpls. (D-2) EPqp is time information of the synchronization signal EPSYNC. Further, (e-1) SETpls and (e-2) SETqp are time information representing the rising edge of PCLK. Since these have been described above, description thereof will be omitted.

  (E-3) SETcnt is the count value of the counter 72. In this example, Mnow = 192 is constant. At this time, (f) PCLK is generated. Since PCLK is generated in synchronization with exactly 2 GCLK after SPSYNC, the scan end point EP is also detected when it is delayed by 2 GCLK from EPSYNC. Therefore, (c-2) EPpls is delayed by 1 GCLK, (d-1) Error Lerr is detected from each signal value when EPdet is “H”.

  (G) is pSet, and (h) countN is the count value of the counter 81 which is cleared to “0” by (c-1) SPpls and incremented by (g) pSet. From these, the number of PCLK cycles n and the phase error m2 from the start of scanning to the end of scanning EP are detected.

  In FIG. 18, a counter 81 is a counter that is cleared to “0” by SPpls and increments by pSet, and outputs the count value countN. The subtraction unit 82 subtracts the reference count value RefN from the value countN (n in FIG. 19) of the counter 81 when EPdet is “H”, and outputs a subtraction result diffN (= n−RefN).

The error detection unit 84 calculates the phase difference diffM by performing the following equation, assuming that SETqp and SETcnt when EPdet is “H” are Endqp and Endcnt, respectively.
diffM = Endcnt · Mp + (EPqp−Endqp)
Here, Mp is the time information division number of GCLK, and is 64 in this example. In the example of FIG. 19, diffM = 144.

The error calculation unit 83 performs the following calculation and outputs an error Lerr in units of the phase difference Tv between the multiphase clocks VCLK0 to VCLK15.
Lerr = diffN · K + diffM
Here, Tp = K · Tv, Tp: PCLK cycle.

  Similar to FIG. 4, it is also possible to calculate Lerr = diffN · K + diffM−RefM, and to set the reference time setting value more finely so as to control the pixel clock frequency more accurately.

  Next, a preferred configuration and operation of the modulation data generation unit 119 that modulates according to image data based on the pixel clock PCLK generated by the pixel clock generation unit 118 of FIG. 12 will be described.

  FIG. 20 is a diagram illustrating a detailed configuration example of the modulation data generation unit 119. FIG. 21 is a diagram illustrating an example of a timing diagram of each signal of the modulation data generation unit 119. The detailed operation will be described with reference to FIGS. In this example, it is assumed that modulation data MData obtained by performing 8-value pulse width modulation according to the image data PData is generated.

  In FIG. 20, the modulation data generation unit 119 is supplied with GCLK to each unit and operates as a reference clock. The clock pattern generation unit 90 corresponds to a clock having a predetermined phase difference of the pixel clock PCLK from the Set signal that is supplied from the pixel clock generation unit 118 and configured from the SETpls and SETqp signals and the pixel clock frequency instruction signal Mnow. A clock pattern signal CKP (here, CKP0 to 3 and a clock pattern delayed by 0, π / 8, π / 4, and 3π / 8 phases from PCLK, respectively) is generated. This clock pattern signal CKP is a signal that changes with reference to GCLK, and is 64-bit data corresponding to 64 periods Tqp obtained by dividing the GCLK cycle by time information QP. If the period Tqp is “H”, the clock pattern signal CKP corresponds to this clock pattern signal CKP. When the bit to be “1” is “L”, it is “0”.

  The clock pattern generation procedure is performed as follows. First, offset data sofs0-3 indicating the rising edge of each clock pattern and falling offset data rofs0-3 are obtained. Sofs0 = SETqp, sofs1 = SETofs + Mnow / 8, sofs2 = SETofs + Mnow / 4, sofs3 = SETofs + 3Mnow / 8, and rofs0-3 adds Mnow / 2 to sofs0-3, respectively. Next, from the MSB of the clock pattern CKP for each cycle of GCLK, conversion from “sofs” to “0”, sofs to rofs is converted to “1”, and rofs is converted to “0”.

  If each offset data is 64 or more, this conversion is performed by delaying 1 GCLK for every 64. For example, when Mnow = 192 and SETqp = 16, CKP1 has sofs = 40 and rofs = 136 (= 2GCLK + 8), so the pattern of the first GCLK cycle is “MSB (= 63) to the 24th bit. 0 ”, 23 to 0 bits are“ 1 ”, the second GCLK cycle pattern is all“ 1 ”, the third GCLK cycle pattern is 63 to 56 bits“ 1 ”, and 55 to 0 bits are“ 1 ”. 0 ”.

  The image data decoding unit 91 converts the image data PData into 8-value pulse width modulation data DecData (8 bits). In the pulse width modulation data DecData, each bit corresponds to MSB to LSB in order of time in a period in which one cycle of the pixel clock PCLK is time-divided into eight. For example, if PData = 3, it is converted to DecData = 'b11100000 (' b indicates binary notation). Alternatively, it may be converted as DecData = 'b00000111, or both modes may be switched by adding a mode switching signal. Note that this conversion method can be freely selected within a range that does not contradict the gist of the present invention.

  The modulation pattern generation unit 92 generates a modulation pattern signal MDP from the pulse width modulation data DecData and the clock pattern signals CKP0 to CKP3. Similar to the clock pattern signal CKP, the modulation pattern signal MDP is a signal that changes based on GCLK and is 64-bit data corresponding to 64 periods Tqp obtained by dividing the GCLK cycle by the time information QP.

  The serializer 93 generates modulation data MData that serially outputs the modulation pattern signal MDP from the MSB in order (that is, in time order) by Tv time with reference to the multiphase clocks VCLK0 to VCLK15.

  In FIG. 21, a specific numerical example will be described. (A) is GCLK which becomes a reference clock. Now, when (b-1) SETpls and (b-2) SETqp constituting the Set signal are supplied as shown in the figure, the pixel clock is generated as (c-1) PCLK. Further, it is assumed that the pixel clock frequency instruction signal Mnow = 192. Although not actually generated, the clocks whose phases are delayed by π / 8, π / 4, and 3π / 8, respectively, are (c-2) PCLK1, (c-3) PCLK2, and (c-4) PCLK3. Shown for explanation.

  (D-1) to (d-4) are clock patterns CKP0 to CK3 representing PCLK and PCLK1 to PCLK3, respectively. Each 64 bits of data is in time order from MSB to LSB and expressed in HEX. Therefore, from these clock patterns CKP <b> 0 to 3, patterns (referred to as PT <b> 0 to PT <b> 7 in order of time) indicating periods (tp <b> 0 to tp <b> 7) obtained by time-dividing the pixel clock PCLK into eight can be generated. That is, PT0 = CKP0 & ˜CKP1, PT1 = CKP1 & ˜CKP2,..., PT7 = ˜CKP3 & ˜CKP0. Here, & indicates a logical product, and ~ indicates a negative logic.

  (E) DecData is pulse width modulation data and is converted as shown in the figure. (F) MDP is a modulation pattern signal. First, ({64 {DecData [7-i]}} & PTi) when i is changed from 0 to 7 is calculated, and then the logical sum of these is calculated. Can be obtained. Here, {64 {DecData [i]}} is data obtained by connecting DecData [i] for 64 bits.

  By serializing the modulation pattern signal thus generated, (g) MData modulation data can be generated. In this example, a pulse whose width is modulated so that the first 3/8 period of the PCLK period Tp is “H” and the remaining period is “L” is generated.

  In addition, instead of generating clock patterns CKP0 to CK3 whose phases are shifted by π / 8 each, patterns PT0 to PT7 indicating respective periods obtained by time-dividing one cycle of the pixel clock PCLK into eight are generated, The modulation pattern signal MDP may be generated from these and the pulse width modulation data DecData.

  Furthermore, in the above example, the case of performing 8-value pulse width modulation has been described, but other modulation schemes can also be applied. For example, when 16-value pulse width modulation is performed, the image data decoding unit 91 converts the image data PData into 16-bit pulse width modulation data DecData, and the clock pattern generation unit 90 is π / 16 each of the pixel clock PCLK. Eight clock patterns CKP0 to CKP7 whose phases are shifted may be generated, and the modulation pattern generation unit 92 may generate the modulation pattern signal MDP in the same manner.

  Further, this configuration example may be applied to the pixel clock output unit 58 of FIG. In other words, the clock pattern PCKP of the pixel clock PCLK is generated (the above-described clock pattern signal CKP0 may be used), and this is serially transmitted from the MSB (that is, in time order) on the basis of the multiphase clocks VCLK0 to VCLK and serially Tv time. If output, the pixel clock PCLK can be generated.

  As described above, according to the second configuration example of the pixel clock generation unit, the pixel clock is generated based on the multiphase clocks VCLK0 to VCLK15 generated with high accuracy, and the pixel clock is adjusted in accordance with the variation of the scanning time. Since the frequency is controlled, it is possible to generate a pixel clock that can correct this error with high accuracy even if the scanning average speed fluctuates, and the pixel clock frequency is controlled separately for each surface of the polygon mirror. Therefore, even if there is a scanning speed error for each surface, a pixel clock that can be corrected with high accuracy can be generated.

  Further, since the generation of the pixel clock can be accurately controlled in units of the phase difference Tv between the multiphase clocks VCLK0 to VCLK15, it is not necessary to increase the oscillation frequency of the multiphase clock, so that the circuit design is facilitated and the current consumption can be reduced. . For example, when the pixel clock is generated with the same resolution as the first configuration example described above, the oscillation frequency of the multiphase clock may be 1/16. In other words, the pixel clock generation resolution can be improved 16 times when the oscillation frequencies are the same. That is, a highly accurate pixel clock can be generated. Furthermore, since most of the pixel clock generators operate with the clock GCLK obtained by further dividing one of the multiphase clocks, the operating frequency can be further reduced and the current consumption can be reduced.

  Further, when this pixel clock generation unit is applied to an image forming apparatus, an image is formed on the basis of a pixel clock in which a scanning speed error is corrected with high accuracy, so that a high quality image can be obtained.

(Second Embodiment)
Next, a second embodiment of the image forming apparatus according to the present invention will be described. FIG. 22 is a diagram showing the configuration of the second embodiment of the image forming apparatus according to the present invention. The image forming apparatus according to the second embodiment is different from the first embodiment in that an image (electrostatic latent image) is obtained by irradiating light emitted from a plurality of light sources onto a photoconductor using a common scanning optical system. This is a point using a multi-beam scanning optical system for forming the.

  In FIG. 22, the semiconductor lasers 124 and 125 are laid out so that the optical axes of the collimating lenses 122 and 123 coincide with each other, have an emission angle symmetrically in the main scanning direction, and the emission axes intersect at the reflection point of the polygon mirror 104. Has been. A plurality of beams emitted from the respective semiconductor lasers 124 and 125 are collectively scanned by the polygon mirror 104 via the cylinder lens 120 and imaged on the photoconductor 105 by the fθ lens 106, the mirror 110, and the toroidal lens 107. Is done. Image data for one line is stored in the image processing unit 133 for each light source, read out for each surface of the polygon mirror, and written in two lines at the same time.

  Photodetectors PD1 (108) and PD2 (109) are disposed at both ends of the mirror 110, and the start and end of scanning are detected. That is, the laser beams emitted from the two light sources reflected by the polygon mirror 104 are sequentially incident on the PD1 before scanning the photosensitive member 105 for one line, and are incident on the PD2 after scanning.

  In each of the photodetectors PD1 and PD2, the incident laser light is converted into a first synchronization signal SPSYNC and a second synchronization signal EPSYNC, respectively, and input to the synchronization signal separation unit 126. Since the two light sources are arranged to scan the photosensitive member 105 with a time difference, the synchronization signal separation unit 126 similarly synchronizes the synchronization signal SPSYNC with the synchronization signals SPSYNCa and SPSYNCb corresponding to the respective light sources. The signal EPSYNC is separated into synchronization signals EPSYNCa and EPSYNCb corresponding to the respective light sources.

  FIG. 23 is a diagram illustrating an example of the timing of the synchronization signal from the photodetector. (A) is the first synchronization signal SPSYNC, and (b) is the second synchronization signal EPSYNC. Here, assuming that the laser beam of the semiconductor laser 125 is scanned first, the synchronization signal (a) SPSYNC is separated into (c-1) SPSYNCa and (c-2) SPSYNCb. Similarly, the synchronization signal (b) EPSYNC is separated into (d-1) EPSYNCa and (d-2) EPSYNCb.

  The separated one set of synchronization signals SPSYNCa and EPSYNCa is supplied to the pixel clock generator 127 as shown in FIG. 22, and the other set of SPSYNCb and EPSYNCb is supplied to the pixel clock generator 130.

  The pixel clock generation unit 127 measures the scanning time Tlinea from the two synchronization signals SPSYNCa and EPSYNCa, and generates a pixel clock PCLKa having a frequency determined so that a predetermined number of clocks fit within the time interval. The image processing unit 133 generates image data a based on the pixel clock PCLKa.

  The modulation data generation unit 128 generates modulation data a from the input image data a on the basis of the pixel clock PCLKa, and drives the semiconductor laser 125 via the laser driving unit 129.

  Similarly, the pixel clock generation unit 130 generates the pixel clock PCLKb from the two synchronization signals SPSYNCb and EPSYNCb, and the image processing unit 133 generates the modulation data generation unit 131 from the image data b generated based on the pixel clock PCLKb. Modulation data b is generated, and the semiconductor laser 124 is driven via the laser driving unit 132.

  Here, the pixel clock generation units 127 and 130 perform the same function as the pixel clock generation unit 111 of FIG. 1 and can apply the first configuration example and the second configuration example of the pixel clock generation unit described above. Detailed configuration and operation description are omitted. The description of the modulation data generation units 128 and 131 is also omitted.

  If the high-frequency clock generation units 1 and 51 are configured to be used in common by the pixel clock generation units 127 and 130, the circuit scale can be reduced and the current consumption can be reduced. Further, the two edge detection units 2 and 3 (or 52 and 53) for detecting the synchronization signal may be shared by the pixel clock generation units 127 and 130, and the detection signal may be separated.

  Furthermore, since some of the calculation processes of the filters 6 and 56 and the frequency calculation units 7 and 57 operate only once per line, they are shared and processed in time series for a plurality of pixel clock frequency calculations. You may make it do.

  According to this embodiment, (3) even if there is a scanning speed error for each light source, that is, the wavelengths of the two light sources are different, and the scanning speed varies due to chromatic aberration of the scanning optical system. Even if the scanning speeds of the two beams are different (for example, even if the scanning times Tlinea and Tlineb of the two beams in FIG. 23 vary independently), the pixel clocks PCLKa and PCLKb Since the frequency is controlled independently, the speed fluctuation can be corrected with high accuracy, and a high-quality image can be formed.

  In addition, the multi-beam scanning optical system has a configuration in which a plurality of laser beams emitted from one semiconductor laser array are scanned using a common scanning optical system, instead of a configuration having a plurality of semiconductor lasers. The same applies to such an optical system. Although the multi-beam scanning optical system has various forms, the operational effects of the present invention can be applied regardless of the form of the scanning optical system, and therefore, detailed illustration and description thereof are omitted.

(Third embodiment)
Furthermore, a third embodiment of the image forming apparatus according to the present invention will be described. A third embodiment of the image forming apparatus according to the present invention is a multicolor image forming apparatus having a plurality of photoconductors, and includes separate photoconductors corresponding to cyan, magenta, yellow, and black colors, and scanning. An optical system is also provided corresponding to each photoconductor, and an image (electrostatic latent image) corresponding to each color is formed on each photoconductor. A color image is formed by transferring an image of each color onto one image forming medium (for example, paper).

  The image forming apparatus of the third embodiment can be realized simply by including the four image forming apparatuses of FIG. In addition, a configuration in which a part of the scanning optical system is shared can be applied for miniaturization. However, since each optical path is different, it may be considered that a plurality of different image forming apparatuses are provided.

  FIG. 24 is a diagram showing an example of such a configuration. FIG. 24 is a sub-scanning sectional view, and shows only a part of the units. Hereinafter, the third embodiment will be described with reference to FIG.

  In FIG. 24, a polygon mirror 151 has a two-stage configuration, rotates around a dotted line as an axis, and is commonly used in each scanning optical system. Laser light emitted from the semiconductor laser 161a is reflected at a point a of the polygon mirror 151 through a collimator lens and a cylinder lens (both not shown). Similarly, laser beams emitted from the semiconductor lasers 161 b to d are reflected at points b to d of the polygon mirror 151. The laser beam reflected by the polygon mirror 151 scans the photosensitive member 157 via the scanning lenses 152 and 154 and the folding mirrors 153, 155 and 156 (the beam scanning direction, ie, the main scanning direction is relative to the drawing). Image (electrostatic latent image). Here, “a” to “d” at the end of the figure correspond to the semiconductor lasers “a” to “d”, and images corresponding to the respective colors of yellow, magenta, cyan, and black are formed. A color image is formed by transferring the image of each color formed on each of the photoreceptors 157a to 157d to an image forming medium that is placed on the intermediate transfer belt 158 and moves in the direction of the arrow.

  At this time, the beam is guided to the detector (photodetector) 171 by the mirrors 170 arranged on both sides outside the effective scanning range, and the start and end of scanning are detected and converted into synchronization signals SPSYNC and EPSYNC. These synchronization signals SPSYNC and EPSYNC are supplied to the pixel clock generator 164 in the same manner as described above, and generate a pixel clock PCLK whose frequency is controlled so as to correct the scanning speed error. The image processing unit 165 generates image data PData based on the pixel clock PCLK. The modulation data generation unit 163 generates modulation data from the input image data PData using the pixel clock PCLK as a reference, and drives the semiconductor laser 161 via the laser driving unit 162. These are similarly performed for each beam corresponding to each color.

  Further, the first and second configuration examples of the pixel clock generation unit described above can be applied to the pixel clock generation unit 164. Here, the scanning time in each scanning optical system differs depending on the manufacturing accuracy and assembly accuracy of each part of the scanning optical system, deformation due to changes with time, etc., and two photodetectors that detect the start and end of scanning Since the distance between them varies depending on the assembling accuracy and the like, a reference value RefN as a reference for image clock frequency control is obtained in advance for each scanning optical system at the time of manufacture of the image forming apparatus (the image deterioration is caused by a change over time, etc.). When they occur, they may be obtained again), and these are given to the pixel clock generator 164 as reference values RefN, respectively.

  In addition, since the scanning start detection position by the synchronization signal SPSYNC may be different for each scanning optical system, image writing is started after a predetermined time (after a predetermined cycle of the pixel clock PCLK) after the rising of the synchronization signal SPSYNC. The writing start offset is obtained in advance for each scanning optical system.

  FIG. 25 is a diagram showing the relationship of the scanning width with respect to the scanning time in each scanning optical system. (A-1) indicates the scanning width of one line of the scanning optical system a. SPa and EPa are positions in which the position of the detector that detects the start and end of scanning is associated with the photosensitive member. Let this distance be La. Further, when the one-dot width of the image is Lp, La / Lp = RefNa is the number of dots in one line, and this is set as the reference value RefN. In addition, a range where an image is actually formed is an area between PSP and PEP. (A-2) indicates the scanning time for one line of the scanning optical system a.

  Corresponding to the scanning start position SP and the end position EP, synchronization signals SPSYNC and EPSYNC are detected, respectively, and this time interval is set as a scanning time Tla. Although the scanning time Tla varies depending on various factors as described above, the pixel clock cycle Tpa is controlled so that the relationship of Tpa = Tla / RefNa is established. Therefore, after a predetermined PCLK cycle from SPSYNC (N1 N2), the output write pulse always forms dots at the same position on the scanning line (D1 and D2). Also, the actual image writing is started after the Nofsa cycle.

  Similarly, (b-1) indicates the scanning width of one line of the scanning optical system b, and assuming that the distance between the scanning start position SPb and the end position EPb is Lb, Lb / Lp = RefNb is a reference value. Set as RefN. (B-2) indicates the scanning time of one line of the scanning optical system b, and the time interval between the synchronization signals SPSYNC and EPSYNC is the scanning time Tlb. Similarly, the pixel clock cycle Tpb is controlled so that the relationship of Tpb = Tlb / RefNb is established. Furthermore, by setting the image writing start offset Nofsb according to the distance difference between the two scanning start positions SPa and SPb, the range PSP to PEP in which the image is actually formed coincides regardless of the scanning optical system.

  As described above, according to the image forming apparatus of the third embodiment, even if the scanning speed error occurs due to various factors including the speed error for each scanning optical system, the scanning speed corresponding to each color to form an image. Since the frequency of the pixel clock PCLK is controlled independently according to the difference and fluctuation, the color image formed in this way does not cause color shift, does not cause color reproducibility and resolution degradation, and has high quality. Can be obtained.

  As described above, according to the first to third embodiments, the scanning speed errors (1) to (4) shown in the above-mentioned problems of the prior art can be corrected with high accuracy. In the present invention, the non-linearity error of the scanning speed is also highly accurate by making the following changes to the first to third embodiments (by making the following fourth embodiment). Can be corrected.

(Fourth embodiment)
Hereinafter, a fourth embodiment will be described with reference to the drawings. FIG. 28 is a diagram illustrating a third configuration example of the pixel clock generation unit. The pixel clock generation unit of FIG. 28 can be applied as each pixel clock generation unit of the image forming apparatus of FIGS. In FIG. 28, blocks with the same reference numbers as those in FIG. 2 have the same configuration and perform the same functions, and thus detailed description thereof will be omitted.

  The frequency calculation unit 201 in FIG. 28 calculates an appropriate pixel clock frequency according to the error data Err in the same manner as the frequency calculation unit 7 in FIG. 2, converts this into a pixel clock average frequency signal Mavg, and outputs it.

  Further, the frequency modulation unit 202 converts the pixel clock average frequency signal Mavg in accordance with frequency modulation data FMData supplied from a frequency modulation data generation unit 203 described later, thereby performing a pixel clock frequency instruction signal for performing desired frequency modulation. Mnow is generated and supplied to the frequency divider 4. The frequency divider 4 divides the high-frequency clock VCLK in accordance with the pixel clock frequency instruction signal Mnow to generate the pixel clock PCLK. Therefore, the frequency of the pixel clock PCLK can be modulated by modulating the pixel clock average frequency signal Mavg.

  The frequency modulation data generation unit 203 generates frequency modulation data FMData corresponding to a scanning position (in this case, represented by the number of pixel clocks PCLK n) with the first synchronization signal SPSYNC as the origin. This frequency modulation data FMData is a pixel clock frequency corresponding to the scanning speed V (n) at the scanning position n, and here, M (n) represented by the frequency division value of the high frequency clock VCLK and the pixel clock average frequency signal Mavg. Is the difference.

  29 shows a scanning speed V (n) (FIG. 29A) with respect to the scanning position n, a deviation Δ (n) from the ideal position (FIG. 29B), and frequency modulation data FMData (n) (FIG. 29B). It is a figure which shows an example of c)). The deviation Δ from the ideal position is an integrated value of V (n) −Vavg. Since the non-linearity error of the scanning speed is mainly determined by the accuracy of the scanning optical system and the assembly error, the frequency modulation data FMData may be acquired in advance, for example, when the apparatus is manufactured and stored. An example of the acquisition method of frequency modulation data is shown. First, scanning is performed at a constant pixel clock frequency, and a deviation Δ from the ideal position at each scanning position is measured. Since the differential value of the deviation Δ is the scanning speed V, it is converted into the pixel clock frequency from this, and the difference from the pixel clock average frequency signal Mavg is obtained. Briefly, the inclination between predetermined scanning positions (Δn in FIG. 29) is approximated to the scanning speed V ′, and a converted value from this value is used as frequency modulation data in this region (broken lines in FIG. 29). . In this way, frequency modulation data can be easily obtained, and the same data can be used between the areas, so that the amount of memory for storing data can also be reduced. If it is desired to correct the scanning speed with higher accuracy, the region Δn may be shortened. For the frequency modulation data FMData, the difference data ΔM of the frequency division ratio M can be obtained simply. Conversion to the pixel clock frequency instruction signal Mnow can be performed by adding the difference data ΔM to the pixel clock average frequency signal Mavg.

  Further, in order to perform the frequency modulation of the pixel clock with higher accuracy, the frequency modulation data may include not only the frequency division ratio M but also its decimal part. The processing of the decimal part may be performed in the same manner as described above. That is, the M value and C value in FIG. 5, or the M value and F value in FIG. As described above, when frequency modulation is divided into regions, the processing is simple if the region length Δn is an integral multiple (1 or more) of Na (Na = 2 ^ a, a: number of decimal digits in binary notation). It is more suitable. In the following detailed description, the case where the frequency modulation data FMData is handled by the integer part ΔM and the a-digit decimal part ΔF will be described.

  Next, details of each part of the third configuration example of the pixel clock generation unit will be described. The frequency calculation unit 201 applies the same configuration as in FIG. 8 (not shown). However, the counter 30, the conversion unit 31, and the addition unit 32 have the same functions as the frequency modulation unit 202 described later, and thus are shared and deleted from the frequency calculation unit 201. Therefore, the output M of the selection unit 28 and the output F of the selection unit 29 are output as the pixel clock average frequency signal Mavg.

  FIG. 30 is a diagram illustrating a detailed configuration example of the frequency modulation unit 202. The frequency modulation unit 202 in FIG. 30 uses the pixel clock frequency indication signal Mnow as frequency data (M ′, F ′) obtained by adding the pixel clock average frequency signal Mavg (M, F) and the frequency modulation data FMData (ΔM, ΔF). Convert to Here, ΔM is a positive / negative number, and ΔF is a positive number. That is, the adding unit 211 adds F and ΔF to obtain F ′. At this time, if there is a carry, CO is output. The adding unit 210 adds M, ΔM, and the carry signal CO to obtain M ′. The counter 212, the conversion unit 213, and the addition unit 214 perform the same functions as the counter 30, the conversion unit 31, and the addition unit 32 of FIG. 8, respectively, and convert M 'and F' into a pixel clock frequency instruction signal Mnow. Since the operation is the same as described above, detailed description thereof is omitted.

  FIG. 31 is a diagram illustrating a detailed configuration example of the frequency modulation data generation unit 203. The frequency modulation data storage unit 220 in FIG. 31 is a memory that stores frequency modulation data FMData corresponding to each area in the scan line with each area number as an address, and stores data corresponding to the supplied address signal. Output. The data to be stored is obtained in advance as described above. This data may be stored in another storage unit in the apparatus and loaded when the apparatus is started up. Further, the frequency modulation control unit 221 calculates an area number in the scanning line and generates an address signal. That is, the address is cleared to 0 by the input of the synchronization signal SPSYNC, the pixel clock PCLK is counted, and the address signal is incremented every time the area length Δn is reached. Note that the detection pulse SPpls may be input instead of the synchronization signal SPSYNC. Also, if the area length of each area is set in advance and the address is incremented every time the area length is reached, the area length can be changed according to the amount of frequency change, and the amount of storage memory can be reduced. Both reduction and improved frequency correction accuracy can be achieved.

  By the way, if the scanning speed or the pixel clock frequency is changed, the frequency modulation data needs to be changed in proportion thereto. For example, when changing the pixel density by changing the pixel clock frequency without changing the scanning speed (polygon rotation speed), the frequency modulation data obtained in advance may be changed in proportion to the magnification to be changed. That is, for example, when frequency modulation data is calculated by halving the pixel clock frequency at the time of calculation to halve the pixel density, the data obtained by halving the frequency modulation data at the time of calculation is stored as frequency modulation data It may be stored in the unit 220.

  According to the third configuration example of the pixel clock generation unit, in addition to the effects of the first configuration example, it is possible to generate a high-accuracy pixel clock in which a nonlinear error is also corrected. Further, when this pixel clock generation unit is applied to an image forming apparatus, an image is formed on the basis of a pixel clock in which a scanning speed error is corrected with high accuracy, so that a high quality image can be obtained. Also, if the nonlinearity error has periodicity for each scanning line, such as the scanning speed nonlinearity error differs for each surface of the polygon mirror, frequency modulation data corresponding to each surface is acquired in advance, and that surface is scanned during scanning. The frequency modulation data corresponding to the above may be used.

  FIG. 32 is a diagram showing another configuration example of the frequency data generation unit suitable for such a case. In FIG. 32, the frequency modulation control unit 221 calculates an area number in the scan line and generates an address signal, as in FIG. The frequency modulation data storage memories 223 (1) to (Nf) store the frequency modulation data FMData corresponding to each area and each area in the scanning line with each area number when the number of polygon mirror faces is Nf. Is stored as an address, and data corresponding to the supplied address signal is output. Here, the memory corresponding to which surface is effectively selected is selected by a memory selection signal. The memory selection signal generation unit 222 converts the surface selection signal FNo output from the frequency calculation unit 201 into a memory selection signal and outputs it. Here, the surface selection signal FNo indicates a relative surface number, and the memory selection signal corresponds to an absolute surface number.

  An example of this association method is shown. When acquiring frequency modulation data, first, scanning is performed at a constant pixel clock frequency (without frequency control), and a deviation Δ from the ideal position at each scanning position is measured for each surface. Since the scanning speed is different, the output Lerr of the comparison unit 5 is unique for each surface and takes different values. Usually, the absolute surface number of each surface can be specified from at least the permutation of the error Lerr. Therefore, the error Lerr for each surface is also stored corresponding to the memory number storing the frequency modulation data calculated from the deviation Δ from the ideal position. Next, during normal operation, after the rotation of the polygon mirror is stabilized, scanning is performed at a constant pixel clock frequency (without frequency control), and the surface selection signal FNo and the error Lerr are obtained in association with each other and measured. By matching the error Lerr sequence with the stored error Lerr sequence, the surface selection signal FNo and the memory number are associated with each other. Thereafter, a pixel clock frequency control operation may be performed. The accuracy can be improved by using the average of the error Lerr for a plurality of lines. In this way, even if the non-linearity error of the scanning speed differs for each surface of the polygon mirror, the pixel clock frequency correction corresponding to each non-linearity error can be performed, so that a more accurate pixel clock can be generated.

  Next, another configuration example of the pixel clock generation unit will be described. FIG. 33 is a diagram illustrating a fourth configuration example of the pixel clock generation unit. The pixel clock generation unit of FIG. 33 can be applied as each pixel clock generation unit of the image forming apparatus of FIGS. In FIG. 33, blocks denoted by the same reference numerals as those in FIG. 12 have the same configuration and perform the same functions, and thus detailed description thereof is omitted. The frequency calculation unit 231 in FIG. 33 calculates an appropriate pixel clock frequency according to the error data Err in the same manner as the frequency calculation unit 57 in FIG. 12, converts this into a pixel clock average frequency signal Mavg, and outputs it. The frequency modulation unit 232 and the frequency modulation data generation unit 233 perform the same functions as those of the frequency modulation unit 202 and the frequency modulation data generation unit 203 in FIG. However, in this example, the scanning position (n) is counted by operating based on the clock GCLK instead of the pixel clock PCLK and counting the set pulse Set. Of course, the operation may be performed based on the pixel clock PCLK. According to the fourth configuration example of the pixel clock generation unit, in addition to the effects of the second configuration example, it is possible to generate a high-accuracy pixel clock in which nonlinear errors are also corrected. Further, when this pixel clock generation unit is applied to an image forming apparatus, an image is formed on the basis of a pixel clock in which a scanning speed error is corrected with high accuracy, so that a high quality image can be obtained.

  As described above, according to the fourth embodiment of the present invention, the pixel clock for correcting the scanning speed errors (1) to (5) shown in the above-mentioned problems of the prior art with high accuracy is generated. be able to. With this pixel clock as a reference, modulation data generated by modulating the image data is generated by the modulation data generation unit described below, and the semiconductor laser is driven via the laser drive unit, so that even scanning speed errors can be accurately detected. It is possible to form a high-quality image corrected to the above.

  FIG. 34 is a diagram illustrating a configuration example of the modulation data generation unit 119. The modulation data generation unit 119 in FIG. 34 generates modulation data for driving the semiconductor laser from image data composed of density data Dden and phase data Dph. This modulation is PWM modulation that modulates the pulse width of one dot. Density data indicates the pulse width, and phase data indicates the pulse position in the dot. The modulation data generation unit of FIG. 34 is preferably applied as the modulation data generation unit of the image forming apparatus of FIGS.

  In FIG. 34, a data converter 301 converts density data Dden into PWM modulation pulse width data Dout. As described above, the width of one dot, that is, one cycle of the pixel clock PCLK is represented by an M value in units of the phase difference Tv between the high-frequency multiphase clocks VCLK0 to VCLK, and the target pixel clock frequency is determined by Mtarget. And At this time, assuming that the maximum value of the density data Dden is dmax (for example, if the density data is represented by 4 bits, the maximum value dmax = 15), the conversion data Dout is obtained by calculating Dout = Mtarget * Dden / dmax. This conversion may be obtained by calculation for each dot. However, the conversion data generation unit 307 generates a conversion data table LUT (Look Up Table) in which conversion data corresponding to density data is determined in advance. The data may be supplied to the data conversion unit 301 and converted according to the converted data. Alternatively, the conversion data generation unit 307 may store separately obtained conversion data. FIG. 35A shows an example of the converted data. Further, the data conversion unit 301 generates a signal that sets Dzero to H when the density data is 0, and sets Dfull to H when the density data is full density (dmax). Actually, the pixel clock PCLK frequency is controlled each time due to fluctuations in scanning speed, and the pixel clock frequency at that time may not coincide with Mtget. In that case, the difference is supplied as correction data, and the data correction unit 302 corrects the difference to generate corrected PWM modulation data Dpwm. In addition, when the pixel clock generation unit shown in FIG. 33 that modulates the pixel clock frequency in one line and corrects the nonlinear error of the scanning speed is used, if the frequency modulation data FMData is supplied as correction data, the frequency modulation of the pixel clock is performed. Correction according to is performed. Detailed configuration and operation will be described later. In addition, when the difference from the pixel clock Mtarget is very small, generally there is almost no difference in the full density as an image, and therefore the data correction unit 302 may be omitted for the sake of simplicity.

  The delay unit 303 delays the phase data Dph by the calculation time of the data conversion unit 301 and the data correction unit 302, and makes the supply time coincide with the PWM modulation data Dpwm. It is also assumed that the Dfull and Dzero signals are output after being adjusted for delay.

  The edge time calculation unit 304 is based on PWM modulation data Dpwm, full density signal Dfull, zero density signal Dzero, and phase data Dph, and is based on PCLK data representing rise time information of the pixel clock PCLK supplied from the pixel clock generation unit As described above, the rising time information WPS and the falling time information WPR of the modulation data are generated by a calculation described later.

  The Set / Rst pulse generation unit 305 generates a set pulse WPSpls, a reset pulse WPRpls, and phase information WPSqp, WPRqp from the rising and falling time information WPS, WPR of the modulation data.

  The modulation data output unit 306 generates and outputs a modulation data pulse from the set pulse WPSpls, the reset pulse WPRpls, and the phase information WPSqp, WPRqp.

  Next, the detailed configuration and operation of each unit in FIG. 34 will be described. FIG. 36 is a diagram illustrating an example of the data correction unit 302. The data correction unit 302 in FIG. 36 corrects data by performing an operation of Dpwm = Dout (1 + ΔM / Mtarget), where ΔM is a difference between the target pixel clock frequency Mtarget and the current pixel clock frequency M. Note that, as described above, the frequency modulation data FMData (or the upper part of the data) may be added to the difference data. In the data correction unit 302, the divider 310 first calculates ΔM ÷ Mtarget. In general, since it is difficult to configure a high-speed divider, a multiplier that performs an operation of ΔM × 1 / Mtarget by giving an inverse number of Mtarget may be used. The multiplier 311 is a multiplier that multiplies the input PWM modulation data Dout by the output of the divider 310 to obtain Dout · ΔM / Mtarget. The delay unit 312 delays the PWM modulation data Dout by the calculation time of the multiplier 311. The adder 313 adds the output of the delay unit 312 and the output of the multiplier 311 and outputs the corrected PWM modulation data Dpwm (== Dout (1 + ΔM / Mtarget)).

  FIG. 37 is a diagram illustrating a table representing the calculation performed by the edge time calculation unit 304, and FIG. 38 is a signal waveform diagram illustrating an example of the calculation. In the present example, the PCLK data representing the rise time information of the pixel clock PCLK is data generated based on the internal operation clock GCLK, and the set pulse PCKset representing the rise of the pixel clock, its phase information setph, and the set pulse. Information consisting of data centpos indicating the center position of the pixel clock starting from the rising edge of PCKset and data nextpos indicating the rising position of the next pixel clock starting from the rising edge of the set pulse PCKset is supplied.

  A full density signal Dfull (when H is full density) indicating whether the dot is a full density dot, or a zero density signal Dzero (H is zero density) indicating whether the dot is a zero density (ie, white dot) dot ), Phase data Dph (here, it is assumed that there are three dot phase states of left / right / middle) and each state (S1 to S1) of whether or not the previous dot ends in the lighting state. In response to S10), the modulation data rise time information WPS, fall time information WPR, previous dot fall time information prevRST, and a signal prev (prev ′ at the next dot) indicating whether or not the dot ends in the lighting state. Is generated as shown in FIG. Here, X means that the state of the signal may be anything, and “-” shown in the column of WPS or the like indicates that the dot is not valid data. For example, when the full density signal Dfull = H, prev = H is set regardless of the state of other signals. When prev ′ = L, WPS = setph is substituted and output. At this time, other information is not valid data.

Based on FIG. 38, further calculation examples will be described. Here, when Dpwm = full, Dfull = H is indicated, when Dpwm = zero, Dzero = H, and other values indicate values of modulation data. First, in the dot cycle of (1), Dpwm = d0 (that is, Dfull = L, Dzero = L), Dph = left, and prev ′ = L, so that the state of S5 in FIG. = Setph, WPR = setph + d0, prevRST = invalid, prev = L. In the figure, each time information is indicated by an arrow, and invalidity is indicated by a cycle without entry.
Thereafter, since the dot cycle (2) is in the state of S7, WPS = n1-d1, WPR, prevRST = invalid, prev = H
In the dot cycle (3), in state S4, prevRST = setph, other invalid, prev = L
(The description of the cycle is omitted).

  Further, (k) PCLK and (l) WrPLS represent the pixel clock and modulation data in real time for explanation.

  Next, the Set / Rst pulse generation unit 305 divides the rise time information WPS of the modulation data into the GCLK count number WPScnt and the phase information WPSqp (specifically, for example, the lower 6 bits are the phase information and more) Indicates a count number), a pulse obtained by delaying the PCKset pulse by the GCLK count number WPScnt is output as a set pulse WPSpls, and phase information WPSqp is also output in accordance with the output. Similarly, if the prevRST time information is invalid, the falling time information WPR of the modulation data is divided into the GCLK count number WPRcnt and the phase information WPRqp, and a pulse obtained by delaying the CKset pulse by WPRcnt is output as the reset pulse WPRpls. In addition, phase information WPRqp is output. If the prevRST time information is valid, the reset pulse WPRpls and the phase information setph are output in the same cycle as the PCKset pulse before that, and then the generation based on the falling time information WPR of the modulation data is performed.

  FIG. 39 is a diagram illustrating a configuration example of the modulation data output unit 306. In FIG. 39, a delay unit 320 outputs a pulse S obtained by delaying WPSpls supplied from the Set / Rst pulse generation unit 305 according to phase information WPSqp with reference to the multiphase clocks VCLK0 to VCLK15. A clock GCLK is also input to specify the period QT in the GCLK cycle. Alternatively, a period signal QT indicating a period may be input (in this case, the high-frequency clock generation unit 51 generates this QT signal). That is, the pulse S is a pulse obtained by delaying WPSpls by WPSqp · Tv. Similarly, the delay unit 321 outputs a pulse R obtained by delaying WPRpls supplied from the Set / Rst pulse generation unit 305 in accordance with the phase information WPRqp with reference to the multiphase clocks VCLK0 to VCLK15. R is a pulse obtained by delaying WPRpls by WPRqp · Tv. The SR-F / F 322 is a Set-Reset flip-flop that outputs the modulation data WrPLS that is set “H” at the rising edge of the pulse S and reset “L” at the rising edge of the pulse R.

  In this way, by applying the full density signal Dfull, even if the target pixel clock frequency Mtarget does not match the current pixel clock frequency M, for example, Dpwm = M−1, the pulse is not lost. Concentration pulses can be generated. Therefore, it is not necessary to supply the current pixel clock frequency as correction data, so that the configuration is simple and the speed can be increased.

  Also, in general, in order to correct the tone non-linearity depending on the image forming apparatus so that the desired density data can be faithfully reproduced as the actual image density, the density data is generally corrected by a so-called gamma correction. Made. This gamma correction may be performed simultaneously by the data converter shown in FIG. That is, as shown in the curve of FIG. 35B, the conversion data may be stored as conversion data such that the full density dmax becomes the target pixel clock frequency Mtarget. In this way, the circuit scale can be reduced.

  As described above, the modulation data generation unit of the present embodiment can be realized with a simple configuration without increasing the circuit scale without increasing the circuit scale even if the pulse width modulation resolution is improved. Modulated data with pulse width modulation with high resolution can be generated, and even if there is a change in scanning speed, the error is generated based on a pixel clock that accurately follows the error, so a high-quality image can be obtained. It is done. Further, even if the pixel clock frequency correction corresponding to the non-linearity error of the scanning speed is performed, the correction corresponding to the frequency variation of the pixel clock is performed, so that it is faithful to the desired density data regardless of the non-linear error of the scanning speed. An image with a smooth gradation can be obtained.

The present invention can be used in laser printers, digital copying machines, and the like.

1 is a diagram illustrating an overall configuration of a first embodiment of an image forming apparatus of the present invention. It is a figure which shows the 1st structural example of a pixel clock generation part. FIG. 3 is a timing diagram illustrating an example of signals in a pixel clock generation unit in FIG. 2. It is a figure which shows the structural example of a comparison part. It is a figure which shows the structural example of a frequency calculating part. It is a flowchart explaining the procedure in which a calculation control part outputs a signal. It is a figure explaining an example of the drawing-in process by the control method of a 1st embodiment. It is a figure which shows another structural example of a frequency calculating part. It is a figure explaining an example of a filter characteristic. It is a figure which shows the structural example of the filter which implement | achieves the transfer function H (z). It is a figure explaining operation | movement of a modulation data generation part. It is a figure which shows the 2nd structural example of a pixel clock generation part. It is a figure which shows the timing of each clock produced | generated by the high frequency clock production | generation part. It is a figure which shows the structural example of a high frequency clock generation part. It is a figure which shows the structural example of a counting part. It is a figure which shows the structural example of a pixel clock output part. It is a figure which shows an example of the timing of each signal of a counting part and a pixel clock output part. It is a figure which shows the structural example of a comparison part. It is a figure which shows an example of the timing of each signal of a comparison part. It is a figure which shows the structural example of a modulation data generation part. It is a figure which shows an example of the timing of each signal of a modulation data generation part. It is a figure which shows the structure of 2nd Embodiment of the image forming apparatus of this invention. It is a figure which shows an example of the timing of the synchronizing signal from a photodetector. It is a figure which shows the structure of 3rd Embodiment of the image forming apparatus of this invention. It is a figure which shows the relationship of the scanning width with respect to the operation time in each scanning optical system. It is a general schematic block diagram of the image forming apparatus by a prior art example. It is a figure which shows an example of the nonlinearity error of the scanning speed in 1 line. It is a figure which shows the 3rd structural example of a pixel clock generation part. It is a figure which shows an example of scanning speed V (n) with respect to scanning position n, deviation (n) from ideal position, and frequency modulation data FMData (n). It is a figure which shows the detailed structural example of a frequency modulation part. It is a figure which shows the detailed structural example of a frequency modulation data generation part. It is a figure which shows another structural example of a frequency data generation part. It is a figure which shows the 4th structural example of a pixel clock generation part. It is a figure which shows the structural example of a modulation data generation part. It is a figure which shows an example of conversion data. It is a figure which shows an example of a data correction part. It is a figure which shows the table | surface showing the calculation performed by an edge time calculating part. It is a signal waveform diagram which shows an example of a calculation. It is a figure which shows the structural example of a modulation data output part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 High frequency clock generation part 2 1st edge detection part 3 2nd edge detection part 4 Frequency divider 5 Comparison part 6 Filter 7 Frequency calculation part 51 High frequency clock generation part 52 1st edge detection part 54 Count part 58 Pixel clock output part 70 SET time calculation unit 71 RST time calculation unit 72 counter 75 counter 78 delay unit 92 modulation pattern generation unit 93 serializer 101 semiconductor laser 102 collimator lens 103 cylinder lens 104 polygon mirror 105 photoconductor 106 fθ lens 108, 109 photo detector PD1, and PD2
DESCRIPTION OF SYMBOLS 110 Mirror 111 Pixel clock generation part 112 Image processing part 113 Modulation data generation part 114 Laser drive part 118 Pixel clock generation part 119 Modulation data generation part 126 Synchronization signal separation part 127 Pixel clock generation part 128 Modulation data generation part 130 Pixel clock generation part 130 131 Modulation data generation unit 133 Image processing unit 153, 155, 156 Folding mirror 201 Frequency calculation unit 202 Frequency modulation unit 203 Frequency modulation data generation unit 210, 211, 214 Addition unit 212 Counter 213 Conversion unit 220 Frequency modulation data storage unit 221 Frequency Modulation control unit 222 Memory selection signal generation unit 223 Frequency modulation data storage memory 231 Frequency calculation unit 232 Frequency modulation unit 233 Frequency modulation data generation unit 301 Data conversion unit 302 Data correction unit 303 Delay Unit 304 Edge Time Calculation Unit 305 Set / Rst Pulse Generation Unit 306 Modulation Data Output Unit 307 Conversion Data Generation Unit

Claims (8)

In a pulse width modulation device that generates a pulse width modulation signal that is pulse width modulated according to image data based on a pixel clock generated by a pixel clock generation device,
The pixel clock generator includes a multi-phase clock generator for generating a multi-phase clock having a phase number P and a phase difference of T / P by a period T, and first and second synchronization signals to be input. Comparing means for detecting a time interval, comparing the detected time interval with a target value, and outputting an error from the target value, and calculating a set value of the pixel clock frequency according to the error output from the comparing means A frequency calculation means for outputting a frequency instruction signal for instructing a pixel clock frequency in accordance with the set value of the calculated pixel clock frequency, and a phase difference T / P of the multiphase clock as a unit time, and the unit according to the frequency instruction signal Counting means for calculating the rise time and fall time of the pixel clock by counting the number of times, and calculated by the counting means on the basis of the multiphase clock. And a pixel clock output unit that generates a pixel clock in accordance with the rising time and falling time of the pixel clock,
The pulse width modulation device converts density data indicating the dot density of the image data into pulse width data in units of the phase difference T / P according to a conversion rule determined in advance according to the frequency of the pixel clock. Data conversion means; edge time calculation means for calculating rise time and fall time of the pulse width modulation signal according to the pulse width data based on the rise time of the pixel clock calculated by the counting means; and the polyphase A pulse width modulation apparatus comprising pulse width modulation signal output means for generating a pulse width modulation signal according to a rise time and a fall time of the pulse width modulation signal with a clock as a reference. 2. The pulse width modulation device according to claim 1, wherein the image data includes phase data indicating the phase of a dot, and the edge time calculation means is at a rise time of a pixel clock calculated by the counting means. Based on the pulse width data and the phase data, the pulse width modulation device calculates a rise time and a fall time of the pulse width modulation signal. 3. The pulse width modulation device according to claim 1 or 2, wherein the data conversion means uses the predetermined phase difference T / P as a unit when the concentration data is full concentration as the conversion rule. The pixel clock is converted into a control target value Mtarget of the pixel clock and generates a full density signal indicating the full density, and the edge time calculation means takes the full density signal into account and rises the pulse width modulation signal A pulse width modulation device for calculating a time and a falling time. 4. The pulse width modulation device according to claim 1, wherein the pulse width modulation device includes the conversion rule determined in advance by the data conversion unit and the frequency of the pixel clock at the time of conversion. 5. The pulse width data correcting means corrects the pulse width data into data corresponding to the frequency of the pixel clock at the time of conversion according to the difference between the edge time calculating means and the edge time calculating means corrected by the pulse width data correcting means. A pulse width modulation device that calculates rise time and fall time of the pulse width modulation signal in accordance with pulse width data. The pulse width modulation device according to claim 4,
The frequency calculation means of the pixel clock generation device corresponds to a region obtained by dividing a period between the first and second synchronization signals into a plurality of regions, and is frequency modulation that is difference data from a set value of the pixel clock frequency Frequency modulation data generating means for generating data; and a frequency modulation means for adding a set value of the pixel clock frequency and the frequency modulation data and outputting a frequency instruction signal for instructing the pixel clock frequency according to the added value. ,
The pulse width modulation device corrects data according to the frequency modulation data. In a pixel forming apparatus that drives a light source with a pulse width modulation signal generated by a pulse width modulation device and scans a light beam output from the light source onto a scanned medium to form an image.
The pulse width modulation device includes a multi-phase clock generating unit that generates a multi-phase clock having a phase number P and a phase difference of T / P by a period T, and the first and second synchronization signals that are input. Comparing means for detecting a time interval, comparing the detected time interval with a target value, and outputting an error from the target value, and calculating a set value of the pixel clock frequency according to the error output from the comparing means A frequency calculation means for outputting a frequency instruction signal for instructing a pixel clock frequency in accordance with the set value of the calculated pixel clock frequency, and a phase difference T / P of the multiphase clock as a unit time, and the unit according to the frequency instruction signal Counting means for calculating the rise time and fall time of the pixel clock by counting the number of times, and density data instructing the density of the dots of the image data. Data conversion means for converting to pulse width data in units of the phase difference T / P according to a conversion rule determined in advance according to the frequency of the clock, and the pulse width based on the rise time of the pixel clock calculated by the counting means Edge time calculation means for calculating the rise time and fall time of the pulse width modulation signal according to data, and the pulse width modulation signal according to the rise time and fall time of the pulse width modulation signal with reference to the multiphase clock An image forming apparatus comprising: pulse width modulation signal output means for generating In a pixel forming apparatus that drives a light source with a pulse width modulation signal generated by a pulse width modulation device and scans a light beam output from the light source onto a scanned medium to form an image.
The pulse width modulation device includes a multi-phase clock generating unit that generates a multi-phase clock having a phase number P and a phase difference of T / P by a period T, and the first and second synchronization signals that are input. Comparing means for detecting a time interval, comparing the detected time interval value with a target value, and outputting an error from the target value, and calculating a set value of the pixel clock frequency according to the error output from the comparing means In accordance with the set value of the calculated pixel clock frequency, the frequency calculation means for outputting the frequency instruction signal for instructing the pixel clock frequency and the period between the first and second synchronization signals are made to correspond to a plurality of divided areas. Frequency modulation data generating means for generating frequency modulation data that is differential data from the set value of the pixel clock frequency, the set value of the pixel clock frequency and the frequency modulated data And a frequency modulation means for outputting a frequency instruction signal indicating the pixel clock frequency according to the added value, and a phase difference T / P of the multiphase clock as a unit time, and the number of the unit times according to the frequency instruction signal Counting means for calculating the rise time and fall time of the pixel clock by counting the density data indicating the density of the dot of the image data according to a conversion rule determined in advance according to the frequency of the pixel clock Data conversion means for converting to pulse width data in units of T / P, pulse width data correction means for correcting the pulse width data in accordance with the frequency modulation data, and the rise time of the pixel clock calculated by the counting means Based on the corrected pulse width data, the rise time and rise of the pulse width modulation signal Edge time calculation means for calculating a fall time, and pulse width modulation signal output means for generating a pulse width modulation signal according to the rise time and fall time of the pulse width modulation signal with the multiphase clock as a reference An image forming apparatus. 8. The image forming apparatus according to claim 6, wherein the data conversion unit has a conversion rule for correcting a nonlinear characteristic between the density data generated during image formation and the density of the formed image as a conversion rule. An image forming apparatus.

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