JP5276351B2 - Image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To capacitate excellent image forming by dissolving a skew in the synchronization between lines. <P>SOLUTION: In an image forming apparatus that outputs a reference clock, divides the output reference clock based on a set multiple, and generates an image clock based on the division, a BD signal width that indicates dynamic deviation characteristics is detected, and the multiple is set in accordance with the detected BD signal width. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to an image forming technique.

  2. Description of the Related Art Conventionally, in an image forming apparatus that forms an image with a laser beam scanning unit, such as a laser printer or a digital multi-function peripheral, image formation is performed by high resolution, multi-gradation expression, smoothing processing, or the like in order to improve image quality.

  As a typical method to compensate for high image quality, the amount of light applied to the photoconductor, called pulse width modulation (hereinafter abbreviated as PWM modulation) or luminance modulation, of image information is intensified in pixel units. There is a method for controlling the dot density, etc. In recent years, the combination of PWM modulation and luminance amount modulation is used to express the gradation expression of dots (formed pixel dots) to be formed in units of pixels. Various attempts have been made to improve image quality such as gradation and image quality by changing the position of the formed pixel dots and the center of gravity of the formed pixel dots.

(PWM modulation)
Regarding the PWM modulation technique, there is a configuration using a reference clock n times the image clock frequency defining one pixel (see Patent Document 1). According to the controller shown in FIG. 1 of Japanese Patent Application Laid-Open No. H10-32077, the input multi-tone input image information is converted into multi-tone image information for the image forming apparatus, so that the multi-tone expression can be expressed with a lookup table. Expands to a pixel pattern. Then, binary data is set to the video band buffer by the write parallel serial conversion unit in the order of the formation pixel arrangement, and is transferred as image information (VDO) for the image forming apparatus by the sequentially input image clock (4VCLK).

  At that time, the image clock (4VCLK) is constituted by a four-fold value of the reference clock (VCLK) as a multi-value clock. In other words, 4-bit PWM modulation having multi-level (4-bit) gradations formed by dividing one pixel into four parts is performed, and 16 gradations are expressed. If the PWM modulation data is 8 bits, 256 gradations can be expressed. PWM modulation requires a reference clock that is a multiple of the image clock, and the relationship between the resolution and the reference clock is proportional. Furthermore, the synchronization accuracy with the horizontal synchronization signal for achieving phase synchronization of each line image is also an important factor.

  In Patent Document 1, there is no description regarding the control of the center of gravity of the formed pixel dot. However, if the formation process of the multi-value expression in one pixel is controlled from the right side, the left side, or the center, the pixel It is also possible to control the position of the equal-width dots formed inside.

(Brightness modulation)
With respect to the luminance amount modulation technique, the latent image potential formed on the photoconductor is controlled by controlling the intensity of the light applied to the photoconductor. In recent years, high-frequency modulation technology can be implemented along with PWM modulation control in units of formed pixel dots. There is also a proposal for controlling the amount of luminance in units of pixels, that is, controlling the light source for each pixel by synchronizing luminance modulation with PWM modulation and further improving the gradation expression (Patent Literature). 2).

  When the number of gradations is increased to improve gradation expression, the clock frequency also increases. When forming extremely small pixel dots by PWM modulation, there is a limit to the switching response of a laser as a light source. In response to the problem that a predetermined pulse width for forming a pixel dot having an extremely small width cannot be obtained, Patent Document 2 discloses a configuration in which luminance modulation is performed in synchronization with PWM modulation processing. That is, the expression of the pixel dots formed on the photoconductor is improved by making it possible to set the intensity of the luminance intensity by the luminance amount modulation at the time of PWM modulation conversion executed for each formed pixel dot. Thereby, the followability (gradation) of the gradation density change of the image formed on the photoconductor can be expressed as a smoother change.

  On the other hand, the specifications of an image forming apparatus using optical scanning have reached a resolution of 2400 dpi (dot / inch) and a printing speed of 80 ppm (print / minute). As the performance of the image forming apparatus is improved, various proposals such as correction of the positions of formed pixel dots have been made in order to realize further improvement in image quality.

  In order to form highly accurate pixel dots on the photoreceptor, a pixel dot array in the optical scanning direction (hereinafter referred to as the main scanning direction) and each optical scanning line (hereinafter referred to as the sub-scanning direction). It is necessary to align the pixel dot phase with high accuracy. In order to realize this, position correction control for correcting the positions of the formed pixel dots in the main scanning direction and the sub-scanning direction has been proposed.

  Patent Document 3 discloses a configuration in which an output clock of a PLL synthesizer that generates a reference clock for PWM modulation is used at a maximum oscillation frequency. Patent Document 3 discloses a content in which a pixel dot position and a pixel dot width to be formed are corrected by a higher frequency modulation means by always operating at a maximum oscillation frequency from a PLL that generates a frequency clock higher than an image clock serving as a reference clock. To do.

On the other hand, with the advent of multi-laser elements (such as VCSELs), there are image forming units that simultaneously expose a plurality of light sources. In order to perform image formation by scanning blinking control of a plurality of light emitting elements arranged on the matrix, individual element drive control must be adjusted in time, and the pixel dot array formed on the photoconductor must be adjusted. Must not. There is also a proposal for pixel dot arrangement control in which correction of the formed pixel dot position is applied (Patent Document 4).
Japanese Patent Laid-Open No. 8-321952 JP 2001-119648 A JP 2004-249497 A JP 2006-175646 A

  In the above conventional example, it is possible to correct the position, width diameter, etc. of the pixel dots formed during optical scanning (during laser beam scanning) with an extremely small number of μm.

  However, in order to reduce the amount of quantization error when synchronizing the horizontal synchronization signal, which is a reference signal for achieving phase synchronization between lines, and the image clock, the synchronization clock must be generated at a high frequency. For this reason, there is a limit in the current IC operation clock range, and there is a problem that even when optical scanning is started, a deviation of several μm due to a synchronization deviation between lines cannot be corrected.

  In addition, there is a problem that image formation between lines is displaced due to information on static deviation such as scanning magnification deviation and dynamic deviation characteristics such as temperature variation and aging of the apparatus.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to eliminate a synchronization shift between lines and enable good image formation.

An image forming apparatus according to the present invention that achieves the above object is as follows.
A rotating scanning mechanism that scans the laser beam with a rotating mirror, a reference clock output unit that outputs a reference clock, and the output reference clock based on a set multiplication number, and the image clock is divided by the frequency division. an image clock generating means for generating, the rise of the detecting means for detecting a synchronization signal for rotation synchronization of the optical scanning start timing by the laser beams scanned by the scanning mechanism, before Symbol synchronization signal detected by the detection means a width detecting means for detecting a width of up to falling from, based on the width of the front Symbol said synchronization signal detected by the width detection means, have a, a correction means for correcting the multiplication number, detected by the detection means The surface to be scanned is irradiated with a laser beam based on the generated synchronization signal and the image clock generated by the image clock generation means. An image forming apparatus which performs scanning,
The correction means corrects the multiplication number so that the multiplication number changes during one line scanning on the surface to be scanned .

  According to the present invention, it is possible to eliminate the synchronization shift between lines and to form a good image.

(First embodiment)
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings. However, the constituent elements described in this embodiment are merely examples, and the technical scope of the present invention is determined by the scope of claims, and is limited by the following individual embodiments. is not.

(Configuration of image forming apparatus)
FIG. 8 is a diagram exemplarily showing a schematic configuration of the image forming apparatus according to the embodiment of the present invention. The image forming apparatus can obtain a full-color image by superposing four color toner images of yellow, cyan, magenta, and black using an electrophotographic system. Needless to say, the gist of the present invention is not limited to a color image forming apparatus, but can also be applied to a monochrome image forming apparatus using an electrophotographic system.

  The image forming unit 800 includes a paper feeding unit 821, a photoreceptor 822 (Y, M, C, K), a charging sleeve 823 (Y, M, C, K colors), and a toner container 825 (Y, M, C, K colors). ), And a developing sleeve 826 (Y, M, C, K). The image forming unit 800 includes an intermediate transfer member 827, a transfer roller 828, and a heat fixing device 830.

  The photosensitive member 822, the charging sleeve 823, the toner container 825, and the developing sleeve 826 are all-in-one cartridges 801 (Y, M, C, and K) that are combined into one unit for each of Y, M, C, and K. . The all-in-one cartridge 801 (Y, M, C, K) is hereinafter also referred to as “cartridge 801 (Y, M, C, K)”. Each of the cartridges 801 (Y, M, C, K) is configured to be detachable.

  A charging sleeve 823 (Y, M, C, K) of the cartridge 801 (Y, M, C, K) in each color of yellow (Y), magenta (M), cyan (C), and black (K) is used as a photosensitive member 822. (Y, M, C, K) are charged. Exposure light (laser) from the scanner unit 824 (Y, M, C, K) on the charged photoconductor 822 (Y, M, C, K) based on the exposure time converted by the image processing unit (not shown). ) To form an electrostatic latent image on the photoreceptor 822 (Y, M, C, K).

  The electrostatic latent image is transferred from the toner container 825 (Y, M, C, K) to the photosensitive member 822 (Y, M, C, K) by the developing sleeve 826 (Y, M, C, K). K) A toner image of each color is formed on top. Then, the toner image of each color is superimposed on the intermediate transfer member 827 to form a multicolor toner image. The multicolor toner image formed on the intermediate transfer body 827 is sandwiched between the transfer rollers 828 and pressed to transfer the multicolor toner image (hereinafter also simply referred to as “toner image”) to the recording material 811. The multicolor toner image on the recording material 811 is fixed by the heat fixing device 830, and the recording material 811 is discharged to a discharge tray (not shown). The toner remaining on the intermediate transfer member 827 is removed (cleaned) by a cleaner 829, and the cleaned waste toner is stored in a cleaner container (not shown).

  Hereinafter, the embodiment will be described in detail with the following flows (1) to (7).

  (1) “First, the technical significance of static deviation characteristics and dynamic deviation characteristics according to the present embodiment will be described.

  (2) Next, referring to FIG. 1, an image having a function of reducing the amount of quantization error when synchronizing the horizontal synchronizing signal and the image clock, and a function of suppressing deviation in image formation between lines. The function of the forming apparatus will be described.

  (3) Next, the detailed configuration of the horizontal synchronization high-frequency clock generation unit 20 in FIG. 1 will be described with respect to the reduction of the quantization error amount when synchronizing the horizontal synchronization signal and the image clock.

  (4) Next, the operation results realized by the image forming apparatus will be described with reference to FIGS. 3A and 3B.

  (5) Next, how the real-time deviation detector 75 in FIG. 1 detects the BD signal will be described with reference to FIG. The BD signal refers to a synchronization signal detected outside the image writing area for synchronizing the optical scanning start timing for writing the laser beam in the main scanning direction.

  (6) Next, how the dynamic deviation characteristic is corrected and the arbitrary multiplication number divider 30 outputs the corrected image clock will be described with reference to FIG.

  (7) The arithmetic processing until the arbitrary multiplication number divider 30 generates the corrected image clock will be specifically described in more detail.

(1) Static deviation characteristics and dynamic deviation characteristics (a) Static deviation characteristics In order to accurately form pixel data developed by the image processing unit on the photoreceptor as dots, the positions and widths of the formed pixel dots It is necessary to perform optical scanning so as to accurately reproduce the diameter. However, in the image forming apparatus, since the optical scanning optical system including the scanner unit 824 and the like incorporate various tolerances in the reproducibility accuracy, it is necessary to devise to realize high-precision assembly.

  For example, a scanning optical lens or the like may have an accuracy tolerance of the lens itself called a scanning magnification or a half magnification, or an accuracy error determined when the lens is assembled in a lens system. In addition, even if each surface length, which is a surface division error, is uniformly manufactured for each surface length in the polygon mirror, an accuracy error at the time of division is generated, and an error variation appears in the surface length of each surface. The factor of the innate accuracy error determined in the manufacturing process is called the static deviation characteristic of the image forming apparatus. That is, although the accuracy error value is different for each manufacturing device, the accuracy error value is constant in the same apparatus. When pixel dots are imaged with a uniform transition time (image clock), for example, the characteristics of the scanning optical system lens and the characteristics due to the surface separation error of the polygon mirror surface are formed on the photoconductor as they are due to the static deviation characteristics. The Rukoto. For this reason, it is necessary to correct a position and a width diameter for every formation pixel dot. That is, when the scanning optical system is incorporated in the image forming apparatus, the correction value of the lens system with respect to the photoconductor varies depending on the image forming apparatus, but is almost fixed in the same image forming apparatus. In order to correct the scanning magnification or the half magnification of the scanning optical lens system, the deviation conversion unit may correct the static deviation characteristics based on the correction data.

(B) Dynamic Deviation Characteristics On the other hand, in an optical scanning optical system, the laser scanning speed (optical scanning speed) is the most important parameter for position correction and width diameter correction of pixel dots to be formed. It affects the superiority or inferiority of Even if the image forming apparatuses have the same optical scanning speed, for example, the root that controls the optical scanning speed uses the rotation of the motor, so that the speed deviation of the rotational speed of the motor affects the optical scanning speed. That is, even if the motor rotation speed is controlled to rotate at a constant speed, rotation unevenness with periodicity occurs. As a result, the fluctuation of the optical scanning speed is real time. That is, the optical scanning speed changes in real time. This characteristic is classified into static deviation characteristics as device-specific information. However, the characteristics cannot be specified by, for example, which polygon mirror is used as in the above-described surface division error, and in this embodiment, the characteristics do not correspond to each surface of the polygon mirror in a one-to-one correspondence. This is called the dynamic deviation characteristic. Below, the correction | amendment which detects the precision resulting from a dynamic deviation characteristic in real time, and cancels a dynamic deviation characteristic according to the detection result is demonstrated below.

  Dynamic deviation characteristics are potentially due to various static deviation characteristics. For example, there are static deviation characteristics in the scanning optical system, such as an alignment tolerance of a polygon mirror constituting the optical scanning optical system, a surface division error of the polygon mirror, a weight distribution with respect to the axis rotation of the polygon mirror, and the like. When optical scanning is performed by adding a motor rotation operation that rotates the polygon mirror at a constant speed under this condition, the speed unevenness (deviation) of the rotation speed of the polygon mirror depends on the value of each static deviation characteristic. It can be increased to various speed deviation values. By adding some motion to an object with static deviation characteristics, the result of synergistic summation based on various factors can appear as the optical scanning speed, which can occur as a change in optical scanning speed with a slight deviation is there. In an actual polygon mirror, an object called a balancer for adjusting the weight balance of clay or the like is placed at an appropriate position, and the fluctuation of the optical scanning speed is adjusted by adjusting the object. However, in an image forming apparatus aiming at better image quality, it is necessary to correct pixel dot formation according to the optical scanning speed for each pixel dot in order to more faithfully represent the position and width of the formed pixel dot. .

  (2) Next, referring to FIG. 1, an image having a function of reducing the amount of quantization error when synchronizing the horizontal synchronizing signal and the image clock, and a function of suppressing deviation in image formation between lines. The function of the forming apparatus will be described.

(Functional configuration of image forming apparatus)
(Reduction of the amount of quantization error that occurs in phase matching between the image clock and the BD signal)
FIG. 1 is a block diagram illustrating a functional configuration of the image forming apparatus according to the present embodiment. The BD signal (synchronization signal) is a reference signal for aligning the phase of the pixel dot arrangement between the lines formed on the photoconductor, and is input to the line area instruction unit 10. The line area instruction unit 10 uses a line end (line END) signal, which will be described later, as another input signal, and generates a control signal that rises based on the input (reception) of the BD signal and falls based on the input (reception) of the line END signal. Generate.

  The line area instruction unit 10 aligns the pixel dot arrangement phase for each line and generates a video enable signal indicating an allowable range of image information (hereinafter referred to as a video signal) in the line. As will be described in detail later, the reference clock starts to be output in response to the input of the synchronization signal (BD signal) to the line area instruction unit 10 functioning as the synchronization signal input means. The line area instruction unit 10 inputs the video enable signal to the horizontal synchronization high frequency clock generation unit 20.

  The horizontal synchronization high-frequency clock generation unit 20 functions as a generation unit (reference clock output unit) that generates a reference clock (hereinafter also referred to as a source clock) serving as a reference in synchronization with the start of scanning of laser light. The horizontal synchronous high frequency clock generation unit 20 generates a reference clock (source clock) that is a source for generating an image clock based on the input video enable signal. The horizontal synchronous high-frequency clock generation unit 20 is configured by a DDL circuit using a transmission delay of a digital gate circuit as shown in an example in FIG. When the video enable signal is input to the horizontal synchronization high-frequency clock generation unit 20, oscillation of a reference clock (source clock) that is phase-synchronized with the BD signal is started.

  Until the oscillation of the reference clock (source clock) starts, a certain transmission delay time occurs in the DLL circuit with reference to the leading edge of the video enable signal. In this case, the transmission delay variation component, which is a clock jitter component, is composed of digital gate circuits having the same frequency, and the reference jitter (source clock) is repeatedly generated, so that almost no clock jitter component is generated. As an example, in the repetition of one cycle of the source clock, only a jitter component of about 1/1000 is actually measured.

  The reference clock (source clock) output from the horizontal synchronous high-frequency clock generation unit 20 is input to the arbitrary multiplication frequency dividing unit 30 and the line elapsed position recognition counter unit 40 before the BD signal of the next line is input. Is done. The horizontal synchronization high-frequency clock generation unit 20 ends the generation of the reference clock (source clock) by a signal indicating the end of scanning of one line on the photosensitive member recognized by an optical scanning position detection unit (not shown).

  Line synchronization is established between lines by the BD signal of the next line. The pixel dot arrangement phase formed between the lines is phase-synchronized with the BD signal generated for each line, and a good reference clock (source clock) having almost no clock jitter component is used as the horizontal synchronization high-frequency clock generation unit 20. Is generated.

  In order to form a good image, it is necessary to correct a shift between lines due to a good arrangement of pixel dots formed on the photoreceptor and phase alignment for each line.

  The image forming apparatus according to the present embodiment is configured to generate a clock for the generated BD signal and stop the clock oscillation at the end of the line. Therefore, the quantization error generated at the time of synchronization for each line is minimized. It becomes possible to suppress.

  The source clock output from the horizontal synchronization high-frequency clock generation unit 20 is input to the arbitrary multiplication number frequency division unit 30 and to the line elapsed position recognition counter unit 40. The horizontal synchronization high-frequency clock generation unit 20 includes a frequency adjustment circuit that finely adjusts the frequency of the source clock to be output.

  Arbitrary multiplication frequency divider 30 can divide the frequency of the source clock by an arbitrary integer value so as to converge to the set image clock frequency and output it as an image clock. The arbitrary multiplication frequency dividing unit 30 divides the source clock based on the set multiplication number, and generates an image clock for controlling the timing of image formation in units of pixels.

  The image forming unit 76 can execute image formation based on the image clock for controlling the image forming timing in units of pixels output (corrected) by the arbitrary multiplication number frequency dividing unit 30.

  The CPU 55 accumulates correction data for correcting the position of the formation pixel dot for one line calculated for each line in the clock rate instruction FIFO memory unit 50 for each formation pixel dot. The clock rate instruction FIFO memory unit 50 writes the correction data in the divided integer value information storage unit 35 for each formed pixel dot at the time of actual line formation. Arbitrary multiplication frequency divider 30 writes frequency division integer value information storage unit 35 for each pixel dot (each pixel unit), and divides the source clock by an arbitrary integer value based on the updated correction data. , Output the image clock. The arbitrary multiplication number divider 30 can correct the transition time amount and phase timing of one period of the image clock based on the correction data written in the divided integer value information storage unit 35. Details of this will be described later with reference to FIG.

  On the other hand, the line elapsed position recognition counter unit 40 can function as a counter that counts the source clock, and can generate a timing signal when the count value reaches a preset value. Further, the line elapsed position recognition counter unit 40 also has a function of detecting various timings in pixel dots formed by light scanning a line in the main scanning direction and feeding back to the deviation converting unit.

  The line end (END) signal generated by the line elapsed position recognition counter unit 40 is input to the line area instruction unit 10 as described above. The timing signal generated by the line elapsed position recognition counter unit 40 is input to the laser driver 95 (hereinafter also referred to as “Laser driver 95”) via the UNBL instruction unit 80 and the Laser APC instruction unit 85.

  The UNBL instruction unit 80 receives a BD signal and a timing signal output from the line elapsed position recognition counter unit 40. The UNBL instruction unit 80 emits scanning light in front of the light receiving element to capture the reception timing of the BD signal, and generates an unblanking signal that is a control timing signal for stopping the laser emission when the BD signal is input. In the following description, the unblanking signal is indicated as “UNBL signal”. The UNBL signal is input to the laser driver 95.

  The laser driver 95 can control the amount of laser light that is a scanning light source. When the light amount control is executed for each line, when the scanning for one line on the photosensitive member is finished and the process proceeds to the next line scanning, the line elapsed position recognition counter unit 40 emits the light for timing detection. A timing signal is available.

  The device deviation memory unit 60 stores the dynamic deviation characteristics described above. The dynamic deviation characteristic stored in the apparatus deviation memory unit 60 is as illustrated in FIG. 3B (a), which will be described later, and will be described in detail later as polygon rotation speed unevenness.

  In FIG. 1, a real-time deviation detector 75 can detect an optical scanning speed deviation amount that varies depending on the surface angular velocity of the polygon mirror surface, the reflecting surface state, and various factors. The details of the real-time deviation detection unit will be specifically described with reference to FIGS. 4 and 5A and 5B described later. The real-time deviation detection unit 75 inputs the detection result to the deviation conversion unit 70.

  The deviation conversion unit 70 uses, as conversion data, data for correcting the deviation (for example, a time conversion value) based on the data detected by the real-time deviation detection unit 75 (for example, the BD signal width based on the source clock). The data is transferred to the CPU 55. Here, the BD signal width corresponds to the number of pulses from the rising edge to the falling edge of the BD signal as shown in FIG. Note that it is only necessary to distinguish the rising and falling edges of the BD signal. In order to detect the rising and falling edges of the BD signal, the circuit may be configured as low active, or the circuit may be configured as waste active. In conjunction with the sequence control of the image forming apparatus, the real-time deviation detector 75 can collect deviation data for each polygon mirror surface. Note that the BD signal width does not indicate the actual length in meters, but can be converted into the number of source clocks, and corresponds to the time length. The actual BD signal width in meters does not change.

  The CPU 55 accumulates correction data for correcting the position of the formed pixel dots for one line in the clock rate instruction FIFO memory unit 50 for each formed pixel dot based on the dynamic deviation characteristic information.

  The CPU 55 can function as a correction unit that generates or outputs correction data for changing the multiplication number for each pixel in order to correct the deviation (dynamic deviation characteristic information).

  Arbitrary multiplication frequency divider 30 writes frequency division integer value information storage unit 35 for each pixel dot (for each pixel unit), and divides the source clock by an arbitrary integer value based on the updated correction data. To do. At this time, the correction data based on the dynamic deviation characteristic information is reflected in the frequency division of the source clock. Reflecting the deviation correction data for each period (for each pixel unit) of the image clock generated by the arbitrary-multiplier frequency dividing unit 30, the formed pixel dots are arranged in one line and in the phase between the lines. , Formed in a relatively good position. At this time, the CPU 55 can function as a control unit that controls the scanning optical system with the image clock corrected based on the correction data.

  (3) Next, a detailed configuration of the horizontal synchronization high-frequency clock generation unit 20 in FIG. 1 will be described with respect to the reduction of the quantization error amount when synchronizing the horizontal synchronization signal and the image clock.

(Configuration Example of Horizontal Synchronous High Frequency Clock Generation Unit 20)
Next, the DLL circuit unit of the horizontal synchronous high frequency clock generation unit 20 will be described with reference to FIG. FIG. 2A shows a general digital multivibrator circuit. When the input becomes high level, the circuit starts oscillation of the source clock after the gate transmission delay time. This transmission delay time can be determined by the transistor configuration of the gate circuit. The configuration of FIG. 2A is a combination of a NAND gate circuit and an OR gate circuit. FIG. 2B shows a configuration example in which a NOT gate circuit and an OR gate circuit are combined. The horizontal synchronization high-frequency clock generation unit 20 uses the DLL circuit to synchronize with the leading edge of the input of the BD signal (for example, the leading edge portion 305 in FIG. 3A (c)), and after the gate transmission delay time, Start oscillation. When the UNBL signal based on the line END signal becomes the next high level due to the end of the writing of one line image, the CPU 55 can control the horizontal synchronous high-frequency clock generation unit 20 to stop the oscillation of the source clock. is there.

  The DLL circuits shown in FIGS. 2A and 2B are exemplary, and the DLL circuit can be configured using a gate transmission delay with the circuit configurations shown in FIGS. 2C to 2E, for example. Needless to say. For example, as shown in FIG. 2 (e), a plurality of stages having different gate transmission delay characteristics may be provided in parallel, and a signal selector circuit 201 that operates under the control of the horizontal synchronous high-frequency clock generation unit 20 may be provided. Is possible. According to the configuration of FIG. 2E, the signal selector circuit 201 can select and output the frequency of the source clock having a different gate transmission delay (delay time).

  If the gate transmission delay is used, oscillation and stop of the source clock can be controlled in synchronization with the BD signal. In addition, if they are configured with the same gate circuit, the transmission delay time of the source clock that starts oscillating by the BD signal generated for each line is almost the same time, so the phase variation for each line can be almost ignored. Value. That is, the occurrence of periodic jitter at the source clock frequency due to variations in gate transmission delay is reduced.

  However, in the case of a DLL circuit, there is a problem in that the frequency of the source clock is set to a desired value (fine adjustment). Therefore, the frequency of the source clock finely adjusted by dividing the frequency of the circuit configuration shown in FIGS. 2A to 2E with the same configuration, although it is different from the arbitrary frequency divider 30. Can be generated.

  (4) Next, an operation result realized by the image forming apparatus according to the present embodiment will be described with reference to FIGS. 3A and 3B.

  FIG. 3A is a diagram exemplarily showing the timing of correction control for forming pixel dots. In FIG. 3A, the UNBL (unblanking) signal is an output signal that is turned on when one line image is written and is output from the UNBL instruction unit 80. When the BD signal is detected, the UNBL signal is turned off. As shown in FIG. 3A, the source clock stops oscillating at the end of writing one line image, starting from the BD signal at the start of writing the line image (FIG. 3A (a)).

  FIG. 3A (b) shows an uncorrected timing chart focusing on the timing at reference numeral 301 in FIG. 3A (a). FIG. 3A (c) shows a timing chart at the time of correction execution focusing on the timing at reference numeral 301 in FIG. 3A (a).

  The source clock output from the horizontal synchronous high-frequency clock generation unit 20 is an image clock that has been subjected to frequency division by 8 by the arbitrary frequency division unit 30. In the example of FIG. 3A, the multiplication number is “8”, but it goes without saying that the gist of the present invention is not limited to this multiplication number. For example, it can be arbitrarily determined in accordance with conditions such as the number of PWM modulation bits, position correction, and dot width diameter correction according to the specifications of the image forming apparatus. When the multiplication number is “8”, 8 times the source clock is one image clock. An image clock obtained by dividing the source clock generated based on the BD signal by 8 by frequency division is output from the arbitrary frequency division unit 30.

  The first three pixel dots are formed on the n line, and the first three pixel dots are similarly formed on the next n + 1 line to form a one dot vertical line. 3A (b) and 3 (c), the portions corresponding to the first pixel dot and the third pixel dot are blank, and the hatched portion (second pixel dot) is a portion forming a 1-dot vertical line. Equivalent to. Due to the deviation of the optical scanning speed of the polygon scanner, for example, an inter-pixel dot shift 302 of 1/8 dot (corresponding to one pulse of the source clock) occurs between the n line and the n + 1 line at the second pixel dot. To do.

  At the time of correction execution, in order to generate the image clock 303 corresponding to the blank portion (first pixel dot) where no pixel dot is formed, the multiplication number of the first pixel dot is set so as to be shortened by one pulse of the source clock. Control. That is, the arbitrary multiplication number dividing unit 30 can match the rising timings of the image clocks in the n and n + 1 lines by controlling the uncorrected multiplication number 8 to be changed to the multiplication number 7. . As a result, the inter-line pixel dot deviation 302 that occurs during uncorrection can be eliminated by executing correction.

  FIG. 3C shows an example of a change in which the multiplication number is reduced from 8 to 7. Without being limited to this example, the arbitrary multiplication number dividing unit 30 increases (changes) the multiplication number of the image clock 303 corresponding to the blank portion not forming the pixel dot, for example, the multiplication number 8 to the multiplication number 9, Control of delaying the output of the image clock in the n + 1 line is also possible.

  Further, by combining with PWM modulation under the control of the CPU 55, pixel dot position correction can be executed in units of 1 / n (n ≧ 2) integer dots. Further, the dot width of the pixel dots to be formed can be corrected by the original function of PWM, and the positions of the pixel dots to be formed can be corrected by combining these. As described above, FIGS. 3A to 3C describe the case where the position of one pixel is corrected independently for each pixel unit.

  In addition, the correction control timing for forming pixel dots, which is different from FIG. 3A, will be described below with reference to FIGS. 3B (a) to 3 (c).

  First, as shown in FIG. 3B (a), the polygon rotational speed unevenness (measured rotational speed unevenness) shown here is an example assumed for easy explanation of the present invention. The polygon rotation speed cycle is not necessarily a fixed value, and may vary depending on the device, the environment, or the date and time.

  The sine wave (Sin wave) shown in FIG. 3B (a) indicates polygon rotation speed unevenness, and the corresponding polygon surface number is assigned to the scanning surface of the polygon mirror at that time. In FIG. 3B (a), a case will be described in which there is a phase relationship in which the polygon rotational speed unevenness is one cycle and that there is one cycle for six polygons. Essentially, the polygon rotation speed irregularity operates asynchronously in the phase relationship with the polygon mirror surface, so it does not necessarily have the phase relationship shown in the figure, but maintains a random phase relationship. It is. FIG. 3B (a) shows the phase relationship in one of the polygonal surfaces corresponding to the timing of one polygon rotation speed unevenness at random. The polygon rotation speed unevenness portion indicated by (1) in the figure gradually changes from the set value of the polygon rotation speed to a faster rotation. As a result, as shown in (1) of FIG. 3B (b), a one-line image is formed which is contracted from the distance surrounded by the dotted line indicating the case where the speed is constant. Furthermore, since each pixel has a predetermined fixed multiple of the source clock, the length of each pixel gradually decreases as well. That is, in the case of the polygon rotation speed unevenness of (1), the formed dots are formed smaller at the end of the line, and the image length of the entire formed line is shortened. Similarly, the polygon rotation speed unevenness portion indicated by (2) in the figure continues to change from the polygon rotation speed at the end of the polygon rotation speed (1), and gradually changes rapidly. The speed gradually decreases. As a result, as shown in (2) of FIG. 3B, a one-line image that is further shrunk from the distance surrounded by the dotted line indicating the case where the speed is constant is formed. Since each pixel has a predetermined fixed multiple of the source clock, the pixel length of the central portion of the entire line is formed to be the smallest, and the pixel dots gradually spread toward both sides. In the case of (2) polygon rotation speed unevenness, line image formation is completely different from the formation dot rhythm shown in (1).

  In FIG. 3B (b), a scanning rhythm difference for each line for one period of polygon rotation speed unevenness from (2) to (3) to (7) is expressed. As can be seen from the figure, the image length of each line changes like a sine wave according to the degree of polygon rotation speed unevenness shown in FIG. 3B (a). In other words, if the source clock multiplication is set to a uniform fixed value as in the past, the polygon rotation speed unevenness may appear in the image as it is, and the polygon rotation speed unevenness is not noticeable. In some cases, they were screened for use. According to the present embodiment, a high-quality image can be obtained without doing this.

  The control corresponding to the case described above is shown in FIG. As in the case described with reference to FIG. 3A, a case will be described in which the set standard multiplication number of the source clock for generating the image clock is set to 8. Each pixel is based on a multiplication factor of 8. Then, the CPU 55 sets the multiplication number according to the polygon rotation speed.

  That is, pixel dot formation is executed by the image clock generated by multiplying by 8 at the specified scanning speed. In the case of a polygon rotation speed change as indicated by (1) in FIG. 3B (a), as shown by (1) in FIG. 3B (c), correction control is performed while gradually making the multiplied value correspond to the speed deviation gradient. Just do it. That is, since the degree of change in the polygon rotation speed is reflected in the degree of change in the scanning speed, the multiplication number of the source clock that generates the image clock may be corrected according to the degree of change. That is, in the case of the polygon rotation speed unevenness of (1) to (7) in FIG. 3B (a), image formation is executed while correcting the multiplication number as shown in (1) to (7) of FIG. 3B (c). This will give a good image. As a result, the synchronization shift between lines is eliminated, and good image formation becomes possible.

  (5) Next, with reference to FIG. 4, as an explanation relating to the correction process of the dynamic deviation characteristic, the real-time deviation detector 75 in FIG. 1 detects the BD signal width (number of source clocks). Explain what you are doing.

  With reference to FIG. 4 and FIG. 5, it will be described that dynamic deviation information is detected in real time (asynchronously with the polygon surface period) and position correction or width diameter correction of pixel dots to be formed is performed. 4A, reference numeral 100 is a light receiving element, reference numeral 110 is a photoreceptor (corresponding to reference numeral 822 in FIG. 8), and reference numeral 120 is a laser light source capable of irradiating a laser. Reference numeral 130 denotes a scanner device, which includes a polyhedral polygon mirror 140 (rotary scanning mechanism) that is a rotating body for optical scanning, and a motor that rotates the polygon mirror 140 at a predetermined rotational speed. Laser light emitted from the laser light source 120 is reflected by the polygon mirror 140 and guided to the photoconductor 110. The light receiving element 100 is disposed in the vicinity of the photoconductor 110 and can receive the laser light at a timing immediately before the laser beam is guided to the photoconductor 110. When the light receiving element 100 receives laser light, it outputs a BD signal as its detection signal. This BD signal output corresponds to the “BD signal” shown in FIGS.

  When the surface length distance of each surface of the polygon mirror 140 is zero error (static deviation = 0) and the rotation speed is rotating at a constant speed (dynamic deviation = 0), the source clock and the light sensitive to the BD signal are detected. The position on the body 110 can always indicate a certain position. That is, it becomes possible to form pixel dots without causing a positional shift between lines. According to the timing based on the image clock divided by the source clock, the pixel dots on the photoconductor 110 formed by the irradiated laser light are formed at the same position in all lines.

  However, if a rotational deviation of the polygon mirror 140 (rotary scanning mechanism) occurs as a dynamic deviation characteristic, a BD signal having the same signal width cannot be detected.

  FIG. 4B is a diagram exemplarily showing the relationship between the source clock when a dynamic deviation occurs and the BD signal width in each line (n + 0 to n + 6). The dynamic deviation characteristic is as described above.

  The real-time deviation detector 75 can count the number of source clocks output from the horizontal synchronous high-frequency clock generator 20 and detect the BD signal width (the number of pulses of the detection signal (source clock)). The real-time deviation detection unit 75 inputs this detection result to the deviation conversion unit 70. The deviation conversion unit 70 converts the input source clock number (BD signal width (number of pulses of the detection signal (source clock))) into time, and transfers the conversion result to the CPU 55 as conversion data. In the present embodiment, based on the number of source clocks detected by the real-time deviation detector 75, the source clock is divided by the arbitrary multiplication frequency divider 30 according to the dynamic deviation characteristic. Details will be described later.

  (6) Next, with reference to FIG. 5, a description will be given of how the dynamic deviation characteristic is specifically corrected and the arbitrary multiplication frequency divider 30 outputs the corrected image clock. Do.

  The CPU 55 generates correction data corresponding to the time converted value corresponding to the BD signal width (the number of pulses of the detection signal (source clock)) and stores it in the lookup table. In this lookup table, when the number of surfaces of the polygon mirror 140 (rotary scanning mechanism) is “6”, the first measurement surface data is n + 0, and the number of surfaces (N) is n + 1, n + 2,. Can be classified according to

  In FIG. 5B, the polygon mirror 140 (rotary scanning mechanism) of the scanner device 130 is exemplified as having 6 faces. When the polygon mirror 140 (rotary scanning mechanism) rotates, the rotation frequency of the polygon mirror rises as shown in FIG. 5A, and then the rotation frequency (rotation speed) converges to the clock frequency.

  However, as described above, even if adjustment is performed by a balancer, deviation occurs at a certain range speed in a certain time period. This variation is the dynamic deviation characteristic described above.

  FIG. 5C shows a state in which the deviation portion is divided and enlarged in one cycle. The rotation frequency (speed) of the polygon mirror has a deviation in which the rotation speed is increased or decreased relatively longer than the polygon surface period. In other words, the rotational frequency (speed) of the polygon mirror increases and decreases with a longer period than the switching period of each surface of the polygon mirror 140 (rotary scanning mechanism).

  The real-time deviation detector 75 counts the number of source clocks at a specific timing at which the image forming apparatus operates, and detects the BD signal width (the number of pulses of the detection signal (source clock)). Then, the deviation conversion unit 70 converts the input source clock number (BD signal width (number of pulses of the detection signal (source clock))) into time, and transfers the conversion result to the CPU 55 as conversion data. The CPU 55 can obtain dynamic deviation characteristic information from the input time conversion. Then, the CPU 55 specifies the correction data of the dynamic deviation characteristic information, and each time the correction data for correcting the position of the formed pixel dot for one line is corrected for each surface of the polygon mirror 140, the clock rate instruction FIFO memory unit. 50.

  More specifically, the CPU 55 supplies correction data corresponding to the time-converted data input from the correction execution lookup table stored in advance in the device deviation memory unit 60 to the clock rate instruction FIFO memory unit 50 for each pixel dot formed. accumulate. The clock rate instruction FIFO memory unit 50 writes the correction data in the divided integer value information storage unit 35 for each formed pixel dot at the time of actual line formation. The arbitrary multiplication frequency divider 30 divides the source clock by an arbitrary integer value based on the correction data written and updated for each pixel dot in the divided integer value information storage unit 35, and outputs an image clock. . The image clock output from the arbitrary multiplication frequency divider 30 reflects the correction data. By executing image formation based on the image clock, the synchronization deviation between lines is eliminated, and good image formation is achieved. Is possible.

  The pulse width of the BD signal (time corresponding to a certain number of source clocks) described in this correction control corresponds to time by measuring the raw signal of the light receiving element that receives the BD signal. The light receiving time of light scanned on the same light receiving element surface length is determined in proportion to the light scanning speed. That is, the difference in the optical scanning speed appears in the difference in the pulse width of the BD signal emitted from the light receiving element. At this time, when the period time is longer than the time for scanning one line of the image (BD signal period) as in the polygon rotation speed unevenness, the change in the scanning unevenness in one line is comparatively gentle. For this reason, if the inclination of a part of one line can be specified, the change degree for all lines can be calculated. At this time, as shown in FIG. 4B, the time phase at the end of the BD signal is the same as the phase of one cycle of the polygon rotation speed unevenness.

  (7) In the following, description will be given of arithmetic processing up to which the arbitrary multiplication number dividing unit 30 generates a corrected image clock.

  Specifically, the expansion / contraction of the line image (image recorded over one main scanning line) is calculated (dynamic deviation characteristic calculation method described in the present invention) to correct the multiplication number of the source clock. The means for calculating the image clock cycle time length will be described.

  In general, the rotational speed of a motor that drives a polygon mirror is controlled within a certain range so that the motor rotates at a constant speed by servo control or the like. However, in reality, polygon rotation speed unevenness as shown in FIG. 3B (a) occurs due to the factors described in the above description of the dynamic deviation characteristics.

  The polygon rotation speed cycle shown in FIG. 3B (a) is determined by an optical scanning system unit called an optical box incorporated in the apparatus. The polygon rotation speed changes depending on individual motors that control the rotation of the polygon mirror and its control system circuit. Deviation (peak value) and width (frequency) are determined.

  That is, the variation deviation amount (peak value) and width (frequency) called polygon rotation speed unevenness are values peculiar to individual optical box units attached to the apparatus. Once attached to the device, although there are some differences due to temperature changes during operation, etc., the rotation speed unevenness of this polygon mirror is fixed and does not fluctuate in general, and the above-mentioned period specific to the optical box unit is repeated. As a result, it appears in the image with a constant rhythm. Except for the occurrence of malfunctions and malfunctions, etc., there are usually differences in the degree of control variation, but the errors are negligible, and they do not change in the big picture.

  Therefore, the rotational speed unevenness information of the polygon mirror specific to the optical box unit attached to the apparatus just described is measured and stored in the attached apparatus deviation memory unit 60 in advance as a static deviation characteristic. That is, the apparatus deviation memory unit 60 stores in advance information on the rotational speed unevenness of the polygon mirror of the Sin wave (speed change in one cycle time amount) illustrated in FIG. 3B (a). Then, using the sine wave stored in advance in the device deviation memory unit 60, the CPU 55 sets the correction multiplication number as follows.

  1. First, the real-time deviation detection unit 75 detects the width time length of the BD signal by counting the number of source clocks output from the horizontal synchronization high-frequency clock generation unit 20. Here, BDl (n) is assumed for convenience. n indicates the number of faces. Then, the CPU 55 calculates the average of them as BDlav based on BDl (n) detected while the polygon mirror rotates a plurality of times, and stores it in the apparatus deviation memory unit 60. This BDlav is, for example, measured in advance when the image forming apparatus is activated, or stored in the apparatus deviation memory unit 60 in advance as an ideal value measured at the factory.

  2. The CPU 55 obtains the average of the maximum values detected for each predetermined period from BDl (n) as BDlmax and stores it in the device deviation memory unit 60. Note that the calculation timing of BDlmax is the same as that of BDlav. Then, a coefficient for normalizing the sine curve of BDl (n) is obtained from the obtained BDlav and BDlmax by the following equation.

BDreg = 1 ÷ (BDlmax−BDlav) (1)
3. The device deviation memory unit 60 stores a sine wave shown in FIG. 3B (a) in advance. For comparison with BDl (n) described later, the amplitude is normalized to ± 1.

  4). Then, Equation (3) is obtained from the relationship of Equation (2).

(BDl (n) −BDave) × BDreg = y = sin θ (2)
θ = sin ⁻¹ ((BD1 (n) −BDave) × BDreg) (3)
5. On the other hand, a change in the width time length of the BD signal in FIG. 4B is recorded, and the change amount is set to ΔBDl (n).

  As shown in FIG. 3B (b), the extension of the length of one scanning line appears in the BD signal width (pulse time width (number of source clocks)) shown in FIG. 4 (b). The element width of the light-receiving element that detects the beam that is the source of the BD signal (specifically, the element width that is received by the 5 mm square chip) and the scanning length of one line are not variable lengths. That is, the scanning speed deviation amount appears as a BD signal width at a similar ratio. That is, a variation similar to the polygon rotation speed unevenness (dynamic deviation characteristic) that can be approximated to the Sin wave shown in FIG. 5 appears in the width of the BD signal. Therefore, the phase of the polygon rotational speed unevenness can be specified from the transition state of the change in the amount of the BD signal width, and how the polygon rotational speed changes in the line length can be predicted in real time.

  6). And CPU55 calculates | requires (theta) in real time by the following calculations.

  If ΔBDl (n)> 0, the value in the range of (−1/2) π <θ <(1/2) π among the phases obtained from the equation (3) is defined as θ.

  If ΔBD1 (n) = 0 and ΔBD1 (n−1)> 0, θ = (1/2) π obtained from equation (3).

  If ΔBD1 (n) = 0 and ΔBD1 (n−1) <0, θ = (− 1/2) π obtained from the equation (3).

  If ΔBDl (n) <0, the value in the range of (1/2) π <θ <(− 3/2) π among the phases obtained from the equation (3) is defined as θ.

  7). Further, the apparatus deviation memory unit 60 stores in advance an array table in which the θ section is divided into sections at predetermined intervals and an array of multiplication numbers is assigned to each section in advance.

  8). The CPU 55 reads the arrangement table from the device deviation memory unit 60,5. The θ obtained by the above operation is compared with the arrangement table. Then, the section in which θ is included is specified, the array value of the multiplication number assigned thereto is read, and correction data for correcting the position of the formed pixel dot for one line is generated. Further, the CPU 55 accumulates the generated array value as correction data in the clock rate instruction FIFO memory unit 50 for each formed pixel dot. The result is shown in FIG. 3B (c).

  The sampling time for inferring the change in the polygon rotation speed from the change in the pulse width time amount of the BD signal is set as the preliminary operation for starting the printing operation, and the printer main body instructs the polygon rotation to perform scanning. Start up to speed. When the polygon rotation speed reaches the set value, a scanner ready signal is issued to indicate that the optical scanning speed is locked within a certain range. After that, the paper is fed, the operation for image formation is started, and when a predetermined number of copies are printed, the operation is stopped. The time required from when the scanner ready signal is issued to the start of image formation is at least several seconds. Since this time of several seconds is equivalent to several thousand shots for the BD signal (required time per line), it is sufficient time to execute control for sampling, calculating, and confirming the polygon rotation speed change. ing. Therefore, it can be inferred from the transition of the change in the amount of BD signal width without any problem how the polygon rotation speed period changes for the line length.

(Effect of 1st Embodiment)
As described above, since the source clock is started by the circuit shown in FIG. 2, the amount of quantization error when synchronizing the horizontal synchronizing signal and the image clock can be reduced.

  Further, after reducing the quantization error amount, a multiplication number for generating an image clock is set according to the BD signal width detected by the real-time deviation detector 75, and synchronization between lines is more accurately performed. Displacement is eliminated and good image formation becomes possible.

(Second Embodiment)
In the second embodiment, first, the operation of the transmission delay type oscillation circuit 21 configured by a DDL circuit using the transmission delay of the digital gate circuit in the configuration example of the horizontal synchronous high frequency clock generation unit 20 described in FIG. This will be explained in detail. Next, the frequency stabilization means for the source clock, which is a feature of this embodiment, will be described with reference to FIG.

  FIG. 6 is a diagram exemplarily showing operation timing for explaining the DDL circuit characteristics for easily explaining the frequency stabilization correction means of the source clock in the present embodiment.

  FIG. 6A shows a transmission delay type oscillation circuit 21 in a horizontal synchronous high-frequency clock generation unit 20 that generates a source clock based on a video enable signal indicating an allowable range of a video signal output from the line area instruction unit 10. The example of a specific circuit is shown. Note that the video enable signal is expressed as Video-Enable in FIG.

  As shown in FIG. 6B, when the video enable signal changes to enable (in the region where Video-Enable is high level), the transmission delay oscillation circuit 21 changes the multivibrator oscillation to the leading edge of the BD signal. Oscillation starts in synchronization with. When the video enable signal is disabled (in the region where Video-Enable is low level), the oscillation operation of the transmission delay oscillation circuit 21 is stopped. As shown in FIG. 6A, the oscillation frequency is a repetition of signal transmission between a transmission delay a that is a signal transmission required time of the NAND gate circuit and a transmission delay b that is a signal transmission required time of the OR gate circuit. Thus, oscillation is generated as shown in FIG. Since this transmission delay time is already known, it is not particularly shown, but is determined by the circuit form constituting the gate circuit, the amount of voltage applied to the basic transistor constituting the IC, and the stray capacitance. Although there is a thermal factor in the transmission delay time, it is related to the influence of the relative positional deviation between the lines in the case of the scanning optical system of this apparatus. Since the time difference scale is too different from the fluctuation and the influence of heat is not a problem, the explanation is omitted. In this embodiment, the transmission delay type oscillation circuit 21 is configured with the circuit configuration shown in FIG. With the mechanism in which the frequency of the source clock that is oscillated and output is determined in accordance with the supply power supply voltage supplied to the transmission delay type oscillation circuit 21, as shown in FIG. Multivibrator oscillation will be repeated.

  Next, the frequency stabilization correcting means of the source clock will be described with reference to FIG. FIG. 7 is a diagram showing a configuration example which is another form of the above-described horizontal synchronous high frequency clock generation unit 20, and basically uses a general digital multivibrator circuit shown in FIG.

  The horizontal synchronous high frequency clock generation unit 20 includes the above-described transmission delay type oscillation circuit 21 and frequency stabilization correction circuit 22. As described above, the object is to detect the frequency of the source clock output from the transmission delay oscillation circuit 21 in real time and to control the supply voltage to the transmission delay oscillation circuit 21 in an analog manner. In order to achieve this object, the present invention is not limited to the frequency stabilization correction circuit 22 shown in FIG. That is, the frequency voltage conversion circuit 23 converts one cycle time of the source clock frequency output from the transmission delay type oscillation circuit 21 into a voltage value. The voltage comparator 24 compares a predetermined reference voltage value corresponding to the set frequency value of the source clock with the converted voltage in real time. The reference voltage value is not particularly described in the present embodiment, but can be set by the CPU 55 so that the CPU 55 can perform correction control according to the environment and state of the apparatus or by correcting the formed image. It is configured.

  The voltage comparator 24 digitally determines whether the source clock frequency is high or low, and outputs the analog voltage value to the power supply generator 26 for each step. As a result, the supply power generator 26 supplies a desired voltage value to the transmission delay type oscillation circuit 21. The frequency stabilization correction circuit 22 referred to in the present embodiment does not directly correct the set frequency value directly, but determines whether it is higher or lower than the set frequency value at the time of detection. Based on this determination, so-called convergence correction control is performed in which a desired value in which the supply voltage value is set in advance is set as one step and the voltage value is continuously changed. As a result, the rapid frequency change of the source clock is suppressed, the image clock fluctuation of several hundred to several tens of times of the source clock is gradually eased, and the position correction of the formed image is difficult to notice with human eyes. This is correction control for the purpose of doing so.

(Effect of 2nd Embodiment)
As described above, if the horizontal synchronous high-frequency clock generation unit 20 is configured by the transmission delay type oscillation circuit 21 and the frequency stabilization correction circuit 22 shown in the present embodiment, a desired value is selected for the frequency of the source clock of the DLL circuit. The problem of doing (fine adjustment) can be solved. The oscillation clock frequency value can be automatically handled in a uniform process without adjusting the device at the time of shipment.

  As a result, a source clock having a stable frequency value that can be finely adjusted by the CPU 55 is output from the horizontal synchronization high-frequency clock generation unit 20 to the arbitrary multiplication frequency divider 30. The image clock output from the arbitrary multiplication frequency divider 30 reflects the correction data. By executing image formation based on the image clock, the synchronization deviation between lines is eliminated, and the image clock is excellent. Image formation becomes possible.

1 is a block diagram showing a functional configuration of an image forming apparatus according to an embodiment. 3 is a diagram illustrating a configuration example of a horizontal synchronization high frequency clock generation unit 20. FIG. It is a figure which shows the timing of the correction control which forms a pixel dot exemplarily. It is a figure which shows the timing of the correction control which forms a line image exemplarily. It is a figure explaining correction | amendment of the dynamic deviation characteristic in 1st Embodiment. It is a figure explaining correction | amendment of the dynamic deviation characteristic in 1st Embodiment. FIG. 6 is a diagram for explaining the operation of a horizontal synchronization high-frequency clock generation unit 20. It is a figure which shows the structural example of the horizontal synchronous high frequency clock generation part in 2nd Embodiment. 1 is a diagram exemplifying a schematic configuration of an image forming apparatus according to an embodiment of the present invention.

Explanation of symbols

10 Line area instruction unit 20 Horizontal synchronous high frequency clock generation unit 30 Arbitrary multiplication frequency division unit 35 Frequency division integer value information storage unit 40 Line elapsed position recognition counter unit 55 CPU
70 Deviation conversion unit 76 Image forming unit

Claims (5)

A rotating scanning mechanism that scans the laser beam with a rotating mirror, a reference clock output unit that outputs a reference clock, and the output reference clock based on a set multiplication number, and the image clock is divided by the frequency division. an image clock generating means for generating, the rise of the detecting means for detecting a synchronization signal for rotation synchronization of the optical scanning start timing by the laser beams scanned by the scanning mechanism, before Symbol synchronization signal detected by the detection means a width detecting means for detecting a width of up to falling from, based on the width of the front Symbol said synchronization signal detected by the width detection means, have a, a correction means for correcting the multiplication number, detected by the detection means The surface to be scanned is irradiated with a laser beam based on the generated synchronization signal and the image clock generated by the image clock generation means. An image forming apparatus which performs scanning,
The image forming apparatus according to claim 1, wherein the correction unit corrects the multiplication number so that the multiplication number changes during one line scanning on the surface to be scanned . Based on the detection result of the width detection means, further has a calculation means for calculating the fluctuation of the scanning speed of the laser beam,
The image forming apparatus according to claim 1, wherein the correction unit corrects the multiplication number based on a fluctuation in a scanning speed of the laser beam obtained by the calculation unit. Wherein by irradiating the laser beam after scanning one line on the surface to be scanned, a light emitting means for emitting a laser beam to said detecting means to generate the synchronization signal, the synchronization signal the synchronization signal is input It further has an input means,
The reference clock output means, said in response to the synchronization signal to the synchronization signal input means is input, the image forming apparatus according to claim 1 or 2, and outputs the reference clock. Said width detection means, the width from the rise of the synchronizing signal to the fall, according to claim 1, wherein the obtaining the number of the reference clock included between leading edge of the sync signal to the fall The image forming apparatus according to claim 1.   The image forming apparatus according to claim 1, wherein the detection unit is a single light receiving element.

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