JP4313132B2 - Pixel clock generation circuit, pixel clock and pulse modulation signal generation circuit, optical scanning apparatus, and image forming apparatus - Google Patents

Description

  The present invention relates to generation and phase control of a pixel clock in an image forming apparatus such as a laser printer and a digital copying machine, and more particularly to generation of a pixel clock and a pulse modulation signal. The present invention relates to a generation circuit, a pixel clock and pulse modulation signal generation circuit that generates a pulse modulation signal optimal for modulating the light output of a light source, and an optical scanning device and an image forming apparatus that constitute each circuit.

  FIG. 37 shows a conventional image forming apparatus. The figure shows a general configuration in an image forming apparatus such as a laser printer or a digital copying machine. Laser light emitted from a semiconductor laser unit 1001 as a light source is scanned by a rotating polygon mirror 1002 and passes through a scanning lens 1003. Then, a light spot is formed on the photoconductor 1004 that is a medium to be scanned, and the photoconductor 1004 is exposed to form an electrostatic latent image. At this time, a phase-synchronized image clock (pixel clock) is generated for each line based on the output signal of the photodetector 1005 and supplied to the image processing unit 1006 and the laser drive circuit 1007. In this way, the semiconductor laser unit 1001 controls the emission time of the semiconductor laser according to the image data generated by the image processing unit 1006 and the image clock whose phase is set for each line by the phase synchronization circuit 1009. The electrostatic latent image on the scanned medium 1004 is controlled.

  In such a scanning optical system, variations in the distance from the rotation axis of the deflecting / reflecting surface in a deflector such as a polygon scanner cause uneven scanning speed of a light spot (scanning beam) that scans the surface to be scanned. This uneven scanning speed causes fluctuations in the image and degradation in image quality. Accordingly, when high quality image quality is required, it is necessary to correct scanning unevenness.

  Furthermore, in the case of a multi-beam optical system having a plurality of light sources, if there is a difference in the oscillation wavelength of each light source, an exposure position shift occurs in the case of an optical system in which the chromatic aberration of the scanning lens is not corrected, The scanning width when the spot corresponding to the light emitting source scans the scanned medium is different for each light emitting source. This becomes a factor of image quality deterioration, and the scanning width needs to be corrected. The occurrence of scanning unevenness due to the optical system has different characteristics on the scanning line depending on the characteristics of the optical system.

  Conventionally, the technique for correcting the above-described scanning unevenness or the like is basically a method of controlling the position of the light spot along the scanning line by changing the frequency of the pixel clock (see Patent Documents 1 and 2). .

  As another technique, as shown in FIG. 38, the scanning speed is detected by counting the number of clocks between the photo detector A 1107 and the photo detector B 1108 installed at both ends of the photoconductor 1105, and the polygon mirror 1104 is rotated. There is a way to control the speed.

  On the other hand, as a method for modulating the light output of the light source, there are a power modulation method for modulating the light amount itself, a pulse width modulation method for modulating the lighting time of light, and a power / pulse width mixed modulation method in which both are combined. Among them, the pulse width modulation method is generally widely used. As this method, for example, a triangular wave or a sawtooth wave corresponding to each pulse generation period is generated, and each waveform is compared with an analog video signal using a comparator. A method has been proposed in which a delay pulse is generated by generating and digitally dividing the clock, and a pulse width modulation signal is generated by the logical sum or logical product (see Patent Document 3).

  Further, in an image forming apparatus that performs gradation representation of an image by pulse width modulation, a means for determining a delay amount based on an input image signal based on a predetermined reference clock signal, and a delay time set in the delay amount There has been proposed an image forming apparatus including a means for generating a signal having a delayed predetermined pulse width and performing the pulse width modulation in accordance with the signal having the predetermined pulse width (see Patent Document 4).

  Further, for example, in the configuration of FIG. 38, there is also a method of controlling the position of the light spot by counting the time interval between two detection signals with a high frequency clock and shifting the phase of the write clock based on this count information (patent). Reference 5).

Japanese Patent Laid-Open No. 11-167081 Japanese Patent Laid-Open No. 2001-228415 Japanese Patent Laid-Open No. 2001-15853 JP-A-6-284276 JP 2002-36626 A

  However, the conventional method (frequency modulation method) that changes the frequency of the pixel clock generally has a complicated configuration of the pixel clock control unit, and becomes more complicated as the frequency modulation width becomes minute, so that high-precision control is possible. Is difficult. Even with a light beam deflected by the same deflecting and reflecting surface of the deflector, uneven scanning speed occurs due to the rotation jitter of the deflector and the expansion and contraction of the scanning lens due to temperature change, and controls the rotation motor of the deflector. In this method, there is a limit to the accuracy of control.

  On the other hand, in recent years, the operating speed of image forming apparatuses such as laser printers and digital copiers has been increased. However, when a triangular wave or sawtooth wave is used in a pulse modulation circuit that generates image forming timing, a triangular wave or sawtooth wave is used. The linearity / reproducibility of the system and speeding up the operation are not compatible. Further, in the case of a frequency dividing circuit using a high frequency clock after digitally dividing, the maximum operating frequency depends on the device, and the gradation of the image and the increase in the operating speed are not compatible. For example, in order to realize 256-value modulation with a pulse width of 50 MHz with a pulse width, it is difficult to generate a triangular wave or a sawtooth wave having a good linearity and swing in a period of 20 ns, and 50 MHz × 256 = 12.8 GHz. It is also difficult to realize a digital frequency dividing circuit that generates a clock for the above.

The present invention has been made in view of the above problems,
An object of the present invention is to provide a pixel clock generation device that can control the phase of a pixel clock with high accuracy with a simple configuration, reduce scanning unevenness, and correct fluctuations in scanning width.

  Another object of the present invention is to generate a pixel clock that enables high-accuracy phase control with a simple configuration, and to arbitrarily generate a pulse modulation signal having a desired pattern with a simple configuration. An object of the present invention is to provide a pixel clock generation and pulse modulation signal generation circuit capable of reducing scanning unevenness even when the height is high, correcting fluctuations in scanning width, and realizing high gradation of an image.

  Still another object of the present invention is to provide an optical scanning device and an image forming apparatus equipped with the above-described pixel clock generation device.

Pixel clock generating circuit of the present invention, a high-frequency clock generating means for generating a high frequency clock, the reference pixel clock based on the phase data for instructing a transition timing of the high frequency clock and the reference pixel clock output from the high-frequency clock generating means produced, also, a reference pixel clock generating means for varying the period of the reference pixel clock, a reference pixel clock generated by the reference pixel clock generating unit generates the pixel clock of two or more of the plurality of reference pixel clock Based on that.

The pixel clock and pulse modulation signal generation circuit according to the present invention is based on high-frequency clock generation means for generating a high-frequency clock, and phase data indicating the transition timing of the high-frequency clock and the reference pixel clock output from the high-frequency clock generation means. generates a reference pixel clock, also a reference pixel clock control means for varying the period of the reference pixel clock, two or more reference pixel clock generated by the reference pixel clock control means of successive reference pixel clock as pixel clock Clock generation means for generating and serial modulation signal generation means for inputting modulation data representing a desired bit pattern corresponding to image data, converting the modulation data into a serial pulse train based on the high frequency clock, and outputting a pulse modulation signal The main feature is to have

  Further, the pulse modulation signal generation circuit of the present invention receives a high frequency clock generation means for generating a high frequency clock, modulation data representing a desired bit pattern, converts the modulation data into a serial pulse train based on the high frequency clock, The main features are a serial modulation signal generating means for outputting a pulse modulation signal and a pulse train control means for changing the number of pulse trains per pulse modulation signal.

  Further, by mounting the pixel clock generation device with improved phase accuracy of the write clock of the present invention in the optical scanning device and the image forming device, for example, a periodic pixel clock for determining one dot or one pixel is used. Therefore, it is possible to form an image at a high speed with a flexible time width.

(1) A configuration in which two or more consecutive reference pixel clocks are defined as one pixel or a pixel clock and the phase of the pixel clock is shifted improves the phase shift accuracy per pixel, and has a relatively simple configuration. This makes it possible to control the phase of the pixel clock with higher accuracy.
(2) The configuration for generating the transition timing of the reference pixel clock in synchronization with the transition of the high-frequency clock enables the phase control of the pixel clock to be controlled in finer steps without requiring a high-frequency clock.
(3) With a configuration in which the cycle of the reference pixel clock is changed in one clock step of the high-frequency clock, it is possible to control the phase of the pixel clock with higher accuracy.
(4) Since the cycle of the reference pixel clock changes in half clock steps of the high-frequency clock, more accurate pixel clock phase control can be realized in fine steps.
(5) Phase control can be performed with high accuracy based on the comparison result between the count value obtained by counting the high frequency clock and the phase data in synchronization with the high frequency clock.
(6) By providing the phase shift amount data with a bit width corresponding to the phase shift amount that is actually controlled, the phase shift amount data can be provided with a small bit width.
(7) By storing the phase shift amount data and calling the phase shift amount data at the timing of the pixel clock, the load on the external circuit can be reduced.
(8) Pixel clock phase control can be freely performed for each pixel and for each line. By storing the same phase shift amount data at the same pixel position for at least one line and outputting the same phase shift amount data at the same pixel position of each line, the load on the external circuit can be reduced. For example, not only the same correction is always performed for each line that corrects the scanning unevenness caused by the characteristics of the scanning lens, but also a correction that changes for each line such as a rotation unevenness of the polygon mirror can be handled.
(9) With respect to two or more consecutive reference pixel clocks, one phase shift data is given for one specific reference pixel, so that even a linear velocity exceeding the upper limit frequency of the pixel clock is changed to a pixel clock by phase shift. This makes it possible to control the phase of the pixel clock with high accuracy.
(10) A high-accuracy pixel that can cope with a case where the phase variation of the pixel clock is large by giving two or more phase shift data of two or more consecutive reference pixel clocks to a specific pixel. The clock phase can be controlled.
(11) With the phase shift data correction method that changes the pixel clock that provides the phase shift data for each line, it is possible to obtain a high-quality image with a small amount of dot position deviation in the main scanning direction, and perform phase shift. By generating the pixel clock at the same clock timing in the sub-scanning direction, it is possible to prevent the formation of a vertical stripe image that appears in the sub-scanning direction, and to control the phase of the pixel clock with high quality.
(12) By giving phase shift data to non-consecutive reference pixels, it is possible to prevent the occurrence of image bias, distortion, etc. that occur when pixel clocks that perform phase shifting are continuous, for example. High-quality pixel clock phase control is possible.
(13) By applying the pixel clock generation device of the present invention to an optical scanning device, it is possible to control scanning light with high accuracy.
(14) By applying the pixel clock generation device of the present invention to an optical scanning device having a plurality of light sources, an optical scanning device with little main scanning dot position deviation can be realized even in a high-speed machine. Furthermore, dot position shift in the main scanning direction due to exposure shift caused by oscillation wavelength error between light emitting sources can be realized with a control circuit that does not complicate the synchronization circuit and phase shift circuit and further reduces the memory capacity. Can do.
(15) By applying the pixel clock generation device and the optical scanning device of the present invention to an image forming apparatus, it is possible to control the phase of the pixel clock in finer steps without the need for a high-frequency clock, and the main scanning dot An image forming apparatus with little misalignment can be realized.
(16) By deploying the pixel clock generator or image forming apparatus of the present invention to a tandem color machine, main-scanning dot position shift correction corresponding to each color of cyan, magenta, yellow, and black, and high corrected high An image quality image can be obtained, and color misregistration can be effectively reduced.
(17) A configuration in which two or more consecutive reference pixel clocks are defined as one pixel or pixel clock and the phase of the pixel clock is shifted improves the phase shift accuracy per pixel, and has a relatively simple configuration. The period of the pixel clock can be controlled, and the phase control of the pixel clock with high accuracy and the generation of the pulse modulation signal corresponding to the phase control are possible.
(18) Since the pixel clock transition timing is generated in synchronization with the transition of the high-frequency clock, a high-frequency clock is not required, and the cycle of the pixel clock can be controlled in fine steps with a simple configuration. Further, an arbitrary pulse modulation signal can be generated. Furthermore, a pulse modulation signal that does not affect the image can be obtained.
(19) The pixel clock cycle can be controlled with a simple configuration, and by making the number of bits constituting modulation data variable, an arbitrary pulse modulation signal can be generated and a pulse modulation signal that does not affect the image can be obtained. Can do. In addition, since the pixel clock transition timing is generated in synchronization with the transition of the high-frequency clock, a high-frequency clock is not required, and the cycle of the pixel clock can be controlled in finer steps with a simple configuration.
(20) With a simple configuration, the cycle of the pixel clock can be controlled in fine steps, and a pulse modulation signal that does not affect the image can be generated by a configuration in which the pulse output frequency in the pulse train is constant. Further, according to the pulse width modulation circuit of the present invention, the density of the pulse width modulation can be changed, so that, for example, the gradation in the highlight portion can be improved.
(21) With a simple configuration, the cycle of the pixel clock can be controlled in fine steps, and when changing the number of bits constituting the modulation data, a pulse modulation signal that does not affect the image by changing the pulse output pattern in the pulse train. Can be generated.
(22) The period of the pixel clock can be controlled based on the phase data with a simple configuration, and the modulation data generating means can influence more arbitrary images by a configuration in which the number of bits constituting the modulation data is variable based on the phase data. It is possible to generate a pulse modulation signal that is not performed with high accuracy.
(23) With the configuration in which the modulation data is input in synchronization with the pixel clock, a highly accurate pulse modulation signal synchronized with the pixel clock can be generated.
(24) In pixel clock generation, the same phase shift amount data is stored at the same pixel position for at least one line, and the same phase shift amount data is output at the same pixel position of each line, thereby reducing the load on the external circuit. The pixel clock generation circuit can be configured, and a high-quality image with a small dot position shift amount in the main scanning direction can be obtained. Thus, for example, the same clock phase correction can be performed for each line so as to correct the scanning unevenness caused by the characteristics of the scanning lens. Furthermore, it is possible to cope with corrections that change for each line such as uneven rotation of the polygon mirror. In addition, since the pixel clock for performing phase shift is generated at the same clock timing in the sub-scanning direction, it is possible to prevent the formation of vertical streak images that appear in the sub-scanning direction, thereby enabling high-quality pixel clock phase control. Become.
(25) By giving phase shift data to non-consecutive reference pixels, it is possible to prevent the occurrence of image bias, distortion, etc. that occur when pixel clocks that perform phase shifting are continuous, for example. High-quality pixel clock phase control is possible.
(26) A high-speed pulse modulation signal can be generated with a simple configuration, and even when the operation speed is high, it is possible to realize high gradation of an image. Furthermore, a pulse modulation signal that does not affect the image can be obtained.
(27) By generating a pulse modulation signal that follows the pixel clock and the high-speed pixel clock with a simple configuration and modulating the optical output of the laser light source or the like, it becomes possible to control the scanning light with high precision (28). By applying the present invention to an optical scanning device that performs optical scanning with a plurality of light sources, wavelength error correction for each light source is performed by phase shift or pulse modulation of a pixel clock, thereby achieving high-resolution optical scanning on a scanned medium. Is possible.
(29) By applying the present invention to the image forming apparatus, it is possible to configure a high-resolution image forming apparatus in which the dot position deviation is reduced by the main scanning dot position deviation correction with respect to the position deviation in the main scanning direction.
(30) By developing the present invention in a tandem color machine, color misregistration is performed by allocating main scanning dot position misalignment correction amounts to each color of cyan, magenta, yellow, and black with respect to misregistration in the main scanning direction. It is possible to form a high-resolution color image with reduced image quality.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a first configuration of a pixel clock generation circuit according to Embodiment 1 of the present invention. FIG. 2 shows a time chart of the first embodiment.

  The pixel clock generation circuit according to the present invention generates a pixel clock based on high-frequency clock generation means for generating a high-frequency clock and phase data indicating the transition timing of the high-frequency clock and pixel clock output from the high-frequency clock generation means In addition, it is basically composed of pixel clock generation means for changing the cycle of the pixel clock.

  In FIG. 1, the pixel clock generation circuit 10 includes a high frequency clock generation circuit 11, a counter 12, a comparison circuit 13, a pixel clock control circuit 14, and a clock generation circuit 15. The high frequency clock generation circuit 11 generates a high frequency clock VCLK serving as a reference for the reference pixel clock PCLK. The counter 12 is a counter that operates at the rising edge of the high-frequency clock VCLK and counts VCLK. The comparison circuit 13 compares the value of the counter 12 with a preset value and phase data indicating the phase shift amount as the transition timing of the pixel clock given from the outside, and based on the comparison result, the control signal a and the control signal b Is output. The pixel clock control circuit 14 controls the transition timing of the reference pixel clock PCLK based on the control signal a and the control signal b. Further, the reference pixel clock PCLK is generated by the clock generation circuit 15 configured by a counter circuit or the like so as to become one pixel clock PCLK ′ in units of two or more reference pixel clocks, and finally. The pixel clock PCLK ′ is output.

  Here, the phase data is used to correct the scanning unevenness caused by the characteristics of the scanning lens, to correct the dot positional deviation due to the rotational irregularity of the polygon mirror, and to correct the dot positional deviation caused by the chromatic aberration of the laser beam. Data for indicating the amount of phase shift, and is generally given as a digital value of several bits.

  The operation of the pixel clock generation circuit in FIG. 1 will be described with reference to timing charts in FIGS. Here, the pixel clock PCLK indicates the reference pixel clock, and is divided by 8 of the high-frequency clock VCLK, and the duty ratio is 50% as a standard. FIG. 2A shows how a standard pixel clock PCLK with a duty ratio of 50% corresponding to VCLK divided by 8 is generated. FIG. 2B shows a state in which the pixel clock PCLK having a phase delayed by 1/8 clock with respect to the VCLK divided by 8 is generated. FIG. 2C shows a state in which a pixel clock PCLK having a phase advanced by 1/8 clock with respect to the VCLK divided by 8 is generated. Phase data 7, 8, and 6 correspond to phase shift amounts 0, +1, and -1, respectively.

  First, FIG. 2A will be described. Here, a value of “7” is given as the phase data. In the comparison circuit 13, “3” is set in advance. The counter 12 operates and counts at the rising edge of the high frequency clock VCLK. The comparison circuit 13 first outputs the control signal a when the value of the counter 12 reaches “3”. Since the control signal a is “H”, the pixel clock control circuit 14 changes the pixel clock PCLK from “H” to “L” at the clock timing of the circled number 1. Next, the comparison circuit 13 compares the given phase data with the counter value, and outputs a control signal b if they match. In FIG. 2A, when the value of the counter 12 reaches “7”, the comparison circuit 13 outputs the control signal b. Since the control signal b is “H”, the pixel clock control circuit 14 changes the pixel clock PCLK from “L” to “H” at the clock timing of the circled number 2. At this time, the comparison circuit 13 simultaneously resets the counter 12 and starts counting from 0 again. Thereby, as shown in FIG. 2A, the pixel clock PCLK having a duty ratio of 50% corresponding to the frequency division of the high frequency clock VCLK by 8 can be generated. Note that if the set value of the comparison circuit 13 is changed, the duty ratio changes.

  Further, a pixel clock PCLK ′ composed of two or more reference pixel clock units is generated from the reference pixel clock PCLK by the clock generation circuit 15.

  Next, FIG. 2B will be described. Here, it is assumed that “8” is given as the phase data. The counter 12 counts the high frequency clock VCLK. The comparison circuit 13 first outputs the control signal a when the value of the counter 12 reaches “3”. Since the control signal a is “H”, the pixel clock control circuit 14 changes the pixel clock PCLK from “H” to “L” at the clock timing of the circled number 1. Next, the comparison circuit 13 outputs the control signal b when the value of the counter 12 matches the given phase data (here, “8”). Since the control signal b is “H”, the pixel clock control circuit 14 changes the pixel clock PCLK from “L” to “H” at the clock timing of the circled number 2. At this time, the comparison circuit 13 simultaneously resets the counter 12 and starts counting from 0 again. Thereby, as shown in FIG. 2B, it is possible to generate the pixel clock PCLK whose phase is delayed by 1/8 clock with respect to the divided frequency clock of the high frequency clock VCLK.

  Further, a pixel clock PCLK ′ composed of two or more reference pixel clock units is generated from the reference pixel clock PCLK by the clock generation circuit 15. Consider a case where the pixel clock PCLK ′ is a signal corresponding to two clocks of the pixel clock PCLK. At this time, the relationship between the periods of the pixel clocks PCLK and PCLK ′ can be expressed by the following equation. PCLK × 2 = PCLK ′ Therefore, when the phase is delayed by 1/8 clock in one reference pixel clock, it is equivalent to delaying the clock by 1/16 PCLK ′ with respect to the pixel clock PCLK ′.

  Next, FIG. 2C will be described. Here, “6” is given as the phase data. The counter 12 counts the high frequency clock VCLK. The comparison circuit 13 first outputs the control signal a when the value of the counter 12 reaches “3”. Since the control signal a is “H”, the pixel clock control circuit 14 changes the pixel clock PCLK from “H” to “L” at the clock timing of the circled number 1. Next, the comparison circuit 13 outputs the control signal b when the value of the counter 12 coincides with the given phase data (here, “6”). Since the control signal b is “H”, the pixel clock control circuit 14 changes the pixel clock PCLK from “L” to “H” at the clock timing of the circled number 2. At this time, the comparison circuit 13 simultaneously resets the counter 12 and starts counting from 0 again. Thereby, as shown in FIG. 2C, it is possible to generate the pixel clock PCLK in which the phase is advanced by 1/8 clock with respect to the divided frequency clock of the high frequency clock VCLK.

Further, the reference pixel clock PCLK is generated from the reference pixel clock PCLK by the clock generation circuit 15 in units of two or more reference pixel clocks. Consider a case where the pixel clock PCLK ′ is a signal corresponding to two clocks of the pixel clock PCLK. At this time, the relationship between the periods of the pixel clocks PCLK and PCLK ′ can be expressed by the following equation. PCLK × 2 = PCLK '
Therefore, when the phase is advanced by 1/8 clock in the reference pixel clock, it is equivalent to advancing the clock by the phase of 1/16 PCLK ′ with respect to the pixel clock PCLK ′.

  For example, by providing the phase data in synchronization with the rising edge of the pixel clock PCLK, the phase of the pixel clock PCLK can be changed every clock. Further, by making the number of bits of the phase data the same as the number of count bits of the counter 12, the comparison circuit 13 has a simple configuration.

  FIG. 3 shows a timing chart of each signal of the high frequency clock, the phase data, and the reference pixel clock PCLK. FIG. 4 shows the relationship between the phase data and the phase shift amount.

  When the phase data is changed in synchronism with 00, 01, 01, 11, 11, 00 and the reference pixel clock, the reference pixel clock changes in one clock step of the high frequency clock, and 0, + 1/8 PCLK, + 1/8 PCLK , −1/8 PCLK, −1/8 PCLK, 0, and so on.

  Therefore, the phase of the pixel clock PCLK ′ composed of two or more reference pixel clocks PCLK can also be controlled with high accuracy by the simple configuration described above with the accuracy of the high frequency clock.

  FIG. 5 shows a phase shift correction method by the pixel clock generation circuit of FIG. In the pixel clock generation circuit of FIG. 1, by applying phase data in synchronization with the pixel clock PCLK or PCLK ', the phase of the pixel clock PCLK' can be advanced or delayed.

  When the present invention is applied to the conventional image forming apparatus shown in FIG. 37, the semiconductor laser unit follows the image data generated by the image processing unit and the pixel clock PCLK ′ whose phase is set by the phase synchronization circuit. The electrostatic latent image on the scanned medium can be controlled by controlling the light emission time.

  FIG. 5 shows an electrostatic latent image or a dot image when the horizontal axis is the main scanning direction and the vertical axis is the sub-scanning direction. In the ideal state of FIG. 5A, the dot positions in the ideal state in which the scanning speed unevenness and the exposure deviation as described above do not occur at all are shown, and continuous six dots at 1200 dpi (dot diameter of about 21.2 μm). Is the result of scanning.

  Before the correction in FIG. 5B, the dot position accuracy of the first dot is the same, but the dot position deviation due to the above scanning speed unevenness and exposure deviation has occurred, which is ideal for the sixth dot. It is assumed that a dot position deviation of 10.6 μm, which corresponds to 1/2 dot of 1200 dpi with respect to the state, occurs. In this state, since the time required for writing one dot is 1 pixel clock = 1PCLK ′, when the phase shift resolution is 1/8 PCLK ′, it is synonymous with that the dot position can be corrected with 1/8 dot accuracy. .

  After the correction shown in FIG. 5C, when the phase shift resolution is 1/8 dot, that is, 1/8 PCLK ′, it is −1/8 PCLK ′ from the state before the correction in which the ½ dot position shift occurs from the ideal state. Theoretically, the dot position of the sixth dot can be shifted by −1/8 PCLK ′ × 4 = −1 / 2 PCLK ′ by performing the phase shift on the four reference pixel clocks in the pixel region. Thus, the dot position can be corrected with an accuracy of 1/8 PCLK ′.

  In this way, by shifting the phase of the pixel clock PCLK ′ serving as a reference clock for image data, uneven scanning speed generated by a deflector such as a polygon scanner, or a transmission wavelength difference between light emitting sources in a multi-beam optical system. It is possible to correct the dot position shift in the main scanning direction due to the exposure shift caused by the above with the accuracy of the phase shift.

  FIG. 6 shows the relationship between the pixel clock and the pixel in the present invention. FIG. 6A shows pixel generation and pixel clock PCLK waveforms in the constant speed mode, and FIG. 6B shows pixel generation and pixel clock PCLK ′ waveforms in the half speed mode. As shown in the figure, the constant speed mode is a mode in which the phase of the pixel clock can be advanced or delayed with respect to the reference pixel clock PCLK when one waveform of the reference pixel clock PCLK is defined as one reference pixel. In this embodiment, an example in the case of a phase shift accuracy of 1/8 PCLK is shown.

  When one period of the pixel clock PCLK is defined as one reference pixel, two or more periods, here two periods are defined as one pixel, and a mode in which the phase of the pixel clock can be advanced or delayed is defined as a half-speed mode.

  In the half speed mode, the relationship of the pixel clock PCLK ′ = 2PCLK is established in terms of the period with respect to the reference pixel clock PCLK in the constant speed mode. At this time, the pixel clock PCLK ′ in the half-speed mode outputs the reference pixel clock PCLK in the constant-speed mode through a clock generation circuit such as a counter at the output stage. Therefore, the phase shift accuracy is, for example, ± 1 in the constant-speed mode. When the phase shift resolution is / 8 PCLK, the reference pixel clock cycle is doubled in the half-speed mode, so that the relative accuracy is ± 1/16 PCLK ′. On the other hand, in the half speed mode, it corresponds to two clocks in the constant speed mode in one pixel. Therefore, when the two reference pixel clocks in one pixel are phase-shifted with the same sign, ± 1/16 PCLK ′ The phase can be shifted with respect to one pixel with an accuracy of ± 1/8 PCLK ′, which is twice as large as.

  In other words, in the half-speed mode, the pixel clock period per pixel is longer and the writing speed is lower than in the constant-speed mode, but when considering the dot position correction accuracy of the image, the half-speed mode is different from the constant-speed mode. The dot position can be corrected with double accuracy, and there is an advantage that image formation with higher accuracy is possible.

  In the present invention, in order to perform dot position correction with higher accuracy, a method of increasing the pixel clock frequency is conceivable. However, for example, when the pixel clock frequency is increased from 100 MHz to 200 MHz, it is essential to increase the speed of the entire ASIC. It becomes.

  However, when a high frequency clock having a period of 1/8 or 1/16 of the pixel clock frequency is required as in the present invention, the clock is equivalent to 800 to 1.6 GHz, which increases technical problems.

  Therefore, the pixel clock frequency is kept as it is, and the pixel clock frequency is redefined as one pixel corresponding to a plurality of reference pixel clocks, and the phase shift is performed. The accuracy increases, that is, the dot position accuracy can be increased. Details thereof will be described later.

  Further, when high-quality and high-speed image formation is performed in the image forming apparatus, the transfer of image data may not be in time when the linear speed exceeds the upper limit speed of the write clock that is the transfer timing of the image data. Thus, for example, when one reference pixel width is used as a reference pixel clock, two reference pixels continuous in the main scanning direction are defined as one pixel, and image data transfer is performed using the pixel clock.

  At this time, the image data transfer is as if, for example, the pixel clock has been reduced from 1200 dpi data transfer to 600 dpi data transfer, and a highly accurate pixel clock can be generated even for a linear speed exceeding the upper limit frequency of the pixel clock. A simple pixel clock generator can be configured.

  FIG. 7 shows the relationship between the pixel clock and the pixel in the present invention. 7 shows a constant speed mode which is an embodiment of the prior art when there is no clock generation circuit constituting the pixel clock generation circuit of FIG. 1, and a divide-by-2 circuit as a clock generation circuit which converts a reference pixel clock into a pixel clock. An embodiment of the half-speed mode, which is an embodiment in the case where is configured, is shown. In the present embodiment, an example in which the phase shift accuracy of the pixel clock is 1/8 PCLK is shown.

  At this time, as shown in the figure, the constant speed mode is a mode in which the phase of the pixel clock can be advanced or delayed with respect to the reference pixel clock PCLK when one waveform of the reference pixel clock PCLK is defined as one reference pixel. . On the other hand, when one period of the pixel clock PCLK is defined as one reference pixel, two or more periods, here, two periods are defined as one pixel, and a mode in which the phase of the pixel clock can be advanced or delayed is a half speed mode. .

  In the half speed mode, the relationship of the pixel clock PCLK ′ = 2PCLK is established in terms of the period with respect to the reference pixel clock PCLK in the constant speed mode. At this time, the pixel clock PCLK ′ in the half-speed mode outputs the reference pixel clock PCLK in the constant-speed mode through a clock generation circuit such as a counter at the output stage. Therefore, the phase shift accuracy is, for example, ± 1 in the constant-speed mode. When the phase shift resolution is / 8 PCLK, the reference pixel clock cycle is doubled in the half-speed mode, so that the relative accuracy is ± 1/16 PCLK ′. On the other hand, in the half speed mode, it corresponds to two clocks in the constant speed mode in one pixel. Therefore, when the two reference pixel clocks in one pixel are phase-shifted with the same sign, ± 1/16 PCLK ′ The phase can be shifted with respect to one pixel with an accuracy of ± 1/8 PCLK ′, which is twice as large as.

  In other words, in the half-speed mode, the pixel clock period per pixel is longer and the writing speed is lower than in the constant-speed mode, but when considering the dot position correction accuracy of the image, the half-speed mode is different from the constant-speed mode. The dot position can be corrected with double accuracy, and there is an advantage that image formation with higher accuracy is possible.

  FIG. 8 shows the relationship between the pixel clock and the pixel in another embodiment of the present invention. In this embodiment, when the phase shift accuracy in the constant speed mode is ± 1/8 PCLK, the dot position correction in the main scanning direction of the pixels in the 1/4 speed mode in which four reference pixels are defined as one pixel is shown. Yes. Similarly to the above example, in the pixel clock generation circuit capable of phase shifting with ± 1/8 PCLK accuracy with respect to the reference pixel, when the four reference pixels are defined as one pixel, the dot position correction accuracy in the main scanning direction is 1 / When the pixel clock in the 4-speed mode is PCLK ″, the range is ± 1/32 PCLK ″ to ± 1/8 PCLK ″. Accordingly, although the writing speed is 1/4, the dot position accuracy in the main scanning direction can be corrected with high accuracy in units of 1/32 pixels.

  FIG. 9 shows the relationship between the pixel clock and the pixel in another embodiment of the present invention. FIG. 9 shows dot position correction in the half speed mode when the dot position correction accuracy in the constant speed mode is ± 1/16 PCLK. In the embodiment of FIG. 9, the writing speed is ½ of the constant speed mode, but the dot position correction accuracy in the main scanning direction per pixel is ± 1/32 PCLK ′ accuracy. Therefore, when the ¼ times speed mode is compared, a pixel clock generation method is realized in which the writing speed is twice and the dot position correction accuracy is almost equal.

  FIG. 10 shows an embodiment of a cycle change of the pixel clock PCLK in the present invention. 10A and 10B show the high-frequency clock VCLK, the pixel clock PCLK, and the phase data, respectively, from the top. The pixel clock in the figure represents the reference pixel clock PCLK.

  First, FIG. 10A will be described. When the phase data is 0, the pixel clock PCLK is equivalent to 8 clocks of the high frequency clock VCLK, when the phase data is −1, 7 clocks (−1/8 PCLK phase shift), and when the phase data is +1, 9 clocks (+1/8 PCLK) Phase shift). FIG. 10A shows an example in which the cycle of the pixel clock changes in one clock step of the high-frequency clock VCLK due to increase / decrease of the phase data.

  On the other hand, in FIG. 10B, when the phase data is 0, the high frequency clock is 8 clocks, but when the phase data is −1, 7.5 clocks (−1/16 PCLK phase shift), -2 is 7 clocks (-2 / 16PCLK phase shift), +1 is 8.5 clocks (+ 1 / 16PCLK phase shift), and +2 is 9 clocks (+ 2 / 16PCLK phase shift). FIG. 10B shows an example in which the period of the pixel clock changes in half clock steps of the high frequency lock by increasing or decreasing the phase data.

  As shown in FIGS. 10A and 10B, by providing phase data for each clock of the pixel clock PCLK, the cycle of the pixel clock PCLK follows the value of the phase data, and FIG. In one clock step of VCLK, FIG. 10B changes in half clock steps.

  Consider a case where the above example is applied to the present invention in which two consecutive clocks PCLK ′ of the pixel clock PCLK are defined as one pixel. At this time, the writing speed is ½ of the constant speed mode, but the dot position correction accuracy per pixel in the main scanning direction is ± 1/1 because it is one clock unit of the high frequency clock in FIG. If it is 8PCLK accuracy and the maximum ± 1/8 PCLK phase adjustment per reference pixel is possible, the phase shift can be performed with a maximum ± 1/16 PCLK ′ accuracy per pixel. On the other hand, in FIG. 10B, since it is a 1/2 clock unit of the high-frequency clock, it becomes ± 1/16 PCLK accuracy, and if correction is possible with a maximum ± 2/16 PCLK accuracy per reference pixel, a maximum ± 2 / 32PCLK ′ phase adjustment is possible.

  In the present invention, since the cycle of the pixel clock PCLK ′ is larger than the reference pixel clock PCLK, dot data can be corrected with high accuracy by providing the phase data in synchronization with the reference pixel clock PCLK.

  FIG. 11 shows a second configuration of the pixel clock generation circuit according to the first embodiment of the present invention. FIG. 11 is obtained by adding a phase data decoding circuit 16 to the configuration of FIG. Here, it is assumed that the phase data corresponds to the phase shift amount as shown in FIG. The phase data decoding circuit 16 obtains a counter value corresponding to the phase shift amount from the inputted phase data, and outputs it to the comparison circuit 13. Thereby, the phase data does not need to have the bit width of the counter 12 as its bit width. For example, when the pixel clock generation circuit 10 is incorporated in a chip, the number of pins can be reduced. The configuration of the comparison circuit 13 may be the same as that in FIG. The operation of FIG. 11 is the same as that of FIG.

  FIG. 13 shows a third configuration of the pixel clock generation circuit according to Embodiment 1 of the present invention. FIG. 13 is obtained by adding a phase data storage circuit 17 for storing a plurality of phase data in the configuration of FIG. A plurality of phase data are set in advance in the phase data storage circuit 17 in advance, one phase data is sequentially read out in synchronization with the reference pixel clock PCLK, and is supplied to the comparison circuit 13. Although omitted in FIG. 13, the phase data storage circuit 17 includes an address counter.

  Thus, for example, in the case of data that is the same phase data for each line, such as phase data for correcting scanning unevenness caused by the characteristics of the scanning lens, the phase data storage circuit 17 stores the phase data for one line in advance. If the data is stored and the phase data is sequentially read from the head address of the phase data storage circuit 17 and output to the comparison circuit 13 every time the line is scanned, it is necessary to output the same phase data for each line from the outside. The burden on the external control circuit can be reduced.

  In addition to the phase data storage circuit, by adding a phase combining path that combines external phase data given from the outside and internal storage data output from the phase data storage circuit and outputs combined phase data, the scanning lens characteristics In addition to phase data based on static characteristics such as the above, it is possible to cope with phase data correction based on dynamic characteristics such as rotation irregularities of the polygon mirror, temperature characteristics of the optical system, and changes with time.

  FIG. 14 shows another embodiment of the present invention. This embodiment is a schematic diagram of pixel generation when the reference pixel clock in one reference pixel is PCLK and the three reference pixels are defined as one pixel (1/3 speed mode). In the figure, the horizontal axis indicates the main scanning direction, and the vertical axis indicates the writing line. When the phase is advanced in units of 1/8 PCLK with respect to one reference pixel clock with respect to the reference pixel clock PCLK, 3 pixels with 10 pixels. An example in which the phase is advanced by 8 PCLK is shown in the figure.

  (A) In the pattern of the pixel 1, the phase shift is performed at the pixel clock position common to each line. However, in this case, since the clock for performing the phase shift in the vertical direction is formed on the same line, the influence on the image such as vertical stripes can be considered. Therefore, by changing the position of the reference pixel clock for performing the phase shift in the same pixel for each line as shown in the pattern of the pixel 2 in FIG. Image formation is possible.

  FIG. 15 shows another embodiment of the present invention. The present embodiment is a schematic diagram of pixel generation when a reference pixel clock in one reference pixel is PCLK and four reference pixels are defined as one pixel (1/4 speed mode).

  In this embodiment, in 6 pixels (24 reference pixels PCLK), the 1/8 PCLK phase is advanced (7/8 PCLK) by 3 references each of (a) pixel 1, (b) pixel 2, and (c) pixel 3. Similarly, pixel delay is performed for 1/8 PCLK phase (9/8 PCLK) for all three reference pixels (a) pixel 1, (b) pixel 2, and (c) pixel 3. Both ends of are located at the same positions as the pixels in the initial state where no phase shift is performed.

  At this time, when the phase shift is performed with respect to the continuous reference pixel clock as in (a) pixel 1, the influence on the image due to the concentration of the phase-adjusted pixels can be considered. Therefore, as shown in (b) or (c), by setting so as not to give phase shift data to continuous reference pixels, the influence on the image can be reduced.

  Further, (b) the pixel 2 gives phase shift data only for one reference pixel per pixel, but as shown in (c) pixel 3, by performing two or more phase shifts in one pixel. High-precision dot position correction can be performed for one pixel.

  FIG. 16 shows a configuration of a pixel clock and pulse modulation signal generation circuit according to the second embodiment of the present invention. The pixel clock and pulse modulation signal generation circuit 24 includes a high-frequency clock generation circuit 20 that is high-frequency clock generation means, a pixel clock control circuit 21 that is reference pixel clock generation means, and a modulation data generation circuit 22 that is modulation data generation means. And a serial modulation signal generation circuit 23 which is a serial modulation signal generation means, and a clock generation circuit 25 which generates a pixel clock PCLK ′ from a pixel clock PCLK which is an output signal of the pixel clock control circuit.

  The high frequency clock generation circuit 20 generates a high frequency clock VCLK serving as a reference for the reference pixel clock PCLK, which is a basic period representing one dot. The pixel clock control circuit 21 generates the reference pixel clock PCLK based on the phase data indicating the transition timing between the high frequency clock VCLK and the reference pixel clock PCLK. The cycle of the reference pixel clock PCLK changes based on the phase data. The modulation data generation circuit 22 generates modulation data representing a desired bit pattern (pulse pattern) based on image data given from outside such as an image processing unit (not shown).

  The phase data is also given to the modulation data generation circuit 22. The modulation data generation circuit 22 changes or corrects the number of bits constituting the modulation data based on the phase data. The serial modulation signal generation circuit 23 receives the modulation data output from the modulation data generation unit 22, converts it into a serial pulse pattern sequence (pulse sequence) based on the high-frequency clock VCL, and outputs it as a pulse modulation signal. . The pixel clock PCLK output from the pixel clock control circuit 21 is also supplied to the serial modulation signal generation circuit 23.

  The serial modulation signal generation circuit 23 inputs (loads) the modulation data output from the modulation data generation circuit 22 in synchronization with the reference pixel clock PCLK, so that the pulse modulation signal PM following the change in the cycle of the pixel clock is generated. Output.

  For example, if modulation data from the outside is directly input to the serial modulation signal generation circuit 23, the modulation data generation circuit 22 can be omitted.

  FIG. 17 shows an output image of the pixel clock PCLK ′ in the second embodiment of the present invention. Here, a case where the pixel clock PCLK is divided by 8 of the high frequency clock VCLK when the phase shift of the phase data is 0 is shown.

  As shown in FIG. 17, by providing phase data for each clock of the pixel clock PCLK, the cycle of the pixel clock PCLK changes in 1 or 1/2 steps of the high-frequency clock VCLK according to the value of the phase data. FIG. 17A shows an embodiment that changes in one clock step of the high-frequency clock VCLK, and FIG. 17B shows an embodiment that changes in 1/2 clock.

  FIG. 18 shows a pulse output (PM signal) image according to the present invention, that is, an image for outputting a pulse train corresponding to one dot.

  As shown in FIG. 18, for example, when one dot is composed of eight pulse trains, the pulse trains can be serially output, so each of the eight pulse trains is turned on (for example, black) and off (for example, It is possible to output a desired pulse at a desired position in one dot by arbitrarily setting it as (for example, white). This pulse output is not limited to one dot width, and the same applies to a plurality of dots such as two dots and three dots.

  FIG. 19 shows the relationship between the reference pixel clock and the pulse output in the present invention. The serial modulation signal generation circuit 23 inputs or loads modulation data at the rising edge of the reference pixel clock PCLK, converts the modulation data into a serial pulse train based on the high frequency clock VCLK, and outputs it as a pulse modulation signal PM. In FIG. 19, black indicates ON (1) and white indicates OFF (0). FIG. 19A shows an example in which the phase shift is 0. In this case as well, the reference pixel clock PCLK is a frequency-divided signal of the high-frequency clock VCLK, and one dot, that is, one pixel is composed of eight pulse trains. Let's say.

  FIG. 19B shows a case where the phase shift is −1, that is, the reference pixel clock PCLK is divided by 7 (7 / 8PCLK), and the phase shift is +1, that is, the reference pixel clock PCLK is divided by 9 (9/9). 8PCLK) is shown as an example. As shown in FIG. 19B, the pulse train of the pulse modulation signal PM also changes in accordance with the change in the cycle of the reference pixel clock PCLK. In this case, the pulse output frequency in the pulse train is made as constant as possible or the pulse train pulse output pattern is not changed as much as possible. For example, in FIG. 19 (b), 4/8 → 3/7, 4/8 → 5/9. This can be realized by making the bits constituting the modulation data variable according to the phase data.

  FIG. 5 shows a phase shift correction method using the pixel clock and pulse modulation signal generation circuit shown in FIG. In FIG. 16, by providing phase data in synchronization with the pixel clock PCLK or PCLK ′, the phase of the pixel clock PCLK ′ can be shifted or advanced. When the present invention is applied to the conventional image forming apparatus shown in FIG. 37, the semiconductor laser unit follows the image data generated from the image processing unit and the pixel clock PCLK ′ whose phase is set by the phase synchronization circuit. By controlling the light emission time, the electrostatic latent image on the scanned medium can be controlled. As described above, FIG. 5 shows an electrostatic latent image or a dot image when the horizontal axis is the main scanning direction and the vertical axis is the sub-scanning direction.

  Since the relationship between the pixel clock and the pixel in the second embodiment of the present invention is the same as that described in FIGS. 6 to 9 of the first embodiment, the description thereof is omitted.

  The pixel clock control circuit 21 constituting the pixel clock and pulse modulation signal generation circuit according to the second embodiment of the present invention uses the pixel clock generation circuit 10 according to the first embodiment (FIGS. 1, 11, and 13). . Therefore, the description is omitted.

  Next, the modulation data generation circuit 22 and the serial modulation signal generation circuit 23 shown in FIG. 16 will be described.

  20, 21, and 22 show examples of pulses generated using a conventional pulse width modulation circuit when each dot is composed of, for example, 8 pulses. Here, FIG. 20 shows an example of forming a pulse from the right, FIG. 21 shows an example of forming a pulse from the left, and FIG. 22 shows an example of forming a pulse from the inside. As described above, the conventional technique cannot generate a desired pulse at a desired position, and even if it can, a complicated configuration is required.

  FIG. 23 shows an example of a pulse output image according to the present invention. In this embodiment, since the figure becomes complicated when the number of pulses is large, an example of pulse output in the case of 4 bits, that is, a case where one dot is composed of 4 pulses P1 to P4 is shown. As shown in FIG. 23, according to the modulation data generation circuit 12 and the serial modulation signal generation circuit 13 of the present invention, a pulse can be output at an arbitrary position of one dot, and 16 patterns of patterns can be obtained by combining four pulses. Pulse train output is possible. Similarly, 32 outputs are possible with 5 pulses, and 64 outputs with 6 pulses. Such a pulse train having an arbitrary pulse pattern can be easily generated by using, for example, a look-up table (LUT).

  FIG. 24 shows a configuration example using an LUT as the modulation data generation circuit 22 of FIG. FIG. 24 shows a configuration example in the case where the 4 bits shown in FIG. 23, that is, 16 bit patterns of pulses P1 to P4 are stored in the lookup table (LUT) 1221. In FIG. 24, the LUT 1221 is composed of a total of 64 bits, 4 bits in the horizontal direction and 16 columns in the vertical direction, and 16 addresses from 0000 to 1111 are given. Therefore, by inputting image data as address data, it is possible to output bit strings (pulse strings) P1 to P4 having a desired pattern as modulation data. Also, as shown in FIG. 22, the output is inverted between combinations of image data such as 0000 and 1111 and 0010 and 1101, so if an image data bit is an inverted signal, the LUT 1221 is not 16 columns but 8 columns. The same function can be realized if there is a line. By using the data inversion signal, the memory can be reduced to half as described above, which leads to reduction in size and cost. Further, by configuring a plurality of LUTs having different bit patterns for the same image data and selecting them according to the value of the phase data, the number of bits (bit pattern) of the modulation data can be easily changed based on the phase data.

  Also, the serial modulation signal generation circuit 23 in FIG. 16 inputs modulation data output from the modulation data generation circuit 22 constituted by the LUT as described above, and converts it into a serial pulse train. The serial modulation signal generation circuit 23 can be configured using a shift register. For example, the modulation data output from the modulation data generation circuit 22 is loaded in parallel according to the reference pixel clock PCLK or the pixel clock PCLK ′, which is a load signal, and sequentially in synchronization with the high frequency clock VCLK from the high frequency clock generation circuit 20. Due to the configuration for performing the shift operation, a pulse modulation signal of a serial pulse train corresponding to the bit pattern of the modulation data is output.

  FIG. 25 shows an example of pulse train change according to the phase data of the present invention. FIG. 25 shows an example in which the output pulse pattern of the pulse train 16 is converted into the output pulse pattern of the pulse train 14. As shown in the figure, when an output pattern having 16 output pulses is output and a predetermined density is output at a predetermined position by an image forming apparatus or the like, a case is considered in which the last two pulses are deleted while leaving the data pattern as it is. At this time, for example, the density is changed from 8/16 to 6/14 (when the density is considered in terms of the number of pulses). In such a case, by changing the data pattern as shown by the arrow in FIG. 25 using the memory or the decoder, the density becomes 7/14, and in this example, the density matches. Further, even if the densities do not match, it is possible to minimize the density change caused by changing the number of pulses by having a conversion unit that converts the density to the density closest to the density at the first 16 pulses. Become.

  FIG. 26 shows another example of pulse train change according to the phase data and the like of the present invention. The figure shows an example in which an output pulse pattern with 16 pulses is converted into an output pulse pattern with 18 pulses. Similarly to FIG. 25, a data conversion unit for data conversion is configured so that the densities in the pulse trains are matched as much as possible, and in this embodiment, a method of converting from 8/16 to 9/18 is indicated by an arrow.

  As described above, when changing the number of pulses constituting the pulse train, by having a data conversion unit according to the number of pulses, even if the number of pulses is changed, the high resolution without affecting the image density or the like. An image forming apparatus can be realized.

  Further, in this embodiment, the embodiment has been described based on the number of pulses 16 for the sake of simplicity. However, since the data conversion unit can be configured with a finer pitch as the number of pulses constituting the pulse train increases, the change in image density due to the change in the number of pulses. It is possible to realize a configuration with little influence on the above.

  FIG. 27 shows another example of pulse train change according to the phase data and the like of the present invention. FIG. 27 shows an example using a method and configuration different from those shown in FIGS. Consider the case where the number of output pulses is changed to 14, 16, and 18, as shown in FIG. The number of pulses to be output is changed to 14, 16, and 18, but only 14 pulses (black or white) that can actually be output are from the left. At this time, as shown in the figure, when the number of pulses is 16, the two rightmost pulses in the pulse train are always white, and when the number of pulses is 18, the four rightmost pulses in the pulse train are always white.

  For example, in the case of a raster scanning type image forming apparatus, even if a pulse is output with a duty of less than 100%, the light on the photoconductor has a Gaussian distribution, so that a solid black image can be output. Therefore, as shown in FIG. 27, a configuration in which the number of pulses is changed without changing the data pattern by setting the duty to 14 / 18≈77.8% as a maximum, and a high-resolution image can be obtained without the data conversion unit. Can be realized.

  FIG. 28 shows a configuration of a pulse modulation signal generation circuit according to the present invention. In a conventional pulse modulation circuit for generating image formation timing, when a triangular wave or a sawtooth wave is used, the linearity / reproducibility of the triangular wave or the sawtooth wave is not compatible with an increase in operating speed. For example, when the pixel clock is doubled, a pulse width modulation signal cannot be generated unless the frequency of the triangular wave or sawtooth wave is doubled. Therefore, the pulse modulation has better linearity and swing as the pixel clock becomes faster. It becomes difficult to generate a signal.

  The pulse modulation signal generation circuit 26 of the present invention includes a high frequency clock generation circuit 20, a modulation data generation circuit 22, and a serial modulation signal generation circuit 23. The high-frequency clock generation circuit 20 generates a high-frequency clock VCLk that is much faster than a basic cycle that represents one dot, which is generally called a pixel clock required by an image forming apparatus. The modulation data generation circuit 22 generates modulation data representing a desired bit pattern based on image data given from outside such as an image processing unit (not shown). The serial modulation signal generation circuit 23 receives the modulation data output from the modulation data generation circuit 22, converts it into a serial pulse pattern sequence (pulse sequence) based on the high frequency clock VCLK, and outputs it as a pulse modulation signal PM. To do. For example, if modulation data from the outside is directly input to the serial modulation signal generation circuit 23, the modulation data generation circuit 22 can be omitted.

  The greatest feature of the pulse modulation signal generation circuit 26 is that modulation data is input to the serial modulation signal generation circuit 23, and a pulse train corresponding to the bit pattern of the modulation data is serially based on a high-frequency clock much faster than the pixel clock. The output is to generate a pulse modulation signal PM.

  For example, a shift register may be used for the serial modulation signal generation circuit 23. Therefore, a complicated configuration for generating a conventional pulse modulation signal is not necessary, and a pulse modulation signal generation circuit capable of high-speed operation with a simple configuration can be realized. The pulse train generation method according to FIG. 28 is the same as that described with reference to FIGS.

  FIG. 29 shows the relationship between pixels and dot images in the embodiment of the present invention (FIG. 28). The pulse modulation signal generation circuit of the present embodiment disassembles one reference pixel into pixels 1, 2,... Composed of a plurality of two or more pulse trains with respect to a pulse train corresponding to one reference pixel in the pulse modulation signal, It has a function of generating a pulse train.

  A reference pixel mode in which one modulation data is input to one reference pixel to generate a pulse train using the pulse modulation signal generation circuit of FIG. 28, and a plurality of modulation data of two or more for one reference pixel in the present invention Is an example of a relationship between a pixel and a dot image generated based on a pulse train in the double-speed pixel mode in which a plurality of patterns are generated within one reference pixel, and in this embodiment, two patterns of pulse trains are generated.

  In FIG. 29, when the number of bits for generating a pulse train for one reference pixel in the reference pixel mode is 8, the number of bits for generating a pulse train per pixel in the double-speed pixel mode is 4 bits, which is half that number. At this time, since the number of bits in one reference pixel corresponding to one pixel in the reference pixel mode is reduced to 4 bits per pixel in the double speed pixel mode, bit conversion from 8 bits to 4 bits is performed for each pixel. As a result, the pulse train generation speed per pixel is improved, and here it is doubled, whereby a pulse modulation signal generation circuit corresponding to a high-speed device can be configured.

  According to the present invention, it is possible to provide a pulse modulation signal generation circuit that does not require a complicated configuration or the like for generating a pulse pattern and can realize high gradation of an image even when the operation speed is high with a very simple configuration. Further, by applying this to the image forming apparatus, for example, it is possible to form an image with an arbitrary time width without using a periodic pixel clock for determining one dot or one pixel. In addition, by making the pulse modulation unit and the high-frequency clock generation unit into an integrated circuit on the same chip, it is possible to provide an optical scanning device and an image forming apparatus that are small, low cost, and power-saving.

  FIG. 30 shows a configuration example of an optical scanning apparatus and an image forming apparatus to which the pixel clock and pulse modulation signal generation circuit according to the present invention is applied. In FIG. 30, reference numeral 200 denotes a laser scanning optical system. In this embodiment, a single beam scanning optical system is shown. 209 and 210 are detection means (such as a photosensor), 220 is a dot position deviation detection / control unit, 230 is a high frequency clock generation unit, 240 is a pixel clock generation unit, 250 is an image processing unit, 260 is a laser drive signal generation unit, Reference numeral 270 denotes a laser driving unit. Here, the high-frequency clock generation unit 230 corresponds to the high-frequency clock generation circuit 20 described in FIG. 16 and the like, and the pixel clock generation unit 240 similarly corresponds to the pixel clock control circuit 21 and the clock generation circuit 25. The laser drive signal generation unit 260 corresponds to the modulation data generation circuit 22 and the serial modulation signal generation circuit 23 and constitutes a pulse modulation signal generation unit.

  In FIG. 30, a laser beam from a semiconductor laser 201 passes through a collimator lens 202 and a cylinder lens 203, is scanned by a polygon mirror 204, passes through an fθ lens 205 and a toroidal lens 206, is reflected by a mirror 207, and is reflected on a photosensitive member 208. By entering, an image (electrostatic latent image) is formed on the photoreceptor 208. The start point and end point of this scanning laser light are detected by photosensors 209 and 210 as detection means, and input to the dot position deviation detection / control unit 220. The dot position deviation detection / control unit 220 measures the time during which the laser beam is scanned between the photosensors 209 and 210, obtains the deviation amount by comparing it with a reference time, and corrects the deviation amount. And output to the pixel clock generation unit 240 and the laser drive signal generation unit 260. Note that the output signal of the photosensor 209 is also provided to the image processing unit 250 as a line synchronization signal. When the modulation data is generated from the image data by the image processing unit 250, the phase data may be supplied to the image processing unit 250 and the output to the laser drive signal generation unit 260 may be omitted.

  If the pixel clock generation unit 240 does not include a phase data storage circuit, the dot position deviation detection / control unit 220 outputs phase data to the pixel clock generation unit 240 for each line. In the case where the circuit is provided, the phase data is obtained in advance, for example, to the pixel clock generator 240 in advance. In addition, the dot position deviation detection / control unit 220 not only uses phase data (first phase data) for always performing the same correction for each line that corrects scanning unevenness caused by the characteristics of the scanning lens, but also the polygon mirror. When phase data (second phase data) corresponding to correction such as rotation unevenness that changes for each line is also generated, and the pixel clock generation unit 240 includes a phase data synthesis circuit, the phase data Data is also output to the pixel clock generator 240.

  As described in the first and second embodiments, the pixel clock generation unit 240 generates a pixel clock based on the high-frequency clock output from the high-frequency clock generation unit 230 and the phase data from the dot position deviation detection / control unit 220. The image processing unit 250 and the laser drive signal generation unit 260 are provided.

  The image processing unit 250 inputs an image read by an image input device such as a scanner (not shown), and generates image data synchronized with a horizontal synchronization signal and a pixel clock. This image data is generally generated in consideration of the photosensitive characteristics of the photoreceptor.

  The laser drive signal generator 260 generates modulation data from the image data as described above, and converts the modulation data into a serial string, thereby outputting a pulse modulation signal PM synchronized with the pixel clock. This pulse modulation signal PM is input to the laser drive unit 270, and the light of the semiconductor laser 201 is modulated by the laser drive unit 270 in accordance with the pulse modulation signal PM, and an image with no positional deviation is formed on the photoconductor 208. Can do.

  Note that the image processing unit 250 may generate modulation data from the image data and transfer it to the laser drive signal generation unit 260. In this case, the laser drive signal generation unit 260 directly converts this modulation data into a serial pulse train.

  When a multi-beam scanning device described later is used, for example, a plurality of pixel clock generation units 240 and laser drive signal generation units 260 (modulation data generation unit and serial modulation signal generation unit) are prepared, and the photo sensor 211 is further prepared. , 212, a plurality of sets of phase data for a plurality of lines are simultaneously generated, each phase data is supplied to each pixel clock generation unit, and each pixel clock is generated. The transferred image data for a plurality of scanning lines may be processed by the respective laser drive data generation units so as to output a plurality of pulse modulation signals.

  FIG. 31 shows a configuration example of an optical scanning device using the pixel clock and pulse modulation signal generation circuit of the present invention. A printed circuit board 802 on which a drive circuit for controlling a semiconductor laser and a pixel clock generation device are formed is mounted on the rear surface of the light source unit 801 in FIG. 31, and the above-described spring is applied to the wall surface of the optical housing orthogonal to the optical axis. In contact, the inclination is adjusted by the adjusting screw 803 and the posture is maintained. The adjusting screw 803 is screwed into a protrusion formed on the wall surface of the housing. Inside the optical housing, the cylinder lens 805, the polygon motor 808 that rotates the polygon mirror, the fθ lens 806, the toroidal lens, and the folding mirror 807 are positioned and supported, and the printed circuit board 809 on which the synchronization detection sensor is mounted. Is mounted on the wall of the housing from the outside in the same manner as the light source unit. The upper portion of the optical housing is sealed with a cover 811 and fixed to the frame member of the image forming apparatus main body with a plurality of mounting portions 810 protruding from the wall surface.

  The present invention can also be applied to a multi-beam scanning device which is an optical scanning device configured using a plurality of light sources. Hereinafter, a multi-beam scanning device (multi-beam optical system) will be described.

  FIG. 32 shows the configuration of the multi-beam scanning device. In this example, as shown in FIG. 33, n = 2 semiconductor laser arrays in which two light emitting sources are monolithically arranged at a distance ds = 25 μm are used, and arranged in the sub-scanning direction with the optical axis of the collimating lens being symmetric. Is done.

  In FIG. 32, the semiconductor laser arrays 301 and 302 are arranged so that the optical axes of the collimating lenses 303 and 304 coincide with each other, have an emission angle symmetrically in the main scanning direction, and the emission axes intersect at the reflection point of the polygon mirror 307. Has been. A plurality of beams emitted from the respective semiconductor laser arrays 301 and 302 are collectively scanned by a polygon mirror 307 through a cylinder lens 308 and imaged on a photoconductor 312 by an fθ lens 310 and a toroidal lens 311. Print data for one line is stored in the buffer memory in the image processing apparatus for each light source, read out for each surface of the polygon mirror, and recording is performed on two lines simultaneously.

  FIG. 33 shows the configuration of the light source unit. The semiconductor lasers 403 and 404 are individually cylindrical in mating holes 405-1 and 405-2 (not shown) formed on the back side of the base member 405 slightly inclined by a predetermined angle in the main scanning direction, in the embodiment, about 1.5 °. The heat sink portions 403-1 and 404-1 are mated, and the protrusions 406-1 and 407-1 of the holding members 406 and 407 are aligned with the notches of the heat sink portion so that the arrangement direction of the light emitting sources is aligned, and from the back side It is fixed with screws 412. Further, the collimating lenses 408 and 409 are adjusted in the optical axis direction so that the outer circumference thereof is aligned with the semicircular mounting guide surfaces 405-4 and 405-5 of the base member 405. It is positioned and glued so that it becomes a parallel light beam.

  In the embodiment, as described above, since the light beams from the respective semiconductor lasers are set so as to intersect within the main scanning plane, the mating holes 405-1 and 405-2 and the semicircular attachment are provided along the light beams. The guide surfaces 405-4 and 405-5 are formed to be inclined. The base member 405 is engaged with the holder member 410 by the cylindrical engagement portion 405-3, and the screw 413 is screwed into the screw holes 405-6 and 405-7 through the through holes 410-2 and fixed. Configure.

  In the light source unit described above, the cylindrical portion 410-1 of the holder member is engaged with the reference hole 411-1 provided in the mounting wall 411 of the optical housing, the spring 611 is inserted from the front side, and the stopper member 612 is inserted into the cylindrical portion protrusion 410. The holder member 410 is held in close contact with the back side of the mounting wall 411 by engaging with -3. At this time, one end of the spring is hooked on the protrusion 411-2 to generate a rotational force with the center of the cylindrical portion as the rotational axis, and an adjustment screw 613 provided to lock the rotational force causes the rotation around the optical axis to be θ. Rotate the entire unit to adjust the pitch. The aperture 415 is provided with a slit for each semiconductor laser, and is attached to the optical housing to define the emission diameter of the light beam.

  FIG. 34 shows another configuration of the light source unit. FIG. 34 shows an example in which light beams from a semiconductor laser array having four light emitting sources are combined using beam combining means. The basic components are the same as those in FIG. 33, and a description thereof is omitted here.

  In the present invention, the phase shift value for each data area in the plurality of light sources is shifted so that the relative position of the data area between the adjacent light sources and the clock for performing the phase shift in the data area do not coincide with the sub-scanning direction. By setting the data correction start timing, it is possible to prevent image bias due to phase shift data between multiple light sources, that is, generation of vertical streak images due to phase shift, and high image quality in the main scanning direction due to phase shift In addition, it is possible to obtain a high-quality image in the sub-scanning direction.

  Thus, in order to correct the optical scanning length difference and magnification difference caused by the wavelength error of each LD constituting the multi-beam, the phase shift is performed on the pixel clock, so that the scanning length is reduced to the phase shift accuracy. It is possible to correct the difference in thickness and reduce the variation in scanning light.

  FIG. 35 shows a configuration example of an image forming apparatus to which the present invention is applied. Around the photosensitive drum 901 that is the surface to be scanned, a charging charger 902 that charges the photosensitive member to a high voltage, and a developing roller that attaches the charged toner to the electrostatic latent image recorded by the optical scanning device 900 and visualizes it. 903, a toner cartridge 904 for supplying toner to the developing roller, and a cleaning case 905 for scraping and storing toner remaining on the drum. As described above, a plurality of lines are simultaneously recorded on the photosensitive drum for each surface. The recording paper is supplied from the paper supply tray 906 by the paper supply roller 907 and is sent out by the registration roller pair 908 in accordance with the recording start timing in the sub-scanning direction, and the toner is transferred by the transfer charger 906 when passing through the photosensitive drum. The image is transferred, fixed by the fixing roller 909, and discharged to the paper discharge tray 910 by the paper discharge roller 912.

  FIG. 36 shows an example in which the present invention is mounted on a tandem color machine which is an image forming apparatus having a plurality of photoconductors. The tandem color machine requires separate photoconductors corresponding to each color of cyan, magenta, yellow, and black, and the optical scanning optical system forms a latent image through a separate optical path corresponding to each photoconductor. . Therefore, the main scanning dot position shift generated on each photoconductor often has different characteristics.

  By applying the pixel clock generation circuit of the present invention to a tandem color machine, it is possible to obtain a high-quality image in which the main scanning dot position deviation is favorably corrected. In particular, in terms of image quality, the present invention is effective for misregistration in the main scanning direction, and an image with good color reproducibility in which color misregistration between stations is effectively reduced can be obtained.

  For example, in a tandem color machine, when color misregistration between stations occurs on the order of several tens of μm, the phase of the pixel clock whose main scanning position deviation exceeds 1/8 dot is shifted to correct the main scanning position deviation. By doing so, the amount of dot position deviation of each color can be reduced to about 2.6 μm (21.2 μm / 8) corresponding to 1/8 dot at 1200 dpi.

1 shows a first configuration of a pixel clock generation circuit according to Embodiment 1 of the present invention; The time chart of Example 1 is shown. The timing chart of each signal of a high frequency clock, phase data, and reference pixel clock PCLK is shown. The relationship between phase data and a phase shift amount is shown. 2 shows a phase shift correction method by a pixel clock generation device. The relationship between the pixel clock of this invention and a pixel is shown. The relationship between the pixel clock of this invention and a pixel is shown. The relationship between the pixel clock in another Example of this invention and a pixel is shown. The relationship between the pixel clock in another Example of this invention and a pixel is shown. An example of a cycle change of the pixel clock PCLK in the present invention will be described. 2 shows a second configuration of the pixel clock generation circuit according to the first embodiment of the present invention. FIG. 11 shows the phase data applied. 3 shows a third configuration of the pixel clock generation circuit according to Embodiment 1 of the present invention. The pixel generation in 1/3 speed mode is shown. The pixel generation in the 1/4 speed mode is shown. 6 shows a configuration of a pixel clock and pulse modulation signal generation circuit according to Embodiment 2 of the present invention. 7 shows an output image of a pixel clock PCLK ′ in Embodiment 2 of the present invention. An image for outputting a pulse train corresponding to one dot is shown. The relationship between the reference pixel clock and the pulse output in the present invention is shown. An example of the pulse produced | generated using the conventional pulse width modulation circuit is shown. An example of the pulse produced | generated using the conventional pulse width modulation circuit is shown. An example of the pulse produced | generated using the conventional pulse width modulation circuit is shown. 2 shows an example of a pulse output image according to the present invention. A configuration example using an LUT as a modulation data generation circuit is shown. An example of a pulse train change by the phase data etc. of this invention is shown. The other example of the pulse train change by the phase data etc. of this invention is shown. The other example of the pulse train change by the phase data etc. of this invention is shown. 1 shows a configuration of a pulse modulation signal generation circuit according to the present invention. The relationship between the pixel in FIG. 28 and a dot image is shown. 2 shows a configuration example of an optical scanning apparatus and an image forming apparatus to which the present invention is applied. 1 shows a configuration example of an optical scanning device using the present invention. 1 shows a configuration of a multi-beam scanning device. 1 shows a light source unit of a multi-beam scanning device. The other structure of a light source unit is shown. 1 shows a configuration example of an image forming apparatus to which the present invention is applied. An example in which the present invention is mounted on a tandem color machine will be described. The prior art is shown. Other prior art is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Pixel clock generation circuit 11 High frequency clock generation circuit 12 Counter 13 Comparison circuit 14 Pixel clock control circuit 15 Clock generation circuit

Claims (30)

High-frequency clock generation means for generating a high-frequency clock, and reference pixel clock generation means for changing the cycle of the reference pixel clock based on phase data indicating the transition timing between the high-frequency clock and the reference pixel clock output from the high-frequency clock generation means And a pixel clock generating circuit configured to generate one pixel clock in units of two or more consecutive reference pixel clocks.   2. The pixel clock generation circuit according to claim 1, wherein a transition timing of the reference pixel clock is synchronized with a transition of the high frequency clock.   2. The pixel clock generation circuit according to claim 1, wherein the cycle of the reference pixel clock changes in one clock step of the high frequency clock.   2. The pixel clock generation circuit according to claim 1, wherein the cycle of the reference pixel clock changes at a 1/2 clock step of the high frequency clock. The high-frequency clock generating means for generating a high-frequency clock, the counting means for counting the high-frequency clock output from the high-frequency clock generating means, and the phase data indicating the count value of the counting means and the transition timing of the reference pixel clock are compared. Comparing means and reference pixel clock control means for performing transition of the reference pixel clock based on the result of the comparing means, and the pixel clock is configured so as to constitute one pixel clock in units of two or more consecutive reference pixel clocks. pixel clock generation circuit and generates a.   6. The pixel clock generation circuit according to claim 5, further comprising phase data decoding means for decoding the phase data and supplying the decoded output to the comparison means.   6. The pixel clock generation circuit according to claim 5, further comprising phase data storage means for storing a plurality of phase data, sequentially reading the data in synchronization with a reference pixel clock, and supplying the phase data to the comparison means.   8. The pixel clock generation circuit according to claim 7, wherein the phase data storage means stores in advance phase data for one line, and sequentially reads out in synchronization with the reference pixel clock every time the line is scanned. Generation circuit.   6. The pixel clock generation circuit according to claim 1, wherein phase shift data is given to one reference pixel clock for one specific pixel.   6. The pixel clock generation circuit according to claim 1, wherein phase shift data is given to two or more reference pixel clocks for a specific pixel.   6. The pixel clock generation circuit according to claim 1, wherein when the phase shift data of a specific pattern is provided in synchronization with the reference signal, the reference clock number from the reference signal to the reference pixel clock to which the phase shift data is applied is determined for each reference signal generation. A pixel clock generation circuit, wherein   6. The pixel clock generation circuit according to claim 1, wherein phase shift data is given to a discontinuous reference pixel clock. High-frequency clock generation means for generating a high-frequency clock, and reference pixel clock generation means for changing the cycle of the reference pixel clock based on phase data indicating the transition timing between the high-frequency clock and the reference pixel clock output from the high-frequency clock generation means A modulation data generating means for inputting image data and generating modulation data representing a desired bit pattern from the image data; and inputting the modulation data and outputting a pulse modulation signal of a serial pulse train based on the high frequency clock A pixel clock and pulse modulation signal generation circuit comprising a serial modulation signal generation means, wherein one pixel clock is generated in units of two or more consecutive reference pixel clocks.   14. The pixel clock and pulse modulation signal generation circuit according to claim 13, wherein the transition timing of the reference pixel clock is synchronized with the transition of the high frequency clock.   15. The pixel clock and pulse modulation signal generation circuit according to claim 13 or 14, wherein the modulation data generation means varies the number of bits constituting the modulation data.   16. The pixel clock and pulse modulation signal generation circuit according to claim 15, wherein the modulation data generation means modulates the pulse output frequency in the pulse train to be constant when changing the number of bits constituting the modulation data (number of pulses). A pixel clock and pulse modulation signal generation circuit characterized by generating data.   16. The pixel clock and pulse modulation signal generation circuit according to claim 15, wherein when the number of bits constituting the modulation data (number of pulses) is changed, the modulation data generation means does not change the pulse output pattern in the pulse train. Generating a pixel clock and pulse modulation signal.   16. The pixel clock and pulse modulation signal generation circuit according to claim 15, wherein the modulation data generation means makes the number of bits constituting the modulation data variable based on phase data instructing a transition timing of the reference pixel clock. A pixel clock and pulse modulation signal generation circuit which is characterized.   19. The pixel clock and pulse modulation signal generation circuit according to claim 13, wherein the serial modulation signal generation unit outputs the modulation data in synchronization with a reference pixel clock output from the pixel clock generation unit. A pixel clock and pulse modulation signal generation circuit characterized by being inputted.   20. The pixel clock and pulse modulation signal generation circuit according to claim 13, wherein the pixel clock generation means provides a phase shift from a reference signal when providing phase shift data of a specific pattern in synchronization with the reference signal. A pixel clock and pulse modulation signal generation circuit characterized in that the number of reference clocks up to a reference pixel clock for supplying data is changed every time a reference signal is generated.   The pixel clock and pulse modulation signal generation circuit according to any one of claims 13 to 19, wherein the pixel clock generation means provides phase shift data with respect to a discontinuous reference pixel clock. Pulse modulation signal generation circuit.   Clock generation means for generating a clock, modulation data generation means for inputting image data, generating modulation data representing a desired bit pattern from the image data, input the modulation data, and a serial pulse train based on the clock A serial modulation signal generation means for outputting a pulse modulation signal, wherein the modulation data generation means makes the number of bits constituting the modulation data variable and a bit pattern composed of a specific number of bits N is one reference pixel A pulse modulation signal generating circuit, wherein a pulse modulation signal is generated by using each of two or more bit patterns configured with less than N bits as one pixel.   13. The pixel clock generation according to claim 1, a light source, a deflection unit that deflects a light beam emitted from the light source, a light guide unit that guides the light beam deflected by the deflection unit to a scanned medium, and a pixel clock generation according to claim 1. An optical scanning device comprising a circuit.   24. The optical scanning device according to claim 23, wherein the light source is a multi-beam light source composed of a semiconductor laser array that optically combines a plurality of semiconductor lasers or is monolithic.   25. The image forming apparatus according to claim 23, wherein the image is formed by scanning the scanned medium.   26. The image forming apparatus according to claim 25, wherein a light guide unit that guides the light beam deflected by the deflecting unit onto a plurality of scanned media is used to scan the plurality of scanned media to form an image. An image forming apparatus corresponding to a color machine.   The pixel clock according to any one of claims 13 to 22, a light source, a deflecting unit that deflects the light beam emitted from the light source, a light guide unit that guides the light beam deflected by the deflecting unit to a scanned medium, An optical scanning device comprising a pulse modulation signal generation circuit or a pulse modulation signal generation circuit, and modulating a light beam output from the light source based on a pulse modulation signal output therefrom.   28. The optical scanning device according to claim 27, wherein the light source is a multi-beam light source composed of a semiconductor laser array in which a plurality of semiconductor lasers are optically synthesized or monolithic.   29. An image forming apparatus using the optical scanning device according to claim 27 or 28 as a light source and a scanning optical system that scans a light beam emitted from the light source. 30. The image forming apparatus according to claim 29, wherein a light guide unit that guides the light beam deflected by the deflecting unit onto a plurality of scanned media is used to scan the plurality of scanned media to form an image. An image forming apparatus corresponding to a color machine.

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