JP4313116B2 - Pixel clock generation apparatus and image forming apparatus - Google Patents

Description

  The present invention relates to a laser printer, a digital copying machine, and other image forming apparatuses, and more particularly to an apparatus and method for generating a pixel clock used in these image forming apparatuses.

  FIG. 40 shows a general configuration of an image forming apparatus such as a laser printer or a digital copying machine.

  In FIG. 40, the laser beam output from the semiconductor laser unit 3009 is scanned by a rotating polygon mirror 3003 to form a light spot on a photosensitive member 3001 that is a scanned medium via a scanning lens 3002, and the photosensitive member. 3001 is exposed to form an electrostatic latent image. At this time, the photodetector 3004 detects the scanning beam for each line. The phase synchronization circuit 3006 receives the clock from the clock generation circuit 3005, generates an image clock (pixel clock) synchronized in phase for each line based on the output signal of the photodetector 3004, and generates an image processing unit 3007. And supplied to the laser driving circuit 3008.

  In this way, the laser drive circuit 3008 controls the light emission time of the semiconductor laser unit 3009 according to the image data generated by the image processing unit 3007 and the image clock whose phase is set for each line by the phase synchronization circuit 3006. Thus, the formation of the electrostatic latent image on the photosensitive member 3001 is controlled.

  In such a scanning optical system, variations in the distance from the rotation axis of the deflecting / reflecting surface of a deflector such as a polygon mirror cause uneven scanning speed of a light spot (scanning beam) that scans the surface to be scanned. This uneven scanning speed causes fluctuations in the image and causes deterioration in image quality. When high image quality is required, it is necessary to correct scanning unevenness.

  Furthermore, in a multi-beam optical system that simultaneously scans using a plurality of light beams, if there is a difference in the oscillation wavelength of each light source, the exposure position shift will occur in an optical system in which the chromatic aberration of the scanning lens is not corrected. As a result, a difference occurs in the scanning width when the light spot corresponding to each light source scans the scanning medium for each light source, and this causes deterioration in image quality. Need to do.

  Conventionally, as a technique for correcting scanning unevenness, for example, as described in Patent Document 1 and Patent Document 2, the frequency of the pixel clock is basically changed to control the light spot position along the scanning line. How to do is known.

  Also known is a method of detecting the scanning speed by counting the number of clocks during which the scanning beam passes through the two photodetectors installed at both ends of the photosensitive member, and controlling the rotational speed of the polygon mirror according to the result. It has been.

  FIG. 41 shows an example of this conventional method, in which 3115 is a photoconductor, 3117 and 3118 are photo detectors installed at both ends of the photoconductor 3115, and 3111 is the number of clocks between detection signals by the photo detectors 3117 and 3118. A scanning speed detection unit 3112 that detects a scanning speed and outputs a correction signal is a polygon motor control unit that controls the rotational speed of a drive motor (not shown) of the polygon mirror 3114 in accordance with the correction signal. 3121 is a semiconductor laser, 3122 is a collimator lens, 3123 is a cylinder lens, 3116 is an f-θ lens, 3120 is a toroidal lens, and 3119 is a mirror.

Japanese Patent Laid-Open No. 11-167081 JP 2001-228415 A

  However, the conventional method (frequency modulation method) for changing the frequency of the pixel clock generally has a complicated configuration of the pixel clock control unit, and the complexity increases as the frequency modulation width becomes minute. There is a problem that it is not easy to realize the control. Further, even with a light beam deflected by the same deflecting / reflecting surface, there is a problem that uneven scanning speed occurs due to rotation jitter of the deflector and expansion / contraction of the scanning lens due to temperature change. Further, the method for controlling the rotating motor of the deflector has a limit in control accuracy.

Now, although partially repeated, in the image forming apparatus, a deviation between the actual main scanning dot position and the ideal main scanning dot position occurs. As the cause,
(1) The fθ characteristic of the scanning lens is not sufficiently corrected.
(2) Deterioration in processing accuracy and mounting accuracy of optical components of the optical scanning optical system.
(3) The focal length of the scanning optical system changes due to the deformation of the optical parts and the change in refractive index due to environmental changes such as the temperature and humidity in the apparatus, and the fθ characteristic deteriorates.
And so on.

  In particular, the main scanning dot position shift due to environmental fluctuations cannot be avoided even if optical adjustment or electrical correction is performed at the time of shipment of the apparatus. For example, even if there is no problem during the first printing, the temperature in the apparatus rises when printing is continuously performed, and the color of the first print and the color after printing a plurality of prints may change. May happen.

  Therefore, a main object of the present invention is to correct a main scanning dot position shift due to such an environmental change with high accuracy in an image forming apparatus, and to provide a pixel clock generation apparatus and method capable of such correction. It is to provide.

  Another main object of the present invention is to provide a pixel clock generation apparatus and method that can easily and flexibly cope with a difference in characteristics of a scanning optical system in an image forming apparatus and enables high-accuracy correction of main scanning dot position deviation. Is to provide.

  In the present invention, the characteristic value of the relationship between the dot position deviation of the real image height and the ideal image height of the scanning optical system is grasped in advance by a preliminary experiment or simulation, and a lookup table is created from the characteristic value. . Then, the phase shift data corresponding to the time variation between the horizontal synchronizing signals is read from the lookup table, and the phase of the pixel clock is controlled according to the phase shift data, so that the main scanning dot position deviation is corrected with high accuracy. Is.

That is, the invention of claim 1
High-frequency clock generation means for generating a high-frequency clock;
Detecting means for detecting a time interval between at least two horizontal synchronizing signals;
A comparison means for comparing the time interval detected by the detection means with a preset target value and outputting the difference as a comparison result;
Phase shift data generating means for generating phase shift data for controlling the phase shift amount of the pixel clock;
Pixel clock generation means for generating a pixel clock according to the phase shift data based on the high frequency clock generated by the high frequency clock generation means;
The phase shift data generating means includes
One or more lookup tables storing a pattern of the phase shift data, and a correction circuit;
The correction circuit includes:
A comparison circuit that outputs a deviation signal between the comparison result output from the comparison unit and a correction signal based on the past comparison result output from the comparison unit before the comparison result, and the comparison circuit that is output from the comparison circuit An integrator that integrates the deviation signal and outputs a correction signal; and a data holding circuit that holds the correction signal output from the integrator; and the correction signal held in the data holding circuit is the past Is supplied to the comparison circuit as a correction signal based on the comparison result of
The phase shift data generation means reads out and outputs phase shift data from the lookup table based on the correction signal output from the integrator.
This is a pixel clock generation device.

According to a second aspect of the present invention, in the pixel clock generation device according to the first aspect of the present invention, the phase control of the pixel clock is performed in units of each data area by using a plurality of continuous pixel clocks as one data area. It is.

According to a third aspect of the present invention, in the pixel clock generation device according to the first or second aspect , the phase shift data generation means has a plurality of look-up tables and reads out the phase shift data within one scanning period. Is characterized by switching.

According to a fourth aspect of the present invention, in the pixel clock generating device according to the first or second aspect of the present invention, the intervals of the pixel clocks to be phase shifted are substantially equal.

According to a fifth aspect of the present invention, in the pixel clock generation device according to the first or second aspect of the present invention, the intervals of the pixel clocks to be phase-shifted are made uneven.

According to a sixth aspect of the present invention, in the pixel clock generating device according to the first aspect of the present invention, an image height section with a large amount of change in main scanning dot position deviation is compared with an image height section with a small amount of change in main scanning dot position deviation. The interval between pixel clocks for phase shifting is reduced.

According to a seventh aspect of the invention, in the pixel clock generation device according to the fourth aspect of the invention, the phase shift data generation means is a value obtained by multiplying the reference clock value by the correction magnification corresponding to the resolution, with respect to the interval of the pixel clock to be phase shifted. It is characterized by including a means for setting.

According to an eighth aspect of the invention, in the pixel clock generation device according to the first or second aspect of the invention, the phase shift data generation means switches a look-up table for reading phase shift data for each scanning line. It is.

According to a ninth aspect of the present invention, in the pixel clock generation device according to the first or second aspect of the invention, the phase shift data generation means is configured to output phase shift data when scanning lines outputting the same phase shift data pattern are continuous. The pattern is changed.

According to a tenth aspect of the present invention, in the pixel clock generation device according to the first or second aspect of the invention, the phase shift data generation means has a look-up table when scanning lines outputting the same phase shift data pattern are continuous. The pattern of the phase shift data is changed by switching between.

According to a eleventh aspect of the present invention, in the pixel clock generation device according to the tenth aspect of the invention, the phase shift data pattern after switching the lookup table is phase-shifted in the phase shift data pattern before switching the lookup table. The pixel clock at a substantially intermediate position of the pixel clock is phase-shifted.

According to a twelfth aspect of the present invention, in the pixel clock generation device according to the tenth aspect of the invention, the phase shift data pattern after switching the lookup table is phase-shifted in the phase shift data pattern before switching the lookup table. The pixel clock at a position shifted by a fixed number of clocks from the pixel clock is phase-shifted.

According to a thirteenth aspect of the present invention, in the pixel clock generation device according to the tenth aspect of the present invention, the phase shift data generating means includes N (where N ≧ 2) consecutive scanning lines to which the same phase shift data pattern is output. In this case, the phase shift data pattern is changed by switching the look-up table in the next scanning line.

According to a fourteenth aspect of the present invention, in the pixel clock generating device according to the tenth, eleventh, twelfth or thirteenth aspect of the present invention, the switching of the look-up table is performed when the scanning lines outputting the same phase shift data pattern are continuous. It is characterized in that it is performed only in an effective scanning area where image formation is performed in a line.

The invention of claim 15
Image formation in which one or more light beams output from one or more light sources are incident on a deflecting unit, and an image is formed on the scanned medium by scanning the scanned medium with the light beam deflected by the deflecting unit A device,
The pixel clock generation device according to any one of claims 1 to 14 ,
Horizontal synchronization detection means for detecting scanning timings of two or more specific horizontal scanning positions by the light beam in order to generate two or more horizontal synchronization signals to be supplied to the pixel clock generation device;
The image forming apparatus is characterized in that the light source is driven in synchronization with a pixel clock generated by the pixel clock generation apparatus.

According to a sixteenth aspect of the present invention, in the image forming apparatus according to the fifteenth aspect , the horizontal synchronization detecting means includes three light detecting means for receiving the light beam, and the three light detecting means are the light beam. Are provided such that the optical path lengths from the deflecting means to the light detecting means are substantially the same.

According to a seventeenth aspect of the present invention, in the image forming apparatus according to the fifteenth aspect , the horizontal synchronization detecting means separates a part of the light beam deflected by the deflecting means, and the light beam separated by the means. And two or more light detecting means provided at positions corresponding to the two or more specific horizontal scanning positions, respectively.

According to an eighteenth aspect of the present invention, in the image forming apparatus according to the fifteenth aspect , the horizontal synchronization detecting means separates a part of the light beam deflected by the deflecting means, and the light beam separated by the means. And two or more reflecting members provided at positions corresponding to the two or more specific horizontal scanning positions, and one light detecting means for receiving the light beam reflected by all the reflecting members. It is characterized by that.

According to a nineteenth aspect of the present invention, in the image forming apparatus according to the fifteenth aspect , the horizontal synchronization detecting means separates a part of the light beam deflected by the deflecting means, and the light beam separated by the means. Two or more reflecting members or reflecting / transmitting members respectively provided at positions corresponding to the two or more specific horizontal scanning positions, and a light beam reflected by all the reflecting members or reflecting / transmitting members It is characterized by comprising one light detection means for receiving the light.

A twentieth aspect of the invention is the image forming apparatus according to the fifteenth aspect , further comprising a reference light source, and a reference light beam output from the reference light source is incident on the deflecting unit, and the deflecting unit. The reference light beam deflected by the above scans the outside of the scanned medium, and the horizontal synchronization detecting means receives the reference light beam deflected by the deflecting means. It is characterized by comprising two or more light detection means respectively provided at positions corresponding to.

A twenty-first aspect of the invention is the image forming apparatus according to the fifteenth aspect of the invention, further comprising a reference light source, and a reference light beam output from the reference light source is incident on the deflection means, and the deflection means The reference light beam deflected by the above scans the outside of the scanned medium, and the horizontal synchronization detecting means receives the reference light beam deflected by the deflecting means at the two or more specific horizontal scanning positions. It is characterized by comprising two or more reflecting members provided at positions corresponding to 1 and one light detecting means for receiving the reference light beam reflected by all the reflecting members.

According to a twenty-second aspect of the present invention, in the tandem-type image forming apparatus, the pixel clock generating device according to any one of the first to fourteenth aspects, and the pixel clock generating device supplied to the pixel clock generating device, for each color station. It has a horizontal synchronization detection means for generating the above horizontal synchronization signal, and the image writing light source of each color station is driven in synchronization with the pixel clock generated by the pixel clock generation device corresponding to the station. It is characterized by that.

(1) According to the inventions of claims 1 to 22 , the main scanning dot position shift due to the characteristics of the scanning optical system in the image forming apparatus or environmental fluctuations can be corrected with high accuracy, and therefore high-quality image formation can be achieved. Possible. Further, it is possible to easily cope with differences in characteristics of the scanning optical system only by changing the lookup table. Furthermore, the frequency of the high-frequency clock for generating the pixel clock does not need to be so high as compared to the pixel clock frequency, which is a great technical and cost advantage in realizing the pixel clock generating device.

(2) Further , since the fluctuation of the scanning time is detected by dividing it into two or more sections of the scanning line and the phase of the pixel clock can be controlled according to the scanning time fluctuation of each section, the entire scanning line can be controlled. Compared with the case where the phase control of the pixel clock is performed in accordance with the variation of the scanning time, the main scanning dot position deviation can be corrected with higher accuracy.

(3) According to the invention of claim 2 , the size (data amount) of the lookup table for storing the phase shift data of the pixel clock can be reduced.

(4) According to the third aspect of the present invention, even when the difference in main scanning dot position deviation characteristics varies greatly depending on the scanning region, the main scanning dot position can be selected by selecting and using a lookup table suitable for each region. It is possible to correct the deviation with high accuracy.

(5) According to the invention of claim 4 , visual image unevenness due to position correction of consecutive dots on the scanning line is less likely to occur.

(6) According to the invention of claim 5 , periodic scanning unevenness does not occur as compared with the case of correcting the dot positions at regular intervals.

(7) According to the sixth aspect of the invention, it is possible to perform highly accurate main scanning dot position deviation correction from an image height having a large change amount of main scanning dot position deviation to an image height having a small change amount.

(8) According to the invention of claim 7 , it is possible to perform dot position correction at a constant rate regardless of the resolution.

(9) According to the inventions of claims 8 to 14 , it is possible to prevent occurrence of vertical streak noise or the like that is conspicuous when dot position correction is performed on consecutive scanning lines according to the same phase shift data pattern. it can. According to the fourteenth aspect of the present invention, since a plurality of look-up tables need only be prepared for effective scanning regions that directly affect the image quality, the number of look-up tables and the overall size can be reduced.

(10) According to the eighteenth , nineteenth and twenty-first aspects of the present invention, only one light detecting means for detecting the horizontal synchronization is required. is there.

(11) According to the inventions of claims 20 and 21 , since horizontal synchronization is detected by a reference light beam that is not modulated by image data, three or more horizontal synchronization signals are reliably generated even in a scanning line during image recording. be able to. Therefore, “real time” pixel clock phase control according to the scanning time variation between three or more horizontal synchronizing signals becomes possible.

(12) According to the invention of claim 22, the horizontal dot position shift can be corrected with high accuracy for each color, and therefore the color shift can also be corrected effectively, so that the color reproducibility is high. A color image with high image quality can be formed.
And so on.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

<< Basic configuration of pixel clock generator >>
A basic configuration of the pixel clock generation device of the present invention will be described. This pixel clock generator outputs a pixel clock PCLK that determines the pixel timing of the image forming apparatus. As will be described later, two pixel clocks generated by detecting the scanning beam of the image forming apparatus with a photodetector. The above horizontal synchronization signals sync1 to n (n ≧ 1) are input.

  As shown in FIG. 1, the pixel clock generation device includes a high frequency clock generation unit 2, a detection unit 3, a comparison unit 4, a phase shift data generation unit 5, and a pixel clock generation unit 6.

  The high frequency clock generation unit 2 is a means for generating a high frequency clock VCLK that serves as a reference for the pixel clock PCLK.

The detection unit 3 is a means for detecting a time interval between two horizontal synchronization signals, counts the high frequency clock VCLK generated between the two horizontal synchronization signals, and outputs the count value.

  The comparison unit 4 compares the time interval (high-frequency clock count value) detected by the detection unit 3 with a preset target value (specifically, the time interval represented by the count value of the high-frequency clock) It is means for outputting the difference (horizontal scanning time or speed deviation).

  The phase shift data generation unit 5 is a means for generating phase shift data for controlling the phase shift amount of the pixel clock in order to correct the difference (horizontal scanning time or speed shift amount) obtained by the comparison unit 4. is there. As will be described later, the phase shift data generation unit 5 incorporates one or more look-up tables (LUTs) storing phase shift data patterns, and reads and outputs the phase shift data from the LUTs.

  The pixel clock generation unit 6 is a means for generating a pixel clock PCLK whose phase is controlled according to the phase data shift based on the high frequency clock VCLK.

  FIG. 2 shows an example of the internal configuration of the pixel clock generator 6. In FIG. 2, the pixel clock generation unit 6 includes a counter 21, a comparison circuit 22, and a pixel clock control circuit 23.

  The counter 21 operates at the rising edge of the high frequency clock VCLK and counts the same clock. The comparison circuit 22 uses the count value of the counter 21, a preset value (for example, 3), and phase shift data (phase for determining the transition timing of the pixel clock) given from the phase shift data generation unit 5 (FIG. 1). And the control signals a and b are output based on the comparison result. The pixel clock control circuit 23 controls the transition timing of the pixel clock PCLK based on the control signal a and the control signal b.

  The operation of the pixel clock generation unit 6 will be described with reference to timing diagrams of FIGS. Here, the pixel clock PCLK is divided by 8 of the high-frequency clock VCLK, and the duty ratio is 50% as a standard. FIG. 3 shows how a standard pixel clock PCLK with a duty ratio of 50% corresponding to the frequency division of the high frequency clock VCLK by 8 is generated, and FIG. FIG. 5 shows a state in which the pixel clock PCLK having a phase advanced by 1/8 clock with respect to the frequency-divided clock of the high-frequency clock VCLK is generated. .

  First, FIG. 3 will be described. Here, a value of “7” is given as the phase shift data. The value preset in the comparison circuit 22 is “3”. The counter 21 operates at the rising edge of the high frequency clock VCLK and performs counting.

  The comparison circuit 22 first outputs the control signal a when the value of the counter 21 reaches a preset value “3”. Since the control signal a becomes “H”, the pixel clock control circuit 23 changes the pixel clock PCLK from “H” to “L” at the rising timing of the high-frequency clock VCLK shown in FIG.

  Next, the comparison circuit 22 compares the given phase data value with the count value, and outputs a control signal b when they match. In FIG. 3, when the value of the counter 21 reaches “7”, the comparison circuit 22 outputs the control signal b. Since the control signal b becomes “H”, the pixel clock control circuit 23 changes the pixel clock PCLK from “L” to “H” at the rising timing of the high frequency clock VCLK shown in FIG. At this time, the comparison circuit 22 resets the counter 21 at the same time and restarts counting from zero.

  As a result, as shown in FIG. 3, a pixel clock PCLK having a duty ratio of 50% corresponding to the frequency division of the high frequency clock VCLK by 8 is generated. Note that if the value preset in the comparison circuit 22 is changed, the duty ratio of the pixel clock PCLK changes.

  Next, FIG. 4 will be described. Here, a value of “8” is given as the phase shift data. The counter 21 counts the high frequency clock VCLK.

  The comparison circuit 22 first outputs the control signal a when the value of the counter 21 reaches “3”. Since the control signal a becomes “H”, the pixel clock control circuit 23 changes the pixel clock PCLK from “H” to “L” at the rising timing of the high-frequency clock VCLK shown in FIG.

  Next, the comparison circuit 22 outputs the control signal b when the value of the counter 21 matches the value of the given phase shift data (here, “8”). Since the control signal b becomes “H”, the pixel clock control circuit 23 changes the pixel clock PCLK from “L” to “H” at the rising timing of the high-frequency clock VCLK shown in FIG. At the same time, the comparison circuit 22 resets the counter 21 and restarts counting from zero.

  As a result, as shown in FIG. 4, a pixel clock PCLK having a phase delayed by 1/8 clock with respect to the divided clock of the high frequency clock VCLK by 8 is generated.

  Next, FIG. 5 will be described. Here, a value of “6” is given as the phase shift data. The counter 21 counts the high frequency clock VCLK.

  The comparison circuit 22 first outputs the control signal a when the value of the counter 21 reaches “3”. Since the control signal a becomes “H”, the pixel clock control circuit 23 changes the pixel clock PCLK from “H” to “L” at the rising timing of the high frequency clock shown in FIG.

  Next, the comparison circuit 22 outputs the control signal b when the value of the counter 21 matches the value of the given phase shift data (here, “6”). Since the control signal b becomes “H”, the pixel clock control circuit 23 changes the pixel clock PCLK from “L” to “H” at the rising timing of the high-frequency clock indicated by a. At the same time, the comparison circuit 22 counter 21 is reset and the count is restarted from zero.

  As a result, as shown in FIG. 5, a pixel clock PCLK in which the phase is advanced by 1/8 clock with respect to the divided clock of the high frequency clock VCLK by 8 is generated.

  FIG. 6 shows a timing relationship between the high frequency clock, the phase shift data, and the pixel clock.

  FIG. 7 shows an example of the internal configuration of the phase shift data generation unit 5. In FIG. 7, the phase shift data generation unit 5 includes a correction circuit 30, a data generation circuit 34, and a control circuit 35.

  In the present invention, as will be described later, the comparison result by the comparison unit 4 in each scanning line during the recording period of each page in the image forming apparatus is used, or one scanning line or several scans in the inter-page margin period. The comparison result by the comparison unit 4 in the line may be used.

  The correction circuit 30 is a means for generating a correction signal e obtained by averaging the current comparison result of the comparison unit 4 and the previous comparison result. More specifically, the correction circuit 30 includes a comparison circuit 32, an integrator 33, and a data holding circuit 31. The comparison circuit 32 compares the comparison result of the comparison unit 4 with the correction signal held in the data holding circuit 31 and outputs the deviation signal. The integrator 33 outputs a correction signal e obtained by integrating the deviation signal. This correction signal is held in the data holding circuit 31 and is compared with the next comparison result in the comparison circuit 32. By configuring the correction circuit 30 with such a configuration, it is possible to generate stable phase shift data corresponding to a change with time, a temperature change, etc. of the scanning system of the image forming apparatus.

  The data generation circuit 34 includes an LUT storage unit 36 for storing one or more lookup tables (LUTs) 37 storing phase shift data patterns, and phase shift data stored in any one of the LUTs 37. A table address generation circuit 38 for generating an address for reading the pattern, and a shift register circuit 39 for holding the read phase shift data pattern and sequentially outputting the phase shift data in synchronization with the pixel clock PCLK. .

  The control circuit 35 performs selection of the LUT to be read and operation control of the table address generation circuit 38, the shift register circuit 39, and the correction circuit 30. The control circuit 35 receives a pixel clock, a horizontal synchronization signal, and the like necessary for the operation, but are not shown. Depending on the data structure of the LUT stored in the LUT storage unit 36, the shift register circuit 39 can be omitted or replaced by a simple latch circuit.

As described above, as a cause of deviation from the main scanning dot position in the image forming apparatus,
(1) The fθ characteristic of the scanning lens is not sufficiently corrected.
(2) Deterioration in processing accuracy and mounting accuracy of optical components of the optical scanning optical system.
(3) The focal length of the scanning optical system changes due to the deformation of the optical parts and the change in refractive index due to environmental changes such as the temperature and humidity in the apparatus, and the fθ characteristic deteriorates.
And so on.

  In particular, the main scanning dot position shift due to environmental fluctuations cannot be avoided even if optical adjustment or electrical correction is performed at the time of shipment of the apparatus. For example, even if there is no problem during the first printing, the temperature in the apparatus rises when printing is continuously performed, and the color of the first print and the color after printing a plurality of prints may change. May happen.

  Therefore, in the present invention, the characteristic value of the relationship between the dot position deviation of the real image height and the ideal image height of the scanning optical system is grasped in advance by a preliminary experiment or simulation, and a lookup table is obtained from the characteristic value. create. Then, the phase shift data generation unit 5 is provided with this lookup table, and the phase shift data pattern corresponding to the time variation between the horizontal synchronizing signals is read from the lookup table, and the phase of the pixel clock is controlled according to the phase shift data. By doing so, the dot position deviation is corrected with high accuracy. Further, it is intended to easily and flexibly cope with the difference in the characteristics of the scanning optical system in the image forming apparatus only by changing the lookup table, and to enable highly accurate correction of the main scanning dot position deviation.

  Next, an example of the phase shift data pattern generated by the data generation circuit 34 will be described with reference to FIG. Here, the pixel clock PCLK is divided by 8 of the high-frequency clock VCLK. When the value of the correction signal e supplied to the data generation circuit 34 is “0”, phase shift data “7” is generated in the period of all pixel clocks PCLK in one line. When the value of the correction signal e is positive, phase shift data of “8” is generated in e pixel clock PCLK intervals of approximately equal intervals in one line period, and “7” is generated in other pixel clock PCLK intervals. Phase shift data is generated. When the value of the correction signal e is negative, phase shift data of “6” is generated in the pixel clock PCLK interval of approximately equal intervals in one line period, and “7” in the other pixel clock PCLK intervals. ”Is generated. In the LUT 37, a pattern of phase shift data as shown in this example is stored at an address associated with the value of the correction signal e.

  When the scanning optical system of an image forming apparatus in which this pixel clock generation device is used has ideal linearity characteristics, the phase of the pixel clock is shifted by controlling the phase of the pixel clock according to such phase shift data. Are distributed substantially evenly, so that unevenness in the scanning width of each line can be corrected while reducing the influence on the image.

  However, since the linearity characteristic of the actual scanning optical system deviates from the ideal characteristic, as will be described later, a phase shift data pattern LUT is prepared in consideration of the linearity characteristic of the scanning optical system. Further, when a polygon mirror having a plurality of reflecting surfaces is used as a deflector, in order to correct the variation of each reflecting surface with high accuracy, an LUT of a phase shift data pattern is prepared for each reflecting surface, The LUT used corresponding to the switching of the reflecting surface is selected.

  In the pixel clock generation device of the present invention, various modes can be taken regarding the phase shift control of the pixel clock. This will be described in detail later.

  Hereinafter, various embodiments of the pixel clock generation apparatus of the present invention and the image forming apparatus of the present invention using the pixel clock generation apparatus will be described.

  FIG. 9 is a schematic configuration diagram of an image forming apparatus according to Embodiment 1 of the present invention. This image forming apparatus is of an electrophotographic type, and a laser light beam output from the semiconductor laser 100 enters a polygon mirror 103 as a polarizer through a collimator lens 101 and a cylinder lens 102. The laser beam deflected by the polygon mirror 103 passes through the f-θ lens 104 which is a scanning lens, is reflected by the half mirror 105 (partially transmitted), and the surface (scanned surface) of the photosensitive member 106 which is a scanned medium. ) A light beam spot is formed thereon, and an image (electrostatic latent image) is formed.

  Photodetector (light detection means) A107 for generating horizontal synchronization signals 1 and 2 at both end positions of the detection surface that is temporally correlated with the surface to be scanned, which is scanned by the laser beam transmitted through the half mirror 105. And a photodetector B108.

  That is, the horizontal synchronization detecting means in this embodiment separates a part of the laser light beam deflected by the polygon mirror 103 by the half mirror 105, and the separated laser light beam corresponds to two specific horizontal scanning positions. In this configuration, light is received by the photodetectors 107 and 108 arranged at the positions.

  A charging unit for charging the surface of the photosensitive member 106, a developing unit for developing the electrostatic latent image into a toner image, a transfer unit for transferring the developed toner image to a sheet or an intermediate transfer member, and a photosensitive member. There are also general means as this type of image forming apparatus, such as a cleaner means for removing and collecting the toner remaining on the body 106, but these means are not shown in order to avoid complexity.

Reference numeral 110 denotes a pixel clock generation device according to the present invention as described above, 111 denotes an image processing device, 112 denotes a laser drive data generation device, and 113 denotes a laser drive device. The detection signals of the photodetector A 107 and the photodetector B 108 are input to the pixel clock generation device 110 as horizontal synchronization signals 1 and 2 (sync1, sync2), and the horizontal synchronization signal 1 is also input to the image processing device 111 as a line synchronization signal. The Instead of using the detection signals of the respective photodetectors as they are as the horizontal synchronization signal, inverted signals of those signals may be used as the horizontal synchronization signal (see FIG. 10).

  The pixel clock PCLK generated by the pixel clock generation device 110 is input to the image processing device 111 and the laser drive data generation device 112. The image processing device 111 generates image data of each line in synchronization with the line synchronization signal (horizontal synchronization signal 1), and outputs it in synchronization with the pixel clock PCLK. The laser drive data generation device outputs laser drive data (modulation data) corresponding to the image data in synchronization with the pixel clock. The laser driving device 113 drives (modulates) the semiconductor laser 100 according to the laser driving data.

  FIG. 10 is a schematic diagram for explanation. (A) is the linearity characteristic of the scanning optical system, the vertical axis indicates the dot position deviation in the main scanning direction, and the horizontal axis indicates the image height ratio. (B) shows the relationship between the effective writing area and the photodetectors A and B. (C) shows the detection signals of the photodetectors A and B as one signal. (D) is the horizontal synchronization signals 1 and 2 (sync 1 and 2), which are shown here as one signal obtained by inverting the detection signals of the photodetectors A and B.

  When the rotation speed of the polygon mirror fluctuates due to temperature change, secular change, power supply voltage fluctuation, etc., the time interval between the horizontal synchronization signals 1 and 2 changes. In the pixel clock generation device of the present invention, the LUT in which the phase shift data pattern corresponding to the shift amount between the time interval of the horizontal synchronization signals 1 and 2 and the target value is recorded is used as the LUT storage unit of the phase shift data generation unit 5. 36 (FIG. 6), the phase of the pixel clock is appropriately controlled even when the time interval between the horizontal synchronization signals 1 and 2 varies, and the scan width and the dot position deviation in the main scanning direction are high. It is corrected to accuracy. Further, when it is necessary to prepare a phase shift data pattern for each reflecting surface due to variations in processing accuracy of the reflecting surface of the polygon mirror, the LUT corresponding to each reflecting surface is stored in the LUT storage unit 36. In addition, by switching the LUT to be used in accordance with the switching of the reflecting surface, the scanning width and the dot position deviation in the main scanning direction are corrected with high accuracy in any line scanned by any reflecting surface.

  Even during the recording of one page, there are cases where fluctuations in scanning speed due to temperature rise cannot be ignored. It is obvious that such a variation in the page can be corrected with high accuracy by operating the detection unit 3 and the comparison unit 4 of the pixel clock generation device for each line.

  Here, the linearity characteristic and the phase shift data pattern will be described with reference to FIG. (A) shows an example of the linearity characteristic of the scanning optical system, and (b) shows an example of a phase shift data pattern corresponding to each region A, B, C, and D of the reality characteristic.

  In regions such as regions A and C where the slope of the linearity curve is positive, the dot interval in the main scanning direction becomes wider than in the ideal case, so “5” or “6” is used to advance the phase of the pixel clock PCLK. Phase shift data. Then, phase shift data “5” is given where the slope of the linearity curve is large. In a region where the slope of the linearity curve is negative, such as region B or region D, the dot interval becomes narrower than ideal, so the phase of “9” or “8” is used to delay the phase of the pixel clock PCLK. Give shift data. Then, phase shift data of “9” is given where the slope of the linearity curve is large. Further, since the dot interval does not change when the slope of the linearity curve is 0, “7” is given as the phase shift data.

  By preparing an LUT for generating phase shift data corresponding to such linearity characteristics in advance, the phase shift amount of the pixel clock PCLK as one whole line is corrected to be provided to the data generation circuit 34 in FIG. It is made equal to the value of the signal e. That is, when the correction signal e is 0, the number of pixels per line is Np, and phase shift data is generated so that the total value of the phase shift data for one line is equal to “7 × Np”. When the correction signal e is positive, the phase shift data is generated so that the total value of the phase shift data for one line is equal to “7 × Np + e”. When the correction signal e is negative, the phase shift data is generated so that the total value of the phase shift data for one line is equal to “7 × Np− | e |”. By doing so, it is possible to equalize the pixel intervals by aligning the scanning width for each line and correcting the dot position deviation of the main scanning due to the linearity characteristic of the scanning optical system.

  In order to precisely align the image writing start positions of the respective lines, it is preferable to add a counter 24 and a comparison circuit 25 to the pixel clock generation unit 6 as shown in FIG. The counter 24 operates at the rising edge of the high-frequency clock VCLK and counts the same clock. When the horizontal synchronization signal 1 is input, the counter 24 is reset and restarts counting from zero. The comparison circuit 25 compares the value of the counter 24 with the set value, and validates the control signal c when the count value becomes equal to or greater than the set value. The pixel clock control circuit 23 controls the writing timing of the pixel clock PCLK according to the control signal c. Therefore, by determining the set value for the comparison circuit 25 in accordance with the time interval between the horizontal synchronization signal 1 and the image writing start position, the image writing start position of each line can be made uniform.

  Details of the main scanning dot position correction by the phase shift of the pixel clock will be described with reference to FIG.

  An “ideal state” in FIG. 13 indicates a dot position in an ideal state in which there is no uneven scanning speed or no exposure deviation. Here, 1200 dpi and a dot diameter of about 21.2 μm are used.

  “Before correction” in FIG. 13 is a state in which the position of the first dot is the same, but there is a dot position shift due to uneven scanning speed or exposure shift. A position shift of 10.6 μm corresponding to / 2 dots occurs. In this state, the time required to write one dot is equivalent to 1 pixel clock = 1 PCLK. Therefore, if the resolution of the phase shift of the pixel clock is 1/8 PCLK, it is synonymous with correcting the dot position with 1/8 dot accuracy. is there.

  “After correction” in FIG. 13 shows that when the phase shift resolution is 1/8 dot, that is, 1/8 PCLK, the phase of −1/8 PCLK from the “before correction” state where a half-dot position shift occurs from the ideal state. The dot positions when the shift is performed four times in the data area are shown. Theoretically, the dot position of the 6th dot can be shifted by -1/8 PCLK x 4 = -1/2 PCLK, and the dot position can be corrected with an accuracy of 1/8 PCLK against the "ideal state". it can.

  In this manner, the pixel clock generation device can shift the phase of the pixel clock in units of a fraction of a clock for each clock, and the main scanning position of each pixel can be shifted in units of ± “one fraction of a dot”. Therefore, in principle, in the case of ± 1/8 dot shift, the linearity correction amount can be adjusted from 0% to 12.5%. In the case of 1200 dpi writing, the main scanning position deviation within the effective writing width is reduced to 2.6 μm (21.2 μm / 8).

  The frequency of the high-frequency clock VCLK necessary to realize such highly accurate main scanning dot position deviation correction may be eight times the basic frequency of the pixel clock PCLK. If a high-frequency clock having such a frequency is used, the pixel clock generation device is not so difficult to implement, and this is one of the effects of the present invention.

  FIG. 14 is a schematic configuration diagram of an image forming apparatus according to Embodiment 2 of the present invention. The image forming apparatus includes a semiconductor laser 201 as a reference light source for horizontal synchronization detection, in addition to the semiconductor laser 200 as an image writing light source.

  The laser light beam output from the image writing semiconductor laser 200 enters the polygon mirror 206 through the collimator lens 202, the slit of the aperture 204, and the cylinder lens 205. The laser beam deflected by the polygon mirror 206 forms a light beam spot on the surface (scanned surface) of the photosensitive member 209 via the f-θ lens 207 and the transparent member 208, thereby forming an electrostatic latent image.

  A laser light beam output from a semiconductor laser 201 as a reference light source is incident on a polygon mirror 206 via a collimator lens 203, a slit of an aperture 204, and a cylinder lens 205. The laser light beam of the reference semiconductor laser 201 and the laser light beam of the image writing semiconductor laser 200 are incident on the same reflecting surface of the polygon mirror 206. The reference laser beam and the image writing laser beam are incident on the same position in the main scanning direction, but are incident on a position shifted by a certain interval in the sub-scanning direction. As a result, the reference laser beam deflected by the polygon mirror 206 passes through the f-θ lens 208 and the transparent member 208 but does not enter the photoconductor 209. Therefore, the semiconductor laser 201 as the reference light source can emit light regardless of the image data.

  A surface to be detected, which is equivalent to the surface to be scanned of the photoconductor 209 scanned by the image writing laser light beam, is scanned by the reference laser light beam. The horizontal sync signals 1 and 2 (sync 1 and 2) are obtained by detecting the reference laser light with the photodetectors 210 and 211 arranged above.

  That is, the horizontal synchronization detecting means in this embodiment is configured to receive the reference laser beam deflected by the polygon mirror 206 by the photodetectors 210 and 211 arranged at positions corresponding to two specific horizontal scanning positions. .

  The optical path lengths L1 ′ and L2 ′ of the laser beam output from the reference semiconductor laser 201 to the photodetectors 210 and 211, and the output of the writing semiconductor laser 400 to the corresponding position on the photoconductor 209 The positional relationship is determined so that the optical path lengths L1 and L2 of the laser light are substantially the same. Accordingly, it is possible to obtain a horizontal synchronization signal that is not affected by the optical path length difference.

  In FIG. 14, reference numeral 220 denotes a pixel clock generator of the present invention, 221 denotes an image processing device, 222 denotes a laser drive data generator, and 223 denotes a laser driver, which correspond to the first embodiment (FIG. 9). Is the same device. The laser driving device 223 drives the image writing semiconductor laser 200 based on the image data, but also drives the reference semiconductor laser 201 for horizontal synchronization detection.

  In the image forming apparatus of the present embodiment, the time interval between the horizontal synchronization signals is measured in each line in each recorded page, and the deviation from the target value is reflected in the phase control of the pixel clock of the next line. Real-time control is possible. According to such control, even when the influence of the temperature rise in the page cannot be ignored, the scanning width and dot position deviation of each line in the page can be corrected with high accuracy.

  Although the same real-time control is possible in the first embodiment, it is necessary to leave a sufficient interval between the horizontal synchronization detection position and the image writing start / end position in order to perform this. In the case of the present embodiment, the interval can be reduced. Since the linearity of the scanning optical system becomes worse as the distance from the effective image writing area increases, it is generally advantageous to improve the accuracy of the phase control of the pixel clock to be able to approach the horizontal synchronization detection position and the image writing start / end position. .

  Note that a charging unit for charging the surface of the photoconductor 209, a developing unit for developing the electrostatic latent image into a toner image, a transfer unit for transferring the developed toner image to a sheet or an intermediate transfer member, and a photosensitive unit. Although there are means included in this type of image forming apparatus, such as a cleaner means for removing and collecting the toner remaining on the body 209, they are omitted in the drawing.

  FIG. 15 is a schematic configuration diagram of an image forming apparatus according to Embodiment 3 of the present invention. In this image forming apparatus, the laser light beam output from the semiconductor laser 300 enters the polygon mirror 303 through the collimator lens 301 and the cylinder lens 302. The laser light beam deflected by the polygon mirror 303 passes through the f-θ lens 304, is reflected by the half mirror 305 (partially transmitted), and passes through the toroidal lens 314 to the surface of the photosensitive member 306 (covered medium). A light beam spot is formed on the scanning surface) to form an image (electrostatic latent image).

  Photodetector A307, photodetector B308, and photodetector C309 for detecting horizontal synchronization are arranged at both end positions and the center position of the detection surface scanned by the laser light transmitted through half mirror 305. That is, the horizontal synchronization detecting means of the present embodiment receives the laser beam separated by the half mirror 305 by the three photodetectors 307, 308, and 309 arranged at the positions corresponding to the specific three horizontal scanning positions. It is a configuration.

  Reference numeral 310 denotes a pixel clock generation device according to the present invention, 311 denotes an image processing device, 312 denotes a laser drive data generation device, and 313 denotes a laser drive device, which are the same devices as the corresponding parts of the first embodiment. The operation of the pixel clock generator 310 is partially different from the operation of the pixel clock generator 110 of the first embodiment, which will be described later.

  The detection signals of the photo detector A307, the photo detector C309, and the photo detector B308 are input to the pixel clock generation device 310 as horizontal synchronization signals 1, 2, and 3 (sync1, sync2, sync3), and the horizontal synchronization signal 1 is an image as a line synchronization signal. The data is also input to the processing device 311. Instead of using the detection signals of the respective photodetectors as the horizontal synchronization signal as they are, an inverted signal of those signals may be used as the horizontal synchronization signal.

  Note that a charging unit for charging the surface of the photosensitive member 306, a developing unit for developing the electrostatic latent image into a toner image, a transfer unit for transferring the developed toner image onto a sheet or an intermediate transfer member, and a photosensitive member. Although there are means included in this type of image forming apparatus, such as a cleaner means for removing and collecting the toner remaining on the body 306, they are omitted in the drawing.

  FIG. 16 is a schematic diagram for explanation. (A) is the linearity characteristic of the scanning optical system, the vertical axis indicates the dot position deviation in the main scanning direction, and the horizontal axis indicates the image height ratio. (B) shows the relationship between the effective writing area and the photodetectors A, B, and C. (C) shows the detection signals of the photodetectors A, B, and C as one signal. (D) is the horizontal synchronizing signals 1, 2, 3 (sync1, 2.3), which are shown here as one signal obtained by inverting the detection signals of the photodetectors A, B, C.

  The detection unit 3 (FIG. 1) of the pixel clock generation device 310 detects the interval time between the horizontal synchronization signals 1 and 2 and the interval time between the horizontal synchronization signals 2 and 3, respectively.・ Count value is output. The comparison unit 4 (FIG. 1) of the pixel clock generation device 310 compares each time interval with a preset target value and outputs the difference. The measurement of the time interval between the horizontal synchronization signals and the detection of the difference from the target value are performed during a period when the image forming apparatus is not recording an image, for example, a margin between pages. This is because, as is apparent from FIG. 16, the laser light incident on the photodetector C is modulated by image data during the image recording period, and the accuracy of the timing of the detection signal is not guaranteed. The horizontal synchronization signals 1 and 3 are also generated during the image recording period.

  In the phase shift data generator 5 (FIG. 7) of the pixel clock generator 310, the correction circuit 30 includes two correction signals corresponding to the time difference between the horizontal synchronization signals 1 and 2 and the time difference between the horizontal synchronization signals 2 and 3, respectively. e1 and e2 are generated. The LUT storage unit 36 of the data generation circuit 34 stores the LUT of the phase shift data pattern applied between the horizontal synchronization signals 1 and 2 (the first half of the line) and the horizontal synchronization signals 2 and 3 (the second half of the line). LUT of the phase shift data pattern applied to () is stored. In the first half of each line, the control circuit 35 causes the table address generation circuit 38 to generate a table address according to the correction signal e1, and selects an LUT to be applied to the first half of the line. The control circuit 35 counts the pixel clock PCLK with an internal counter from the time when the horizontal synchronizing signal 1 is generated, and from the counted value, the scanning dot position corresponds to the intermediate position of the effective writing area (corresponding to the timing of the horizontal synchronizing signal 2). The table address generation circuit 38 generates a table address in accordance with the correction signal e2, and selects an LUT to be applied to the latter half of the line.

  As for the linearity characteristics of the scanning optical system, the front half and the rear half of the line are not necessarily symmetrical, and the fluctuation of the scanning speed is the same. Therefore, as described above, the scanning time error of the first half and the second half of the line is measured, and based on this, the phase control of the pixel clock is performed according to the corresponding phase shift data pattern for the first half and the second half of the line. By performing the above, it is possible to correct the scanning width and the dot position with higher accuracy.

  FIG. 17 is a schematic configuration diagram of an image forming apparatus according to Embodiment 4 of the present invention. The image forming apparatus includes a semiconductor laser 401 as a reference light source for horizontal synchronization detection, in addition to the semiconductor laser 400 as an image writing light source.

  The laser light beam output from the image writing semiconductor laser 400 enters the polygon mirror 406 through the collimator lens 402, the slit of the aperture 404, and the cylinder lens 405. The laser light beam deflected by the polygon mirror 406 enters the photoconductor 409 via the f-θ lens 407 and the transparent member 408, and forms a light beam spot on the surface (scanned surface) to form an electrostatic latent image. Form.

  A laser light beam output from a semiconductor laser 401 serving as a reference light source enters a polygon mirror 406 via a collimator lens 403, a slit of an aperture 404, and a cylinder lens 405. The laser light beam of the reference semiconductor laser 401 and the laser light beam of the image writing semiconductor laser 400 are incident on the same reflecting surface of the polygon mirror 406. The reference laser beam and the image writing laser beam are incident on the same position in the main scanning direction, but are incident on a position shifted by a certain interval in the sub-scanning direction. As a result, the reference laser beam deflected by the polygon mirror 406 passes through the f-θ lens 407 and the transparent member 408 but does not enter the photoconductor 409. Therefore, the semiconductor laser 401 as the reference light source can emit light regardless of the image data.

  A surface to be detected deviated from the photoconductor 409, which is equivalent to the surface to be scanned of the photoconductor 409 scanned by the image writing laser beam, is scanned by the reference laser beam. By detecting the reference laser beam with the photodetectors 410, 413, and 412 arranged above, horizontal synchronization signals 1, 2, and 3 (sync1, 2, and 3) are obtained. That is, the horizontal synchronization detecting means in the present embodiment has three photo detectors 409, 412, which are arranged such that the reference laser beam deflected by the polygon mirror 40-6 is arranged at positions corresponding to three specific horizontal scanning positions. In this configuration, light is received at 413.

  The optical path lengths L1 ′, L2 ′, L3 ′ of the laser light output from the reference semiconductor laser 401 up to the photodetectors 410, 412, 413 and the corresponding positions on the photoconductor 409 are written. The positional relationship is determined so that the optical path lengths L1, L2, and L3 of the output laser light of the semiconductor laser 400 are substantially the same. Accordingly, it is possible to obtain a horizontal synchronization signal that is not affected by the optical path length difference.

  In FIG. 17, reference numeral 420 denotes a pixel clock generation apparatus according to the present invention, 421 denotes an image processing apparatus, 422 denotes a laser drive data generation apparatus, and 423 denotes a laser drive apparatus, which correspond to the third embodiment (FIG. 15). Is the same device. However, the laser driving device 423 drives the image writing semiconductor laser 400 based on the image data and drives the reference semiconductor laser 401.

  The pixel clock generator 420 can also perform the same operation as the pixel clock generator 420 in the third embodiment. However, in this embodiment, since the three horizontal synchronization signals 1, 2, and 3 can be generated in each line even in the image recording period, the pixel clock generation device 420 can generate the horizontal synchronization signals 1 and 2 in each line in the image recording period. Real-time control is also possible in which the time interval between the horizontal synchronization signals 2 and 3 is measured and the deviation from the target value is reflected in the phase control of the pixel clock of the next line.

  This real-time control will be described in more detail with reference to FIG. Correction signals e1 and e2 corresponding to the difference between the time interval between the horizontal synchronization signals 1 and 2 detected in each line and between the horizontal synchronization signals 2 and 3 and the target value are generated by the correction circuit 30. In the data generation circuit 34, the table address corresponding to the correction signal e1 is generated by the table address generation circuit 38 in the first half of each line, and the corresponding LUT is selected by the control circuit 35. In the latter half of the line, a table address corresponding to the correction signal e2 is generated by the table address generation circuit 38, and a corresponding LUT is selected by the control circuit 35. According to such control, even when the influence of the temperature rise in the page cannot be ignored, the scanning width and dot position shift of each line in the page can be corrected with higher accuracy.

  The image forming apparatus of this embodiment includes a charging unit for charging the surface of the photoreceptor 409, a developing unit for developing the electrostatic latent image into a toner image, and the developed toner image on a sheet or an intermediate transfer member. There are also means included in this type of image forming apparatus, such as a transfer means for transferring the toner to the surface, and a cleaner means for removing and collecting the toner remaining on the photoreceptor 409, but these are not shown in FIG.

<< Various aspects of pixel clock phase shift control >>
Various aspects relating to the phase shift control of the pixel clock will be described below. Here, the phase shift control of the pixel clock will be described on the assumption that two horizontal synchronization signals are detected as in the first and second embodiments, but three (or four or more) as in the third and fourth embodiments. It is obvious that the same pixel clock phase shift control can be applied even when the horizontal synchronization signal of) is detected.

  In the pixel clock generation device of the present invention, a plurality of continuous pixel clocks are defined as one data area, an effective scanning period is divided into a plurality of data areas, phase shift data is set for each data area, Phase shift control can be performed. This division can be performed equally or unevenly.

  FIG. 18 is an explanatory diagram of such pixel clock phase shift control. In FIG. 18, (a) shows horizontal synchronization signals 1 and 2 (sync1, sync2), (b) shows an effective scanning period between both horizontal synchronization signals, and (c) shows a pixel clock. (D) is a linearity curve of the scanning optical system, and the vertical axis indicates main dot displacement. The horizontal axis represents the image height ratio. The image height ratio at the center of the effective scanning period is defined as 0, and the image height ratio at the position where the horizontal synchronizing signals 1 and 2 are generated is defined as 1 and -1.

  (E), (f), and (g) divide the effective scanning period into N data areas, and the pixel clock for each data area so that the main scanning dot position deviation amount becomes 0 at the center of each data area. This shows the main scanning dot position deviation when the phase shift control is performed. The numbers on the horizontal axis are data area numbers. (E) is a case of equal division with a division number N = 15, (f) is an equal division with a division number N = 30, and (g) is a case of non-uniform division with a division number N = 18.

  In (e) to (g), if the amplitude of the main scanning dot position deviation after the phase shift of the pixel clock is X and the dot position deviation amount between the data areas is Y, X is the dot position deviation on the scanning line. The absolute value is shown, and it can be said that the smaller the value, the better the correction. Since the dot position deviation amount Y between the data areas is in a state where the dot positions between the data areas are sparse or dense when the value is large, it is better to take the smallest possible value. I can say that.

  According to the method of controlling the phase shift of the pixel clock by dividing in such a data area, the phase shift data in units of the data area is stored in the LUT storage unit 36 (FIG. 7) of the data generation unit 5 of the pixel clock generation apparatus. Since the stored LUT may be prepared, the size (data amount) of the LUT can be greatly reduced as compared with the case where phase shift data for each pixel clock is prepared without performing division.

  FIG. 19 shows an example of the phase shift of the pixel clock in the data area. When 30 clocks (30 PCLK) is one data area and the phase shift resolution of the pixel clock is ± 1/8 PCLK, the phase shift is performed for the three pixel clocks in the data area to obtain -3/8 PCLK dots. It is an example which performs position correction.

  19A shows a pixel clock train when no phase shift is performed, and FIG. 19B shows a dot shift correction by performing a phase shift of −1/8 PCLK every 10 clocks from the first clock in the data area. The pixel clock train in the case of performing is shown. (C) shows a pixel clock train when a phase shift of −1/8 PCLK is performed every 10 clocks from the fifth clock counted from the first clock of the data area. In (b) and (c), the phase-shifted clock is colored.

  When the phase shift method (b) or the phase shift method (c) is applied to a continuous line, vertical stripes corresponding to the phase-shifted dot positions may appear on the image. In order to reduce such vertical stripes, it is effective to switch the phase shift method for each line. For such switching of the phase shift method, for example, the LUT storing the phase shift data pattern according to each method is stored in the LUT storage unit 36 (FIG. 7) and used by the control circuit 35 for each line. This can be realized by switching the LUT. Alternatively, the phase shift data pattern according to each method is stored in the same LUT, and the control circuit 35 changes the value of the upper bits of the table address generated by the table address generation circuit 38 for each line. However, the phase shift control method can be converted for each line. Alternatively, the same phase shift data pattern is read from the LUT storage unit 36, and the control circuit 34 controls the output method of the phase shift data from the shift register circuit 39, thereby switching the phase shift method of the pixel clock for each line. It is also possible.

FIG. 20 shows an example of the LUT applied to the phase shift control of the pixel clock in each data area with 30 clocks as one data area. The LUT1, LUT2, and LUT3 shown here store phase shift data patterns as illustrated corresponding to correction signals e (see FIG. 7) corresponding to -5, 0, and +5. The value of the phase shift data is “6” for the phase shift data that shifts (advances) the phase of the pixel clock PCLK by −1/16 PCLK, “7” for the phase shift data that does not change the phase of the pixel clock PCLK, Phase shift data for shifting (delaying) the phase by +1/16 PCLK is defined as “8”.

  In each LUT, the phase shift data pattern corresponding to the correction signal e = -5 includes phase shift data for performing phase shift of −1/16 PCLK at five places in 30 clocks, and the correction signal e = 0 The phase shift data pattern corresponding to か ら consists only of phase data without phase shift, and the phase shift data pattern corresponding to the correction signal e = + 5 performs + 1 / 16PCLK phase shift at 5 locations in 30 clocks Including phase shift data. As shown in FIG. 20, the clock position where the phase shift is performed at the same correction signal e differs depending on which LUT is used to generate the phase shift data.

  If the phase shift data is generated using the LUT1 in the A area, the LUT2 in the D area, and the LUT3 in the B area when the scanning optical system has the linearity characteristics as shown in FIG. Thus, the phase shift control of the pixel clock suitable for the dot misregistration characteristic in FIG.

  As described above, the clock positions to be phase-shifted can be set at equal intervals or non-uniform intervals. FIG. 21 shows an example of the phase shift data pattern for such phase shift control together with the main scanning dot position deviation characteristics. Both are patterns for 30 clocks corresponding to the deviation signal e = −5.

  The phase shift data pattern shown in (a) of FIG. 21 is obtained by setting the clocks to be phase-shifted at equal intervals, and the phase shift data pattern shown in (b) is that the clocks to be phase-shifted are set at unequal intervals. Is. In the phase shift data pattern shown in (c), the interval of clocks to be phase shifted depends on the image height.

  When the phase shift control of the pixel clock is performed according to the phase shift data pattern as in (a), it is possible to prevent the occurrence of visual image unevenness due to the continuous phase-shifted clock. In other words, it can be said that the deviation of dot position correction within the control section is reduced.

  However, when phase shift of the pixel clock is performed at a constant interval, when a continuous dot shift of 0.5 mm to 1 mm or more is conspicuous from human visual characteristics, the conspicuous interval is close to the phase shift interval of the pixel clock. It tends to be a noticeable image such as vertical stripes. If the phase shift of the pixel clock is performed at non-uniform intervals according to the phase shift data pattern as shown in FIG. 21B, such periodic scanning unevenness can be prevented.

  In the phase shift data pattern shown in FIG. 21C, the phase shift clock interval is narrow at an image height having a large change amount of the main scanning dot position shift amount, and at an image height having a small main scan dot position shift amount. The interval between the phase-shifted clocks is set to be wide. If the phase control of the pixel clock is performed in accordance with such a phase shift data pattern, highly accurate main scanning dot position deviation correction can be realized at any image height.

  When the pixel clock phase control of the pixel clock is performed according to the phase shift data pattern in which the phase shift clock as shown in FIG. It is possible to easily cope with the change.

For example, assuming that the resolution is 1200 dpi, the phase shift clock interval at that time is N0, the phase shift clock interval at a certain resolution is N, and the magnification of the resolution with respect to the reference resolution is M.
N = M × N0
Can be calculated.

For example, assuming that N0 = 12, the phase shift of ± 1/8 PCLK is possible with respect to the period of the pixel clock PCLK at this time.
For 1200 dpi: M = 1.0 → N = 1.0 × 12 = 12
For 600 dpi: M = 0.5 → N = 0.5 × 12 = 6
For 400 dpi: M = 0.33 → N = 0.33 × 12 = 4
It becomes.

  In this manner, if the interval of the phase-shifted clock is changed in accordance with the resolution, dot position correction can be performed at a constant rate with respect to the image area regardless of the resolution.

  In order to change the interval of the phase-shifted clock as described above, for example, only the reference resolution LUT (or several resolution LUTs) is stored in the LUT in the data generation unit 5 (FIG. 7). The shift register circuit 39 is provided in the unit 36 so that the clock interval is obtained by the above calculation from the phase shift data pattern generated by using the LUT having the reference resolution (or the LUT having the resolution close to the target resolution). What is necessary is just to thin out and output the phase shift data. While it is possible to prepare LUTs for phase shift data patterns for various resolutions with the clock interval obtained by the calculation and select and use the LUT for the target resolution, the overall size of the LUT increases.

  It is also possible to prepare two or more types of phase shift data patterns corresponding to the same correction signal e = −5 and selectively use them. An example is shown in FIG.

  In FIG. 22, the phase shift data patterns of (a1), (b1), and (c1) are the same as the phase shift data patterns of (a), (b), and (c) of FIG. The phase shift data patterns of (a2), (b2), and (c2) are the same type as the phase shift data patterns of (a1), (b1), and (c1), respectively. The position is shifted. Again, phase shift data that advances the phase of the pixel clock PCLK by −1/16 PCLK is defined as “6”, and phase shift data that does not change the phase of the pixel clock PCLK is defined as “7”.

  If lines to which the same phase shift data pattern is applied are continuous, vertical streaks corresponding to clock positions to be phase shifted on the image may occur. In order to avoid such inconvenience, for example, an LUT storing the phase shift data pattern (a1) and an LUT storing the phase shift data pattern (a2) are prepared, and e = −5. When these lines are continuous, it is effective to switch the LUT for each line or every several lines.

  Another example of phase shift data pattern switching will be described with reference to FIG. FIGS. 23A and 23B show phase shift data patterns (for 30 clocks) that are applied when the lines of the correction signal e = −3 are continuous.

  When the same phase shift data pattern is applied to continuous lines as shown in (a), there is a possibility that vertical streak-like noise corresponding to the clock position where the phase is shifted on the image is conspicuous. In order to make such vertical streak noise inconspicuous, as shown in (b), the first phase shift data pattern is applied to a certain line, and the first phase shift is applied to the next line. It is effective to apply the second phase shift data pattern that shifts the phase of the clock at the intermediate position of the clock interval to which the phase of the data pattern is shifted. This is possible by preparing an LUT for the first phase shift data pattern and an LUT for the second phase shift data pattern, and switching each LUT for each line.

  Another example of switching the phase shift data pattern will be described with reference to FIG. FIGS. 24A and 24B show phase shift data patterns (for 30 clocks) that are applied when the line of the correction signal e = −3 is continuous.

  As described above, when the same phase shift data pattern is applied to continuous lines as in (a), vertical streak noise corresponding to the clock position to be phase shifted on the image may be noticeable. It is.

  (B) sequentially shifts the phase-shifted clock position by shifting the applied phase shift data pattern by a multiple of N (in this case, 2) clocks for each line, and in the case of (a) The occurrence of vertical stripe noise such as is prevented. This is possible by preparing a plurality of types of LUTs and selecting and using them for each line, but it is also possible not by LUT switching but by shift control in the shift register circuit 39 (FIG. 7). .

  What needs to be considered to reduce the influence of the phase shift at the same clock position as described above is the range in which the image in the line is actually recorded. Outside of this range, there is no particular problem even if the same phase shift data pattern is repeated on a continuous line. An example of phase shift control of the pixel clock in consideration of this will be described with reference to FIG.

  As shown in FIG. 25, the area A is 2000 clock periods from the generation of the horizontal synchronization signal (sync1) on the scanning start side, and the area C is the 2000 clock period before the generation of the horizontal synchronization signal (sync2) on the scanning end side. From the next clock position to the clock position immediately before the area C is defined as an effective scanning area B where an image is actually recorded.

  The control circuit 35 of the phase shift data generation unit 5 (FIG. 7) of the pixel clock generator counts the pixel clock from the generation of the horizontal synchronization signal sync1, and monitors which of the regions A, C, and B is being scanned, In the scanning period of the area A, the selection of the LUT for switching the phase shift data pattern is not performed. In the scanning period of the effective scanning region B, the control circuit 35 performs LUT selection control for switching the phase shift data pattern for each line as described above. In the period when the scanning of the effective scanning area B is finished and the area C is scanned, the LUT selection for switching the phase shift data pattern is not performed as in the area A.

  As described above, the phase shift data pattern is switched in order to suppress the occurrence of vertical stripes only in the region B that directly affects the image quality, but the regions A and A that do not directly affect the image quality. If C is not switched, the number of required LUTs and the overall size can be reduced.

  Although not shown, the data generation circuit 34 (FIG. 7) is provided with two shift register circuits corresponding to the shift register circuit 39, an adder circuit (combining circuit) is provided on the output side thereof, and the first LUT and the first LUT The first and second phase shift data patterns are read from the two LUTs and stored in the two shift register circuits, respectively, and the two phase shift data output from the two shift register circuits are added by the adder circuit (synthesis circuit). It is possible to obtain a final phase shift data by adding (synthesizing), and a pixel clock generation device having such a configuration is also included in the present invention. In such a configuration, for example, the phase shift data pattern applied to all lines that corrects the scanning unevenness caused by the characteristics of the scanning optical system is set as the first phase shift data pattern, and the rotation unevenness of the polygon mirror is reduced. A phase shift data pattern for correcting such a variation for each line can be used as the second phase shift data pattern.

  An example of the control flow of the control circuit 35 (FIG. 7) when switching the phase shift data pattern as described above for each line or every several lines will be described with reference to FIGS. . Here, it is assumed that real time control is performed in which the difference between the time interval between the horizontal scanning signals 1 and 2 and the target value is detected in each line and reflected in the pixel clock phase shift control in the next line. In addition, in order to simplify the explanation, it is assumed that each scanning line is equally divided into data areas of a certain length.

  FIG. 26 shows an example of a control flow when two LUT1 and LUT2 are selectively applied for each line.

  First, the control circuit 35 initializes counters M and N and a flag ND for control prior to image recording for one page (step S1).

  Steps S2 to S8 are a control process relating to one scanning line.

  The correction signal e for the line is fetched from the correction circuit 30 into the table address generation circuit 38 (step S2). The flag ND is checked (step S3). If ND = 1, a selection signal for LUT1 is given to the LUT storage unit 36, and at the same time, the flag ND is set to 0 (step S5). The table address generation circuit 38 generates a table address, reads the phase shift data pattern from the selected LUT, and controls the shift register circuit 39 to output it in synchronization with the pixel clock (step S6). The counter M is incremented by 1 (step S7), and the value of the counter M is compared with a predetermined value P to determine whether one line has been completed (step S8). If it is in the middle of one line, steps S6 to S8 are repeated. That is, the counter M counts the number of data areas composed of a fixed number of continuous pixel clocks.

  When the value of the counter M exceeds the predetermined value P, it is determined that the scanning of one line has been completed, the counter M is set to 1, and the counter N is incremented by 1 (step S9). Then, the value of the counter N is compared with a predetermined value Q to determine whether one page has been completed (step S10). If it is in the middle of the page, the process returns to step S2.

  When it is determined in step S3 that the flag ND is 0, a selection signal for LUT2 is given to the LUT storage unit 36, and 1 is set in the flag ND (step S4). Therefore, the phase shift data pattern stored in the LUT 2 is applied to the line. Since the flag ND is set to 1, the phase shift data pattern of the LUT 1 is again applied to the next line.

  Note that the description of step S6 will be supplemented. In each of the look-up tables LUT1, LUT2, a series of phase shift data patterns corresponding to each data region M (1, 2,..., P)) on the line is stored. In step S6, the lower bits of the table address generated by the table address generation circuit 38 are set according to the data area number (= counter M value). Therefore, a phase shift data pattern corresponding to the data area is output.

FIG. 27 shows another example of a control flow in the case where two LUT 1 and LUT 2 are alternately applied to each line when lines having the same correction signal e are continuous.

  First, the control circuit 35 initializes counters M and N and a flag ND for control prior to image recording for one page (step S21).

  Steps S22 to S32 are control steps relating to one scanning line.

  The correction signal e for the line is fetched from the correction circuit 30 to the table address generation circuit 38 (step S22), and the value of the correction signal e and the value of the correction signal e fetched in the immediately preceding line are determined to match (step S23). ). There is always a mismatch at the top line of the page. If the correction signal e does not match, the value of the flag ND is checked (step S25). If the value of the flag ND is 0, the selection signal for the LUT2 is stored. If the value of the flag ND is 1, the selection signal for the LUT1 is stored in the LUT. It gives to the part 36 (step S28, S29). That is, LUT1 or LUT2 is continuously applied to continuous lines with different correction signal e values.

  If the value of the correction signal e of the line matches that of the previous line, according to the result of the flag ND check (step S24), the LUT1 selection signal is output and the flag ND is set to 0 (step S27), or Then, a selection signal for LUT2 is output and the flag ND is set to 1 (step S26). That is, when lines with the same correction signal e continue, LUT1 and LUT2 are alternately selected for each line.

  The table address generation circuit 38 generates a table address, reads the phase shift data pattern from the selected LUT, and controls the shift register circuit 39 to output the phase data in synchronization with the pixel clock (step S30). . The counter M is incremented by 1 (step S31), and the value of the counter M is compared with a predetermined value P to determine whether one line has been completed (step S32). If it is in the middle of one line, steps S30 to S32 are repeated.

  When the value of the counter M exceeds the predetermined value P, it is determined that scanning of one line has been completed, the counter M is set to 1, and the counter N is incremented by 1 (step S33). Then, the value of the counter N is compared with a predetermined value Q to determine whether one page has been completed (step S34). If it is in the middle of the page, the process returns to step S22.

  When it is determined in step S3 that the flag ND is 0, a selection signal for LUT2 is given to the LUT storage unit 36, and 1 is set in the flag ND (step S4). Therefore, the phase shift data pattern stored in the LUT 2 is applied to the line. Since the flag ND is set to 1, the phase shift data pattern of the LUT 1 is applied again in the next line.

  By such control, when scanning lines that output the same phase shift data pattern are continuous, switching the lookup table causes the same phase shift data pattern to be output to the continuous scanning lines. For example, it is possible to avoid inconveniences such as vertical streaking at the pixel clock position to be phase-shifted and the boundary position of the data area.

  A supplementary explanation will be given for step S30. In each of the look-up tables LUT1, LUT2, a series of phase shift data patterns corresponding to each data region M (1, 2,..., P)) on the line is stored. In step S30, the lower bits of the table address generated by the table address generation circuit 38 are set according to the data area number (= counter M value). Therefore, a phase shift data pattern corresponding to the data area is output.

  FIG. 28 shows another example of the control flow when switching the LUT applied when a predetermined number of lines having the same correction signal e value continue.

  First, the control circuit 35 initializes control counters M, N, MC and a flag ND prior to recording one page of image (step S41).

  Steps S42 to S55 are control steps relating to one scanning line.

  First, the correction signal e for the relevant line is fetched from the correction circuit 30 into the table address generation circuit 38 (step S42), and the value of the correction signal e and the value of the correction signal e fetched in the immediately preceding line are determined to match (step S42). Step S43). There is always a mismatch at the top line of the page. If the value of the correction signal e matches, the counter MC is incremented by 1 (step S44).

  It is determined whether the value of the counter MC exceeds the predetermined value R (step S45). If not, the value of the flag ND is checked (step S46). If the value of the flag ND is 1, the selection signal of the LUT1 is If the value of ND is 0, a selection signal for LUT2 is given to the LUT storage unit 36 (steps S47 and S48).

  When the value of the counter MC exceeds the predetermined value R, the counter MC is set to 1 (step S49), and the value of the flag ND is checked (step S50). If the value of the flag ND is 1, the selection signal for the LUT 1 is output and the flag ND is set to 0 (step S51). If the value of the flag ND is 0, a selection signal for LUT2 is output and the flag ND is set to 1 (step S52).

  The table address generation circuit 38 generates a table address, reads the phase shift data pattern from the selected LUT, and outputs the phase data from the shift register circuit 39 in synchronization with the pixel clock (step S53). The counter M is incremented by 1 (step S54), and the value of the counter M is compared with a predetermined value P to determine whether one line has been completed (step S55). If it is in the middle of one line, steps S53 to S55 are repeated.

  When the scanning of each line is completed in this way and the value of the counter M exceeds the predetermined value P, the counter M is set to 1 and the counter N is incremented by 1 (step S56). Then, the value of the counter N is compared with a predetermined value Q to determine whether one page has been completed (step S57). If it is in the middle of the page, the process returns to step S42.

  The description of step S53 is supplemented. In each of the look-up tables LUT1, LUT2, a series of phase shift data patterns corresponding to each data region M (1, 2,..., P)) on the line is stored. In step S53, the lower bits of the table address generated by the table address generation circuit 38 are set according to the data area number (= counter M value). Therefore, a phase shift data pattern corresponding to the data area is output.

  As understood from the above description, for example, when R = 2, when three lines having the same correction signal e value are consecutive, the LUT used up to that point is switched to another LUT at the third line. It is done. Accordingly, when continuous dot deviation of, for example, 0.5 mm to 1 mm or more is conspicuous from human visual characteristics, the number of lines (R) for switching the look-up table so that the continuous length of dots is shorter than that. Is set, it is possible to suppress the occurrence of vertical streaks or the like corresponding to the phase-shifted pixel clock or the boundary of the data area on the image.

  Another embodiment of the image forming apparatus using the pixel clock device of the present invention described above will be described below.

  FIG. 29 is a schematic configuration diagram of an image forming apparatus according to Embodiment 5 of the present invention. In this image forming apparatus, the laser light beam output from the semiconductor laser 500 enters the polygon mirror 503 through the collimator lens 501 and the cylinder lens 502. The laser light beam deflected by the polygon mirror 503 passes through the f-θ lens 504, passes through the flat glass 505 (is partially reflected), enters the photosensitive member 506 that is a scanning medium, and the surface (covered object). A light beam spot is formed on the scanning surface to form an image (electrostatic latent image).

  The laser light beam reflected by the first surface of the flat glass 505 is detected by photodetectors 508, 509, and 510 disposed on the detection surface, thereby generating three horizontal synchronization signals sync1, sync2, and sync3. That is, the horizontal synchronization detecting means in this embodiment separates a part of the laser light beam deflected by the polygon mirror 503 by the flat glass 505, and the separated laser light beam corresponds to three specific horizontal scanning positions. The three photodetectors 508, 509, and 510 arranged at the above positions receive light.

  The positional relationship of the photodetectors 508, 509, and 510 is determined so that the optical path lengths until the laser beams deflected by the polygon mirror 503 are incident on the photodetectors 508, 509, and 510 are substantially the same.

  Reference numeral 520 denotes a pixel clock generation device according to the present invention, 521 denotes an image processing device, 522 denotes a laser drive data generation device, and 523 denotes a laser drive device. The horizontal synchronization signals sync1, sync2, and sync3 are input to the pixel clock generation device 520, and the horizontal synchronization signal sync1 is also input to the image processing device 521 as a line synchronization signal.

  Note that a charging unit for charging the surface of the photosensitive member 506, a developing unit for developing the electrostatic latent image into a toner image, a transfer unit for transferring the developed toner image onto a sheet or an intermediate transfer member, and a photosensitive member. Although there are means included in this type of image forming apparatus, such as a cleaner means for removing and collecting the toner remaining on the body 506, it is omitted in the drawing.

  FIG. 30 is a schematic configuration diagram of an image forming apparatus according to Embodiment 6 of the present invention.

  In this image forming apparatus, the laser light beam output from the semiconductor laser 600 is incident on the polygon mirror 603 through the collimator lens 601 and the cylinder lens 602. The laser light beam deflected by the polygon mirror 603 passes through the f-θ lens 604, passes through the flat glass 605 (partially reflected), enters the photosensitive member 606 as a scanning medium, and the surface (covered). A light beam spot is formed on the scanning surface to form an image (electrostatic latent image).

  The laser beam reflected by the first surface of the flat glass 605 is further reflected by the reflecting members 608, 609, and 610 arranged in the scanning direction, and then received by one photodetector 611, whereby the writing start position side Then, three horizontal synchronizing signals 1, 2, 3 (sync1, sync2, sync3) corresponding to the three positions in the writing area on the writing end position side are generated.

  The reflecting members 608, 609, 603 are arranged so that the optical path lengths L1, L2, L3 until the laser light deflected by the polygon mirror 503 enters the photodetector 611 via the reflecting members 608, 609, 610 are substantially the same. A positional relationship 610 is determined. Accordingly, there is no timing shift of the horizontal synchronization signal due to the difference in optical path length.

  620 is a pixel clock generator according to the present invention, 621 is an image processing device, 622 is a laser drive data generator, and 623 is a laser drive, which are the same devices as the corresponding parts of the third embodiment. The horizontal synchronization signals sync1, sync2, and sync3 are input to the pixel clock generation device 620, and the horizontal synchronization signal sync1 is also input to the image processing device 621 as a line synchronization signal.

  As the reflecting members 608, 609, and 610, for example, a mirror or the like in which a reflecting film is formed on one surface of a transparent member such as glass or plastics can be used. Since such a reflecting member is less expensive than a photodetector, it is advantageous in terms of cost compared to a configuration using three photodetectors. This cost advantage is even more pronounced when the synchronization signal is detected at four or more locations.

  Note that a charging unit for charging the surface of the photosensitive member 606, a developing unit for developing the electrostatic latent image into a toner image, a transfer unit for transferring the developed toner image to a sheet or an intermediate transfer member, and a photosensitive member. Although there are means included in this type of image forming apparatus, such as a cleaner means for removing and collecting the toner remaining on the body 606, it is omitted in the drawing.

  31A and 31B are schematic configuration diagrams of an image forming apparatus according to Embodiment 7 of the present invention, in which FIG. 31A shows a planar configuration and FIG. 31B shows a side configuration.

  In this image forming apparatus, the laser light beam output from the semiconductor laser 700 enters the polygon mirror 704 through the collimator lens 701, the slit of the aperture 702, and the cylinder lens 703. The laser light beam deflected by the polygon mirror 704 is incident on a photosensitive member 708 as a scanned medium via scanning lenses 705 and 706 and a beam splitter 707, and forms a light beam spot on the surface (scanned surface). To form an image (electrostatic latent image).

  The beam splitter 707 is formed by joining a pair of right triangle prisms, and the joint surface is a half mirror surface. Most of the laser light beam incident on the beam splitter 707 passes through the half mirror surface and travels toward the photosensitive member 708 to contribute to image formation. However, a part of the incident laser light beam is reflected by the half mirror surface. The reflected (separated) laser light beam is received by photodetectors 709, 710, and 711 disposed below the beam splitter 707, thereby generating horizontal synchronization signals sync 1, sync 2, and sync 3.

  Although not shown in FIG. 31, the image forming apparatus of the present embodiment also includes the same pixel clock generation apparatus, image processing apparatus, laser drive data generation apparatus, and laser drive apparatus as those of the sixth embodiment. In addition, a charging unit for charging the surface of the photoreceptor 708, a developing unit for developing the electrostatic latent image into a toner image, a transfer unit for transferring the developed toner image to a sheet or an intermediate transfer member, a photosensitive unit Means included in this type of image forming apparatus, such as cleaner means for removing and collecting toner remaining on the body 708, is provided.

  FIG. 32 is a schematic configuration diagram of an image forming apparatus according to an eighth embodiment of the present invention, where (a) shows a planar configuration and (b) shows a side configuration.

  In this image forming apparatus, the laser light beam output from the semiconductor laser 800 is incident on the polygon mirror 804 through the collimator lens 801, the slit of the aperture 802, and the cylinder lens 803. The laser light beam deflected by the polygon mirror 804 is incident on a photosensitive member 808 as a scanned medium via scanning lenses 805 and 806 and a beam splitter 807, and forms a light beam spot on the surface (scanned surface). To form an image (electrostatic latent image).

  The beam splitter 807 is formed by joining a pair of right triangle prisms, and the joint surface is a half mirror surface. Most of the laser light beam incident on the beam splitter 807 passes through the half mirror surface and travels toward the photoconductor 808 to contribute to image formation, but a part of the incident laser light beam is reflected by the half mirror surface. As means for guiding the reflected (separated) laser light to the photodetector 814, a reflection member (or reflection / transmission member) 810 and reflection / transmission members 811, 812, 813, 814 are provided below the beam splitter 807. Has been placed. The reflection member (or reflection / transmission member) 810 and the reflection / transmission members 811, 812, 813, and 814 receive the laser beam reflected by the half mirror surface during scanning at the corresponding specific horizontal scanning positions. To do. The laser beam reflected by the reflecting member (or reflecting / transmitting member) 810 is sequentially transmitted through the reflecting / transmitting members 811, 812, 813, and 814 and received by the photodetector 815. The laser beam reflected by the reflection / transmission member 811 is sequentially transmitted through the reflection / transmission members 812, 813, and 814 and received by the photodetector 815. The laser beam reflected by the reflection / transmission member 812 is sequentially transmitted through the reflection / transmission members 813 and 814 and received by the photodetector 815. The laser beam reflected by the reflection / transmission member 813 is transmitted through the reflection / transmission member 814 and received by the photodetector 815. The laser beam reflected by the reflection / transmission member 814 is directly received by the photodetector 815. Therefore, the photodetector 815 can detect the laser beam at the scanning timing of the five horizontal scanning positions and generate five horizontal synchronization signals.

  The reflecting / transmitting member used in this embodiment has both the function of reflecting and transmitting the light beam, and is, for example, a transparent member such as glass or plastics. The shape of the reflecting member (or reflecting / transparent member) 810 and the reflecting / transparent members 811, 812, 813, and 814 is a parallel plate shape that can easily control the reflection / transmission direction of the light beam, but is not limited thereto. Never happen. Such a reflection / transmission member or reflection member is low in cost as compared with the detector, and thus is advantageous in terms of cost as compared with a configuration using five photodetectors.

  Although not shown in FIG. 32, the image forming apparatus of the present embodiment also includes a pixel clock generation device, an image processing device, a laser drive data generation device, and a laser drive device similar to those of the sixth embodiment. A charging means for charging the surface of the photoreceptor 808, a developing means for developing the electrostatic latent image into a toner image, a transfer means for transferring the developed toner image to a sheet or an intermediate transfer body, and a photoreceptor. Means included in this type of image forming apparatus, such as cleaner means for removing and collecting the toner remaining in 808, is also provided.

  FIG. 33 is a schematic configuration diagram of an image forming apparatus according to Embodiment 9 of the present invention. This image forming apparatus includes a semiconductor laser 901 as a reference light source for horizontal synchronization detection, in addition to the semiconductor laser 900 as an image writing light source.

  The laser light beam output from the image writing semiconductor laser 900 enters the polygon mirror 906 through the collimator lens 902, the slit of the aperture 904, and the cylinder lens 905. The laser beam deflected by the polygon mirror 906 enters the photosensitive member 909 via the f-θ lens 907 and the transparent member 908, and forms a light beam spot on the surface (scanned surface) to form an electrostatic latent image. Form.

  A laser light beam output from a semiconductor laser 901 serving as a reference light source enters a polygon mirror 906 via a collimator lens 903, a slit of an aperture 904, and a cylinder lens 905.

  The laser light beam from the reference semiconductor laser 901 and the laser light beam from the image writing semiconductor laser 900 are incident on the same reflecting surface of the polygon mirror 906. The reference laser beam and the image writing laser beam are incident on the same position in the main scanning direction, but are incident on a position shifted by a certain interval in the sub-scanning direction. As a result, the reference laser beam deflected by the polygon mirror 906 passes through the f-θ lens 907 and the transparent member 908 but does not enter the photoconductor 909. Therefore, the semiconductor laser 901 as the reference light source can emit light regardless of the image data.

  A surface to be detected deviated from the photoconductor 909, which is equivalent to the surface to be scanned of the photoconductor 909 scanned by the image writing laser beam, is scanned by the reference laser beam. When the reference laser beam reflected by the reflecting members 911, 912, and 913 at positions corresponding to the three specific horizontal scanning positions is received by the photodetector 914, the horizontal synchronization signals 1, 2, and 3 are received. (Sync1,2,3) is obtained.

  The optical path lengths L1 ′, L2 ′, and L3 ′ from when the laser light beam output from the reference semiconductor laser 901 reaches the photodetector 914 via the reflecting members 911, 912, and 913 are positioned so as to be substantially the same. Is decided.

  33, reference numeral 920 denotes a pixel clock generation apparatus according to the present invention, 921 denotes an image processing apparatus, 922 denotes a laser drive data generation apparatus, and 923 denotes a laser drive apparatus. The laser driving device 923 drives the image writing semiconductor laser 900 based on the image data and drives the reference semiconductor laser 901.

  Since the pixel clock generator 920 generates three horizontal synchronization signals 1, 2, and 3 in each line even during the image recording period, the horizontal synchronization signal 2 and the horizontal synchronization signal 2 between the horizontal synchronization signals 1 and 2 in each line during the image recording period. Real-time control is also possible in which the time interval between the three is measured and the deviation from the target value is reflected in the phase control of the pixel clock of the next line.

  A charging unit for charging the surface of the photoreceptor 909, a developing unit for developing the electrostatic latent image into a toner image, a transfer unit for transferring the developed toner image to a sheet or an intermediate transfer member, and the photoreceptor 909. Although there are means included in this type of image forming apparatus, such as a cleaner means for removing and collecting the toner remaining in the toner, it is omitted in the drawing.

  In place of the semiconductor lasers 900 and 901, a semiconductor laser array including a plurality of image writing semiconductor lasers LD1, LD2, LD3, and LD4 as shown in FIG. 34 and a reference semiconductor laser LD5 spaced apart from the laser diodes. The image forming apparatus having such a configuration can also be used. If such a semiconductor laser array is used as a light source, four lines can be simultaneously written with four laser light beams. Since the difference in the emission wavelength of each of the semiconductor lasers LD1 to LD5 can be easily reduced, it is possible to reduce errors and fluctuations in the scanning position caused by the difference in wavelength for each light source.

  FIG. 35 is a schematic configuration diagram of an image forming apparatus according to Embodiment 10 of the present invention. In this image forming apparatus, the laser light beam output from the semiconductor laser 1000 enters the polygon mirror 1003 through the collimator lens 1001 and the cylinder lens 1002. The laser light beam deflected by the polygon mirror 1003 passes through the f-θ lens 1004, passes through the flat glass 1005 (partially reflected), enters the photoconductor 1006 that is a scanning medium, and the surface (covered object). A light beam spot is formed on the scanning surface to form an image (electrostatic latent image).

  The laser light beam reflected (separated) by the first surface of the flat glass 1005 is a reflecting member (or reflecting / transmitting member) 1008 provided at a position corresponding to three specific horizontal scanning positions, reflecting / transmitting. The light enters the members 1009 and 1010. The laser beam reflected by the reflecting member (or reflecting / transmitting member) 1008 passes through the reflecting / transmitting members 1010 and 1009 and is received by the photodetector 1011. The laser beam reflected by the reflection / transmission member 1010 passes through the reflection / transmission member 1009 and is received by the photodetector 1011. The laser beam reflected by the reflection / transmission member 1009 is directly received by the photodetector 1011. As described above, the photodetector 1011 receives the laser light beam reflected by the first surface of the flat glass 1005 at three locations in the horizontal scanning direction, thereby generating horizontal synchronization signals sync1, sync2, and sync3. Such a horizontal synchronization detection means is advantageous in terms of cost compared to a configuration using three photodetectors because the reflecting member is less expensive than the photodetector. This cost advantage is even more pronounced when the synchronization signal is detected at four or more locations.

  Reference numeral 1020 denotes a pixel clock generation apparatus according to the present invention, 1021 denotes an image processing apparatus, 1022 denotes a laser drive data generation apparatus, and 1023 denotes a laser drive apparatus.

  Note that a charging unit for charging the surface of the photoreceptor 1006, a developing unit for developing the electrostatic latent image into a toner image, a transfer unit for transferring the developed toner image onto a sheet or an intermediate transfer member, and a photosensitive member. There are means included in this type of image forming apparatus, such as a cleaner means for removing and collecting the toner remaining on the body 1006, but they are omitted in the drawing.

  FIG. 36 is a schematic configuration diagram of a multi-beam scanning type image forming apparatus according to Embodiment 11 of the present invention. However, the pixel clock generation device, the image processing device, the laser drive data generation device, and the laser drive device are not shown. Also, charging means for charging the surface of the photoreceptor, developing means for developing the electrostatic latent image formed on the photoreceptor into a toner image, and transferring the developed toner image to a sheet or an intermediate transfer body There are also means included in this type of image forming apparatus, such as a transfer means for cleaning and a cleaner means for removing and collecting toner remaining on the photoreceptor, but they are not shown.

  This image forming apparatus includes a light source unit 2300 that emits four laser light beams. The light source unit 2300 includes a set of a semiconductor laser array 2301 having two light sources and a collimator lens 2303, a set of a semiconductor laser array 2302 having two light sources and a collimator lens 2304, and an aperture 2305.

  As shown in FIG. 37, each of the semiconductor laser arrays 2301 and 2302 is formed by monolithically forming two light emitting sources at an interval of ds = 25 μm, respectively, with respect to the optical axis C of the collimator lenses 2304 and 2305, respectively. They are arranged symmetrically in the sub-scanning direction.

  In FIG. 36, the semiconductor laser arrays 2301 and 2302 are laid out so that the collimator lenses 2303 and 2304 coincide with the optical axis, have an emission angle symmetrical in the main scanning direction, and the emission axes intersect at the reflection point of the polygon mirror 2307. Has been. A plurality of beams emitted from the respective semiconductor laser arrays 2301 and 2302 are deflected by the same reflecting surface of the polygon mirror 2307 through the cylinder lens 2308, and the photoconductor 2312 through the f-θ lens 2310, the mirror 2313, and the toroidal lens 2311. By forming a beam spot thereon, an electrostatic latent image is formed on the photoreceptor 2312. Since a total of four light sources of the semiconductor laser arrays 2301 and 2302 are driven according to one line of image data, writing of the electrostatic latent image is performed simultaneously for four lines.

  In FIG. 36, reference numerals 2318 and 2319 denote photo detectors for generating horizontal synchronizing signals sync1 and sync2. The generated horizontal synchronization signal is input to a pixel clock generation device (not shown), and the horizontal synchronization signal generated by the photo detector 2318 on the scanning start side is input as a line synchronization signal to an image processing device (not shown). This is the same as in each embodiment.

  FIG. 38 is an exploded perspective view for explaining an example of a specific structure of the light source unit 2300. Each of the semiconductor laser arrays 2301 and 2302 has fitting holes (2405-1, 2405-) (not shown) formed on the back side of the base member 2405 inclined at a predetermined angle (about 1.5 ° in this embodiment) in the main scanning direction. 2), the respective cylindrical heat sink parts 2403-1 and 2404-1 are fitted, and the protrusions 2406-1 and 2407-1 of the holding members 2406 and 2407 are aligned with the notch parts of the heat sink part. The arrangement direction is aligned and fixed with screws 2412 from the back side. Further, the collimator lenses 2303 and 2304 are adjusted in the optical axis direction along the outer circumferences of the semicircular mounting guide surfaces 2405-4 and 2405-5 of the base member 2405, respectively, and the diverging beams emitted from the light source Are aligned and bonded so as to be a parallel light beam.

  In the present embodiment, as described above, since the light beams from the respective semiconductor laser arrays are set so as to intersect within the main scanning plane, fitting holes (2405-1, 2405-2) and Semicircular mounting guide surfaces 2405-4 and 2405-5 are formed to be inclined. The base member 2405 engages the cylindrical engagement portion 2405-3 with the holder member 2410, and screws the screw 2413 into the screw holes 2405-6 and 2405-7 through the through holes 2410-2 and 2410-3. Fixed.

  In this light source unit, the cylindrical portion 2410-1 of the holder member 2410 is fitted into a reference hole 2411-1 provided in the mounting wall 2411 of the optical housing, the spring 2611 is inserted from the front side, and the stopper member 2612 is inserted into the cylindrical portion protrusion 2410. -3, the holder member 2410 is held in a state of being in close contact with the back side of the mounting wall 2411. At this time, one end 2611-2 of the spring 2611 is hooked on the protrusion 2411-2 to generate a rotational force with the center of the cylindrical portion as a rotational axis, and an adjustment screw 2613 provided to lock the rotational force causes light to The whole unit is rotated around the axis θ, and each beam spot row is adjusted so as to be alternately arranged by shifting by one line. The aperture 2305 is provided with slits corresponding to the semiconductor laser arrays 2301 and 2302, and is attached to the optical housing to define the light beam emission diameter.

  FIG. 39 is a schematic configuration diagram for explaining an image forming apparatus according to Embodiment 12 of the present invention.

  This image forming apparatus is a tandem apparatus that uses separate photoconductors 2509a, 2509b, 2509c, and 2509d for image formation of each color (cyan, magenta, yellow, and black).

  In such a tandem image forming apparatus, the photoconductor in each color station is scanned by a laser light beam that has passed through a separate optical path, so that the main scanning dot position shift that occurs on the photoconductor has different characteristics for each station. Have. Therefore, good image quality, particularly good color reproducibility cannot be obtained unless the main scanning dot position correction is performed accurately for each color station. For example, when dot misregistration between color stations occurs on the order of several tens of μm, by correcting the main scan misalignment by applying a phase shift to the pixel clock whose main scan misregistration amount exceeds 1/8 dot, The amount of dot misalignment can be reduced to approximately 2.6 μm (21.2 μm / 8), which is equivalent to 1/8 dot at 1200 dpi.

  In FIG. 39, reference numeral 2505 denotes a polygon mirror. Laser light beams output from the light sources for the respective color stations are simultaneously incident on different reflecting surfaces of the polygon mirror 2505 via an optical system such as a collimator lens or a cylinder lens.

  The station including the photoreceptor 2509a will be described. The laser beam deflected by the polygon mirror 2505 passes through the first scanning lens 2506a, the mirror 2513a, the second scanning lens 2507a, the mirrors 2514a and 2515a, and the beam splitter 2508a. The photosensitive member 2509a is scanned to form an electrostatic latent image. A part of the laser light beam reflected by the half mirror surface of the beam splitter 2508a is detected by a photodetector 2510a for horizontal synchronization detection. Since it is clear from the drawings that the scanning systems of the stations of other colors have the same configuration, the description will not be repeated.

  In addition to the horizontal synchronization detection means described above, the pixel clock generation device of the present invention and other means related to driving of the laser light source exist for each station, but other than the horizontal synchronization detection means are not shown. The laser light source of each station is driven in synchronization with the pixel clock generated by the corresponding pixel clock generation device.

  Around the photoconductors 2509a, 2509b, 2509c, and 2509d of each station, there are means for uniformly charging the surface of the photoconductor, means for developing the electrostatic latent image on the photoconductor into a corresponding color toner image, Means for transferring the developed toner image to the transfer body 2516; means for removing and collecting the toner remaining without being transferred to the surface of the photoconductor; means for superimposing and transferring the color toner images on the transfer body 2516 onto the paper; There is a means for fixing the toner image on the upper side, which is not shown.

  The image forming apparatus according to the present embodiment forms a high-quality color image with good color reproducibility because the main scanning dot position deviation in each color station is corrected with high accuracy, and therefore the color deviation is also effectively corrected. be able to.

It is a block diagram of the pixel clock generation device of the present invention. It is a block diagram of the pixel clock generation part in the pixel clock generation apparatus of this invention. It is a timing chart for demonstrating operation | movement of a pixel clock generation part. It is a timing chart for demonstrating operation | movement of a pixel clock generation part. It is a timing chart for demonstrating operation | movement of a pixel clock generation part. It is a timing chart which shows the timing relationship of a high frequency clock, a pixel clock, and phase shift data. It is a block diagram of a phase shift data generation unit. It is a figure which shows the example of a phase shift data pattern. 1 is a schematic configuration diagram of an image forming apparatus according to Embodiment 1 of the present invention. It is a figure for demonstrating main scanning dot position shift and its correction | amendment. It is a figure for demonstrating in association with the linearity characteristic of a scanning optical system, and a phase shift data pattern. It is a block diagram of a pixel clock generation unit. It is a figure for demonstrating correction | amendment of the main scanning dot position shift by the phase shift of a pixel clock. It is a schematic block diagram of the image forming apparatus which concerns on Example 2 of this invention. It is a schematic block diagram of the image forming apparatus which concerns on Example 3 of this invention. It is a figure for demonstrating main scanning dot position shift and its correction | amendment. It is a schematic block diagram of the image forming apparatus which concerns on Example 4 of this invention. It is a figure for demonstrating correction | amendment of the main scanning dot position shift by the division control of the data area, and the shift control of the pixel clock of a data area unit. It is a figure for description of pixel clock phase shift in a data area. It is a figure for description of a lookup table. It is a figure for description of a phase shift data pattern. It is a figure for description of a phase shift data pattern. It is a figure for demonstrating the inconvenience by applying the same phase shift data pattern to a continuous line, and the switching of the phase shift data pattern for the cancellation. An inconvenience caused by applying the same phase shift data pattern to continuous lines and switching of the phase shift data pattern for solving the problem will be described. It is a figure for demonstrating the effective scanning area | region in a scanning line, and the phase shift control of the pixel clock outside the area | region. It is a flowchart which shows the example of a control flow by the control circuit of a phase shift data generation part. It is a flowchart which shows the example of a control flow by the control circuit of a phase shift data generation part. It is a flowchart which shows the example of a control flow by the control circuit of a phase shift data generation part. It is a schematic block diagram of the image forming apparatus which concerns on Example 5 of this invention. It is a schematic block diagram of the image forming apparatus which concerns on Example 6 of this invention. It is a schematic block diagram of the image forming apparatus which concerns on Example 7 of this invention. It is a schematic block diagram of the image forming apparatus which concerns on Example 8 of this invention. It is a schematic block diagram of the image forming apparatus which concerns on Example 9 of this invention. It is the schematic which shows an example of a semiconductor laser array. It is a schematic block diagram of the image forming apparatus which concerns on Example 10 of this invention. It is a schematic block diagram of the image forming apparatus which concerns on Example 11 of this invention. FIG. 37 is an explanatory diagram relating to the semiconductor laser array in FIG. 36. It is a disassembled perspective view for demonstrating an example of the specific structure of the light source unit in FIG. It is a schematic block diagram of the image forming apparatus based on Example 12 of this invention. It is a schematic block diagram of the conventional image forming apparatus. It is a schematic block diagram of the conventional image forming apparatus.

Explanation of symbols

2 High-frequency clock generation unit 3 Detection unit 4 Comparison unit 5 Phase shift data generation unit 6 Pixel clock generation unit 30 Correction circuit 34 Data generation circuit 35 Control circuit 36 LUT storage unit 37 Look-up table (LUT)
38 Table Address Generation Circuit 39 Shift Register Circuit 100 Semiconductor Laser 103 Polygon Mirror 106 Photoconductor 107,108 Photodetector 110 Pixel Clock Generation Device 200 Image Writing Semiconductor Laser 201 Reference Semiconductor Laser 206 Polygon Mirror 209 Photoconductor 210, 211 Photodetector 220 Pixel clock generator 300 Semiconductor laser 303 Polygon mirror 306 Photoconductor 307, 308, 309 Photo detector 310 Pixel clock generator 400 Image writing semiconductor laser 401 Reference semiconductor laser 406 Polygon mirror 409 Photoconductor 410, 412, 413 Photo detector 420 Pixel Clock generator 500 Semiconductor laser 503 Polygon mirror 506 Photoconductor 508, 509, 510 Photodetector 520 Pixel clock generator 600 Semiconductor laser 603 Polygon mirror 606 Photoconductor 608, 609, 610 Reflective member 611 Photodetector 620 Pixel clock generator 700 Semiconductor laser 704 Polygon mirror 708 Photoconductor 709, 710, 711 Photodetector 800 Semiconductor laser 804 808 Photosensitive member 810 Reflecting member or reflecting / transmitting member 811, 812, 813, 814 Reflecting / transmitting member 815 Photo detector 900 Image writing semiconductor laser 901 Reference semiconductor laser 906 Polygon mirror 909 Photosensitive member 911, 912, 913 Reflecting member 914 Photodetector 920 Pixel clock generator 1000 Semiconductor laser 1003 Polygon mirror 1006 Photoconductor 100 8 Reflecting member or reflecting / transmitting member 1009, 1010 Reflecting / transmitting member 1011 Photo detector 1020 Pixel clock generation device 2300 Light source unit 2307 Polygon mirror 2312 Photoconductor 2318, 2319 Photo detector 2505 Polygon mirror 2506, 2507 Scan lens 2513, 2514, 2515 Mirror 2508 Beam splitter 2509 Photoconductor 2510 Photo detector 2516 Transfer body

Claims (22)

  High-frequency clock generation means for generating a high-frequency clock;
  Detecting means for detecting a time interval between at least two horizontal synchronizing signals;
  A comparison means for comparing the time interval detected by the detection means with a preset target value and outputting the difference as a comparison result;
  Phase shift data generating means for generating phase shift data for controlling the phase shift amount of the pixel clock;
  Pixel clock generation means for generating a pixel clock according to the phase shift data based on the high frequency clock generated by the high frequency clock generation means;
  The phase shift data generating means includes
One or more lookup tables storing a pattern of the phase shift data, and a correction circuit;
  The correction circuit includes:
A comparison circuit that outputs a deviation signal between the comparison result output from the comparison unit and a correction signal based on the past comparison result output from the comparison unit before the comparison result, and the comparison circuit that is output from the comparison circuit An integrator that integrates the deviation signal and outputs a correction signal; and a data holding circuit that holds the correction signal output from the integrator; and the correction signal held in the data holding circuit is the past Is supplied to the comparison circuit as a correction signal based on the comparison result of
  The phase shift data generation means reads out and outputs phase shift data from the lookup table based on the correction signal output from the integrator.
A pixel clock generator characterized by the above. The pixel clock generation device according to claim 1 ,
A pixel clock generation device, wherein a plurality of continuous pixel clocks are used as one data area, and phase control of the pixel clock is performed in units of each data area. The pixel clock generation device according to claim 1 or 2 ,
The phase shift data generating means has a plurality of look-up tables and switches a look-up table for reading phase shift data within one scanning period. The pixel clock generation device according to claim 1 or 2 ,
A pixel clock generation device characterized in that the intervals of pixel clocks to be phase-shifted are substantially equal. The pixel clock generation device according to claim 1 or 2 ,
A pixel clock generation device characterized in that the intervals of pixel clocks to be phase-shifted are made uneven. The pixel clock generation device according to claim 1 ,
Pixel clock generation characterized in that the interval between pixel clocks to be phase-shifted is smaller in an image height section where the amount of change in main scanning dot position deviation is larger than in an image height section where the amount of change in main scanning dot position deviation is small apparatus. The pixel clock generation device according to claim 4 .
The phase shift data generating means includes means for setting the interval between pixel clocks to be phase shifted to a value obtained by multiplying the reference value by a correction magnification according to the resolution. The pixel clock generation device according to claim 1 or 2 ,
The pixel clock generation device according to claim 1, wherein the phase shift data generation means switches a look-up table for reading phase shift data for each scanning line. The pixel clock generation device according to claim 1 or 2 ,
The phase shift data generation means changes the phase shift data pattern when scanning lines outputting the same phase shift data pattern are continuous. The pixel clock generation device according to claim 1 or 2 ,
The phase shift data generation means changes a phase shift data pattern by switching a look-up table when scanning lines outputting the same phase shift data pattern are continuous. . The pixel clock generation device according to claim 10 .
The phase shift data pattern after switching the look-up table is a phase shift of a pixel clock at a substantially intermediate position of the pixel clock phase-shifted in the phase shift data pattern before the look-up table is switched. A pixel clock generator. The pixel clock generation device according to claim 10 .
The phase shift data pattern after switching the look-up table shifts the pixel clock at a position shifted by a fixed number of clocks from the pixel clock that is phase-shifted in the phase shift data pattern before switching the look-up table. A pixel clock generator characterized by the above. The pixel clock generation device according to claim 10 .
The phase shift data generation means switches the look-up table of the phase shift data by switching the look-up table in the next scan line when N scan lines (where N ≧ 2) are output in which the same phase shift data pattern is output. A pixel clock generation device characterized by changing a pattern. The pixel clock generation device according to claim 10, 11, 12, or 13 ,
A pixel clock generation apparatus, wherein switching of a lookup table in a case where scanning lines outputting the same phase shift data pattern are continuous is performed only in an effective scanning area where image formation is performed in the scanning line. Image formation in which one or more light beams output from one or more light sources are incident on a deflecting unit, and an image is formed on the scanned medium by scanning the scanned medium with the light beam deflected by the deflecting unit A device,
The pixel clock generation device according to any one of claims 1 to 14 ,
Horizontal synchronization detection means for detecting scanning timings of two or more specific horizontal scanning positions by the light beam in order to generate two or more horizontal synchronization signals to be supplied to the pixel clock generation device;
The image forming apparatus, wherein the light source is driven in synchronization with a pixel clock generated by the pixel clock generating apparatus. The image forming apparatus according to claim 15 .
The horizontal synchronization detection means has three light detection means for receiving the light beam, and the three light detection means have an optical path length until the light beam enters the light detection means from the deflection means. Are provided so as to be substantially the same. The image forming apparatus according to claim 15 .
The horizontal synchronization detecting means is means for separating a part of the light beam deflected by the deflecting means, and a position corresponding to the two or more specific horizontal scanning positions for receiving the light beam separated by the means. An image forming apparatus comprising two or more light detection means provided in each of the above. The image forming apparatus according to claim 15 .
The horizontal synchronization detecting means includes a means for separating a part of the light beam deflected by the deflecting means, and a position corresponding to the two or more specific horizontal scanning positions where the light beam separated by the means is incident. An image forming apparatus comprising: two or more reflecting members provided on the light receiving unit; and one light detecting unit that receives a light beam reflected by all the reflecting members. The image forming apparatus according to claim 15 .
The horizontal synchronization detecting means includes a means for separating a part of the light beam deflected by the deflecting means, and a position corresponding to the two or more specific horizontal scanning positions where the light beam separated by the means is incident. And two or more reflecting members or reflecting / transmitting members, and one light detecting means for receiving a light beam reflected by all the reflecting members or reflecting / transmitting members. Image forming apparatus. A reference light source;
The reference light beam output from the reference light source is incident on the deflecting means, and the reference light beam deflected by the deflecting means scans the outside of the scanned medium,
The horizontal synchronization detecting means comprises two or more light detecting means provided at positions corresponding to the two or more specific horizontal scanning positions, respectively, for receiving the reference light beam deflected by the deflecting means. The image forming apparatus according to claim 15 . A reference light source;
The reference light beam output from the reference light source is incident on the deflecting means, and the reference light beam deflected by the deflecting means scans the outside of the scanned medium,
The horizontal synchronization detecting means includes two or more reflecting members respectively provided at positions corresponding to the two or more specific horizontal scanning positions on which the reference light beam deflected by the deflecting means is incident, 16. The image forming apparatus according to claim 15 , further comprising a single light detection unit that receives the reference light beam reflected by the reflecting member. In a tandem image forming apparatus,
The pixel clock generation device according to any one of claims 1 to 14 and a horizontal synchronization detection means for generating two or more horizontal synchronization signals supplied to the pixel clock generation device for each color station. Have
An image forming apparatus, wherein the light source for image writing of each color station is driven in synchronization with a pixel clock generated by the pixel clock generation device corresponding to the station.

Images