JP6848745B2 - Optical writing device and image forming device - Google Patents

Description

The present invention relates to an optical writing device and an image forming device.

As an optical writing device used in a laser printer, a digital copying machine, etc., a device having a plurality of light sources and simultaneously scanning a plurality of lines on a photoconductor with light from each light source to write an electrostatic image is known. ..

Further, the optical writing device is known to have a pixel clock generation function of measuring an actual scanning speed and correcting the frequency of the pixel clock based on an error between a measured value and a set value (patented). Document 1). The pixel clock described above is output by multiplying the unit clock ΔT by an integer. However, when the frequency of the corrected pixel clock is not an integral multiple of the unit clock ΔT, the following problems occur.

That is, if the frequency of the corrected pixel clock is, for example, 24.5 times the unit clock ΔT, it is necessary to alternately output the pixel clock of 24 × ΔT and the pixel clock of 25 × ΔT during one scan. By the way, when black and white print data are output alternately for each pixel clock as in (1) and (2) below, it is desirable that the images have the same density. However, the case of (1) looks darker, and there is a risk that density unevenness may occur.
(1) When there is print data (black) in the place where the pixel clock cycle is long (25 × ΔT) and there is print data (white) in the place where the pixel clock cycle is short (24 × ΔT) When there is print data (white) in the long part (24 x ΔT) and print data (black) in the short part (25 x ΔT) of the pixel clock cycle

The present invention has been made in view of the above background, and an object of the present invention is to provide an optical writing device and an image forming device with reduced density unevenness.

The invention according to claim 1, which has been made to solve the above-mentioned problems, measures the scanning speed of one of the two or more light sources in an optical writing device having two or more light sources, and the measured scanning is performed. A pulse clock generator that generates a pixel clock with a period corrected according to the speed, and a pulse width information generated by the pixel clock generator for each pixel clock are generated and output for each light source. The pulse information generation is provided with an output unit and a plurality of image pulse generation / output units provided for each of the two or more light sources to generate and output an image pulse having a pulse width corresponding to the pulse width information. The output unit outputs the pulse width information to be output to a part of the two or more light sources with a delay of one pixel clock, and the image pulse generation / output unit outputs the pulse width information of the two or more light sources. The image pulse to be output with respect to the rest excluding a part is output with a delay of one pixel clock.

As described above, according to the invention of claim 1, the pulse information generation / output unit outputs pulse width information to be output to a part of two or more light sources with a clock delay of one pixel, and outputs an image. The pulse generation / output unit outputs an image pulse to be output to the rest of the two or more light sources except for a part thereof with a clock delay of one pixel. Thereby, the density unevenness can be reduced.

It is a figure which shows the image forming apparatus which incorporated the optical writing apparatus of this invention. It is a figure for demonstrating the positional relationship between the light source mounted on the light source substrate shown in FIG. 1 and a photoconductor. It is a block diagram which shows the writing control part shown in FIG. It is a time chart of the polyphase clock clk_v0 to clk_v3 and the internal operation clock clk_g. It is a time chart of the internal operation clock clk_g, the pixel clock clk_w, and the image pulse. It is a time chart which enlarged a part of FIG. It is a time chart which shows the image pulse corresponding to the information output from the pixel clock clk_w, the pulse information generation / output unit. It is a time chart which shows the pixel clock clk_w, the image pulse output from the image pulse generation / output unit. It is a time chart of an image pulse. It is a block diagram which shows the pulse information generation | output part shown in FIG. 3 in another embodiment.

An embodiment of the present invention will be described with reference to FIGS. 1 to 6. As shown in FIG. 1, the image forming apparatus 1 includes a photoconductor 2, an optical writing apparatus 3, and an optical system 4.

The photoconductor 2 is formed in a substantially columnar shape and rotates about an axis. The photoconductor 2 is negatively charged, and the negative charge of the portion irradiated with light is canceled by the optical writing device 3, so that an electrostatic image is written. The optical writing device 3 is a device that irradiates the photoconductor 2 with light for writing an electrostatic image, and the details will be described later.

The optical system 4 is provided to scan the light from the optical writing device 3 on the surface (optical scanning surface) of the photoconductor 2. The optical system 4 includes a collimator lens 41, a cylinder lens 42, a polygon mirror 43, an fθ lens 44, a mirror 45, a toroidal lens 46, and photodetectors PD1 and PD2.

The laser beam from the optical writing device 3 is shaped by passing through the collimator lens 41 and the cylinder lens 42, and then is incident on the rotating polygon mirror 43. The polygon mirror 43 reflects the incident laser light so as to scan linearly on the photoconductor 2. The laser beam reflected by the polygon mirror 43 is irradiated onto the photoconductor 2 via the fθ lens 44, the mirror 45, and the toroidal lens 46 to form a light spot.

Photodetectors PD1 and photodetectors PD2 are arranged at both ends of the mirror 45, and the start and end of scanning of one of a plurality of laser beams emitted from the optical writing device 3 described later is detected. That is, the laser beam reflected by the polygon mirror 43 is incident on the photodetector PD1 before scanning one line on the photoconductor 2, and is incident on the photodetector PD2 after scanning. In each of the photo detectors PD1 and PD2, the incident laser light is converted into a first synchronization signal SPSYNC and a second synchronization signal EPSINC, respectively, and supplied to an optical writing device 3 described later.

The optical writing device 3 is a writing control unit that controls lighting of a light source substrate 31 on which a plurality of (two or more) light sources 31a1 to 31aN (FIG. 2) of 1ch to Nch are mounted, and a plurality of light sources 31a1 to 31aN. 32 and. A plurality of laser beams are emitted from the light source substrate 31 from the plurality of light sources 31a1 to 31a (hereinafter, may be abbreviated as the light source 31a), and the optical system 4 can scan the plurality of lines at the same time. The dotted line shown in FIG. 1 represents one of the laser beams of the plurality of light sources 31a1 to 31aN mounted on the light source substrate 31.

As shown in FIG. 2, the plurality of light sources 31a are installed apart from each other along the sub-scanning direction orthogonal to the writing scanning direction of the light source 31a. Of course, the light sources 31a may be arranged in a matrix along the scanning direction and the sub-scanning direction.

As shown in FIG. 3, the write control unit 32 includes a PLL 321 as a multi-phase clock generation unit, a 4-division unit 322, a pixel clock generation unit 323, and one pulse information generation / output unit 324. The image pulse generation / output unit 325 of the above is provided.

The PLL 321 is composed of a well-known PLL, and is a multi-phase clock clk_v0, clk_v1, clk_v2 whose phase difference (unit clock) ΔT = T / P is shifted from each other by the period T and the number of phases P based on the reference clock CLKREF. , Clk_v3 is generated (Fig. 4). Although P = 4 is set in FIG. 4, any integer may be used.

The 4-divided section 322 is composed of a well-known frequency divider, and divides one of the polyphase clocks clk_v0 to clk_v3 by 4 to generate an internal operation clock clk_g (FIG. 4). In the present embodiment, the 4-division portion 322 divides the multi-phase clock clk_v0 by 4 to generate the internal operation clock clk_g.

The pixel clock generation unit 323 measures the scanning speed of one of the plurality of light sources 31a mounted on the light source substrate 31, and generates pixel clock information and pixel clock pulses having a period corrected according to the measured scanning speed. .. The pixel clock generation unit 323 is composed of a pixel clock information generation unit 323A, a pixel clock PWM generation unit 323B, and a serializer 323C.

The pixel clock information generation unit 323A measures the scanning speed of one of the plurality of light sources 31a mounted on the light source substrate 31, and generates pixel clock information of a frequency corrected according to the measured scanning speed. The pixel clock information generation unit 323A is supplied with the above-mentioned first synchronization signal SPSYNC, the second synchronization signal EPSNC, the polyphase clocks clk_v0 to clk_v3, and the internal operation clock clk_g. The time difference between the first synchronization signal SPSYNC and the second synchronization signal EPSINC is a value corresponding to the scanning speed of one of the plurality of light sources 31a.

Further, the pixel clock information generation unit 323A is input with a preset target value of the number of pixel clocks to be output during one scan. The pixel clock information generation unit 323A compares the measured time difference (scanning speed) with the target value, and sets the frequency of the pixel clock so that the number of pixel clocks output during one scan becomes the target value. The target value is stored in the CPUIF register 327 by the CPU 326, and is input to the pixel clock information generation unit 323A from the CPUIF register 327. At this time, the pixel clock information generation unit 323A is set so that the frequency of the pixel clock is an integral multiple of the phase difference ΔT of the polyphase clocks clk_v0 to clk_v3.

However, the frequency of the pixel clock set by the pixel clock information generation unit 323A is not always an integral multiple of the phase difference ΔT. For example, consider a case where the frequency of the pixel clock set above is larger than N times the phase difference ΔT (N is an arbitrary integer) and smaller than (N + 1) times the phase difference ΔT, and is not an integral multiple. At this time, the pixel clock information generation unit 323A outputs a mixture of a pixel clock having a period N times the phase difference ΔT and a pixel clock having a period (N + 1) times the phase difference ΔT.

FIG. 5 shows a case where the frequency of the pixel clock clk_w set above is 24.5 times the phase difference ΔT. As shown in the second and seventh positions from the top of the figure, the pixel clock clk_w alternately outputs a period 24 times the phase difference ΔT and a period 25 times. FIG. 5 is an example, and the period of the pixel clock clk_w is set according to the time difference between the first synchronization signal SPSYNC and the second synchronization signal EPSINC.

Next, consider a case where an image pulse in which H and L are switched each time the pixel clock clk_w having a different cycle described above is output is output to a plurality of light sources 31a. In this case, depending on the output timing of the image pulse, the image pulse shown in the upper P1 of FIG. 5 may be output, or the image pulse shown in the lower P2 of FIG. 5 may be output. The image pulse shown in the upper part P1 of FIG. 5 becomes H in a period 24 times shorter than the phase difference ΔT and L in a period 25 times longer than the phase difference ΔT. On the other hand, the image pulse shown in the lower part P2 of FIG. 5 becomes L in a period 24 times shorter than the phase difference ΔT and H in a period 25 times longer than the phase difference ΔT. When the input image pulse is H, the light source 31a is turned on and, for example, black is printed. When the input image pulse is L, the light source 31a is turned off and, for example, white is printed.

Therefore, when the image pulse shown in the lower part P2 of FIG. 5 is input to the light source 31a, the image pulse shown in the upper part P1 of FIG. 5 becomes darker than when it is input to the light source 31a, and the output of the image pulse is increased. There is a problem that density unevenness occurs depending on the timing. The image forming apparatus 1 of the present embodiment suppresses such density unevenness.

The pixel clock information generation unit 323A outputs information about the generated pixel clock clk_w as pixel clock information. The pixel clock information is composed of, for example, PLS, EDG, and WD. The PLS is information indicating whether or not the edge of the pixel clock clk_w is included in the internal operation clock clk_g this time. The EDG is information indicating at which position in the internal operation clock clk_g the pixel clock clk_w rises. WD is information indicating how many times the period of the pixel clock clk_w is the phase difference ΔT.

The pixel clock PWM generation unit 323B is supplied with the PLS, EDG, and WD, and based on this, sequentially outputs a bit string of the pixel clock clk_w indicating H and L for each phase difference ΔT in parallel for each internal operation clock clk_g. .. That is, in the pixel clock PWM generation unit 323B, 16-bit bit strings of the pixel clock clk_w are sequentially output in parallel for each internal operation clock clk_g.

explain in detail. 1 When the internal operation clock clk_g is output, for example, when the pixel clock clk_w as shown in FIG. 6 is output, the bit string is “HHHHHHHHHHHLLLL”. The pixel clock PWM generation unit 323B is provided with a 16-bit output terminal, and outputs the 16-bit bit strings in parallel. The serializer 323C outputs the pixel clock clk_w by supplying the polyphase clocks clk_v0 to clk_v3 and sequentially outputting a 16-bit bit string for each phase difference ΔT.

As shown in FIG. 3, the pulse information generation / output unit 324 includes a pulse information generation unit 324A and a pulse information IF unit 324B.

The pixel clock clk_w is supplied to the pulse information generation unit 324A, and pulse width information, phase information, and shift amount information of the image pulse corresponding to the image data for each pixel clock clk_w are output. The pulse width information, the phase information, and the shift amount information are sequentially output for all the light sources 31a. The pulse width information is information indicating the time for setting the image pulse to H during the one-pixel clock clk_w.

When the pixel clock clk_w is high speed, the pulse information generation / output unit 324 has information indicating the entire width of the 1-pixel clock clk_w (H in total for the 1-pixel clock clk_w) and information indicating 0 (L in total for the 1-pixel clock clk_w). And, only two types of pulse width information may be output. Further, in addition to these two types, the pulse information generation / output unit 324 may output three types of information indicating half of the one-pixel clock clk_w as pulse width information.

The phase information is information indicating the phase difference between the pixel clock clk_w and the image pulse. As described above, the phase information is not necessary when only two types of pulse width information, the full width of the 1-pixel clock clk_w and the information indicating 0, are output. However, an image pulse that is H in the first half of the 1-pixel clock clk_w and L in the second half and L in the first half and H in the first half of the 1-pixel clock clk_w is output to form an image with twice the accuracy of the pixel clock clk_w. If you want to, you need phase information. That is, when the information indicating half of the 1-pixel clock clk_w is output as the pulse width information and the information indicating 0 is output as the phase information, the image pulse generation / output unit 325 described later is H in the first half of the 1-pixel clock clk_w. Moreover, an image pulse that becomes L in the latter half is output. Further, when the information indicating half of the 1-pixel clock clk_w is output as the pulse width information and the information indicating half of the 1-pixel clock clk_w is output as the phase information, it becomes L in the first half of the 1-pixel clock clk_w and H in the latter half. Image pulses can be output.

The shift amount information is information indicating the shift amount of the image pulse for each pixel clock clk_w in order to make the lengths of the scanning lines for each light source 31a uniform, and is set to an integral multiple of the phase difference ΔT. When a plurality of light sources 31a are controlled by the same pixel clock clk_w as described above, the width of the light spot irradiated to the photoconductor 2 for each light source 31a is caused by the difference in the distance between the light source 31a and the photoconductor 2. Is different, and the length of the scanning line is different. The PWM generation unit 325A, which will be described later, shifts the image pulse by the shift amount according to the shift amount information, so that even if there is a difference in the distance between the light source 31a and the photoconductor 2, the variation in the length of the scanning line is suppressed. it can.

The pulse information generation unit 324A can output the pulse width information, phase information, and shift amount information of the light source 31a specified in advance by the CPU 326 to the pulse information IF unit 324B, which will be described later, with a delay of one pixel clock clk_w. ..

The pulse information IF unit 324B outputs pulse width information, phase information, and shift amount information (hereinafter abbreviated as “various information”) from the pulse information generation unit 324A in parallel for each light source 31a.

The image pulse generation / output unit 325 is provided for each light source 31a. The image pulse generation / output unit 325 includes a PWM generation unit 325A and a serializer 325B. Pixel clock information (WD, EDG, PLS) from the pixel clock information generation unit 323A is supplied to the PWM generation unit 325A. Further, the PWM generation unit 325A is supplied with pulse width information, phase information, and shift amount information for each pixel clock from the pulse information IF unit 324B. The PWM generation unit 325A has a pulse width corresponding to the pulse width information, and generates an image pulse whose timing is shifted according to the shift amount information. The multi-phase clocks clk_v0 to clk_v3 are supplied to the PWM generation unit 325A, and the pulse width of the image pulse is set to an integral multiple of the phase difference ΔT. The shift amount is also set to an integral multiple of the phase difference ΔT.

Further, the PWM generation unit 325A sequentially outputs bit strings of image pulses indicating H and L for each phase difference ΔT for each internal operation clock clk_g in parallel. That is, in the PWM generation unit 325A, 16-bit bit strings of image pulses are sequentially output in parallel for each internal operation clock clk_g.

explain in detail. 1 When the internal operation clock clk_g is output, for example, when an image pulse as shown in FIG. 6 is output, the bit string is “HHHHHHHHHHHHHHH”. Each of the PWM generation units 325A is provided with a 16-bit output terminal, and the 16-bit bit strings are output in parallel. Multiphase clocks clk_v0 to clk_v3 are supplied to the serializer 325B, and an image pulse is output by sequentially outputting a 16-bit bit string for each phase difference ΔT.

Multiphase clocks clk_v0 to clk_v3 are supplied to the serializer 325B, and 16-bit bit strings (image pulses) are sequentially output for each phase difference ΔT. The serializer 325B has a built-in shift register function. As a result, when the delay is set by the CPU 326, the serializer 325B delays the bit string by one pixel clock clk_w and outputs it to the drive unit of the light source 31a. On the other hand, if the delay is not set by the CPU 326, the serializer 325B does not delay the bit string and outputs it to the drive unit of the light source 31a.

Next, the operation of the image forming apparatus 1 having the above-described configuration will be described below with reference to FIGS. 7 and 8. The CPU 326 delays the light sources 31a1, 31a3 ... Arranged at odd numbers in the arrangement direction by one pixel clock clk_w with respect to the pulse information generation unit 324A, and outputs pulse width information, phase information, and shift amount information. Specify as. That is, the light sources 31a1, 31a3 ... Arranged at odd numbers correspond to "some light sources".

Further, the CPU 326 does not set a delay for the serializer 323C corresponding to the light sources 31a1, 31a3 ... Arranged at odd numbers in the arrangement direction. Further, the CPU 326 sets a delay for the serializer 323C corresponding to the light sources 31a2, 31a4 ... Arranged even-numbered in the arrangement direction. That is, the even-numbered light sources 31a2, 31a4 ... Correspond to the "remaining light sources".

After that, the CPU 326 starts scanning. The pixel clock information generation unit 323A measures the scanning speed of one of the plurality of light sources 31a mounted on the light source substrate 31, and generates pixel clock information of a frequency corrected according to the measured scanning speed. The case where the frequency of the corrected pixel clock clk_w is 24.5 times the phase difference ΔT is shown. In this case, as shown in FIG. 7, the pixel clock generation unit 323 alternately outputs the pixel clock clk_w of 24 × ΔT and the pixel clock clk_w of 25 × ΔT.

Here, in order to simplify the explanation, a case where an image pulse in which H and L are switched each time the pixel clock clk_w is output is output to a plurality of light sources 31a will be considered. In this case, the image pulse (hereinafter, virtual image pulse) generated from the information output from the pulse information generation / output unit 324 is as shown in FIG. That is, in the present embodiment, the virtual image pulses of 1ch and 3ch corresponding to the odd-numbered light sources 31a1, 31a3 ... Are delayed by the pulse information generation unit 324A by one pixel clock clk_w as shown in FIG. To. Therefore, the odd-numbered (1ch, 3ch ...) Virtual image pulse becomes L in a short cycle of 24 times the phase difference ΔT and H in a long cycle of 25 times the phase difference ΔT. On the other hand, the even-numbered (2ch, 4ch ...) Virtual image pulse becomes H in a short cycle of 24 times the phase difference ΔT and L in a long cycle of 25 times the phase difference ΔT. The odd-numbered (1ch, 3ch ...) Virtual image pulse and the even-numbered (2ch, 4ch ...) Virtual image pulse are out of phase by the 1-pixel clock clk_w.

Virtual image pulse information as shown in FIG. 7 is output from the pulse information generation / output unit 324 and input to the image pulse generation / output unit 325. The plurality of PWM generation units 325A output image pulses generated based on the information from the pulse information generation / output unit 324 to the serializer 325B. In this embodiment, as shown in FIG. 8, the output of the even-numbered (2ch, 4ch ...) Serializer 325B is delayed by one pixel clock clk_w.

Therefore, the phases of the odd-numbered (1ch, 3ch ...) Image pulse and the even-numbered (2ch, 4ch ...) Image pulse match. Moreover, the odd-numbered (1ch, 3ch ...) image pulse becomes L in a short cycle of 24 times the phase difference ΔT and H in a long cycle of 25 times the phase difference ΔT, and the even-numbered (2ch, 4ch ...) virtual pulse. The image pulse becomes H in a short cycle of 24 times the phase difference ΔT and L in a long cycle of 25 times the phase difference ΔT. Since the image pulse that becomes H in a period that is 24 times shorter than the phase difference ΔT or H in a period that is 25 times longer than the phase difference ΔT is not supplied to all the light sources 31a, density unevenness is suppressed. be able to.

According to the above-described embodiment, the light source 31a (some light sources) that outputs the image pulse delayed by the pulse information generation / output unit 324 and the image pulse delayed by the image pulse generation / output unit 325 are generated. The light sources 31a (remaining light sources) to be output are arranged alternately, but the present invention is not limited to this. For example, a random generator or the like may be used to output an image pulse delayed by the pulse information generation / output unit 324 for the light source 31a corresponding to the random number generated by the random generator. That is, the CPU 326 may act as a setting unit and randomly set the light source 31a that outputs the image pulse delayed by the pulse information generation / output unit 324. According to this, even if image data having a periodicity in the scanning direction of the light source 31a is input, density unevenness can be suppressed.

Further, according to the above-described embodiment, the pulse information generation unit 324A outputs the shift amount information of the image pulse, but the present invention is not limited to this. The shift amount information is not essential and does not have to be output.

Further, according to the above-described embodiment, the information output from the pulse information generation unit 324A is delayed by one pixel clock clk_w only for the information corresponding to the designated light source 31a, but this is limited to this. It's not a thing. For example, as shown in FIG. 9, it is conceivable to provide a shift register 324C and a changeover switch 324D between the pulse information IF unit 324B and the image pulse generation / output unit 325.

The shift register 324C is provided for each light source 31a, delays various information output from the pulse information IF unit 324B by one pixel clock clk_w, and outputs the shift register 324C to the image pulse generation / output unit 325 described later.

The changeover switch 324D is provided for each shift register 324C. The changeover switch 324D switches between outputting various information output from the pulse information IF unit 324B with a delay of one pixel clock clk_w through the shift register 324C, or outputting the information as it is without passing through the shift register 324C. The changeover switch 324D is controlled by the CPU 326.

The CPU 326 switches the changeover switch 324D corresponding to the designated light source 31a to the side through which the shift register 324C is passed. In this case as well, the same effect as that of the above-described embodiment can be obtained.

The present invention is not limited to the above embodiment. That is, it can be modified in various ways without departing from the gist of the present invention.

1 Image forming device 3 Optical writing device 4 Optical system 7 Optical system 31a Light source 31a1 to 31aN Light source 323 Pixel clock generation unit 324 Pulse information generation / output unit 325 Image pulse generation / output unit 326 CPU (setting unit)

Japanese Unexamined Patent Publication No. 2006-305780

Claims (6)

In an optical writing device having two or more light sources
A pixel clock generator that measures the scanning speed of one of the two or more light sources and generates a pixel clock with a period corrected according to the measured scanning speed.
A pulse information generation / output unit that generates pulse width information for each pixel clock generated by the pixel clock generation unit and outputs the pulse width information for each light source.
It is provided for each of the two or more light sources, and includes a plurality of image pulse generation / output units that generate and output an image pulse having a pulse width corresponding to the pulse width information.
The pulse information generation / output unit outputs the pulse width information to be output to a part of the two or more light sources with a delay of one pixel clock.
The image pulse generation / output unit is an optical writing device characterized in that the image pulse to be output to the rest of the two or more light sources excluding a part thereof is output with a clock delay of one pixel. A multi-phase clock generator that generates a multi-phase clock that is out of phase with each other by a phase difference T / P with a period T and a number of phases P is provided.
The optical writing device according to claim 1, wherein the pixel clock generation unit corrects the period of the pixel clock so as to be an integral multiple of the phase difference T / P. The optical writing device according to claim 1 or 2, wherein the two or more light sources are provided side by side along a sub-scanning direction orthogonal to the writing scanning direction of the light source. The optical writing device according to claim 3, wherein the partial light source and the remaining light source are alternately arranged side by side along the sub-scanning direction. The optical writing device according to any one of claims 1 to 3, further comprising a setting unit for randomly setting a light source to be a part thereof. The optical writing device according to any one of claims 1 to 5.
An image forming apparatus comprising an optical system for light scanning light from the light source onto an optical scanning surface.

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