JP2007227706A - Method of forming buried wiring layer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a buried wiring layer of multiple films having a high reliability and a high yield causing no increase in resistance in a method of forming the buried wiring layer. <P>SOLUTION: A conductor layer buried in a wiring line groove 3 is polished to polish a buried wiring layer 4, and thereafter the exposed surface of the buried wiring layer 4 is cleaned/subjected to heat treatment with use of an organic gas 5. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for forming an embedded wiring, and in particular, removes residues and metal foreign matters after copper wiring polishing of a semiconductor device having a damascene structure without damage, as well as withstand voltage characteristics, inter-wire leakage resistance, and TDBD. The present invention relates to a method for forming an embedded wiring characteristic in a structure for improving the pressure resistance and the like.

  Conventionally, aluminum has been widely used as an electrode material and wiring material for semiconductor devices. However, in response to recent demands for miniaturization of semiconductor devices and higher processing speeds, the formation of electrodes and wiring should be handled with aluminum. Is getting harder.

  Therefore, an attempt is being made to use copper, which is resistant to electromigration and has a specific resistance smaller than that of aluminum, as a next-generation material for aluminum.

  When copper is used as the electrode material or wiring material, copper is a material that is difficult to selectively etch, so the electrodes and wiring are formed as embedded electrodes or embedded wiring by the damascene method. By increasing the aspect ratio of the electrodes and wirings to be formed, it becomes possible to realize miniaturization and higher speed of the semiconductor device.

Since copper used as such an electrode material or wiring material has a property of being easily oxidized, copper oxide (CuO) or copper oxide is formed on the surface of copper formed as an electrode or wiring in the manufacturing process of a semiconductor device. Copper oxide such as cuprous oxide (Cu ₂ O) is formed.

  Since the copper oxide causes a decrease in characteristics of the semiconductor device such as an increase in electric resistance, a cleaning process is required to remove the generated copper oxide after the electrode formation or the wiring formation.

  Further, in the CMP (chemical mechanical polishing) process for exposing the wiring after embedding the electrode material and the wiring material, Cu scraps and slurry components generated during the polishing and the cleaning liquid after polishing may remain. The cleaning process is performed with chemicals.

  Also, copper is buried in the wiring groove hole mainly by plating, but there are many voids, impurities caused by the plating solution, and copper oxide due to moisture in the plating solution dispersed inside the copper formed by plating. is doing.

  The voids, impurities, and copper oxide cause a decrease in characteristics of the semiconductor device such as an increase in electrical resistance, but further decrease the stress migration characteristics. Therefore, it is necessary to perform a process for removing voids, impurities, and copper oxide that have been generated after the electrode or wiring for plating formation is buried.

Therefore, the copper formed by plating is usually annealed, and the growth of the copper grain boundary by this annealing becomes a driving force for pushing out voids and impurities existing at the grain boundary interface to the outside. (For example, refer to Patent Document 1).
The annealing conditions used at this time are 100 to 400 ° C. in the air or an inert gas atmosphere for about 5 seconds to 1 hour.

In addition, in order to increase the speed of semiconductor devices, it is necessary to lower the dielectric constant of the interlayer insulating film in order to reduce the parasitic capacitance as well as to reduce the resistance of the wiring and electrodes. Attempts have been made to employ low dielectric constant organic insulating materials such as ether (for example, Dow Chemical Company registered trademark SiLK) and porous silica (for example, see Patent Document 2).
Japanese Patent Laid-Open No. 11-297696 JP 2004-071705 A

  However, in the conventional cleaning process, particle removal and chemical solution removal are performed, and then pure water cleaning is performed to remove the attached chemical solution. In this pure water cleaning, the chemical solution is gradually removed. As a result, there is a problem that erosion of copper forming the embedded electrode and the embedded wiring occurs as the cleaning water changes from acidic to neutral and the pH value increases.

Further, the conventional annealing treatment has the following problems.
Conventional annealing is performed in the atmosphere or in an inert gas, but the copper grain boundary grows to some extent due to annealing, and the voids in the plating move to the upper part of the plating layer with the growth, and the voids moved to the upper part. Are removed in the CMP process.

  However, not all the voids inside the plating film move to the upper layer, but the residual voids that cannot be removed by the CMP process move again due to the temperature environment at the time of driving the device, leading to the opening of the wiring and vias ( Stress migration). Further, there is a problem that the void moves due to the device operating current and the standby leakage current and causes the wiring to open.

In addition, impurities caused by the plating solution exist inside the copper film formed by plating, and these impurities cause wiring corrosion. In addition, annealing in the atmosphere oxidizes the copper surface, but copper oxidation proceeds in the depth direction, so copper oxide cannot be completely removed in the CMP process and can remain in the embedded wiring. Sex occurs.
This remaining copper oxide causes an increase in wiring resistance.

  Further, when the cap film is formed on the porous Low-k material, the influence is small. However, when directly polishing the porous Low-k material, there is a possibility that the slurry component or the cleaning liquid component may remain in the porous pores. Therefore, there is a problem and a problem that the insulating property is lowered.

  Therefore, an object of the present invention is to provide a buried multilayer wiring having high reliability and high yield that does not cause an increase in resistance.

FIG. 1 is a diagram illustrating the basic configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
In the figure, reference numeral 1 denotes a lower layer wiring.
In order to solve the above-described problem, the present invention provides a method for forming the buried wiring 4 in which the conductive layer buried in the wiring groove 3 is polished to polish the buried wiring 4, and then the gas is in a gaseous state. The method includes a step of cleaning and heat treating the surface of the exposed portion of the embedded wiring 4 with an organic gas 5.

  As described above, by performing cleaning and heat treatment in the organic gas 5 in a gaseous state after the formation of the embedded wiring 4, metal debris and chemical liquid residual components adhering to the surface of the insulating film 2 after the CMP process are simultaneously removed. In addition, the self-oxide on the surface of the buried wiring 4 can be removed.

  That is, the possible mechanism for removing metal scraps remaining on the wiring surface by the organic gas 5 treatment is to vaporize together with the organic gas 5 while the metal is etched by forming a complex with the metal. It is thought to do.

  In addition, since the metal scrap after polishing is an ultra-fine size having a diameter of 1 to 0.1 μm or less, the metal forming the wiring is also etched while the metal scrap is being etched. Within the time required for removing metal debris by the gas 5, the wiring resistance is not affected at all.

Further, as an effect of cleaning with the organic gas 5, removal of chemical components remaining on the surface, mainly chemical components composed of organic components and water can be mentioned.
Although the chemical component remaining on the wiring surface remains as a so-called watermark, the watermark can be effectively removed by optimizing the type of the organic gas 5 used for the treatment with respect to the remaining chemical component.
In addition, although the process by a liquid phase is also considered, generation | occurrence | production of the watermark by the wettability defect with a substrate surface and generation | occurrence | production of an unprocessed part will be a problem.

In addition, voids and impurities remaining in the buried wiring 4 can be simultaneously reduced by the heat treatment in the gaseous organic gas 5.
That is, the surface of the plated copper is reduced during the annealing with the organic gas 5, so that the surface concentration of the copper oxide is reduced, and the copper oxide inside the plating moves to the surface through the grain boundary.
At this time, since the voids in the conductor layer are originally distributed at the grain boundaries, they move to the surface as the copper oxide moves.

On the other hand, the impurities in the conductor layer also move to the surface as the substance moves at the grain boundaries, and the impurities that have moved to the surface are removed by the organic gas 5.
Therefore, in addition to the conventional grain growth by the annealing effect, the removal of impurities in the grain boundary by the treatment with the organic gas 5 can provide a highly reliable device.

Further, as the organic gas 5 used in the heat treatment step, a gas having a carboxylic acid such as formic acid, acetic acid, propionic acid or butyric acid is desirable, thereby preventing other members such as the insulating film 2 from being damaged. .
The reaction becomes softer as the molecular weight of the carboxylic acid increases.
In particular, organic acids or alcohols having a relatively large molecular weight are good for removing the surfactant in the chemical solution.

On the other hand, since low molecular weight organic acids such as formic acid are effective for removing metal scraps, treatment with high molecular weight organic acids or alcohols may be performed after formic acid treatment.
Moreover, even if it processes by flowing these gases simultaneously, the same effect is acquired.

  Alternatively, the organic gas 5 used in the heat treatment step may be alcohols such as methanol, and since the reaction is generally softer than the gas having carboxylic acid, the insulating film 2 has Si as a constituent element. Even when the organic insulating film is included, the insulating film 2 is not damaged by the heat treatment.

  The above heat treatment is applied to wirings made of various materials, but particularly in the case of copper or an alloy containing copper such as Cu-Al, Cu-Si in which surface oxides and subsequent corrosion are problematic. It becomes effective.

  In the present invention, the cleaning / heat treatment process after polishing is performed as a vapor phase process, so that the cleaning process after the process is not required, and therefore, the copper having a high leak rate of the via contact without causing the corrosion of the wiring or the like. A multilayer wiring can be obtained.

  Further, since the dielectric constant of the insulating film for forming the wiring does not increase with the cleaning / heat treatment process, a high-speed semiconductor device as designed can be configured.

  In the present invention, an interlayer insulating film is provided on a lower wiring or via, an upper wiring or via is formed using a single damascene method or a dual damascene method, and a trench for filling is formed by dry etching using fluorocarbon or the like for the interlayer insulating film. Alternatively, after forming the embedding hole, a metal such as Cu is embedded in the embedding groove or embedding hole, and the unnecessary portion is polished by the CMP method so that the embedded wiring or via can be formed simultaneously or in individual steps. After the formation, the surface is cleaned and heat-treated with a gaseous organic acid or the like.

By using carboxylic acid or alcohol as the organic gas used for cleaning and heat treatment, the organic gas and metal scrap form a complex and are removed in a gas phase.
For example, the carboxylic acid used as the cleaning agent is formic acid [HCOOH],
Acetic acid [CH ₃ COOH: Ethanoic acid]
Propionic acid [C ₂ H ₅ COOH: propanoic acid] Butyric acid [C ₃ H ₇ COOH: butanoic acid]
It is preferable to use one having a relatively low boiling point.

  In addition to the component containing carboxylic acid as the organic gas, a cleaning action can be obtained even if an alcohol component such as methanol or ethanol is vaporized and ejected.

  In this case, the gas-phase cleaning / heat treatment conditions are such that the partial pressure of carboxylic acid in the processing chamber is in the range of 50 Pa to 10,000 Pa, the reduction temperature is 100 ° C. to 400 ° C., the total pressure is 100 Torr to 300 Torr, and the reduction time is 3 minutes. In particular, when the reduction temperature is 400 ° C., by processing under the reaction conditions of a pressure of 100 Torr to 200 Torr for a reduction time of 1 minute, the metal scrap can be uniformly removed in a short reduction time without causing irregularities on the surfaces of the electrodes and wiring. And chemical components can be removed.

  By such cleaning and heat treatment, it becomes possible to simultaneously remove metal debris and chemical residual components adhering to the surface of the insulating film after the CMP process and to remove the self-oxide on the surface of the embedded wiring. In addition, voids and impurities remaining in the embedded wiring can be reduced.

Next, the dual damascene process according to the first embodiment of the present invention will be described with reference to FIGS. 2 to 4. First, with reference to FIG. 2, the cleaning / heat treatment apparatus used for implementing the present invention will be described. .
See Figure 2
FIG. 2 is a conceptual configuration diagram of a cleaning / heat treatment apparatus used in the practice of the present invention.
This cleaning / heat treatment apparatus is a cleaning / heat treatment apparatus that also functions as an ashing apparatus, and includes a processing chamber 11 that includes a gas inlet 12 and an exhaust port 13, and a lower electrode 14 that also functions as a stage provided in the processing chamber 11, A ring-shaped upper electrode 15 provided so as to face the lower electrode 14; an organic gas jet shower head 16 movably fitted in the center of the ring-shaped upper electrode 15; a storage tank 19 for storing organic materials; An organic gas supply pipe 17 connected between the organic gas jet shower head 16 and an organic gas provided in the middle of the organic gas supply pipe 17 is vaporized by heating and vaporizing the organic material into an organic gas. The heater 18 is disposed below the lower electrode 14 that also serves as a stage and heats the substrate 21 to be processed.

  In the cleaning / heat treatment step, as shown in the figure, the organic gas jet shower head 16 is lowered and fitted into the center of the ring-shaped upper electrode 15, and in this state, the vaporizer 18 is discharged from the organic gas jet shower head 16. The substrate 21 after the formation of the embedded wiring heated by the heater 20 to a temperature at which the reaction product is in a gaseous state is ejected by heat treatment, and the gaseous reaction product and Unreacted organic gas is discharged from the exhaust port 13 in a down flow.

Next, a dual damascene process according to the first embodiment of the present invention will be described with reference to FIGS.
See Figure 3
First, after an element isolation insulating film 32 is formed on a p-type silicon substrate 31, a gate electrode 34 is provided via a gate insulating film 33, and an n-type impurity is introduced using the gate electrode 34 as a mask to thereby form an n-type extension region. After forming 35 and then forming sidewalls 36, n-type source / drain regions 37 are formed by introducing n-type impurities again.

Next, after depositing Co on the entire surface, heat treatment is performed to form Co silicide electrodes 38 and 39, and after removing unreacted Co, an SiO ₂ film 40 and a BPSG film 41 are deposited on the entire surface. Then, the surface is flattened to form an SiCN film 42 that serves as an etching stopper.

  Next, a via hole reaching the n-type source / drain region 37 is formed, W is buried through a barrier film 43 made of TiN, and unnecessary portions are removed by CMP to form a W plug 44.

  Next, after depositing a first wiring insulating film 45 made of SiOC using a plasma CVD method, a wiring groove exposing the W plug 44 is formed, and then Cu is formed through a barrier film 46 made of TaN. A first Cu buried wiring 47 is formed by removing unnecessary portions by embedding and CMP.

Next, a substrate to be processed is mounted in the processing chamber 11, and the formic acid gas 48 vaporized by the vaporizer 18 from the organic gas ejection shower head 16 is introduced so that the partial pressure of the formic acid gas 48 becomes 200 Pa. 20, the substrate temperature is set to 150 ° C., and the substrate to be processed is processed in a reduction time of 2 minutes in a state where the total pressure is 200 Torr, and the Cu scrap remaining on the surfaces of the first Cu embedded wiring 47 and the first wiring insulating film 45. As formic acid copper formed by the formic acid oxidation reaction, the remaining chemical solution component is exhausted and removed from the exhaust port 13 as formic acid.
Further, the copper oxide formed on the copper surface is reduced to metallic copper, and exhausted and removed from the exhaust port 13 together with CO ₂ and water vapor (H ₂ O) generated by the reduction reaction.

Next, the plasma CVD method is used to form a SiCN film 49 having a thickness of, for example, 50 nm, a via forming insulating film 50 made of SiO ₂ having a thickness of, for example, 150 nm, and a SiCN film 51 having a thickness of, for example, 50 nm. Then, a second wiring insulating film 52 made of SiOC having a thickness of, for example, 250 nm, and a SiCN film 53 having a thickness of, for example, 50 nm are sequentially deposited.

See Figure 4
Next, after a wiring groove 54 having a width of, for example, 0.12 μm is formed in the second wiring insulating film 52 by plasma etching using a fluorocarbon-based etching gas, the first Cu is embedded in the via forming insulating film 50. A via hole 55 having a diameter reaching the wiring 47 of, for example, 0.12 μm is formed.

Next, after the substrate to be processed in which the wiring groove 54 and the via hole 55 are formed is placed and fixed on the lower electrode 14 in the above-described processing chamber, 400 sccm of O ₂ is introduced to 70 Pa from the gas inlet. Then, the heater 20 is heated to a substrate temperature of 80 ° C. and 600 W of electric power is applied to generate oxygen plasma, and plasma treatment is performed in this oxygen plasma for 60 seconds to etch resist residues and the like accompanying the etching process. The residue is removed by ashing.

  Next, again, the wiring trench 54 and the via hole 55 are filled with Cu via the barrier film 56 made of TaN, and unnecessary portions are removed by CMP to form the Cu via 57 and the second Cu buried wiring 58.

Next, the substrate to be processed is mounted again in the processing chamber 11, and the formic acid gas 59 vaporized by the vaporizer 18 from the organic gas ejection shower head 16 is introduced so that the partial pressure of the formic acid gas 59 becomes 200 Pa. The substrate temperature is set to 150 ° C. by the heater 20, and the substrate to be processed is processed in a processing time of 2 minutes in a state where the total pressure is 200 Torr. As the copper formate formed by the oxidation reaction, the residual chemical component is exhausted and removed from the exhaust port 13 as formic acid.
Further, the copper oxide formed on the copper surface is reduced to metallic copper, and exhausted and removed from the exhaust port 13 together with CO ₂ and water vapor (H ₂ O) generated by the reduction reaction.

  Thereafter, according to the required number of multilayer wiring layers, via formation insulating film and interlayer insulation film deposition process, wiring trench and via hole formation process, ashing process, via and embedded wiring formation process, and The semiconductor device is completed by repeating the cleaning / heat treatment process.

In Example 1 of the present invention, 20M (2 × 10 ⁷ ) via chains were formed in the above-described two-layer wiring structure shown above and the leakage yield between the chains was confirmed. The leakage yield of the via chain was 100%. And a sufficient yield was obtained.

  Further, when the relative dielectric constant after cleaning and heat treatment of the SiCN film to be the barrier films 53, 51, 49 in this case was measured, it was about 3.6, which was slightly reduced from about 3.8 before the processing. Was.

As described above, in Example 1 of the present invention, cleaning and heat treatment are performed as gas phase treatment using vaporized formic acid gas, so that the reaction product does not remain on the surface of the substrate to be processed. Therefore, since a cleaning process using pure water is not required, a contact failure due to corrosion of the embedded wiring or via does not occur.
In addition, since the relative dielectric constant of the interlayer insulating film accompanying the cleaning / heat treatment is not increased, signal delay due to the increase in parasitic capacitance does not occur.

In addition, the surface of the plated copper is reduced during the cleaning and heat treatment process using the organic gas, so that the surface concentration of the copper oxide is reduced, and the copper oxide inside the plating moves to the surface through the grain boundary.
At this time, since the voids in the conductor layer are originally distributed at the grain boundaries, they move to the surface along with the movement of the copper oxide and are released from the surface.

  Furthermore, the impurities in the conductor layer also move to the surface as the substance moves at the grain boundaries, and the impurities that have moved to the surface are removed by the organic gas.

  Incidentally, after the above-described CMP process, when a two-layer wiring structure was produced without performing cleaning and heat treatment with formic acid gas, the leakage yield of the via chain having the same structure as in Example 1 was 90%, and the insulation characteristics There was a lack.

Next, a dual damascene process according to the second embodiment of the present invention will be described. As the second wiring insulating film 52, an organic insulating material having a low dielectric constant such as polyether (for example, registered trademark SiLK ^™ , Dow Chemical Co., Ltd.) is used. Along with this, the ashing process is performed using hydrogen plasma, and the cleaning and heat treatment is performed using methanol gas. The basic process and structure are the same as in the above embodiment. Since it is exactly the same as 1, detailed description of the process is omitted.

In Example 2, methanol gas vaporized by the vaporizer 18 from the organic gas jet shower head 16 is introduced into the processing chamber 11 so that the partial pressure becomes 200 Pa, and the substrate temperature is set to 150 ° C. by the heater 20. Then, the substrate to be processed was processed in a processing time of 2 minutes in a state where the total pressure was 200 Torr, and Cu scrap remaining on the surface of the first Cu embedded wiring 47 or the second Cu embedded wiring 58 was formed by a formic oxidation reaction. As the formic acid copper, the residual chemical component is exhausted and removed from the exhaust port 13 together with the formic acid.
At the same time, the copper oxide formed on the surface of the first Cu embedded wiring 47 is reduced to metallic copper.

  The leak yield in Example 2 was 100% as the leak yield of the via chain having the same structure as that of Example 1 described above, and an insulating property equivalent to that of Example 1 was obtained.

  Incidentally, after the above-described CMP process, a two-layer wiring structure was prepared without performing cleaning / heat treatment with methanol gas. As a result, the leakage yield of the via chain having the same structure as that of Example 1 was 89%. The physical constitution was lacking.

  Next, although the dual damascene process of Example 3 of the present invention will be described, porous silica is used as the second wiring insulating film 52 and the SiCN film thereon is omitted, and accordingly, an ashing process is performed. It is performed lightly using oxygen plasma, and cleaning and heat treatment are performed using acetic acid gas and methanol whose reaction is softer than formic acid gas. The basic process and structure are completely the same as those of the first embodiment. Since it is the same, detailed description of the process is omitted.

  The porous silica in this case is formed, for example, by spin-coating a porous silica raw material (NCS) manufactured by Catalyst Chemical Industry Co., Ltd. on a substrate to be processed, followed by baking (baking) and curing (curing).

  Acetic acid gas and methanol vaporized by the vaporizer 18 from the organic gas jet shower head 16 are introduced into the processing chamber 11 so that each partial pressure becomes 100 Pa, the substrate temperature is set to 200 ° C. by the heater 20, The substrate to be processed is processed in a processing time of 2 minutes under a pressure of 200 Torr, and Cu scrap remaining on the surface of the first Cu embedded wiring 47 or the second Cu embedded wiring 58 is converted into copper acetate formed by an acetylation reaction. The residual chemical component is exhausted and removed from the exhaust port 13 together with acetic acid.

  At the same time, the copper oxide formed on the surface of the first Cu embedded wiring 47 or the second Cu embedded wiring 58 is reduced to metallic copper. In addition, the chemical components that have entered the cavities of the NCS are simultaneously removed by the gasified methanol.

The leakage yield in Example 3 was 100% as the leakage yield of the via chain having the same structure as that of Example 1 described above, and the insulation resistance equivalent to that of Example 1 was obtained.
Moreover, the dielectric constant of the porous silica after the cleaning and heat treatment was about 2.2, and almost no change was observed between the dielectric constants before the treatment.

  Incidentally, after the above-described CMP process, when a two-layer wiring structure was produced without performing cleaning / heat treatment with acetic acid gas, the leakage yield of the via chain having the same structure as that of Example 1 was 55%, and insulation was performed. Tolerance was largely lacking.

  Next, the dual damascene process of Example 4 of the present invention will be described. The same SiOC film as the second wiring insulating film 52 is used as the insulating film 50 for via formation, etc., and the other processes and structures are as follows. Since it is exactly the same as the first embodiment, detailed description of the process is omitted.

  The leak yield in Example 4 was 100% as the leak yield of the via chain having the same structure as that of Example 1 described above, and the insulation resistance equivalent to that of Example 1 was obtained.

  Incidentally, after the above-described CMP process, a two-layer wiring structure was prepared without performing cleaning and heat treatment with formic acid gas. As a result, the leakage yield of the via chain having the same structure as that of Example 1 was 88%. Resistance was reduced.

Next, a single damascene process according to a fifth embodiment of the present invention will be described with reference to FIGS. 5 to 7. The basic structure and processing conditions are the same as those described above except that the dual damascene process is replaced with a single damascene process. This is exactly the same as Example 1.
See Figure 5
First, although not shown in the figure, the W plug 44 connected to the MOSFET and the Co silicide electrode provided on the n-type source / drain region is formed in the same manner as in FIG. After depositing an insulating film 45 for one wiring, a wiring groove exposing the W plug 44 is formed, and then Cu is buried through a barrier film 46 made of TaN, and unnecessary portions are removed by CMP. A first Cu embedded wiring 47 is formed.

Next, a substrate to be processed is mounted in the processing chamber 11, and the formic acid gas 48 vaporized by the vaporizer 18 from the organic gas ejection shower head 16 is introduced so that the partial pressure of the formic acid gas 48 becomes 200 Pa. 20, the substrate temperature is set to 150 ° C., the substrate to be processed is processed in a reduction time of 2 minutes under the condition that the total pressure is 200 Torr, and the Cu scrap remaining on the surfaces of the first Cu embedded wiring 47 and the first wiring insulating film 45. Is formic acid copper formed by the formic acid reaction, and the remaining chemical components are exhausted and removed from the exhaust port 13 together with formic acid.
Further, the copper oxide formed on the copper surface is reduced to metallic copper, and exhausted and removed from the exhaust port 13 together with CO ₂ and water vapor (H ₂ O) generated by the reduction reaction.

Next, the plasma CVD method is used to form a SiCN film 49 having a thickness of, for example, 50 nm, a via forming insulating film 50 made of SiO ₂ having a thickness of, for example, 150 nm, and a SiCN film having a thickness of, for example, 50 nm. After sequentially depositing the film 51, a via hole 60 having a diameter of, for example, 0.12 μm reaching the first Cu embedded wiring 47 is formed in the via forming insulating film 50 by plasma etching using a fluorocarbon-based etching gas.

Next, after the substrate to be processed in which the via hole 60 is formed is placed and fixed on the lower electrode 14 in the above-described processing chamber, 400 sccm of O ₂ is introduced from the gas introduction port to 70 Pa, and the heater 20 is used. Heating to a substrate temperature of 80 ° C. and applying 600 W of power to generate oxygen plasma, performing plasma treatment for 60 seconds in this oxygen plasma, and ashing etching residues such as resist residues accompanying the etching process Remove.

See FIG.
Next, again, the via hole 60 is filled with Cu via the barrier film 61 made of TaN, and unnecessary portions are removed by CMP to form a Cu via 62.

Next, a substrate to be processed is mounted in the processing chamber 11, and the formic acid gas 63 vaporized by the vaporizer 18 from the organic gas jet shower head 16 is introduced so that the partial pressure of the formic acid gas 63 becomes 200 Pa, and the heater 20, the substrate temperature is set to 150 ° C., and the substrate to be processed is processed in a reduction time of 2 minutes in a state where the total pressure is 200 Torr. The remaining chemical solution components are exhausted and removed from the exhaust port 13 together with formic acid as copper formate.
Further, the copper oxide formed on the copper surface is reduced to metallic copper, and exhausted and removed from the exhaust port 13 together with CO ₂ and water vapor (H ₂ O) generated by the reduction reaction.

  Next, the second wiring insulating film 52 made of SiOC having a thickness of, for example, 250 nm and the SiCN film 53 having a thickness of, for example, 50 nm are sequentially deposited again using the plasma CVD method.

See FIG.
Next, a wiring groove 64 having a width reaching, for example, 0.12 μm is formed in the second wiring insulating film 52 again by plasma etching using a fluorocarbon-based etching gas.

Next, the substrate to be processed in which the wiring trench 64 is formed is again placed and fixed on the lower electrode 14 in the above-described processing chamber, and then 400 sccm of O ₂ is introduced from the gas inlet to 70 Pa. The substrate is heated to a substrate temperature of 80 ° C. by the heater 20 and 600 W of electric power is applied to generate oxygen plasma. The plasma treatment is performed in this oxygen plasma for 60 seconds, and etching residues such as resist residues accompanying the etching treatment Remove by ashing.

  Next, the wiring trench 64 is again filled with Cu through the barrier film 65 made of TaN, and unnecessary portions are removed by CMP to form the second Cu embedded wiring 66.

Next, the substrate is mounted in the processing chamber 11, the formic acid gas 67 vaporized by the vaporizer 18 from the organic gas jet shower head 16 is introduced so that the partial pressure of the formic acid gas 67 becomes 200 Pa, and the heater 20. Formic acid formed by formic oxidation reaction by processing the substrate to be processed in a reduction time of 2 minutes with a substrate temperature of 150 ° C. and a total pressure of 200 Torr, and Cu residue remaining on the surface of the second Cu embedded wiring 66 As the copper, the residual chemical component is exhausted and removed from the exhaust port 13 together with formic acid.
Further, the copper oxide formed on the copper surface is reduced to metallic copper, and exhausted and removed from the exhaust port 13 together with CO ₂ and water vapor (H ₂ O) generated by the reduction reaction.

  After that, depending on the number of multilayer wiring layers required, via formation insulating film deposition process, via hole formation process, ashing process, via formation process, cleaning / heat treatment process, interlayer insulation film deposition process, wiring trench The semiconductor device is completed by repeating the forming process, the ashing process, the buried wiring forming process, and the cleaning / heat treatment process.

In the fifth embodiment of the present invention, when the insulation resistance was confirmed by forming 20M (2 × 10 ⁷ ) via chains in the two-layer wiring structure having the same structure as the first embodiment, the leakage yield of the via chains was It was 100% and sufficient insulation resistance was obtained.

  Incidentally, after the above-described CMP process, when a two-layer wiring structure was produced without performing cleaning and heat treatment with formic acid gas, the leakage yield of the via chain having the same structure as in Example 1 was 80%, and the insulation resistance Decrease was observed.

Next, the single damascene process of the sixth embodiment of the present invention will be described. As the second wiring insulating film 52, an organic insulating material having a low dielectric constant such as polyaether (for example, registered trademark SiLK ^™ , Dow Chemical Co., Ltd.) is used. Along with this, the ashing after the wiring trench etching was performed using hydrogen plasma, and cleaning and heat treatment were performed using formic acid gas. Since the process and structure are exactly the same as those in the fifth embodiment, detailed description of the process is omitted.

In Example 6, in the cleaning / heat treatment process, the substrate is mounted in the processing chamber 11, and the formic acid gas vaporized by the vaporizer 18 from the organic gas ejection shower head 16 is adjusted to a partial pressure of formic acid gas of 200 Pa. Then, the substrate temperature is set to 150 ° C. by the heater 20 and the substrate to be processed is processed in a reduction time of 2 minutes in a state where the total pressure is 200 Torr, and the first Cu embedded wiring 47 or the second Cu embedded wiring 58 is processed. The Cu waste remaining on the surface of the metal is converted to copper formate formed by the formic acid reaction, and the remaining chemical component is exhausted and removed from the exhaust port 13 together with formic acid. Further, the copper oxide formed on the copper surface is reduced to metallic copper, and exhausted and removed from the exhaust port 13 together with CO ₂ and water vapor (H ₂ O) generated by the reduction reaction.

  The leakage yield in Example 6 was 100% as the leakage yield of the via chain having the same structure as that of Example 5 described above, and the same reliability as that of Example 5 was obtained.

  Incidentally, after the above-described CMP process, a two-layer wiring structure was prepared without performing formic acid cleaning and heat treatment, and the leakage yield of the via chain having the same structure as that of Example 6 was 87%. A decrease in physical constitution was observed.

  Next, the single damascene process of the seventh embodiment of the present invention will be described. In this example, porous silica is used as the second wiring insulating film 52 and the SiCN film thereon is omitted. The ashing process after the etching formation is lightly performed using oxygen plasma, and the cleaning and heat treatment are performed using acetic acid gas and methanol, which are softer than formic acid gas. Is exactly the same as in Example 5 above, and a detailed description of the process is omitted.

  Also in this case, the porous silica is spin-coated with a porous silica raw material (CNS) manufactured by Catalyst Kasei Kogyo Co., Ltd. on the substrate to be processed, and then fired (baked) and cured (cured). To form.

  In the cleaning / heat treatment process of Example 7, acetic acid gas and methanol vaporized by the vaporizer 18 from the organic gas jet shower head 16 are introduced into the processing chamber 11 so that the partial pressures thereof are 100 Pa. Then, the substrate temperature is set to 200 ° C. by the heater 20 and the substrate to be processed is processed in a processing time of 2 minutes in a state where the total pressure is 200 Torr, and the Cu remaining on the surface of the first Cu embedded wiring 47 or the second Cu embedded wiring 58 is left. Residual chemical liquid components are exhausted and removed from the exhaust port 13 together with acetic acid using scrap as copper acetate formed by an acetic acid reaction.

  At the same time, the copper oxide formed on the surface of the first Cu embedded wiring 47 or the second Cu embedded wiring 58 is reduced to metallic copper, and the chemical component that has entered the cavities of the NCS by the gasified methanol is simultaneously generated. Remove.

  The leakage yield in Example 7 was 100% as the leakage yield of the via chain having the same structure as that of Example 5 described above, and the insulation resistance equivalent to that of Example 5 was obtained.

  Incidentally, after the above-described CMP process, a double-layer wiring structure was prepared without performing cleaning and heat treatment with acetic acid and methanol gas. The leak yield of the via chain having the same structure as that of Example 7 was 30%. There was a significant decrease in insulation properties.

  Next, a single damascene process according to the eighth embodiment of the present invention will be described. The same SiOC film as the second wiring insulating film 52 is used as the via forming insulating film 50, and the other processes and structures are as follows. Since it is exactly the same as the fifth embodiment, detailed description of the process is omitted.

  The leak yield in Example 8 was 100% as the leak yield of the via chain having the same structure as that of Example 5 described above, and the insulation resistance equivalent to that of Example 5 was obtained.

  Incidentally, after the above-described CMP process, when a two-layer wiring structure was prepared without performing cleaning and heat treatment with formic acid, the leakage yield of the via chain having the same structure as in Example 8 was 40%, and the reliability There was a significant decline.

  The embodiments of the present invention have been described above. However, the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications can be made. The width of the wiring is arbitrary, and may be determined as appropriate according to the required degree of integration.

  In each of the above embodiments, the via and the embedded wiring are formed of Cu. However, the present invention is not limited to Cu, and is not limited to Cu, but also alloys such as Cu-Al and Cu-Si. Further, it is applied to metals other than Cu such as Al and Ag, or metal nitrides such as TiN and TaN, and W.

  In each of the above embodiments, formic acid or acetic acid is used as the carboxylic acid in the cleaning / heat treatment process after the CMP process, but is not limited to these carboxylic acids, such as propionic acid or butyric acid. Other carboxylic acids may be used.

  Further, in Example 3 and Example 7 described above, methanol is used as a part of the gas used in the cleaning / heat treatment process after the CMP process, but it is not limited to methanol. Other alcohols such as propyl alcohol may be used.

  Further, in each of the above embodiments, the plasma type and the organic gas are properly used according to the type of the interlayer insulating film to be used, but such a usage is not indispensable, and other plasma types and organic types are mutually used. It may be implemented by replacing with gas.

Further, it is merely an example in which the wiring insulating film and the via forming insulating film in each of the above embodiments are combined, and it goes without saying that it can be applied to an interlayer insulating film structure using other insulating materials. Instead, a SiN film or a SiOCN film may be used, or a SiO ₂ film or a SiOCN film may be used instead of the SiOC film.

  When the SiOCN film was cleaned and heat-treated in the same manner as in the example of the present invention, the relative dielectric constant after the treatment was about 2.9, and there was almost no change from the relative dielectric constant before the treatment. A slight decrease was observed.

  As a practical example of the present invention, a multilayer wiring structure of a highly integrated semiconductor device is typical, but the invention is not limited to a wiring structure in a semiconductor device, and a wiring connection structure of an optical device using a ferroelectric substance. It is also applicable.

It is explanatory drawing of the fundamental structure of this invention. It is a notional block diagram of the cleaning and heat treatment apparatus used for carrying out the present invention. It is explanatory drawing to the middle of the dual damascene process of Example 1 of this invention. It is explanatory drawing after FIG. 3 of the dual damascene process of Example 1 of this invention. It is explanatory drawing to the middle of the single damascene process of Example 5 of this invention. It is explanatory drawing to the middle after FIG. 5 of the single damascene process of Example 5 of this invention. It is explanatory drawing after FIG. 6 of the single damascene process of Example 5 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Lower layer wiring 2 Insulating film 3 Wiring groove hole 4 Embedded wiring 5 Organic gas 11 Processing chamber 12 Gas inlet 13 Exhaust port 14 Lower electrode 15 Ring-shaped upper electrode 16 Organic gas ejection shower head 17 For supplying organic gas Piping 18 Vaporizer 19 Storage tank 20 Heater 21 Substrate 31 P-type silicon substrate 32 Element isolation insulating film 33 Gate insulating film 34 Gate electrode 35 n-type extension region 36 Side wall 37 n-type source / drain region 38 Co silicide electrode 39 Co silicide electrode 40 SiO ₂ film 41 BPSG film 42 SiCN film 43 Barrier film 44 W plug 45 First wiring insulating film 46 Barrier film 47 First Cu buried wiring 48 Formic acid gas 49 SiCN film 50 Via forming insulating film 51 SiCN film 52 Second wiring insulating film 53 SiCN film 54 Wiring groove 55 Via hole 56 Barrier film 57 Cu via 58 Second Cu buried wiring 59 Formic acid gas 60 Via hole 61 Barrier film 62 Cu via 63 Formic acid gas 64 Groove for wiring 65 Barrier film 66 Second Cu buried wiring 67 Formic acid gas

Claims (4)

The method includes the step of cleaning the surface of the exposed portion of the embedded wiring with a gaseous organic gas after polishing the embedded wiring by polishing the conductor layer embedded in the wiring groove, A method of forming embedded wiring. 2. The embedded wiring forming method according to claim 1, wherein the organic gas contains carboxylic acid. 3. The method for forming a buried wiring according to claim 2, wherein the carboxylic acid is any one of formic acid, acetic acid, propionic acid and butyric acid. 2. The embedded wiring forming method according to claim 1, wherein the organic gas is an alcohol.

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