CN106783730B - Method for forming air gap/copper interconnection - Google Patents
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- CN106783730B CN106783730B CN201611234439.6A CN201611234439A CN106783730B CN 106783730 B CN106783730 B CN 106783730B CN 201611234439 A CN201611234439 A CN 201611234439A CN 106783730 B CN106783730 B CN 106783730B
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Abstract
A method for forming air gap/copper interconnection includes providing a semiconductor substrate, completing CMOS device front process on the semiconductor substrate, then forming a conventional first dielectric/copper interconnection structure on the semiconductor substrate; carrying out surface treatment on the conventional first dielectric/copper interconnection structure in an oxygen-containing atmosphere to form a layer of copper oxide on the surface of the copper interconnection line; etching a first medium in the middle of the copper interconnection line by using etching equipment; etching by adopting fluorine-based gas and oxygen-based gas in the process of etching the first medium, wherein the copper interconnection line is protected from being exposed in the etching gas atmosphere by copper oxide; reducing copper oxide on the surface of the copper interconnection line, namely converting the copper oxide on the surface of the copper interconnection line into metal copper again; removing residual photoresist by adopting wet-process liquid medicine and cleaning; a second dielectric is deposited to form an air gap/copper interconnect structure.
Description
Technical Field
The invention relates to the field of semiconductor processing and manufacturing, in particular to a method for forming an air gap/copper interconnection.
Background
With the development of moore's law, transistors have smaller feature line widths, higher integration density and stronger performance. For a Complementary Metal Oxide Semiconductor (CMOS) transistor, speed is an important index for characterizing its performance.
As is clear to those skilled in the art, the speed of CMOS is related to the delay of CMOS, which can be subdivided into the delay of the former device and the delay of the latter interconnect; also, as semiconductor process dimensions decrease, the impact of the CMOS delay of the latter interconnect lines becomes greater and greater, already becoming the dominant delay in advanced processes. The delay of the subsequent interconnect line is mainly determined by the resistance R of the interconnect line and the capacitance C (i.e., RC) between the interconnect lines.
In order to reduce the RC delay of the subsequent interconnect line, ic manufacturers have sought to reduce the resistance and capacitance between the interconnect lines, such as by using a lower resistivity copper line instead of an aluminum line and a lower dielectric constant low-k dielectric instead of a silicon dioxide dielectric.
For the latter, the dielectric between the interconnecting wires has been updated from SiO with several technological advances2→F dopedSiO2In the improvement process of (FSG) → BD I → BD II → BD III, the dielectric constant of the medium between the interconnecting wires is continuously reduced, thereby satisfying the requirement of reducing the subsequent interconnecting wireThe requirement of the connection RC.
As is well known, the relative permittivity of vacuum is 1, and the relative permittivity of air is also about 1, which is the most common medium of minimum relative permittivity. Therefore, the use of air in place of the conventional dielectric between interconnect lines has also been proposed, which is the air gap/copper interconnect structure technique.
The air gap formation method can be roughly classified into the following two categories:
the first kind, firstly, a normal medium/copper interconnection structure is formed by adopting a traditional process, then, the medium between copper interconnection lines is removed by an etching process, and finally, an air gap is formed by a chemical vapor deposition process;
in the second category, a sacrificial layer, such as a thermal degradable polymer, is used to remove the sacrificial layer after the copper interconnect structure is completed, thereby forming the air gap.
Currently, the first method is more process compatible for most integrated circuit manufacturing enterprises and is therefore more acceptable. The following is a brief description of the process of fabricating an air gap/copper interconnect structure using the first method in the prior art with reference to fig. 1-3.
Step S01: a conventional first dielectric 102/copper 104 interconnection structure is formed on a semiconductor substrate 101, and the process of this part is completely the same as that of the conventional CMOS process, and there is no additional process cost and risk (as shown in fig. 1), which is not described herein again;
step S02: removing the first dielectric between the copper interconnection wires, such as by using a dielectric etching process to remove a portion of the first dielectric to obtain the structure shown in fig. 2; however, the surface of the copper 104 is oxidized during the etching process, resulting in a certain thickness of copper oxide 105;
step S03: removing residual photoresist by adopting a subsequent cleaning liquid medicine and cleaning the silicon wafer; during cleaning, since the copper oxide 105 is easily corroded by the subsequent cleaning solution and the subsequent cleaning solution does not corrode the barrier layer 103, the barrier layer "ears" 103' are finally left, as shown in fig. 3.
Due to the presence of the barrier layer "ears" 103', this structure has a series of negative effects on subsequent processes and device performance, such as occurs when using chemical vapor deposition media:
firstly, the step coverage around the barrier layer "ear" 103' becomes poor;
② the barrier layer ears 103' have poor mechanical strength to cause collapse;
thirdly, the electric field intensity at the tip of the ear 103' of the barrier layer changes, and the like, which directly causes the performance deterioration of the CMOS transistor and the like.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a method for forming an air gap/copper interconnection, so as to solve the problem of transistor performance deterioration caused by the existence of a barrier layer 'ear', avoid the generation of the barrier layer 'ear', facilitate the deposition of a medium and the formation of an air gap by a chemical vapor deposition process and improve the transistor performance.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a method of forming an air gap/copper interconnect, comprising:
step S1: providing a semiconductor substrate, firstly completing the previous process of a CMOS device on the semiconductor substrate, and then continuously forming a next copper interconnection line, namely forming a conventional first medium/copper interconnection structure on the semiconductor substrate;
step S2: performing surface treatment on the conventional first dielectric/copper interconnection structure in an oxygen-containing atmosphere to form a layer of copper oxide on the surface of the copper interconnection line;
step S3: etching the first medium in the middle of the copper interconnection line by using etching equipment; etching by adopting fluorine-based gas and oxygen-based gas in the process of etching the first medium, wherein the copper interconnection line is protected from being exposed in the etching gas atmosphere by the copper oxide;
step S4: reducing the copper oxide on the surface of the copper interconnection line, namely converting the copper oxide on the surface of the copper interconnection line into metallic copper again;
step S5: removing residual photoresist by adopting wet-process liquid medicine and cleaning;
step S6: and depositing a second medium to form the air gap/copper interconnection structure.
Preferably, the step S1 specifically includes:
step S11: depositing a first dielectric layer on a semiconductor substrate;
step S12: forming a Damascus groove or a dual Damascus hole groove in the first dielectric layer by adopting a photoetching process;
step S13: respectively depositing a barrier layer material and a copper interconnection material;
step S14: and forming a barrier layer and a copper interconnection layer through a grinding process, namely forming a conventional first medium/copper interconnection structure on the semiconductor substrate.
Preferably, the first dielectric material in the conventional first dielectric/copper interconnect structure is one or more of silicon oxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, silicon nitride, and nitrogen-doped silicon carbide.
Preferably, the dielectric is a silicon carbide/carbon doped silicon oxide/silicon oxide multilayer stack structure doped with nitrogen.
Preferably, in step S2, a layer of copper oxide is formed on the surface of the copper interconnect line, wherein the thickness of the layer of copper oxide is controllable and uniform, and the thickness of the layer of copper oxide is 30 to 300 angstroms.
Preferably, in step S3, the first dielectric layer is etched by using a CF4/O2 mixed gas.
Preferably, in step S4, the reducing substance used for reducing the copper oxide byproduct on the surface of the copper wire is hydrogen gas and/or ammonia gas or plasma of hydrogen gas and/or ammonia gas.
Preferably, in step S5, the post-wet chemical solution for removing the residual photoresist is selected to have a higher etching rate for the residual photoresist than for the copper oxide.
Preferably, in step S6, the second dielectric layer is deposited by a chemical vapor deposition method or by a plasma enhanced chemical vapor deposition apparatus.
Preferably, the second dielectric layer is one or more of silicon oxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, silicon nitride and nitrogen-doped silicon carbide.
According to the technical scheme, the method for forming the air gap/copper interconnection structure comprises the steps of firstly forming a layer of copper oxide with uniform thickness on the surface of copper in a conventional medium/copper interconnection structure through a surface treatment technology, then converting the copper oxide on the surface of the copper into metal copper again by adopting a reducing substance after medium etching, and finally removing residual photoresist by adopting a subsequent wet method liquid medicine and cleaning, so that an ear structure of a barrier layer caused by the fact that the copper oxide is corroded by the subsequent wet method liquid medicine in the prior art is avoided, the subsequent medium deposition and the air gap formation are facilitated, and the performance of a transistor is improved.
Drawings
FIG. 1 is a typical schematic diagram of a prior art method for forming a conventional first dielectric/copper interconnect structure on a semiconductor substrate
FIG. 2 is a schematic diagram of a prior art structure after a first dielectric/copper interconnect structure is completed to remove the first dielectric between copper interconnect lines
FIG. 3 is a schematic diagram showing the structure of the barrier layer "ear" left after the post-cleaning step in the prior art
FIG. 4 is a schematic flow chart of a method for forming an air gap/copper interconnection according to the present invention
FIG. 5 is a cross-sectional view of the air gap/copper interconnect formed after step S1 is completed according to one embodiment of the present invention
FIG. 6 is a cross-sectional view of the air gap/copper interconnect formed after step S2 is completed according to one embodiment of the present invention
FIG. 7 is a cross-sectional view of the air gap/copper interconnect formed after step S3 is completed according to one embodiment of the present invention
Figure 8 is a cross-sectional view of the air gap/copper interconnect formed after step S3 is completed in one embodiment of the method of forming an air gap/copper interconnect of the present invention
Detailed Description
The following describes in detail embodiments of the present invention with reference to the drawings. It is understood that the invention is capable of modification in various forms and that the description and drawings are to be regarded as illustrative in nature, and not as restrictive.
A method of forming an air gap/copper interconnect according to the present invention will now be described in further detail by way of example with reference to figures 4-8. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 4, a flow chart of a preferred embodiment of a method of forming an air gap/copper interconnect according to the present invention is shown. In this embodiment, a method of forming an air gap/copper interconnect includes the steps of:
step S01: providing a semiconductor substrate, firstly completing the previous process of a CMOS device on the semiconductor substrate, and then continuously forming the next copper interconnection line, namely forming a conventional first dielectric/copper interconnection structure on the semiconductor substrate. Specifically, referring to fig. 5, fig. 5 is a schematic cross-sectional view of the air gap/copper interconnect formed after step S1 is completed according to an embodiment of the present invention.
As shown in the figure, in this step, a previous process of the CMOS device is completed on a substrate silicon wafer 301, and then a subsequent interconnect line is formed to form a conventional dielectric 302/copper interconnect 304 structure, where 303 is a barrier layer.
The specific steps of forming conventional pre-CMOS device structures on a wafer using a conventional CMOS process followed by copper interconnect process to form interconnect lines are described below with a 12-inch wafer silicon wafer as an alternative embodiment.
Specifically, in this embodiment, step S1 may include the following steps:
step S11: depositing a first dielectric layer 302 on a semiconductor substrate 301;
step S12: forming a Damascus groove or a dual Damascus hole groove in the first dielectric layer 302 by adopting a photoetching process;
step S13: respectively depositing a barrier layer material and a copper interconnection material;
step S14: the barrier layer 303 and the copper interconnect layer 304 are formed by a grinding process, i.e. a conventional first dielectric/copper interconnect structure is formed on the semiconductor substrate.
Preferably, the deposited conventional first dielectric 302 may be one or more of silicon oxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, silicon nitride, and nitrogen-doped silicon carbide, and in an embodiment of the present invention, the first dielectric 302 is a nitrogen-doped silicon carbide/carbon-doped silicon oxide/silicon oxide multilayer stack structure.
Step S2: and carrying out surface treatment on the conventional first dielectric/copper interconnection structure in an oxygen-containing atmosphere to form a layer of copper oxide on the surface of the copper interconnection line. Referring to fig. 6, fig. 6 is a schematic cross-sectional view of the air gap/copper interconnect formed after step S2 is completed according to an embodiment of the present invention.
As shown in FIG. 6, in the present embodiment, a conventional first dielectric/copper interconnect structure is subjected to a surface treatment in an oxygen-containing atmosphere to form a copper oxide 305 with a controllable and uniform thickness on the surface of the interconnect metal copper 304, preferably, the thickness of the copper oxide is 30-300 angstroms.
For example, in this embodiment, a conventional dielectric/copper interconnect structure is placed in a plasma chemical vapor deposition apparatus and treated with an oxygen plasma to provide a 100 angstrom thickness of copper oxide on the surface of the copper interconnect 304.
The copper oxide 305 is not readily etched by fluorine-containing gases, nor is the oxygen in the etching gas readily available to continue oxidizing the interconnect metal copper, and thus acts as a protective layer in subsequent processes.
Step S3: etching the first medium in the middle of the copper interconnection line by using etching equipment; and etching the first medium by adopting fluorine-based gas and oxygen-based gas, wherein the copper oxide protects the copper interconnection line from being exposed in the etching gas atmosphere. Referring to fig. 7, fig. 7 is a schematic cross-sectional view illustrating the formation of step S3 after the completion of step S3 according to an embodiment of the method of forming an air gap/copper interconnect.
Specifically, as shown in fig. 7, in the present embodiment, a photolithography and etching process may be used to remove the first dielectric 302 between the copper interconnect lines 304. During the etching of the first dielectric 302, fluorine-based gas and oxygen-based gas are used for etching, but since the surface of the copper interconnection line 304 has a layer of copper oxide 305 as a protective layer, only the first dielectric 302 to be removed is etched.
In this embodiment, CF4/O may be employed2The mixed gas etches the first dielectric layer 302, and the copper oxide 305 plays a role of an etching protection layer because the copper interconnect 304 has a layer of copper oxide 305 on the surface, which can prevent the metal copper 304 from being oxidized.
Step S4: the copper oxide on the surface of the copper interconnection line is reduced, namely the copper oxide on the surface of the copper interconnection line is converted into metallic copper again.
Specifically, referring to fig. 8, in the present embodiment, a reducing substance may be used to convert the copper oxide 305 on the copper surface into the metal copper 306 again, and preferably, the reducing substance is hydrogen gas, ammonia gas or plasma of hydrogen gas and ammonia gas.
In the embodiment, in the etching chamber, the oxide 305 of copper is reduced by hydrogen plasma and converted into metal copper again, and since the thickness of the oxide 305 of copper is known and uniform, the reduction process condition is convenient to set, and the process uniformity is improved.
Step S5: and removing the residual photoresist by adopting wet-process liquid medicine and cleaning.
Specifically, the photoresist remaining after etching is removed by adopting the subsequent wet method liquid medicine, the surface of the silicon wafer is cleaned, and the corrosion rate of the subsequent wet method liquid medicine to the remaining photoresist is far greater than the corrosion rate to the metal copper, so that the barrier layer 'ear' can not be formed.
Step S6: and depositing a second dielectric material to form the air gap/copper interconnection structure.
Specifically, the second dielectric layer may be deposited by a chemical vapor deposition method to form the air gap/copper interconnect structure. The second dielectric layer can be one or more of silicon oxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, silicon nitride and nitrogen-doped silicon carbide, and air gaps are formed between the copper interconnection lines. In this embodiment, a plasma enhanced chemical vapor deposition apparatus may be used to sequentially deposit nitrogen-doped silicon carbide and carbon-doped silicon oxide, and since the aspect ratio of the trench between the copper interconnects 304 is high, an air gap may be automatically formed between the metal copper interconnects when depositing the second dielectric material, thereby forming an air gap/copper interconnect structure.
In summary, in the method for forming an air gap/copper interconnection provided by the present invention, a layer of copper oxide with controllable and uniform thickness is formed on the copper surface in a conventional dielectric/copper interconnection structure by using a surface treatment technology, and then the copper oxide on the copper surface is converted into metal copper again by using a reducing substance after the dielectric etching, so that the etching rate of the subsequent wet process chemical solution is greatly reduced, the process controllability and consistency are improved, the formation of a barrier layer "ear" structure is avoided, and the performance of a transistor device can be effectively improved.
The above description is only an embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method of forming an air gap/copper interconnect, comprising:
step S1: providing a semiconductor substrate, firstly completing the previous process of a CMOS device on the semiconductor substrate, and then continuously forming a next copper interconnection line, thereby forming a first medium/copper interconnection structure on the semiconductor substrate;
step S2: carrying out surface treatment on the first dielectric/copper interconnection structure in an oxygen-containing atmosphere to form a layer of copper oxide on the surface of the copper interconnection line;
step S3: etching the first medium in the middle of the copper interconnection line by using etching equipment; etching by adopting fluorine-based gas and oxygen-based gas in the process of etching the first medium, wherein the copper interconnection line is protected from being exposed in the etching gas atmosphere by the copper oxide;
step S4: reducing the copper oxide on the surface of the copper interconnection line, so that the copper oxide on the surface of the copper interconnection line is converted into metal copper again;
step S5: removing residual photoresist by adopting wet-process liquid medicine and cleaning;
step S6: and depositing a second medium to form the air gap/copper interconnection structure.
2. The method for forming an air gap/copper interconnect as claimed in claim 1, wherein said step S1 specifically comprises:
step S11: depositing a first dielectric layer on a semiconductor substrate;
step S12: forming a Damascus groove or a dual Damascus hole groove in the first dielectric layer by adopting a photoetching process;
step S13: respectively depositing a barrier layer material and a copper interconnection material;
step S14: and forming a barrier layer and a copper interconnection layer through a grinding process, thereby forming a first medium/copper interconnection structure on the semiconductor substrate.
3. The method of claim 1 or 2, wherein the first dielectric material in the first dielectric/copper interconnect structure is one or more of silicon oxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, silicon nitride, and nitrogen-doped silicon carbide.
4. A method of forming an air gap/copper interconnect as claimed in claim 3 wherein said first dielectric is a nitrogen doped silicon carbide/carbon doped silicon oxide/silicon oxide multilayer stack.
5. The method of claim 1, wherein in step S2, a layer of copper oxide with a controllable and uniform thickness is formed on the surface of the copper interconnect line, and the thickness of the copper oxide is 30-300 angstroms.
6. The method of claim 1, wherein in step S3, CF is used4/O2And etching the first dielectric layer by using the mixed gas.
7. The method of claim 1, wherein in step S4, the reducing substance used for reducing the copper oxide on the surface of the copper interconnect line is hydrogen and/or ammonia gas or a plasma of hydrogen and/or ammonia gas.
8. The method for forming an air gap/copper interconnect as claimed in claim 1, wherein in step S5, the wet chemical solution for removing the residual photoresist has a higher etching rate to the residual photoresist than to the copper oxide.
9. The method of claim 1, wherein in step S6, the second dielectric layer is deposited by a chemical vapor deposition apparatus.
10. The method of any of claims 1 or 9, wherein the second dielectric layer is one or more of silicon oxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, silicon nitride, and nitrogen-doped silicon carbide.
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| JPH04273437A (en) * | 1991-02-28 | 1992-09-29 | Sony Corp | Dry etching method |
| JP3137087B2 (en) * | 1998-08-31 | 2001-02-19 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| TWI227043B (en) * | 2000-09-01 | 2005-01-21 | Koninkl Philips Electronics Nv | Method of manufacturing a semiconductor device |
| US7371427B2 (en) * | 2003-05-20 | 2008-05-13 | Applied Materials, Inc. | Reduction of hillocks prior to dielectric barrier deposition in Cu damascene |
| CN101123215A (en) * | 2006-08-11 | 2008-02-13 | 联华电子股份有限公司 | Copper enchasing technology |
| JP2009194286A (en) * | 2008-02-18 | 2009-08-27 | Panasonic Corp | Semiconductor device and method of manufacturing the same |
| TWI392056B (en) * | 2008-03-12 | 2013-04-01 | Tokyo Electron Ltd | Semiconductor device and method of manufacturing same |
| CN102969273A (en) * | 2012-10-25 | 2013-03-13 | 上海集成电路研发中心有限公司 | Forming method of copper Damascus interconnection structure with air gaps |
| CN103633021B (en) * | 2013-12-02 | 2015-12-30 | 上海华力微电子有限公司 | A kind of method preparing air gap copper interconnection structure |
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Effective date of registration: 20210225 Address after: No. 497, Gauss Road, Zhangjiang, Pudong New Area, Shanghai, 201210 Patentee after: SHANGHAI IC R&D CENTER Co.,Ltd. Patentee after: Semiconductor Manufacturing International (Shanghai) Corp. Address before: 201210 No.497 Gaosi Road, Zhangjiang, Pudong New Area, Shanghai Patentee before: SHANGHAI IC R&D CENTER Co.,Ltd. |