JP2007221656A - High frequency variable gain amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high frequency variable gain amplifier capable of extending a dynamic range of received power by switching the gain in multi-stages. <P>SOLUTION: The high frequency variable gain amplifier can switch the gain in three stages: differential amplifiers 50, 51 are set to an operating state and gain changeover switches 30a, 30b are set to a nonconductive state; while the differential amplifier 50 is set to an operation stop state and the differential amplifier 51 is set to the operating state respectively and the gain changeover switches 30a, 30b are set to a conductive state, path switches 31a, 31b of gain switching paths 310a, 310b are set to the conductive state and path switches 32a, 32b of gain switching paths 311a, 311b are set to the nonconductive state; and conversely, the path switches 31a, 31b of the gain switching paths 310a, 310b are set to the nonconductive state and the path switches 32a, 32b of the gain switching paths 311a, 311b are set to the conductive state. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a high frequency variable gain amplifier.

  The first-stage amplifier circuit in a receiving device of a wireless communication system typified by a mobile phone requires low noise and high gain characteristics when receiving weak signals, and low distortion characteristics and low characteristics when receiving large signals. Gain characteristics are required. In particular, in recent mobile communications, the electric field strength at the time of reception varies greatly depending on the distance between the base station and the terminal, so a large dynamic range is required for the receiving device. A low noise amplifier requires a gain control function. As an amplifier having such a gain control function, for example, an amplifier disclosed in Patent Document 1 is known. Hereinafter, in order to facilitate understanding of the present invention, a brief description will be given with reference to FIG.

  FIG. 10 is a circuit diagram showing a configuration example of a conventional high-frequency variable gain amplifier. In FIG. 10, an input terminal 601 is connected to an input terminal of an amplifier 603 and one end of a strip line 604a via a DC cut capacitor 602a. An output terminal 605 is connected to the output terminal of the amplifier 603 via a DC cut capacitor 602b, and one end of a strip line 604b is connected to the output terminal 607 via a DC cut capacitor 602c, and a power supply terminal 607 is connected via a choke coil 606. Is connected. A bypass capacitor 608 is provided between the power supply terminal 607 and the ground potential (ground).

  The other end of the strip line 604a is connected to one signal electrode of the switch 609a, the other end of the strip line 604b is connected to one signal electrode of the switch 609b, and between the other signal electrodes of the switches 609a and 609b. Are connected via a resistance element 610. The control electrode of the switch 609a is connected to the voltage control terminal 611a, and the control electrode of the switch 609b is connected to the voltage control terminal 611b.

  The paths of the strip line 604a, the switch 609a, the resistance element 610, the switch 609b, and the strip line 604c constitute a signal bypass circuit.

  In the above configuration, when the reception power of the high-frequency signal received by the external reception processing system is lower than a predetermined value, substantially 0 V is applied to the voltage control terminals 611a and 611b to turn off the switches 609a and 609b. Then, the amplifier 603 is set to the ON operation state. As a result, a high frequency signal input from the external receiving system to the input terminal 601 is input to the amplifier 603 via the DC cut capacitor 602a and amplified with high gain, and is output from the output terminal 605 via the DC cut capacitor 602b. Is done.

  On the other hand, when the reception power of the high frequency signal received by the external reception processing system is higher than a predetermined value, the same voltage as that of the power supply terminal 607 is applied to the voltage control terminals 611a and 611b so that the switches 609a and 609b are in a conductive state. And the amplifier 603 is set to the OFF operation state. As a result, the high-frequency signal input from the external receiving system to the input terminal 601 enters the signal bypass circuit via the DC cut capacitor 602a, is attenuated by a predetermined amount by the resistance element 610, and is then applied to the DC cut capacitor 602b. Is output from the output terminal 605 via

  As described above, in the conventional high frequency variable gain amplifier, the set gain is switched between the high gain and the low gain in accordance with the received power of the high frequency signal.

JP 2003-163555 A (High Frequency Variable Gain Amplifier)

  However, the conventional high-frequency variable gain amplifier has a problem that it is difficult to widen the dynamic range of received power because there are only two gains that can be set: high gain and low gain.

  The present invention has been made in view of the above, and an object of the present invention is to obtain a high-frequency variable gain amplifier that can widen the dynamic range of received power by switching gains in multiple stages.

  Another object of the present invention is to obtain the above-described high-frequency variable gain amplifier that can switch the gain in multiple stages without greatly changing the input impedance.

  Another object of the present invention is to obtain the above-described high-frequency variable gain amplifier that can be miniaturized with a small number of elements.

  Another object of the present invention is to obtain the above-described high-frequency variable gain amplifier that can operate with a low power supply voltage and a low current.

  In order to achieve the above-described object, a high-frequency variable gain amplifier according to the present invention includes two positive-phase input / output terminals and two negative-phase input / output terminals connected via corresponding DC cut capacitors. The differential amplifier and the same number N (N ≧ 2) gain switching paths arranged symmetrically on the positive phase side and the negative phase side of the two differential amplifiers, and each gain switching path is a path The first and second gain switching path groups configured by a series circuit of a switch for attenuation and an attenuating resistance element, and a path for applying a gain applying process to an input high-frequency signal and leading to the output terminal are described above. Control means for selectively controlling a path passing through two differential amplifiers and a path passing through each one gain switching path arranged at a symmetrical position in the first and second gain switching path groups, The first and second gain switching path groups are: One end of the first gain switching path group is connected to the positive phase side input terminal of one of the differential amplifiers via the first switching switch, and the other end is connected to the positive phase side of the other differential amplifier. An input terminal is connected via a first DC cut capacitor, and one end of the second gain switching path group is connected to a negative phase side input terminal of one of the differential amplifiers via a second gain switching switch. The other end is connected to the opposite-phase side input end of the other differential amplifier via a second DC cut capacitor, and the control means non-conducts the first and second gain switching switches. When controlling to the state, the two differential amplifiers are both controlled to be in an amplifying operation enabled state, and when controlling the first and second gain switching switches to the conductive state, the two differential amplifiers are controlled. Among them, the differential amplifier in the input stage is deactivated and the differential in the output stage is increased. And control each of the path switches in each of the gain switching paths arranged at symmetrical positions in the first and second gain switching path groups to be in a conductive state. It is characterized by doing.

  According to the present invention, for example, if two gain switching paths are arranged in parallel on the positive phase side of two differential amplifiers, and two gain switching paths are arranged in parallel on the opposite phase side. When the two differential amplifiers are set to the operating state and the first and second gain switching switches are set to the non-conductive state, the input stage differential amplifier is set to the operation stop state, and the output stage differential amplifier is set to the operating state. With each setting, with the first and second gain switching switches set to the conductive state, the path switch in one of the symmetrical gain switching paths is set to the conductive state and is in the symmetrical position Contrary to the case where the path switch for the other gain switching path is set to the non-conductive state, conversely, the path switch for the one gain switching path at the symmetrical position is set to the non-conductive state, and the symmetrical position is set. For the other gain switching route It can be switched in three stages as configuring switch conductive. Thus, the dynamic range of the high frequency received power can be expanded as compared with the conventional example.

  According to the present invention, there is an effect that the dynamic range of the received power can be expanded by switching the gain to multiple stages.

  Exemplary embodiments of a high frequency variable gain amplifier according to the present invention will be explained below in detail with reference to the drawings.

Embodiment 1 FIG.
1 is a circuit diagram showing a configuration of a high-frequency variable gain amplifier according to Embodiment 1 of the present invention. In the high-frequency variable gain amplifier shown in FIG. 1, two differential amplifiers 50 and 51 are arranged in this order between a pair of input terminals 1a and 1b and a pair of output terminals 2a and 2b. The differential amplifiers 50 and 51 have the same configuration, for example, as shown in FIG. FIG. 2 will be described later. In the first embodiment and each of the embodiments described below, “a” and “b” attached to the reference numerals are the same content or arranged symmetrically on the positive phase side and the reverse phase side in the differential configuration. It is attached to the circuit element of the same ability.

  That is, as shown in FIG. 1, the positive phase side input terminal of the differential amplifier 50 is connected to the input terminal 1a, and the negative phase side input terminal of the differential amplifier 50 is connected to the input terminal 1b. The output terminal 2a is connected to the positive phase side output terminal of the differential amplifier 51, and the output terminal 2b is connected to the negative phase side output terminal of the differential amplifier 51. The positive phase side output terminal of the differential amplifier 50 is connected to the positive phase side input terminal of the differential amplifier 51 via the direct current cut capacitor 40a, and the negative phase side output terminal of the differential amplifier 50 is connected to the direct current cut capacitor 40b. To the negative phase side input terminal of the differential amplifier 51.

  Note that feed resistance elements 10 a and 10 b are connected in series between both input ends of the differential amplifier 50, and the series connection ends of the feed resistance elements 10 a and 10 b are connected to the bias terminal 3. Further, feed resistance elements 11 a and 11 b are connected in series between both input terminals of the differential amplifier 51, and the series connection terminals of the feed resistance elements 11 a and 11 b are connected to the bias terminal 4.

  The gain switching paths 310a and 311a constituting the first gain switching path group are arranged in parallel to the positive phase side input terminals of the two differential amplifiers 50 and 51, and the negative phase side input terminals are connected to the negative phase side input terminals. The gain switching paths 310b and 311b constituting the second gain switching path group are arranged in parallel.

  That is, one end of each of the two gain switching paths 310a and 311a is connected in parallel to the positive phase side input terminal of the differential amplifier 50 via a gain switching switch (first gain switching switch) 30a. The other ends of the two gain switching paths 310a and 311a are connected in parallel to the positive phase side input terminal of the dynamic amplifier 51 via a DC cut capacitor (first DC cut capacitor) 41a. The gain switching switch 30a is an NMOS transistor, for example, and its gate electrode is connected to the voltage control terminal 300a.

  The two gain switching paths 310a and 311a are respectively constituted by series circuits of path switches 31a and 32a and attenuation resistance elements 12a and 13a. The path switches 31a and 32a are NMOS transistors, for example, and their gate electrodes are connected to voltage control terminals 301a and 302a.

  Similarly, one end of each of the two gain switching paths 310b and 311b is connected in parallel to the opposite phase side input terminal of the differential amplifier 50 via a gain switching switch (second gain switching switch) 30b. The other ends of the two gain switching paths 310b and 311b are connected in parallel to the opposite phase side input terminal of the differential amplifier 51 via a DC cut capacitor (second DC cut capacitor) 41b. The gain switching switch 30b is an NMOS transistor, for example, and its gate electrode is connected to the voltage control terminal 300b.

  The two gain switching paths 310b and 311b are respectively constituted by series circuits of path switches 31b and 32b and attenuation resistance elements 12b and 13b. Each of the path switches 31b and 32b is, for example, an NMOS transistor, and its gate electrode is connected to the voltage control terminals 301b and 302b.

  Although the control means is not shown, according to the first embodiment, according to the received power of the high frequency signal in the external reception processing system, in the first embodiment, a “high gain state”, “medium gain state”, and “low gain state” The differential amplifier 51 in the output stage can perform an amplification operation in any state so that the corresponding gain application processing can be performed by switching the gain in three stages, and the amplification operation is performed in the differential amplifier 50 in the input stage. In this case, each switch is controlled to be conductive / non-conductive.

  Here, the “high gain state” corresponds to a case where the high-frequency received power is in a power state lower than the predetermined power to the extent that distortion is not caused by the amplification processing in the differential amplifier 50. The “medium gain state” corresponds to a case where the high-frequency received power is in a power state higher than a predetermined power to such an extent that distortion is caused by amplification processing in the differential amplifier 50. The “low gain state” corresponds to a case where the high frequency received power is in a power state higher than the predetermined power to such an extent that distortion larger than the above is generated in the amplification processing in the differential amplifier 50.

  In the gain switching paths 310a and 310b, the path switches 31a and 31b have the same capability (size), and the attenuation resistance elements 12a and 12b have the same value. In the gain switching paths 311a and 311b, the path switches 32a and 32b have the same capability (size), and the attenuation resistance elements 13a and 13b have the same value. Then, between the gain switching paths 310a and 310b and the gain switching paths 311a and 311b, the path switch capability (size) and the resistance value of the attenuation resistance element are set so that a desired gain switching amount is obtained. There is a difference. That is, if the gain switching paths 310a and 310b are for the “medium gain state” and the gain switching paths 311a and 311b are for the “low gain state”, the capability (size) of the path switch is, for example, “Route switches 32a and 32b” <“Route switches 31a and 31b”. The resistance value of the attenuating resistor element is “attenuating resistor elements 13a and 13b”> “attenuating resistor elements 12a and 12b”. Hereinafter, the operation of the control means will be specifically described.

  First, when the reception power of the high-frequency signal in the external reception processing system is in the “high gain state”, the differential amplifier 50 is set in the amplification operation enabled state, and the ground potential is almost set to each of the voltage control terminals 300a and 300b. (0V) is applied to set both gain switching switches 30a and 30b to the non-conductive state. Further, the voltage control terminals 301a, 301b, 302a, and 302b are also supplied with a substantially ground potential (0 V) to set the path switches 31a, 31b, 32a, and 32b to the non-conductive state.

  That is, the high frequency signal input to the input terminals 1a and 1b in the “high gain state” is directed to the differential amplifier 50 and the gain switching switches 30a and 30b. Among them, most of the high-frequency signals directed to the gain switching switches 30a and 30b are reflected by the gain switching switches 30a and 30b and input to the differential amplifier 50, and the amplified high-frequency signals are DC cut capacitors 40a and 40b. To the differential amplifier 51. At this time, in the gain switching paths 310a, 310b, 311a, and 311b, the path switches 31a, 31b, 32a, and 32b are in a non-conducting state, so that the output high-frequency signal of the differential amplifier 50 is directed to these paths. The high frequency signal is almost reflected and input to the differential amplifier 51. That is, the output high frequency signal of the differential amplifier 50 is input to the differential amplifier 51 without being attenuated. The high frequency signal amplified by the differential amplifier 51 is output from the output terminals 2a and 2b to a subsequent processing system.

  Next, when the reception power of the high-frequency signal in the external reception processing system is “medium gain state”, the differential amplifier 50 is set to the operation stop state, and the power supply potential is applied to each of the voltage control terminals 300a and 300b. The gain switching switches 30a and 30b are both set to the conductive state. Then, among the gain switching paths 310a and 310b and the gain switching paths 311a and 311b, for example, a power supply potential is applied to each of the voltage control terminals 301a and 301b in the gain switching paths 310a and 310b to switch the path switches 31a and 31b. 31b is set to a conductive state, and substantially ground potential (0V) is applied to each of the voltage control terminals 302a and 302b in the gain switching paths 311a and 311b to set both the path switches 32a and 32b to a non-conductive state.

  That is, the high-frequency signal input to the input terminals 1a and 1b in the “medium gain state” is the path from the gain switching switches 30a and 30b to the gain switching paths 310a and 310b because the differential amplifier 50 is in an operation stop state. Are input to the attenuating resistance elements 12a and 12b through the switches 31a and 31b, are subjected to a predetermined attenuation process, are input to the differential amplifier 51 through the DC cut capacitors 41a and 41b, and are amplified. The output terminal 2a , 2b to the subsequent processing system.

  Further, when the reception power of the high frequency signal in the external reception processing system is in the “low gain state”, the differential amplifier 50 is stopped and a power supply potential is applied to each of the voltage control terminals 300a and 300b to gain. Both switching switches 30a and 30b are set to a conductive state. This time, a power supply potential is applied to each of the voltage control terminals 302a and 302b in the gain switching paths 311a and 311b to set both the path switches 32a and 32b to the conductive state, and the voltages in the gain switching paths 310a and 310b are set. A ground potential (0 V) is applied to each of the control terminals 301a and 301b to set both the path switches 31a and 31b to a non-conductive state.

  That is, the high-frequency signal input to the input terminals 1a and 1b in the “low gain state” is the path from the gain switching switches 30a and 30b to the gain switching paths 311a and 311b because the differential amplifier 50 is in an operation stop state. Are input to the attenuating resistance elements 13a and 13b through the switches 32a and 32b, subjected to a predetermined attenuation process, input to the differential amplifier 51 via the DC cut capacitors 41a and 41b, and amplified, and then output to the output terminal 2a. , 2b to the subsequent processing system.

  Here, the resistance values of the feed resistance elements 10a, 10b, 11a, and 11b are large enough not to attenuate the high-frequency differential signal so much. In addition, the attenuating resistor element for the medium gain state (in the above example, the attenuating resistor elements 12a and 12b) and the attenuating resistor element for the low gain state (in the above example, the attenuating resistor elements 13a and 13b are Impedance matching is achieved by adjusting resistance values, element lengths and widths so that gains corresponding to the respective powers can be applied.

  Next, FIG. 2 is a circuit diagram showing a configuration example of the differential amplifiers 50 and 51. In FIG. 2, the drain electrodes of the amplifying NMOS transistors 513 a and 513 b are connected to the power input terminal 506 via load inductors 516 a and 516 b, and the drain electrode of the switching NMOS transistor 515 is connected via a feed resistance element 519. It is connected. The output terminals 502a and 502b are connected to connection terminals of the load inductors 516a and 516b and the drain electrodes of the amplification NMOS transistors 513a and 513b. A voltage control terminal 505 is connected to the gate electrode of the switching NMOS transistor 515.

  The gate electrodes of the amplification NMOS transistors 513a and 513b are connected in common, the source electrode of the switch NMOS transistor 515 is connected to the connection line, and the switch NMOS is connected between the connection line and the ground potential (ground). A parallel circuit of a transistor 514 and a bypass capacitor 518 is arranged. A voltage control terminal 504 is connected to the gate electrode of the switching NMOS transistor 514.

  The source electrodes of the amplification NMOS transistors 513a and 513b are connected to the drain electrodes of the amplification NMOS transistors 512a and 512b. The gate electrodes of the amplification NMOS transistors 512a and 512b are connected to the input terminals 501a and 501b, and the source electrodes of the amplification NMOS transistors 512a and 512b are connected via the source inductor 517. Further, constant current NMOS transistors 511a and 511b are arranged between the source electrodes of the amplification NMOS transistors 512a and 512b and the ground potential (ground). Bias terminals 503a and 503b are connected to the gate electrodes of the constant current NMOS transistors 511a and 511b.

  The operation will be described. First, in the operation state in which the high-frequency differential signal input to the input terminals 501a and 501b is amplified, a voltage of about 0.7 V is applied to the bias terminals 503a and 503b, and the constant current NMOS transistors 511a and 511b are applied. A state in which a desired current flows is set, and in the amplifying NMOS transistors 512a and 512b, a voltage about 0.7V higher than the source electrode is applied from the bias terminals 3 and 4 shown in FIG. To.

  At this time, approximately 0 V is applied to the voltage control terminal 504 to set the switching NMOS transistor 514 to a non-conductive state, and approximately the same voltage as the power supply voltage input to the power input terminal 506 is applied to the voltage control terminal 505. The switching NMOS transistor 515 is set to a conductive state. That is, the amplifying NMOS transistors 513a and 513b are electrically connected to the gate electrode through the feed resistor 519 and are electrically connected to each other, and are grounded at a high frequency through the bypass capacitor 518. It is in the state.

  Thus, the high-frequency differential signals input from the input terminals 501a and 501b are amplified by the amplification NMOS transistors 512a and 512b, and output from the output terminals 502a and 502b through the amplification NMOS transistors 513a and 513b. The differential amplifier 51 shown in FIG. 1 is always controlled in such an operating state. On the other hand, the differential amplifier 50 is controlled to such an operation state when in the “high gain state”.

  On the other hand, when the high-frequency differential signal input to the input terminals 501a and 501b is in an operation stop state where the high-frequency differential signals are not amplified, the amplifying NMOS transistors 512a and 512b have the bias terminals 3 and 4 shown in FIG. In this state, a voltage higher than the source electrode by about 0.7V is applied to the gate electrode, but approximately 0V is applied to the bias terminals 503a and 503b to turn off the constant current NMOS transistors 511a and 511b. Set.

  Then, substantially the same voltage as the power supply voltage is applied to the voltage control terminal 504 to set the switching NMOS transistor 514 to the conducting state, and approximately 0 V is applied to the voltage control terminal 505 to bring the switching NMOS transistor 515 into the non-conducting state. Set. That is, the amplification NMOS transistors 513a and 513b are brought into a non-conducting state because approximately 0 V is applied to their gate electrodes.

  As a result, even if a high-frequency differential signal is input from the input terminals 501a and 501b, the constant current NMOS transistors 511a and 511b are in a non-conductive state, and the flowing current is approximately 0A. The amplification NMOS transistors 513a and 513b are also non-conductive. That is, no current flows through the amplification NMOS transistors 512a and 512b, no amplification operation is performed, and no high-frequency differential signal is output from the output terminals 502a and 502b. The differential amplifier 50 shown in FIG. 1 is controlled to such an operation stop state in the “medium gain state” and the “low gain state”.

  As described above, the amplification NMOS transistors 512a and 512b to which the high-frequency differential signal is input are shown in FIG. 1 in both the “operation state” in which the differential amplifier performs amplification and the “operation stop state” in which amplification is not performed. In this state, a voltage about 0.7 V higher than the source electrode is applied from the bias terminal 3 to the gate electrode of the differential amplifier 50 in conjunction with the gain switching of the high-frequency variable gain amplifier. "And" operation stop state ", there is an effect that the input impedance of the input terminals 501a and 501b (input terminals 1a and 1b in FIG. 1) does not change so much. This indicates that the feed resistance elements 11a and 11b and the bias terminal 4 are not necessarily provided in the differential amplifier 51 that is always in the “operating state” in FIG.

  As described above, according to the first embodiment, since the variable gain of the high-frequency variable gain amplifier can be switched in three stages, an effect that a wider dynamic range than that of the conventional example can be realized.

  At this time, when the high-frequency received power is large, the input stage differential amplifier is stopped, the high-frequency signal power is attenuated through the path having the desired attenuation amount, and is input to the output stage differential amplifier. The differential amplifier is not required to have high saturation characteristics. Therefore, it is possible to realize a high-frequency variable gain amplifier that can operate with a low power supply voltage and a low current.

  Further, in the gain switching path, in the conventional example, the path switch is arranged on both sides of the attenuation resistance element. However, in the first embodiment, the path switch is arranged only on one side of the attenuation resistance element. As a result, the number of path switches can be reduced and the circuit can be reduced in size.

  In addition, the input impedance of the differential amplifier in the input stage can be set so that it does not change much between the “operating state” and the “operating stopped state”, so that the “operating state” and “operating stopped state” are linked with the gain switching. Even if it is switched to "," the effect that a high-frequency variable gain amplifier whose input impedance does not change much can be realized.

Embodiment 2. FIG.
FIG. 3 is a circuit diagram showing a configuration of a high-frequency variable gain amplifier according to Embodiment 2 of the present invention. In FIG. 3, the same reference numerals are given to components that are the same as or equivalent to the components shown in FIG. 1 (Embodiment 1). Here, the description will be focused on the portion related to the second embodiment.

  As shown in FIG. 3, in the high frequency variable gain amplifier according to the second embodiment, the gain shown in FIG. 1 (Embodiment 1) is gained with respect to the positive phase side input terminals of the differential amplifiers 50 and 51. A switching path 312a is added in parallel to the gain switching paths 310a and 311a. Further, a gain switching path 312b is added in parallel to the gain switching paths 310b and 311b with respect to the respective negative phase side input terminals of the differential amplifiers 50 and 51. In this configuration, the entire gain switching paths 310a, 311a, 312a constitute a first gain switching path group, and the entire gain switching paths 310b, 311b, 312b constitute a second gain switching path group. is doing.

  The gain switching path 312a is configured by a series circuit of a path switch 33a and an attenuation resistance element 14a. The gain switching path 312b includes a series circuit of a path switch 33b and an attenuation resistance element 14b. The path switches 33a and 33b are, for example, NMOS transistors and have the same capability (size), and their gate electrodes are connected to the voltage control terminals 303a and 303b. Further, the resistance values of the attenuating resistance elements 14a and 14b are equal. The attenuation resistance elements 14a and 14b are impedance matched by adjusting the resistance value, the element length, and the width so that a gain can be applied corresponding to the power to be handled.

  According to this configuration, when the differential amplifier 50 is brought into the operation stop state, the voltage control terminals 300a, 300b, 303a, and 303b are applied with a voltage substantially the same as the power supply voltage of the differential amplifiers 50 and 51 to change the gain. The switches 30a and 30b and the path switches 33a and 33b are set in a conductive state, and substantially 0 V is applied to the voltage control terminals 301a, 301b, 302a and 302b to make the path switches 31a, 31b, 32a and 32b non-conductive. By setting the conductive state, it is possible to cope with a larger received power than the “low gain state” described in the first embodiment using the gain switching paths 312a and 312b.

  As described above, according to the second embodiment, the number of variable gain switching stages that can be set can be increased by one as compared with the first embodiment, and a wider dynamic range can be realized. In the second embodiment, an example in which one gain switching path to be symmetrically arranged is added. However, since it can be easily increased by the same procedure, a high frequency variable gain having a wide dynamic range having an arbitrary number of switching stages. An amplifier is easily obtained.

Embodiment 3 FIG.
4 is a circuit diagram showing a configuration of a high-frequency variable gain amplifier according to Embodiment 3 of the present invention. In FIG. 4, the same or similar components as those shown in FIG. 1 (Embodiment 1) are denoted by the same reference numerals. Here, the description will be focused on the portion related to the third embodiment.

  As shown in FIG. 4, in the high frequency variable gain amplifier according to the third embodiment, in the configuration shown in FIG. 1 (the first embodiment), the positive phase side input terminal of the differential amplifier 50 and the gain switching switch 30a. A DC cut capacitor 42a is interposed therebetween, and a DC cut capacitor 42b is interposed between the negative phase side input terminal of the differential amplifier 50 and the gain switching switch 30b.

  A grounding resistance element 15a is provided between the connection end of the gain switching switch 30a and the DC cut capacitor 42a and the ground potential, and the connection end of the gain switching switch 30b and the DC cut capacitor 42b is connected to the ground potential. Between them, a grounding resistance element 15b is provided. Further, a grounding resistance element 16a is provided between the connection end of the gain switching switch 30a and the gain switching paths 310a and 311a and the ground potential, and the gain switching switch 30b and the gain switching paths 310b and 311b are connected to each other. A grounding resistance element 16b is provided between the connection end and the ground potential. Furthermore, a grounding resistance element 17a is provided between the connection end of the gain switching paths 310a and 311a and the DC cut capacitor 41a and the ground potential, and the connection end of the gain switching paths 310b and 311b and the DC cut capacitor 41b. And a grounding potential is provided with a grounding resistance element 17b.

  According to this configuration, the source and drain electrodes of the gain switching switches 30a and 30b are grounded via the grounding resistance elements 15a, 15b, 16a and 16b. The source and drain electrodes of the path switches 31a, 31b, 32a, 32b are grounded via the grounding resistance elements 16a, 16b, 17a, 17b.

  Therefore, according to the third embodiment, even if the DC cut capacitors 42a and 42b are interposed to cut the DC component flowing into the gain switching paths 310a, 311a, 310b and 311b, the gain switching paths 310a, 311a and 310b are interposed. , 311b can be prevented from floating, and a stable gain application operation can be performed.

  In the third embodiment (FIG. 4), the example of application to the first embodiment (FIG. 1) is shown, but the present invention can be similarly applied to the second embodiment (FIG. 3).

Embodiment 4 FIG.
FIG. 5 is a circuit diagram showing a configuration of a high-frequency variable gain amplifier according to Embodiment 4 of the present invention. In FIG. 5, the same or similar components as those shown in FIG. 4 (Embodiment 3) are denoted by the same reference numerals. Here, the description will be focused on the portion related to the fourth embodiment.

  As shown in FIG. 5, in the high frequency variable gain amplifier according to the fourth embodiment, between the positive phase side input terminal of the differential amplifier 50 and the DC cut capacitor 42a in the configuration shown in FIG. 4 (third embodiment). The attenuating resistance element 18a is interposed between the negative phase side input terminal of the differential amplifier 50 and the DC cut capacitor 42b.

  Further, an attenuation resistor element 19a is interposed between the positive phase side input terminal of the differential amplifier 51 and the DC cut capacitor 41a, and between the negative phase side input terminal of the differential amplifier 51 and the DC cut capacitor 41b. Attenuating resistance element 19b is inserted.

  The added attenuation resistance elements 18a, 18b, 19a, and 19b provide a part of resistance values required for the attenuation resistance elements 12a, 12b, 13a, and 13b provided in the gain switching paths 310a, 310b, 311a, and 311b. The resistance value, the element length, and the element width are adjusted in such a manner as to be handled.

  According to this configuration, the added attenuation resistance elements 18a, 18b, 19a, 19b are provided on the input end side of the differential amplifiers 50, 51, so that the gain application amount in each gain switching path is set. Impedance matching can be taken so that the value can be maintained.

  In the fourth embodiment (FIG. 5), an example of application to the first embodiment (FIG. 1) is shown, but the present invention can be similarly applied to the second embodiment (FIG. 4).

Embodiment 5 FIG.
6 is a circuit diagram showing a configuration of a high-frequency variable gain amplifier according to a fifth embodiment of the present invention. In the fifth embodiment, the connection mode between the two-stage differential amplifier and the two gain switching path groups symmetrically arranged on the positive phase side and the negative phase side is the same as that of the first embodiment (FIG. 1). A configuration example in the case of different will be described.

  As shown in FIG. 6, the two-stage differential amplifiers 50 and 52 used in the high-frequency variable gain amplifier according to the fifth embodiment are the two-stage differential amplifier 50 shown in FIG. 1 (the first embodiment). , 51, feed resistance elements 10 a, 10 b, 11 a, 11 b are connected between the respective positive-phase side input terminals and negative-phase side input terminals, and the differential amplifier 52 arranged in the output stage has a differential Although configured as shown in FIG. 2 similarly to the amplifier 50, the operation mode is different from that of the differential amplifier 51 shown in FIG. 1 (Embodiment 1). In the same manner as above, the “operation state” and “operation stop state” are controlled.

  Further, the gain switching paths 320a and 321a constituting the third gain switching path group arranged on the positive phase side and the gain switching path group constituting the fourth gain switching path group arranged on the negative phase side. The paths 320b and 321b are symmetrical as in FIG. 1 (Embodiment 1), and one end of each of the gain switching paths 320a and 321a is input to the positive phase side of the differential amplifier 50 via the gain switching switch 30a. The point that one end of each of the gain switching paths 320b and 321b is connected to the negative phase side input terminal of the differential amplifier 50 via the gain switching switch 30b is the same as that in FIG. 1 (Embodiment 1). Although the same, the configuration and the connection mode of each other end are different.

  That is, as shown in FIG. 6, the gain switching path 320a in the third gain switching path group and the gain switching path 320b in the fourth gain switching path group are the gain switching paths shown in FIG. Similarly to the paths 310a and 310b, the differential amplifiers 50 and 52 are connected between the positive phase side input terminals and between the negative phase side input terminals, but the path switches 31a and 31b are omitted and are used in common. The DC cut capacitors (41a, 41b) are included. In FIG. 6, the gain switching path 320a is configured by a series circuit of an attenuation resistance element 22a and a DC cut capacitor 44a, and the gain switching path 320b is a series circuit of an attenuation resistance element 22b and a DC cut capacitor 44b. It consists of

  On the other hand, the connection destinations of the other ends of the gain switching path 321a in the third gain switching path group and the 321b in the fourth gain switching path group are the same as the gain switching paths 311a and 311b shown in FIG. Differently, they are the positive phase side output terminal and the negative phase side output terminal of the differential amplifier 52. The gain switching path 321a is configured by a series circuit of an attenuating resistance element 23a, a path switch 34a, and a DC cut capacitor 44a, and the DC cut capacitor 44a serves as the other end side and outputs the positive phase side of the differential amplifier 52. Connected to the end. The gain switching path 321b includes a series circuit of an attenuating resistance element 23b, a path switch 34b, and a DC cut capacitor 44b. The DC cut capacitor 44b serves as the other end side, and the output terminal on the opposite phase side of the differential amplifier 52. It is connected to the.

  In the first embodiment, the gain switching path used for the “medium gain state” and the “low gain state” is appropriately selected from among the parallel connections. In the fifth embodiment, the gain switching path is fixedly assigned. . That is, the gain switching paths 320a and 320b are used in the “medium gain state”, and the gain switching paths 321a and 321b are used in the “low gain state”.

  Note that the resistance values of the feed resistance elements 10a, 10b, 11a, and 11b are large enough not to attenuate the high-frequency differential signal much as in the first embodiment. The attenuation resistance elements 22a, 22b, 23a, and 23b are impedance matched by adjusting resistance values, element lengths, and widths so that gains corresponding to the respective powers can be applied. Hereinafter, the operation of the control means (not shown) will be described.

  First, when the reception power of the high-frequency signal in the external reception processing system is in the “high gain state”, the differential amplifiers 50 and 52 are set in an amplification operation enabled state, and the voltage control terminals 300a and 300b are almost connected to each other. A ground potential (0 V) is applied to set both gain switching switches 30a and 30b to a non-conductive state. Also, the ground potential (0 V) is applied to each of the voltage control terminals 301a and 301b to set both the path switches 34a and 34b to the non-conductive state.

  That is, the high frequency signal input to the input terminals 1a and 1b in the “high gain state” is directed to the differential amplifier 50 and the gain switching switches 30a and 30b. Among them, most of the high-frequency signals directed to the gain switching switches 30a and 30b are reflected by the gain switching switches 30a and 30b and input to the differential amplifier 50, and the amplified high-frequency signals are DC cut capacitors 40a and 40b. To the differential amplifier 52. At this time, since the gain switching switches 30a and 30b and the path switches 34a and 34b are in a non-conductive state, most of the high-frequency signals directed to the gain path switching paths 320a and 320b connected between the stages are reflected. Are input to the differential amplifier 52. That is, the output high frequency signal of the differential amplifier 50 is input to the differential amplifier 52 without being attenuated. A part of the high-frequency signal amplified by the differential amplifier 52 is directed to the gain path switching paths 321a and 321b, but most of the high-frequency signal is reflected and returned by the path switches 34a and 34b. And output from the output terminals 2a and 2b to the subsequent processing system.

  Next, when the reception power of the high frequency signal in the external reception processing system is “medium gain state”, the differential amplifier 50 is set to the operation stop state, and the differential amplifier 52 is set to the amplification operation enabled state. Then, a power supply potential is applied to each of the voltage control terminals 300a and 300b to set both of the gain switching switches 30a and 30b to a conductive state. Further, the ground switches (34a, 34b) are both set to a non-conductive state by applying a substantially ground potential (0V) to the voltage control terminals 301a, 301b in the gain switching paths 321a, 321b.

  That is, the high-frequency signal input to the input terminals 1a and 1b in the “medium gain state” is that the differential amplifier 50 is in an operation stop state, so that the gain switching paths 320a and 320b pass through the gain switching switches 30a and 30b. However, since the path switches 34a and 34b are in a non-conducting state, most of the high-frequency signals passing through the gain switching switches 30a and 30b are the gain switching paths 320a and 320b. Are input to a differential amplifier 52 via a DC cut capacitor 43a, 43b and amplified, and are processed from the output terminals 2a, 2b to a subsequent processing system. Is output.

  Further, when the reception power of the high frequency signal in the external reception processing system is “low gain state”, the differential amplifiers 50 and 52 are set to the operation stop state, and the power supply potential is applied to each of the voltage control terminals 300a and 300b. To set both the gain switching switches 30a and 30b to the conductive state. This time, the power supply potential is applied to each of the voltage control terminals 301a and 301b in the gain switching paths 321a and 321b to set both the path switches 34a and 34b to the conductive state.

  That is, the high-frequency signals input to the input terminals 1a and 1b in the “low gain state” are in the operation stop state of the differential amplifier 50, so that the gain switching paths 320a and 320b pass through the gain switching switches 30a and 30b. And the gain switching paths 321a and 321b, the differential amplifier 52 is also in an operation stop state. Therefore, the high-frequency signal input to the gain switching paths 321a and 321b from the gain switching switches 30a and 30b is subjected to predetermined attenuation processing by the attenuation resistance elements 23a and 23b, and the path switches 34a and 34b and the DC cut capacitor 44a. 44b and the positive phase side output terminal and the negative phase side output terminal of the differential amplifier 52 from the output terminals 2a, 2b to the subsequent processing system.

  As described above, according to the fifth embodiment, similarly to the first embodiment, the variable gain of the high-frequency variable gain amplifier can be switched in three stages, so that a wider dynamic range than the conventional example can be realized. An effect is obtained.

  In the fifth embodiment, as in the first embodiment, a high-frequency variable gain amplifier capable of operating with a low power supply voltage and a low current can be realized, and a high-frequency variable gain amplifier whose input impedance does not change much even when the gain is switched. In addition, since the number of path switches used in the gain switching path can be reduced by two as compared with the first embodiment, the circuit size can be further reduced.

Embodiment 6 FIG.
FIG. 7 is a circuit diagram showing a configuration of a high-frequency variable gain amplifier according to Embodiment 6 of the present invention. In FIG. 7, the same or similar components as those shown in FIG. 6 (Embodiment 5) are given the same reference numerals. Here, the description will be focused on the portion related to the sixth embodiment.

  As shown in FIG. 7, in the high frequency variable gain amplifier according to the sixth embodiment, a differential amplifier 53 is added after the differential amplifier 52 in the configuration shown in FIG. The amplifier 53 is an output stage differential amplifier. Further, gain switching paths 322a and 322b corresponding thereto are added. In this configuration, the entire gain switching paths 320a, 321a, 322a are configured as a third gain switching path group, and the entire gain switching paths 320b, 321b, 322b are configured as a fourth gain switching path group. is doing.

  The positive phase side output terminal of the differential amplifier 52 is connected to the positive phase side input terminal of the differential amplifier 53 via the DC cut capacitor 45a, and the negative phase side output terminal of the differential amplifier 52 is connected via the DC cut capacitor 45b. The differential amplifier 53 is connected to the negative phase side input terminal. The output terminal 2a is connected to the positive phase side output terminal of the differential amplifier 53 and the other end of the gain switching path 322a, and the output terminal 2b is connected to the negative phase side output terminal of the differential amplifier 53 and the gain switching path 322b. Is connected to the other end. Between the positive phase side input terminal and the negative phase side input terminal of the differential amplifier 53, feed resistance elements 20 a and 20 b are arranged in series, and the series connection terminal is connected to the bias terminal 5. The feed resistance elements 20a and 20b have resistance values large enough not to attenuate the high-frequency differential signal so much.

  The gain switching path 322a is constituted by a series circuit of an attenuating resistor element 24a, a path switch 35a, and a DC cut capacitor 46a. The attenuating resistor element 24a is connected to the gain switching switch 30a as one end side, and DC cut The capacitor 46a is connected to the positive phase side output terminal of the differential amplifier 53 as the other end side.

  The gain switching path 322b is configured by a series circuit of an attenuation resistance element 24b, a path switch 35b, and a DC cut capacitor 46b, and the attenuation resistance element 24b is connected to the gain switching switch 30b as one end side. A DC cut capacitor 46b is connected to the opposite phase side output terminal of the differential amplifier 53 as the other end side.

  The attenuation resistance elements 24a and 24b are impedance matched by adjusting the resistance value and the length and width of the elements so that a gain can be applied corresponding to the power to be handled. The other ends of the gain switching paths 321a and 321b are not connected to the positive phase side output terminal and the negative phase side output terminal of the differential amplifier 52, but are connected to the positive phase side input terminal and the reverse side of the differential amplifier 53. Connected to the phase side input.

  According to this configuration, in addition to setting the differential amplifiers 50 and 52 to the operation stop state, the differential amplifier 53 is also set to the operation stop state, and the voltage control terminals 300a, 300b, 302a, and 302b are differentially connected. A voltage substantially the same as the power supply voltage of the amplifier is applied to set the gain switching switches 30a and 30b and the path switches 35a and 35b to the conductive state, and approximately 0V is applied to the voltage control terminals 301a and 301b. By setting the switches 34a and 34b to the non-conducting state, it is possible to cope with a larger received power than the “low gain state” described in the fifth embodiment using the gain switching paths 322a and 322b.

  Thus, according to the sixth embodiment, the number of variable gain stages that can be set can be increased by one compared to the fifth embodiment, and a wider dynamic range can be realized. In the sixth embodiment, an example is shown in which one differential amplifier and one gain switching path symmetrically arranged are added. However, since it can be increased easily by the same procedure, a wide dynamic range having an arbitrary number of switching stages is shown. A high-frequency variable gain amplifier having the following can be easily obtained.

Embodiment 7 FIG.
FIG. 8 is a circuit diagram showing a configuration of a high-frequency variable gain amplifier according to Embodiment 7 of the present invention. In FIG. 8, components that are the same as or equivalent to the components shown in FIG. 6 (Embodiment 5) are assigned the same reference numerals. Here, the description will be focused on the portion related to the seventh embodiment.

  As shown in FIG. 8, in the high frequency variable gain amplifier according to the seventh embodiment, in the configuration shown in FIG. 6 (fifth embodiment), the positive phase side input terminal of the differential amplifier 50 and the gain switching switch 30a. A DC cut capacitor 47a is inserted between them, and a DC cut capacitor 47b is inserted between the negative phase side input terminal of the differential amplifier 50 and the gain switching switch 30b.

  A grounding resistance element 60a is provided between the connection end of the gain switching switch 30a and the DC cut capacitor 47a and the ground potential, and the connection end of the gain switching switch 30b and the DC cut capacitor 47b is connected to the ground potential. Between them, a grounding resistance element 60b is provided. Also, a grounding resistance element 61a is provided between the connection end of the gain switching switch 30a and the gain switching paths 320a and 321a and the ground potential, and the gain switching switch 30b and the gain switching paths 320b and 321b are connected to each other. A grounding resistance element 61b is provided between the connection end and the ground potential. Further, a grounding resistive element 62a is provided between the connection end of the path switch 34a and the DC cut capacitor 44a in the gain switching path 321a and the ground potential, and the path switch 34b and the DC cut in the gain switching path 321b. A grounding resistance element 62b is provided between the connection end of the capacitor 44b and the ground potential.

  According to this configuration, the source electrode and the drain electrode of the gain switching switches 30a and 30b are grounded via the grounding resistance elements 60a, 60b, 61a and 61. The source and drain electrodes of the path switches 34a and 34b are grounded through grounding resistance elements 61a, 61b, 62a and 62b.

  Therefore, according to the seventh embodiment, similarly to the third embodiment, even if the DC cut capacitors 47a and 47b are interposed to cut the DC component flowing into the gain switching paths 320a, 321a, 320b, and 321b, the gain is increased. The potentials of the switching paths 320a, 321a, 320b, and 321b can be prevented from floating, and a stable gain application operation can be performed.

  In addition, in this Embodiment 7 (FIG. 8), the example of application to Embodiment 5 (FIG. 6) was shown, However, It can apply similarly to Embodiment 6 (FIG. 7).

Embodiment 8 FIG.
FIG. 9 is a circuit diagram showing a configuration of a high-frequency variable gain amplifier according to the eighth embodiment of the present invention. In FIG. 9, the same or similar components as those shown in FIG. 6 (Embodiment 5) are denoted by the same reference numerals. Here, the description will be focused on the portion related to the eighth embodiment.

  As shown in FIG. 9, in the high frequency variable gain amplifier according to the eighth embodiment, in the configuration shown in FIG. 6 (fifth embodiment), between the positive phase side input terminal of the differential amplifier 50 and the DC cut capacitor 47a. A damping resistance element 63b is inserted between the negative phase side input terminal of the differential amplifier 50 and the DC cut capacitor 47b.

  Further, an attenuation resistor element 64a is interposed between the positive phase side input terminal of the differential amplifier 52 and the DC cut capacitor 43a in the gain switching path 320a, and the negative phase side input terminal of the differential amplifier 52 and the gain switching circuit. Attenuating resistance element 64b is interposed between DC cut capacitor 43b in path 320b.

  Further, an attenuation resistor element 65a is interposed between the positive phase side output terminal of the differential amplifier 52 and the DC cut capacitor 44a in the gain switching path 321a, and the negative phase side output terminal of the differential amplifier 53 and the gain switching circuit. An attenuation resistor element 65b is interposed between the DC cut capacitor 44b in the use path 321b.

  The added attenuation resistance elements 63a, 63b, 64a, 64b, 65a, 65b are resistance values required for the attenuation resistance elements 22a, 22b, 23a, 23b provided in the gain switching paths 320a, 320b, 321a, 321b. The resistance value, the element length, and the element width are adjusted in such a manner that a part of them is handled.

  According to this configuration, since the added attenuation resistance elements 63a, 63b, 64a, and 64b are provided on the input end side of the differential amplifiers 50 and 52, the gain application amount in each gain switching path is set. Impedance matching can be taken so that the value can be maintained.

  In the eighth embodiment (FIG. 9), an example of application to the fifth embodiment (FIG. 6) is shown, but the present invention can be similarly applied to the sixth embodiment (FIG. 7).

  As described above, the high-frequency variable gain amplifier according to the present invention is useful for widening the dynamic range of received power by switching gains in multiple stages without greatly changing the input impedance, and in particular, miniaturization with a small number of elements. It is suitable for enabling operation with a low power supply voltage and a low current.

1 is a circuit diagram showing a configuration of a high-frequency variable gain amplifier according to Embodiment 1 of the present invention. FIG. 2 is a circuit diagram illustrating a configuration example of a differential amplifier illustrated in FIG. 1. It is a circuit diagram which shows the structure of the high frequency variable gain amplifier by Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the high frequency variable gain amplifier by Embodiment 3 of this invention. It is a circuit diagram which shows the structure of the high frequency variable gain amplifier by Embodiment 4 of this invention. It is a circuit diagram which shows the structure of the high frequency variable gain amplifier by Embodiment 5 of this invention. It is a circuit diagram which shows the structure of the high frequency variable gain amplifier by Embodiment 6 of this invention. It is a circuit diagram which shows the structure of the high frequency variable gain amplifier by Embodiment 7 of this invention. It is a circuit diagram which shows the structure of the high frequency variable gain amplifier by Embodiment 8 of this invention. It is a circuit diagram which shows the structural example of the conventional high frequency variable gain amplifier.

Explanation of symbols

1a, 1b Input terminal 2a, 2b Output terminal 3, 4, 5 Bias terminal 10a, 10b, 11a, 11b, 20a, 20b Feed resistance element 12a, 12b, 12a, 12b Attenuation resistance element 15a, 15b, 16a, 16b, 17a, 17b Grounding resistive elements 18a, 18b, 19a, 19b Attenuating resistive elements 22a, 22b, 23a, 23b, 24a, 24b Attenuating resistive elements 30a, 30b Gain switching switches (for first and second gain switching) switch)
31a, 31b, 32a, 32b, 33a, 33b path switch 34a, 34b, 35a, 35b path switch 40a, 40b, 45a, 45b DC cut capacitors 41a, 41b DC cut capacitors (first and second DC cut capacitors) )
42a, 42b, 43a, 43b, 44a, 44b, 46a, 46b, 47a, 47b DC cut capacitors 50, 51, 52, 53 Differential amplifiers 60a, 60b, 61a, 61b, 62a, 62b Grounding resistance elements 63a, 63b 64a, 64b, 65a, 65b Attenuating resistance elements 300a, 300b, 301a, 301b, 302a, 302b Voltage control terminals 310a, 311a, 312a Gain switching paths 310b, 311b constituting a first gain switching path group 312b Gain switching paths 320a, 321a, 322a constituting the second gain switching path group Gain switching paths 320b, 321b, 322b constituting the third gain switching path group Configured gain switching paths 501a, 501b, input terminals 502a, 02b Output terminal 503a, 503b Bias terminal 504, 505 Voltage control terminal 506 Power input terminal 511a, 511b NMOS transistor for constant current 512a, 512b, 513a, 513b NMOS transistor for amplification 514, 515 NMOS transistor for switch 516a, 516b Load inductor 517 Source inductor 518 Bypass capacitor 519 Feed resistance element

Claims (10)

Two differential amplifiers connected between respective positive phase side input / output terminals and negative phase side input / output terminals via corresponding DC cut capacitors;
The two differential amplifiers are composed of the same number N (N ≧ 2) gain switching paths arranged symmetrically on the positive phase side and the negative phase side, and each gain switching path is a path switch and an attenuation switch. First and second gain switching path groups configured by a series circuit with a resistive element;
As a path for applying a gain applying process to an input high-frequency signal and leading to the output end, the path passing through the two differential amplifiers and the symmetrical position in the first and second gain switching path groups are arranged. Control means for selectively controlling a path through each one gain switching path,
The first and second gain switching path groups are:
One end of the first gain switching path group is connected to the positive phase side input terminal of one of the differential amplifiers via the first switching switch, and the other end is connected to the positive phase side of the other differential amplifier. An input terminal is connected via a first DC cut capacitor, and one end of the second gain switching path group is connected to a negative phase side input terminal of one of the differential amplifiers via a second gain switching switch. The other end is connected to the opposite phase side input end of the other differential amplifier via a second DC cut capacitor,
The control means includes
When the first and second gain switching switches are controlled to be in a non-conductive state, both the two differential amplifiers are controlled to be in an amplification operation enabled state, and the first and second gain switching switches are conductive. When controlling to the state, among the two differential amplifiers, the differential amplifier at the input stage is controlled to be in an operation stop state, the differential amplifier at the output stage is controlled to be in an amplification operable state, and the first and second differential amplifiers are controlled. A high-frequency variable gain amplifier, wherein the path switches in each of the gain switching paths arranged at symmetrical positions in the two gain switching path groups are controlled to be in a conductive state.   A DC cut capacitor is inserted between the positive-phase side input terminal and the negative-phase side input terminal of one of the differential amplifiers and the first and second gain switching switches, respectively. Between the connection end of the gain switching switch and the inserted DC cut capacitor and the ground potential, the first and second gain switching switches and one end of the first and second gain switching path groups; Between the connection end of the first and second gain switching path groups, the connection end of the first and second DC cut capacitors, and the ground potential, respectively. 2. The high frequency variable gain amplifier according to claim 1, further comprising a grounding resistance element.   Between the positive phase side input terminal and negative phase side input terminal of one of the differential amplifiers and the inserted DC cut capacitor, and the positive phase side input terminal and negative phase side input terminal of the other differential amplifier Each gain is maintained between the first and second DC cut capacitors so that the gain application amount in each gain switching path in the first and second gain switching path groups can maintain a set value. An attenuating resistance element having an adjusted resistance value, element length, and element width is provided so as to cover a part of the resistance value required for the attenuating resistance element in the switching path. Item 3. The high frequency variable gain amplifier according to Item 2.   The attenuation resistance element in each gain switching path in the first and second gain switching path groups has a resistance value, an element length, and an element so that a predetermined amount of gain can be applied in the gain switching path. The high-frequency variable gain amplifier according to any one of claims 1 to 3, wherein the width is adjusted.   Of the two differential amplifiers, at least the differential amplifier of the input stage has two feed resistance elements arranged in series between the positive phase side input terminal and the negative phase side input terminal, and the two feed resistances. The high-frequency variable gain amplifier according to claim 1, wherein a bias voltage for adjusting an input impedance is applied to a series connection end of the element. Two or more differential amplifiers connected between the respective positive-phase side input / output terminals and the negative-phase side input / output terminals via corresponding DC cut capacitors;
The two or more differential amplifiers are arranged symmetrically on the positive phase side and the negative phase side, and are composed of the same number of gain switching paths as the two or more differential amplifiers, respectively, an attenuation resistance element and a DC cut capacitor, And a third gain switching path configured by a series circuit of a gain switching path, a damping resistance element, a path switch, and a DC cut capacitor. A fourth gain switching path group;
As a path for applying a gain applying process to an input high-frequency signal and deriving it to an output end, it is arranged at a symmetrical position in the path passing through the two or more differential amplifiers and the third and fourth gain switching path groups. And a control means for selectively controlling a path passing through each one of the gain switching paths.
The third and fourth gain switching path groups are:
Each one end of the one gain switching path and the one or more gain switching paths of the third gain switching path group is connected to an input stage of the two or more differential amplifiers via a first switching switch. And one end of each of the one gain switching path and the one or more gain switching paths of the fourth gain switching path group is a second switching switch. To the negative phase side input terminal of the differential amplifier of the input stage, and the one gain switching path of the third gain switching path group and the 1 of the fourth gain switching path group. The other end of each of the two gain switching paths is connected to the positive phase side input terminal and the negative phase side input terminal of the next-stage differential amplifier, and the one or more gain switching paths of the third gain switching path group and The other ends of the one or more gain switching paths of the fourth gain switching path group are in order Connected to the positive phase side input terminal and the negative phase side input terminal of the differential amplifier after the next stage differential amplifier, and when the next stage differential amplifier or the subsequent differential amplifier is an output stage differential amplifier, the output stage differential amplifier Connected to the positive phase side output terminal and the negative phase side output terminal of
The control means includes
When controlling the first and second gain switching switches to the non-conductive state, the two or more differential amplifiers are all controlled to be in an amplifying operation enabled state, and the first and second gain switching switches are controlled. When controlling to the conductive state, the differential amplifier at the input stage is controlled to be in an operation stop state, the differential amplifiers at the subsequent stages are controlled to be in an amplifying operation enabled state, and the third and fourth gain switching are performed. When the path switch in the gain switching path is controlled to be in a non-conducting state for each one or more in the path group and the differential amplifier in the input stage and the differential amplifiers in the next stage are sequentially stopped. The path switch in the gain switching path connected to the positive-phase side input terminal and the negative-phase side input terminal of the differential amplifier that is controlled to be in an amplification operable state among the one or more gain switching paths in the process of controlling Each conductive And when all the differential amplifiers are controlled to be in an operation stop state, they are connected to the positive phase side output terminal and the negative phase side output terminal of the differential amplifier of the output stage among the one or more gain switching paths. A high frequency variable gain amplifier characterized by selecting and executing a case where each of the path switches in the gain switching path is controlled to be conductive.   A direct current cut capacitor is inserted between the positive phase side input terminal and the negative phase side input terminal of the input stage differential amplifier and the first and second gain switching switches, respectively, and the first and second gains are inserted. Between the connection end of the switch for switching and the inserted DC cut capacitor and the ground potential, between the first and second gain switching switches and one end of the third and fourth gain switching paths. Between the connection end and the ground potential, and in the one or more gain switching paths in the third and fourth gain switching path groups, the connection end of the path switch and the DC cut capacitor and the ground potential 7. The high frequency variable gain amplifier according to claim 6, wherein a grounding resistance element is provided between each of the two.   The differential corresponding to the positive-phase side input terminal and the negative-phase side input terminal of the input stage differential amplifier and the inserted DC cut capacitor, and the other end of the third and fourth gain switching path groups. A gain application amount in each gain switching path group in each of the third and fourth gain switching path groups can be maintained between the connection end with the amplifier in each gain switching path. The attenuation resistance element which adjusted the resistance value, element length, and element width in the form which takes part in the resistance value requested | required of the said attenuation resistance element is inserted. High frequency variable gain amplifier.   The attenuation resistance element in each gain switching path in the third and fourth gain switching path groups has a resistance value, an element length, and an element so that a predetermined amount of gain can be applied in the gain switching path. 9. The high frequency variable gain amplifier according to claim 6, wherein the width is adjusted.   Of the two or more differential amplifiers, at least the differential amplifier of the input stage has two feed resistance elements arranged in series between the positive phase side input terminal and the negative phase side input terminal, The high-frequency variable gain amplifier according to claim 6, wherein a bias voltage for adjusting an input impedance is applied to a series connection end of the resistance element.

Images