JP2007220946A - Evaluation method of soi wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method that dispenses with a large-scale apparatus and a number of processes, such as a photolithography process, and can accurately and easily measure the electric characteristics of an SOI wafer, such as electron mobility, interface level density, hole mobility, and BOX layer charge density. <P>SOLUTION: In the method for evaluating the electric characteristics of the SOI wafer using a mercury electrode, the mercury electrode is brought into contact with the SOI wafer, a drain current is measured by changing a gate voltage, the relationship between the gate voltage and the drain current is obtained, the gate voltage is applied by expanding an application range for changing the gate voltage as compared with that required for calculating electric characteristics when calculating the electric characteristics from the relationship between the gate voltage and the drain current, at least the drain current in the application range required for calculating the electric characteristics is measured, and the electric characteristics are calculated from the relationship between the gate voltage and the drain current. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for evaluating an SOI wafer using a mercury electrode, and more particularly, to an SOI wafer evaluation method for evaluating the silicon active layer of the SOI wafer and the interface between the silicon active layer and the buried oxide layer.

  In recent years, SOI wafers having an SOI structure in which a silicon active layer (hereinafter sometimes referred to as an SOI layer) is formed on an electrically insulating silicon oxide film have been improved in device high speed and low power consumption. Because of its excellent high pressure resistance, environmental resistance, etc., it has attracted particular attention as a high performance LSI wafer for electronic devices. This is because an SOI wafer has an embedded oxide film (hereinafter sometimes referred to as a BOX layer or a BOX film) that is an insulator between the support substrate and the SOI layer. This is because it has a great advantage that the withstand voltage is high and the soft error rate of α rays is low.

  In addition, in a thin film SOI wafer having an SOI layer thickness of 1 μm or less, a MOS (Metal Oxide Semiconductor) type semiconductor device formed on the SOI layer has a source / drain PN junction area when operated in a fully depleted type. Since the capacitance can be reduced, parasitic capacitance can be reduced and device drive speed can be increased. Furthermore, since the capacitance of the BOX layer serving as the insulating layer is in series with the depletion layer capacitance formed immediately below the gate oxide film, the depletion layer capacitance is substantially reduced, and low power consumption can be realized.

  Recently, higher-quality SOI wafers are required for further miniaturization and higher performance of electronic devices. For this reason, the quality of the SOI layer of SOI wafers is actively evaluated. As a technique for evaluating the quality of this SOI wafer, a MOS structure is formed on the surface of the SOI layer, and a voltage is applied to the electrode portion to evaluate the quality of the SOI layer.

  However, in order to form a MOS structure for evaluating an SOI wafer on an SOI layer, a large-scale apparatus such as a photolithography process and a large number of processes are required, and a large cost and a rapid process are lacking. There is a bug. Although the quality of the SOI layer surface can be evaluated, the evaluation of the interface between the SOI layer and the BOX layer is incomplete.

  Therefore, an evaluation method for evaluating an SOI wafer more easily using a mercury probe without forming a MOS structure on the SOI wafer through many conventional processes has been developed. As one of them, a Pseudo MOS FET method using an SOI wafer as an evaluation object has been proposed (see, for example, Patent Documents 1 and 2 and Non-Patent Documents 1 and 2). According to this method, the interface state density at the interface between the SOI layer and the BOX layer, the electrical characteristics of the SOI layer, and the like can be measured accurately and simply.

  The Pseudo MOS FET method will be described with reference to the drawings. First, as shown in FIG. 2, a needle probe or a mercury probe is directly contacted as an evaluation electrode on the SOI layer 1 side of the SOI wafer 5 forming a pseudo MOS structure with the BOX layer 2 as a gate oxide film. These are the source electrode 6 and the drain electrode 7. Then, the back surface of the SOI wafer 5, that is, the surface of the SOI wafer on the support wafer 3 side is vacuum-sucked on a stage that is also used as an electrode, or the needle electrode is brought into contact with the back surface of the wafer 5 to form the gate electrode 4. Various electrical characteristics can be obtained by applying a voltage between the electrodes.

  In this evaluation method, if a mercury probe is used, the probe contact hole that occurs when the needle probe is brought into contact with the SOI layer surface is not formed. Therefore, repeated measurement and measurement near the first measurement point can be performed easily. Can be performed and is preferred.

Then, after forming a Pseudo MOS structure as described above, the relationship between the gate voltage _{V G} and the drain current _{I D} by applying a gate voltage to the positive side while applying a drain voltage, i.e. _V G -I _D characteristic By measuring the electron mobility of the SOI layer and the interface state density at the interface between the SOI layer and the BOX layer. On the other hand, by measuring the V _G -I _D characteristic by applying a gate voltage on the negative side while applying a drain voltage, it is possible to evaluate the charge density of the hole mobility and the BOX layer of the SOI layer.
However, it is difficult to accurately measure these electrical characteristics, and in particular, there is a problem in terms of accuracy because variations tend to occur when measuring hole mobility and the like.

JP 2001-60676 A JP 2001-267384 A S. Cristoleveanu et al., "A Review of the Pseudo-MOS Transistor in SOI Wafers: Operation, Parameter Extraction, and Applications" IEEE Trans. Electron Dev, 47 1018 (2000). H.J.Hovel, "Si film electrical characterization in SOI substrates by HgFET technique" Solid-State Electronics, 47, 1311 (2003).

  The present invention has been made in view of the above problems, and the object of the present invention is not to require a large-scale apparatus or a number of processes such as a photolithography process, and the electron mobility, interface state density, and hole transfer. It is to accurately and easily measure the electrical characteristics of the SOI wafer such as the BOX layer charge density. In particular, the object is to more accurately measure the hole mobility of the SOI layer, which has been apt to cause measurement variations, and to improve the accuracy of the measuring apparatus.

  In order to achieve the above object, the present invention is a method for evaluating electrical characteristics of an SOI wafer using a mercury electrode, wherein the mercury electrode is brought into contact with the SOI wafer, and a drain voltage is generated by changing a gate voltage. The relationship between the gate voltage and the drain current is measured, and when calculating the electrical characteristics from the relationship between the gate voltage and the drain current, the application range in which the gate voltage is changed is the application necessary for calculating the electrical characteristics. A gate voltage is applied to extend beyond the range, at least a drain current in an application range necessary for calculating the electrical characteristics is measured, and the electrical characteristics are calculated from a relationship between the gate voltage and the drain current. An SOI wafer evaluation method is provided (claim 1).

As described above, the mercury electrode is brought into contact with the SOI wafer, the gate voltage V _G is changed, the drain current _ID is measured, the relationship between the gate voltage and the drain current is obtained, and the relationship between the gate voltage and the drain current is obtained. When the electrical characteristics of the SOI wafer are calculated from the above, it is possible to charge the BOX film sufficiently by applying the gate voltage by expanding the application range in which the gate voltage is changed from the application range necessary for calculating the electrical characteristics. become things, a small drain current can be accurately measured, V _G -I _D characteristic can be obtained stable data in a wide range. Therefore, distortion is suppressed in the obtained V _{G- ID} curve, and analysis can be performed in a wide and stable range. By calculating from data in this stable range, in particular, hole mobility and BOX The electrical characteristics of the SOI wafer such as the layer charge density can be obtained with high accuracy without variation.

At this time, it is preferable that the application range in which the gate voltage is changed is at least twice the application range necessary for calculating the electrical characteristics.
In this way, by setting the application range for changing the gate voltage to at least twice the application range necessary for calculating the electrical characteristics, the BOX film can be charged more reliably in advance, and V _G − It is possible to further stabilize the _ID curve. Thereby, electrical characteristics can be measured with high accuracy.

At this time, it is preferable that at least the natural oxide film on the surface of the SOI wafer is removed by etching with an aqueous solution containing hydrofluoric acid and left for 10 hours or more, and then the drain voltage is measured by applying the gate voltage. (Claim 3).
In this way, the native oxide film on the SOI wafer surface is removed by etching with an aqueous solution containing hydrofluoric acid, and left for 10 hours or more, and then the gate current is applied to measure the drain current, thereby measuring the electric current on the SOI layer surface. It is possible to stabilize the target state, which is particularly suitable for obtaining the hole mobility and the BOX layer charge density.

In addition, it is preferable that the measurement is performed with reduced accuracy in a range that does not require calculation of electrical characteristics in the application range in which the gate voltage is changed.
As described above, if the measurement is performed with reduced accuracy in the application range where the gate voltage is changed, the measurement time caused by increasing the application range where the gate voltage is changed is measured. Loss can be reduced and measurement efficiency can be improved.

As a method of measuring with a reduced accuracy, it is preferable to increase the application step width when changing the gate voltage.
In this way, as a method of measuring with reduced accuracy, if the applied step width is increased when changing the gate voltage, measurement is performed while maintaining the performance of the measurement device, although it depends on the individual measurement device (tester, etc.). Is possible.

When the drain current is first measured after applying the gate voltage, it is preferable to provide a delay time after the gate voltage is applied and before the drain current is measured.
As described above, when the drain current is measured for the first time after applying the gate voltage, the charging efficiency to the BOX film is improved by providing the delay time after the gate voltage is applied and before the drain current is measured. It becomes.

  As described above, according to the present invention, the BOX film that causes measurement errors can be sufficiently charged in advance, so that a minute drain current can be accurately measured. Therefore, stable data can be obtained in a wide range in the relationship between the gate voltage and the drain current, and the electrical characteristics of the SOI wafer can be obtained with high accuracy without variation. In particular, it is possible to accurately measure the electrical characteristics of SOI wafers such as hole mobility and BOX layer charge density.

Hereinafter, embodiments of the present invention will be described, but the present invention is not limited thereto.
Conventionally, electrical characteristics in the SOI wafer, for example, when the hole mobility and BOX layer charge density and the like are evaluated by measuring the Pseudo MOS FET method accurately measures the relationship between the gate voltage _{V G} and the drain current _{I D} difficult _is, distortion is likely to occur in the V G -I _D curve. Therefore, the electrical characteristics of the SOI wafer calculated from the V _G -I _D curve up being less precise, there is a problem that measurement variation becomes large.

Therefore, as a result of intensive studies on the relationship between the gate voltage and the drain current, the present inventors have found that when the drain current is measured, the application range is more than that required for calculating the electrical characteristics from the V _{G- ID} curve. by applying a gate voltage to set the application range of changing the gate voltage and extended in advance can be sufficiently charged to a factor of measurement errors BOX film, the V _G -I _D curve, without distortion It was found that stable data can be secured in a wide range. Then, by analyzing the range in which such a V _{G- ID} curve is stable, measurement variation can be suppressed easily and effectively, and it is possible to calculate and evaluate highly accurate electrical characteristics. The present invention was completed.

Hereinafter, an SOI wafer evaluation method of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a flowchart showing an example of a procedure in the SOI wafer evaluation method according to the present invention. The flow chart shown in FIG. 1 shows that the prepared SOI wafer was subjected to a hydrofluoric acid cleaning treatment and left for 10 hours, and then the V _{G- ID} characteristics on the hole side of the SOI wafer were measured. In this case, the hole mobility / charge density is evaluated. However, the present invention is not limited to this, and can be appropriately changed according to the purpose.

  First, as shown in FIG. 1, an SOI wafer to be evaluated is prepared (step A). The SOI wafer to be evaluated in the present invention may have any SOI structure in which, for example, a buried oxide film serving as an insulating layer and an SOI layer are formed on a support wafer, and its manufacturing method is particularly limited. It is not something. For example, as an SOI wafer to be prepared, the polished surfaces of two mirror-polished wafers in which a silicon oxide film is formed on at least one silicon wafer surface are bonded to each other, and after heat treatment, one wafer is ground and thinned by polishing. A thing can be used (bonding method). In addition, hydrogen is ion-implanted in advance into one mirror-polished wafer, and another wafer is bonded to the mirror-polished wafer and then polished, followed by heat treatment to peel off one wafer from the hydrogen-ion-implanted layer. Then, after forming the SOI structure, the surface of the thin film that becomes the SOI layer can be polished (hydrogen ion peeling method). Further, a so-called SIMOX (Separated Implanted Oxide) wafer manufactured by performing high-temperature heat treatment after ion implantation of oxygen into one mirror-polished wafer may be used.

  When the prepared SOI wafer is washed with pure water or left in the air, a silicon oxide film is formed on the surface thereof. This silicon oxide film is an extremely thin film and is generally called a natural oxide film. However, since it is not uniformly formed on the surface of the SOI wafer, variations in the oxide film thickness occur in the wafer surface.

  Therefore, first, it is preferable to remove the natural oxide film formed on the surface of the SOI layer of this SOI wafer (step B). For removing the natural oxide film, for example, the SOI wafer may be washed with an aqueous solution containing hydrofluoric acid. The concentration of the hydrofluoric acid in the aqueous solution containing hydrofluoric acid may be such that the natural oxide film can be removed, and the cleaning conditions such as the temperature of the aqueous solution and the cleaning time may be such that the natural oxide film can be similarly removed. If the concentration of hydrofluoric acid is high, the BOX layer interposed between the SOI layer and the supporting wafer may be etched, so it is preferable that the hydrofluoric acid concentration is low. After washing the SOI wafer with an aqueous solution containing such hydrofluoric acid, the wafer is rinsed with pure water and dried. As a drying method, drying may be performed by applying dry air to an SOI wafer, or by using a device such as a spin dryer. Alternatively, it may be dried using a chemical solution such as IPA (isopropyl alcohol).

Next, after drying the SOI wafer, it is allowed to stand for 10 hours or longer (step C).
This is suitable when measuring V _G -I _D characteristic by applying a gate voltage, such as evaluation of example, a hole mobility and BOX layer charge density on the negative side. When measuring these electrical characteristics, if the surface state is not controlled by adsorbing positive charges such as H ⁺ ions on the surface of the SOI layer, the charge on the surface of the SOI layer is not stable and accurate measurement is difficult. is there. Therefore, by thus leaving the SOI wafer more than 10 hours, when the measurement of V _G -I _D characteristic, the electrical state of the SOI layer surface can be made stable. It is considered that the surface charge changes due to the growth of an extremely thin oxide film on the surface of the SOI wafer.
In this way, the electrical state of the SOI layer surface is stabilized, and, as described above, the ultrathin oxide film formed by standing after removing all the natural oxide film with hydrofluoric acid is uniform. Variations in measured values can be reduced, and hole mobility and the like can be evaluated with high accuracy.

To the above SOI wafer, the measurement of _V G -I _D characteristic by using a mercury probe apparatus 21 as shown in FIG. 3 (step D). For example, the SOI wafer W has the SOI layer facing downward, that is, after the surface on the SOI layer side is placed on a stage (not shown) and stored in the apparatus, the surface opposite to the surface placed on the stage, The surface of the SOI wafer W on the support wafer side is adsorbed by the vacuum chuck 22 from above. The vacuum chuck 22 is made of a conductive material such as metal and also serves as a gate electrode.

  When the surface of the SOI wafer W on the support wafer side is attracted to the vacuum chuck 22, the stage is moved away from the SOI wafer W. Thereafter, the mercury probe 23 is brought close to the surface of the SOI layer of the SOI wafer W, and only the mercury electrode portion is brought into contact with the SOI layer. At this time, the mercury probe 23 has a structure as shown in FIG. 4, and one of the mercury electrode portions 24 and 25 is used as a source electrode, and the other is used as a drain electrode. In this way, for example, a Pseudo-MOS structure as shown in FIG. 2 can be formed.

A constant drain voltage is applied in a state in which the Pseudo-MOS structure is formed, and the gate voltage is changed by applying a negative gate voltage to the negative side and monitoring the change in the drain current. relation _G and the drain current _{I D,} i.e. _V G -I _D characteristic of the hole side can be measured. V _G -I _D characteristic of the measured hole side is displayed as shown in FIG. 5, for example.
Then, by using the formula shown from the slope of Parts A and B, for example, in Non-Patent Document 1 or 2 in the V _G -I _D characteristic of the measured hole side as shown in FIG. 5, SOI layer Hole mobility and / or BOX layer charge density can be calculated and evaluated (step E).

When measuring the V _G -I _D characteristic of the process D, in the method for evaluating an SOI wafer according to the present invention, when measuring the drain current by changing the gate voltage, the application range of changing the gate voltage The gate voltage is applied over a wide range by setting it to be expanded from the application range necessary for calculating the electrical characteristics. As a result, the BOX film acting as a capacitor is sufficiently charged in advance, particularly when measuring the hole mobility and the like, so that the measurement of a minute current is not affected by the influence of the BOX film. to be measured, the relationship between the gate voltage and the drain current is stabilized, the data distortion of V _G -I _D curve is suppressed can be taken in a wide range. Then, by analyzing the range in which the relationship between the gate voltage and the drain current is stable and calculating the hole mobility and charge density, measurement variations can be suppressed, and highly accurate electrical characteristics such as hole mobility can be achieved. Obtainable.

Here, when obtaining the hole mobility and BOX layer charge density and the like, the negative side continue to apply to raise the gate voltage V _G in steps from, V _G -I by measuring the drain current to the gate voltage While obtaining a _D curve, this time, conventionally, when the applied range of the gate voltage required to calculate the electric characteristics of the SOI wafer by analyzing the V _G -I _D curve is, for example, -20～0V, the present invention In the evaluation method, for example, the gate voltage is applied by extending the application range in which the gate voltage is changed to −40 to 0 V or higher, and the drain current is measured at least at −20 to 0 V.

On the other hand, the conventional method is a method of measuring the drain current by changing the gate voltage only in the vicinity of the range necessary for calculating the hole mobility. In this case, the gate voltage is applied in the range of -20 to 0V. Was measuring. In this conventional method, difficult to obtain the relation between the stable gate voltage and the drain current, it will be distortion occurs in the V _G -I _D curve, as a result, hole mobility was calculated from the relationship between the gate voltage and the drain current Degrees etc. vary widely and the accuracy becomes low. This is probably because the BOX film works as a capacitor when the gate voltage is applied from the negative side.

However, in the present invention, since the drain current is measured by changing the gate voltage in a range expanded from the application range necessary for calculation of hole mobility and the like, the BOX film that causes variation in the above measurement is measured. Since the charging is sufficiently performed in advance, a stable relationship between the gate voltage and the drain current can be obtained in a sufficiently wide range. Therefore, obtained in V _G -I _D curve a wide range of suppressed distortion, measured variation without any, can be obtained by simply calculating a highly accurate hole mobility and the like.

  In addition, it is preferable that the application range for changing the gate voltage is at least twice the application range necessary for calculating the hole mobility, so that the BOX film can be charged more reliably. It is possible to obtain a more stable relationship between the gate voltage and the drain current, and to calculate the hole mobility and the like with higher accuracy. However, the application range in which the gate voltage is changed may be three times or five times, can be determined as appropriate according to the cost and the like, and is not particularly limited.

  In addition, in a range that is not necessary for calculating electrical characteristics such as hole mobility, it is preferable to measure the drain current with reduced accuracy. In the present invention, there is a possibility that the time required for the measurement will increase by extending the measurement range, in this way, if the measurement is performed with reduced accuracy in a range not required for calculation of the electrical characteristics, Accordingly, time and labor can be reduced, and an increase in cost can be effectively suppressed. Even if the measurement accuracy is lowered, there is no particular problem because it is a range that is not used for calculating the electrical characteristics.

As a specific method of measuring with a reduced accuracy, for example, a method of increasing the gate voltage application step width can be cited. As a specific example, the application range required to calculate the hole mobility is −20 to 0 V, and the range in which the drain current is measured by changing the gate voltage is −40 to 0 V, that is, −40 When the application range of -20V is not used for calculation, the gate voltage is greatly changed every 1V in the range of -40 to -20V, and in the range of -20 to 0V necessary for the calculation, the gate voltage is changed. The voltage is changed every 0.25 V and data is taken finely. In this way, it is possible to efficiently evaluate the electrical characteristics by minimizing the time and measurement time required for the measurement in the range not necessary for the calculation as compared with the range necessary for the calculation.
The method of measuring with reduced accuracy is not limited to the above-described method of increasing the gate voltage application step width, and is not particularly limited as long as it is a method of sufficiently charging the BOX film.

Further, when the drain current is first measured by applying the gate voltage, the BOX film can be charged more reliably by providing a delay time after the gate voltage is applied and before the drain current is measured. Thereby, it is possible to obtain a more stable V _G -I _D characteristic, electrical characteristic calculated becomes highly accurate. The delay time can be, for example, 1 minute to 120 minutes, but is not particularly limited as long as it is determined from the viewpoint of cost and the like. It can be set as long as there is no hindrance to the measurement.

As described above, the evaluation method of the present invention, the charging of the BOX film as a sufficient and accurately measure the drain current of the very small, thereby obtaining a stable V _G -I _D characteristic over a wide range it can, this stable V _G -I _D characteristic calculating the electrical characteristics of the hole mobility or the like of no variation precision from and can be evaluated. Further, the electrical characteristics can be easily and accurately evaluated without requiring a large-scale apparatus such as a photolithography process and a large number of processes.

EXAMPLES Hereinafter, although an Example and a comparative example demonstrate this invention further in detail, this invention is not limited to this.
(Example)
Evaluation target by producing SOI wafer by hydrogen ion delamination method using p-type silicon wafer with diameter of 200mm and crystal orientation <100> as support wafer and bond wafer forming SOI layer An SOI wafer was prepared. Boron was used as a dopant for making this wafer p-type. The SOI layer has a thickness of about 70 nm, and the BOX layer has a thickness of about 150 nm.

First, this SOI wafer was washed with an aqueous solution containing 1% by weight of hydrofluoric acid for 1 minute, rinsed with pure water, then dried by removing moisture with dry air and allowed to stand for 10 hours. After 10 hours, this SOI wafer was placed on a mercury probe device (CVmap 92 manufactured by Four DIMENSIONS), and the drain current was monitored by changing the gate voltage while applying a constant drain voltage. V _{G- ID} characteristics were measured.

As _{V G} applied condition at this time, perform applied from -40V to 0V direction, until -20V is applied at 1V step was applied to _{V G} at 0.25V steps from this larger _{V G.} In this way, the gate voltage was measured while being divided into two sections, and the measurement was performed by changing the application step width.
Further, a delay time of 5 minutes was set at the time of the first drain current measurement, that is, after the gate voltage V _G = −40 V was applied and before the drain current _ID was measured.

FIG. 6 shows a measurement diagram of the V _{G- ID} characteristics obtained as described above. As shown in FIG. 6, a distortion-free V _{G- ID} curve could be obtained. Therefore, it was possible to calculate the hole mobility and BOX layer charge density analyzes the _V G -I _D characteristic of the gate voltage _V G = -19.75V larger range. In FIG. 6, the gate voltage _{V G} in the range of -40 to-20V is omitted is not used in the analysis.
The hole mobility and the repeatability (variation) of the BOX layer charge density at the time of multiple measurements were ± 15% or less at the maximum. Thus, there was little variation and electrical characteristics could be obtained with very high accuracy.

By the evaluation method of the present invention, can be measured stably the V _G -I _D characteristic, it is possible to obtain the electrical characteristics of the SOI wafer with high accuracy. As can be seen from FIG. 6, the strain is suppressed and the V _{G- ID} curve is stable in a wide range. The hole mobility and the BOX layer charge density obtained from this V _{G- ID} characteristic are accurate. It was expensive.
Moreover, the measurement by the evaluation method of the present invention was completed in about 2 hours, and there was no significant difference from the time required for the measurement by the conventional method described below.
As described above, electrical characteristics can be evaluated easily, efficiently, and with high accuracy without requiring large-scale equipment and processes. For example, it is possible to provide accurate data for improving a product or a manufacturing process.

(Comparative example)
An SOI wafer similar to the SOI wafer used in the examples was prepared.
First, this SOI wafer was washed with an aqueous solution containing 1% by weight of hydrofluoric acid for 1 minute, rinsed with pure water, then dried by removing moisture with dry air and allowed to stand for 10 hours. After 10 hours, the SOI wafer is placed on the same mercury probe device and embodiments, by monitoring the drain current by changing the gate voltage while applying a constant drain voltage, the hole-side V _G It was measured -I _D characteristic.

As _{V G} applied condition at this time, perform applied from -20V to 0V direction was measured by applying a _{V G} at 0.25V step in this total applied range.
In addition, a delay time of 5 minutes was set as in the example.
FIG. 7 shows a measurement diagram of the V _{G- ID} characteristics obtained as described above. Incidentally, as can be seen from FIG. 7, the range of the gate voltage _V G = _-20~-10V is distorted _V G -I _D curve, it can not be used in the analysis. Therefore, to calculate the hole mobility and BOX layer charge density from _V G -I _D characteristic of the gate voltage _V G = -10 V larger range.
The hole mobility and the repeatability (variation) of the BOX layer charge density at the time of multiple measurements greatly exceeded ± 15%. Thus, the variation is large and the accuracy is low.

In such a conventional evaluation method, the BOX film is not sufficiently charged as compared with the evaluation method of the present invention, which causes an error in the measurement of the drain current, and distortion occurs in the V _{G- ID} curve. Thus, the electrical characteristics obtained from the V _{G- ID} curve have low accuracy. As described above, with respect to a stable range of V _G -I _D characteristic that can be used in the analysis in order to calculate the electrical properties, in the embodiment to which the present invention, and V G ₌ -19.75V larger range However, in the comparative example, the range is larger than V _G = −10 V, and the range that can be analyzed is narrower than the example. When the range of the stable V _{G- ID} characteristic is narrow as described above, the accuracy of the electric characteristic is low.
Moreover, the time required for the measurement was not so different from the case of carrying out the present invention, and was about 2 hours.

As described above, when measuring electrical characteristics such as hole mobility and BOX layer charge density by the evaluation method of the present invention, it is possible to sufficiently charge the BOX film serving as a capacitor in advance, It is possible to eliminate the cause of measurement error. Therefore it is possible to accurately measure a very small drain current, it is possible to obtain a stable V _G -I _D characteristic in a wide range. Then, by calculating the electrical characteristics from the scope of this stable V _G -I _D characteristic, it is possible to obtain a highly accurate electrical characteristics. As described above, according to the present invention, it is possible to easily, efficiently and accurately measure electrical characteristics without requiring a large-scale apparatus or the like. Thus, for example, since quick and accurate data can be provided, it can be used for improvement of products and manufacturing processes.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

It is a flowchart which shows an example of the evaluation method of the SOI wafer of this invention. It is a schematic diagram for demonstrating the Pseudo MOS FET method. 1 is a schematic configuration diagram of a mercury probe apparatus. It is an electrode top view of the mercury electrode of a mercury probe apparatus. An example of a V _G -I _D characteristic of the hole side which is measured in the evaluation method of an SOI wafer of the present invention is a graph showing. Is a graph showing the V _G -I _D characteristic of the positive hole side measured in Example. It is a graph showing the V _G -I _D characteristic of the measured in Comparative Example holes side.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... SOI layer, 2 ... BOX layer (buried oxide film), 3 ... Support wafer,
4 ... Gate electrode, 5 ... SOI wafer, 6 ... Source electrode, 7 ... Drain electrode,
21 ... Mercury probe device, 22 ... Vacuum chuck, 23 ... Mercury probe,
24, 25 ... mercury electrode part, W ... SOI wafer.

Claims (6)

  A method for evaluating electrical characteristics of an SOI wafer using a mercury electrode, wherein the mercury electrode is brought into contact with the SOI wafer, a gate current is changed, a drain current is measured, and a relationship between the gate voltage and the drain current is measured. When calculating the electrical characteristics from the relationship between the gate voltage and the drain current, the application range for changing the gate voltage is expanded from the application range necessary for calculating the electrical characteristics, and the gate voltage is applied, A method for evaluating an SOI wafer, wherein at least a drain current in an application range necessary for calculating the electrical characteristics is measured, and the electrical characteristics are calculated from a relationship between the gate voltage and the drain current.   2. The method for evaluating an SOI wafer according to claim 1, wherein an application range in which the gate voltage is changed is at least twice an application range necessary for calculating the electrical characteristics.   At least the natural oxide film on the surface of the SOI wafer is removed by etching with an aqueous solution containing hydrofluoric acid, and the drain current is measured by applying the gate voltage after standing for 10 hours or more. The method for evaluating an SOI wafer according to claim 1 or 2.   4. The SOI wafer according to claim 1, wherein measurement is performed with reduced accuracy in a range that does not require calculation of electrical characteristics in an application range in which the gate voltage is changed. 5. Evaluation method.   5. The method for evaluating an SOI wafer according to claim 4, wherein, as the method of measuring with reduced accuracy, the application step width is increased when the gate voltage is changed.   The delay time is provided after the gate voltage is applied and before the drain current is measured when the drain current is first measured after the gate voltage is applied. Of SOI wafers.

Images