CN112151403A - Characterization method based on junctionless transistor - Google Patents
Characterization method based on junctionless transistor Download PDFInfo
- Publication number
- CN112151403A CN112151403A CN202011242826.0A CN202011242826A CN112151403A CN 112151403 A CN112151403 A CN 112151403A CN 202011242826 A CN202011242826 A CN 202011242826A CN 112151403 A CN112151403 A CN 112151403A
- Authority
- CN
- China
- Prior art keywords
- silicon
- vol
- accumulation
- probe
- port
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Abstract
The invention provides a characterization method based on a junctionless transistor, which comprises the following steps: providing silicon on insulator to be tested; placing a first probe and a second probe on the top layer silicon; adjusting the bias voltage applied to the substrate to enable the silicon-on-insulator to be tested to work in the accumulation region and obtain the drain current of the accumulation region; applying bias voltage to the substrate to enable the silicon-on-insulator to be tested to work in a partial depletion region and obtain drain current of the partial depletion region; and characterizing parameters of the silicon-on-insulator to be tested based on the accumulation region drain current and the partial depletion region drain current and voltages applied to the first port, the second port and the third port. The invention realizes a junctionless transistor based on a pseudo MOS transistor; the characterization of the ultrathin heavily doped SOI material can be realized based on the junctionless transistor; the junctionless transistor can simultaneously realize the characterization of the active impurity concentration, the bulk mobility and the interface mobility of p-type and n-type doped SOI.
Description
Technical Field
The invention belongs to the field of electrical characterization of integrated circuits, and particularly relates to a characterization method based on a junction-free transistor.
Background
For SOI materials, there are two different species (silicon and insulator) and there are two silicon/silicon oxide interfaces, which are multilayer heterostructures. Therefore, characterization of SOI performance, especially electrical information, is of great importance. In addition, with the development of integrated circuits, the demand for thin and ultra-thin top-layer silicon SOI materials is more and more extensive, but most of the existing characterization methods are mainly suitable for characterization of thicker (> 1 μm) top-layer silicon, and cannot be completely applied to thin and ultra-thin top-layer silicon. Because electrical parameters of a Silicon-on-Insulator (SOI) wafer, such as mobility, flatband voltage, etc., can be simply and quickly extracted, a pseudo-Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) can be widely applied to characterization of the SOI wafer.
Therefore, how to provide a new characterization method is actually necessary for SOI that is especially suitable for thin and ultra-thin top layer silicon.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a characterization method based on junction-less transistors, which solves the problem of prior art characterization of parameters of silicon-on-insulator.
To achieve the above and other related objects, the present invention provides a characterization method based on a junctionless transistor, the characterization method comprising the steps of:
a method of characterization based on a junctionless transistor, the method comprising the steps of:
providing silicon on an insulator to be tested, wherein the silicon on the insulator to be tested sequentially comprises a substrate, a middle buried oxide layer and top silicon;
placing a first probe and a second probe on the top layer silicon, wherein a space is formed between the first probe and the second probe, the first probe forms a first port, the second probe forms a second port, and the substrate forms a third port;
adjusting a bias voltage applied to the substrate based on the third port toEnabling the silicon-on-insulator to be tested to work in an accumulation region and obtaining the drain current of the accumulation region, wherein the mode of obtaining the drain current of the accumulation region comprises the following steps: i isD accumulation= Ivol accumulation+ Iacc，Ivol accumulationIs body current, IaccIs the accumulation layer current;
adjusting a bias voltage applied to the substrate based on the third port to cause the silicon-on-insulator to be tested to operate in a partially depleted region and obtain a partially depleted region drain current, wherein obtaining the partially depleted region drain current comprises: i isPartial depletion of D= IPartial depletion of vol，IPartial depletion of volIs a body current, wherein the body mobility is set to be constant when the partially depleted region is operated, the body current IPartial depletion of volComprises the following steps: i isPartial depletion of vol=qfGμP,volNA,D(Tsi-WD)VDWherein q is an electronic charge, fGIs a geometric factor, muP,volFor body carrier mobility, NA,DIs the acceptor (p-type doping) or donor (n-type doping) doping concentration, TsiIs the thickness of the top silicon layer, VDIs the drain voltage, WDIs the depletion layer width; and
characterizing parameters of the silicon-on-insulator under test based on the accumulation region drain current and the partially depleted region drain current and voltages applied to the first port, the second port, and the third port.
Optionally, the depletion layer width WDComprises the following steps: wD =（COX/（qNA,D））（VG-VFB) Wherein, COXIs the capacitance per unit area of silicon oxide, q is the electron charge, NA,DIs the acceptor (p-type doping) or donor (n-type doping) doping concentration, VGIs the gate voltage, VFBIs a flat band voltage.
Optionally, based on the depletion layer width WDAnd the body current IPartial depletion of volThe following can be obtained: i isPartial depletion of vol= IPartial depletion of vol=-fGμP,volCOX (VG-V0)VD(a) Wherein V is0=VFB+（qNA,D/ COX）Tsi （b），V0And (b) obtaining the mobility of the silicon body region on the insulator to be tested based on the slope of the formula (a) for the voltage of the pseudo MOS body region which is just completely exhausted, and calculating the concentration of the activated impurity based on the formula (b).
Optionally, the body current I is during operation of the accumulation regionvol accumulationComprises the following steps: i isvol accumulation=qfGμvolNA,DTsiVD(c) Wherein q is an electronic charge, fGIs a geometric factor, muvolFor body carrier mobility, NA，DIs the acceptor (p-type doping) or donor (n-type doping) doping concentration, TsiIs the thickness of the top silicon layer, VDIs the drain voltage.
Optionally, the accumulation layer current I is in operation in the accumulation regionaccComprises the following steps: i isacc=-fGμP,SCOX（（VG-VFB）VD/（1+θacc（VG-VFB）））（d），μP,sAs carrier interfacial mobility, COXIs the capacitance per unit area of silicon oxide, thetaaccAs a degeneration factor, VGIs the gate voltage, VFBAnd (d) obtaining the interface mobility of the silicon on insulator to be tested based on the formula (c) and the formula (d) for flat band voltage.
Optionally, a first pressure at which the first probe contacts the top silicon is between 25g-35 g; the second pressure at which the second probe is in contact with the top silicon is between 25g and 35 g; the first pressure is the same as the second pressure.
Optionally, the top layer silicon comprises a plurality of test silicon units, and the distance between every two adjacent test silicon units is between 100nm and 1 micron.
Optionally, the material of the first probe comprises tungsten carbide and the material of the second probe comprises tungsten carbide.
Optionally, the soi to be tested is disposed on a conductive support stage for testing, and the voltage applied to the substrate is adjusted based on the conductive support stage and the third port.
Optionally, the conductive support platform is further provided with an air hole and an air pump communicated with the air hole, and the silicon on insulator to be tested is arranged on the air hole.
Optionally, the concentration of active impurities of the top silicon of the insulator to be tested is between 1018 cm-3-1019 cm-3In the meantime.
As described above, the characterization method based on the junctionless transistor of the invention realizes the junctionless transistor based on the pseudo MOS transistor; the characterization of the ultrathin heavily doped SOI material can be realized based on the junctionless transistor; the junctionless transistor can simultaneously realize the characterization of the active impurity concentration, the bulk mobility and the interface mobility of the p-type and n-type doped SOI; the method has good effect on the characterization of top silicon below 5nm and is suitable for the characterization of nano silicon.
Drawings
Fig. 1 is a schematic diagram of a pseudo MOS transistor according to the present invention.
FIG. 2 is a schematic diagram showing the connection of the air holes of the metal platform in the pseudo MOS structure of the invention with the air pump.
Fig. 3 shows a schematic diagram of a characterization device of a heavy-doped SOI without a junction transistor constructed for the pseudo MOS of the present invention.
Fig. 4 shows the operation of the junction-less transistor of the present invention.
Fig. 5 shows cross-sectional views of three operating states of a junctionless transistor constructed for the pseudo MOS of the present invention.
FIG. 6 is a schematic diagram of SOI wafer processing silicon islands according to the present invention.
Fig. 7 shows a flow chart of a method for characterization based on a junction-less transistor according to the present invention.
Description of the element reference numerals
100-silicon on insulator to be tested, 101-top silicon, 102-middle buried oxide layer, 103-substrate, 104-first probe, 105-second probe, 106-first port, 107-second port, 108-third port, 109-conductive support platform, 110-air hole, 111-air pump, 112-semiconductor parameter analyzer, 201-source, 202-drain, 203-grid, 204-gate oxide, 205-channel, 301-accumulation region body area, 302-multiphoton accumulation region, 401-partial depletion region body area, 402-depletion region, 501-full depletion region, and S1-S5.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In addition, "between … …" as used herein includes both endpoints.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, the present invention provides a characterization method based on a junctionless transistor, and provides a junctionless transistor characterization technique implemented based on a dummy MOS transistor, which includes: implementing a junction-less transistor based on a dummy MOS transistor; the characterization of the ultrathin heavily doped SOI material can be realized based on the junctionless transistor; the junctionless transistor can simultaneously realize the characterization of the active impurity concentration, the bulk mobility and the interface mobility of p-type and n-type doped SOI. Wherein the steps do not strictly represent the order of the steps of the characterization method of the present invention, and can be interchanged by those skilled in the art, fig. 1 is merely an example.
The characterization method based on the junctionless transistor comprises the following steps:
step S1, providing a to-be-tested soi 100, where the to-be-tested soi 100 includes a substrate 103, a middle buried oxide layer 102, and a top silicon layer 101 in sequence.
Due to the presence of the buried oxide layer (intermediate buried oxide layer 102) in the SOI wafer, the structure is inverted as compared to a conventional MOSFET, as shown in fig. 1. Wherein the substrate 103 is used as a gate, two pressure probes and as a drain and a source, the buried oxide layer is used as a conventional gate oxide layer, and the silicon film (top silicon 101) is used as an active region.
As an example, in the testing process, the soi substrate 100 to be tested is disposed on the conductive support platform 109 for testing, and the conductive support platform 109 may be a metal platform as a support platform. Meanwhile, the voltage applied to the substrate 103 may be adjusted based on the conductive support table.
As shown in fig. 2-3, the conductive support 109 further includes an air hole 110 and an air pump 111 communicating with the air hole 110, and the soi 100 to be tested is disposed on the air hole 110.
Step S2, as shown in fig. 1 and 3, placing a first probe 104 and a second probe 105 on the top layer silicon 101, the first probe 104 and the second probe 105 having a gap therebetween, the first probe 104 forming a first port 106, the second probe 105 forming a second port 107, and the substrate 103 forming a third port 108.
Here, the first port 106, the second port 107, and the third port 108 may be formed by drawing the first probe 104 as the first port 106 for electrical connection through a lead, drawing the second probe 105 as the second port 107 for electrical connection through a lead, and drawing the substrate 103 as the third port 108 through a metal stage and a lead. In one example, the first port 106, the second port 107, and the third port 108 are connected to a semiconductor parameter analyzer 112. In one example, the first probe 104 and the second probe 105 represent a source and a drain, respectively.
It should be noted that as the feature size of MOS transistors shrinks below 20 nm, junctionless transistors can be used to overcome the deteriorating short channel effect. The junctionless transistor relies on heavily doped ultra-thin body SOI as shown in figure 4. 201. 202 and 203 are the source, drain and gate of the junctionless transistor, 204 is the gate oxide and 205 is the channel, respectively.
Unlike conventional surface-inversion MOSFETs, the junctionless transistor is body-conductive (N-type is electron-conductive and P-type is hole-conductive). Since the channel 205 is heavily doped, an on current can be generated. The depletion layer width of the channel region is controlled by the gate voltage, so that the current magnitude is modulated. When the entire depletion layer is fully depleted, the transistor is turned off. Thus, the channel 205 is thin enough to ensure that the transistor does not conduct at a sufficiently low gate voltage.
As shown in fig. 5, the operation states of the junctionless transistor include: accumulation region (on-state), partially depleted (switching region), and fully depleted region (off-state). To ensure proper operation of a junctionless transistor, ultra-thin heavily doped SOI wafers must be characterized prior to fabrication, including mobility, active impurity concentration. By adjusting the substrate bias voltage, the junctionless transistor with the pseudo MOS transistor structure can work in an accumulation region, a body conduction region and a fully depleted region. Wherein, when the junctionless transistor is in the accumulation region, a multi-sub accumulation region 302 is formed at the interface of the accumulation region body region 301 and the buried oxide 102, and thus the drain current includes a body current and an accumulation region current; when the junctionless transistor is in body conduction, a depletion region 402 is formed at the interface of the partially depleted region body 401 and the buried oxide 102, so the drain current only includes the partially conducting body current; when the jfet is fully depleted, the entire body region is covered in the fully depleted region 501, so the drain current is 0 (actually small due to some other leakage). Therefore, the characterization method of the junctionless transistor can be used for a pseudo MOS transistor. Because the pseudo MOS transistor technology has no damage to the wafer and can represent two carriers simultaneously, the invention provides a structure of a junctionless transistor by using a pseudo MOS transistor to represent an ultrathin heavily doped SOI wafer.
Step S3, adjusting the bias voltage applied to the substrate 103 based on the third port 108 to make the soi 100 under test operate in an accumulation region and obtain an accumulation region drain current, where the obtaining of the accumulation region drain current includes: i isD accumulation= Ivol accumulation+ Iacc，Ivol accumulationIs body current, IaccIs the accumulation layer current; and
step S4, adjusting the bias voltage applied to the substrate 103 based on the third port 108, so that the soi 100 to be tested operates in a partially depleted region, and acquiring a partially depleted region drain current, where the acquiring the partially depleted region drain current includes: i isPartial depletion of D= IPartial depletion of vol，IPartial depletion of volIs the body current.
Step S5, characterizing parameters of the silicon-on-insulator to be tested based on the accumulation region drain current and the partially depleted region drain current and the voltages applied to the first port, the second port, and the third port. The bulk mobility, the interface mobility and the activated impurity concentration of the silicon-on-insulator to be tested can be obtained based on the variation relationship between the drain current of the accumulation region and the drain current of the partial depletion region and the bias voltage.
Specifically, in the partially depleted region, only a part of the body region is turned on. Assuming that the body mobility is constant, the drain current can be expressed as: i isPartial depletion of D=IPartial depletion of volWherein, IPartial depletion of vol=qfGμP,volNA,D (Tsi-WD)VD(1) Q is an electronic charge, fGIs a geometric factor, muP,volFor body carrier mobility, NA,DIs the acceptor (p-type doping) or donor (n-type doping) doping concentration, T, of the top layer siliconsiIs the thickness of the top silicon layer, VDIs the drain voltage, WDIs the depletion layer width. VDThe drain voltage refers to the voltage of one of the probes, and the voltage of the other probe is the source voltage, and is selected to be ground.
In the formula, q is the electron charge, fGIs a geometric factor, TsiIs the thickness of the top layer silicon, all according to the constant, V, of the silicon on insulator to be measuredDIs the drain voltage, i.e., the voltage applied to the test probe.
Further, for heavily doped SOI wafers (10)18 cm-3~1019 cm-3) Depletion layer width WDThe approximation is: wD =（COX/（qNA,D））（VG-VFB) (2) wherein COXIs the capacitance per unit area of silicon oxide, q is the electron charge, NA,DDoping concentration of top silicon acceptor (p-type doping) or donor (n-type doping), VGIs a gate voltage, i.e. a voltage applied to the substrate 103, VFBFor flat band voltage, it can be obtained based on the existing characterization method, such as using the general transistor characterization method (e.g. Y-function) to characterize VFB. In one example, at ID-VGFlat band voltage is read on the curve.
Substituting the above equation (2) into equation (1), equation (1) is rewritten as:
Ipartial depletion of vol=-fGμP,volCOX (VG-（VFB+（qNA,D/ COX）Tsi）)VDI.e. IPartial depletion of vol=-fGμP,volCOX (VG-V0)VD(a) (ii) a Obtaining a relation between the drain current and the gate voltage of the partially depleted region, wherein V0=VFB+（qNA,D/ COX）Tsi （b），V0Is the voltage at which the dummy MOS body region has just been fully depleted. Slope based on equation (a)
The body mobility is obtained, and the activation impurity concentration is calculated based on the formula (b). When the gate voltage is equal to V0, the silicon film is fully depleted and thus the dummy MOS is in an off state.
In addition, when the accumulation region works, the drain current is the sum of the body current and the accumulation layer current, and the mode of obtaining the drain current of the accumulation region comprises the following steps: i isD accumulation= Ivol accumulation+ Iacc，Ivol accumulationIs body current, IaccIs the accumulation layer current. Using sheet resistance approximation, the body current is: i isvol accumulation=qfGμvolNA,DTsiVD(c) Q is an electronic charge, fGIs a geometric factor, muvolFor body carrier mobility (which may be obtained based on equation (a) when operating in a partially depleted region), NA，DDoping concentration for acceptor (p-type doping) or donor (N-type doping) (N working in partially depleted regionA,DEqual), TsiIs the SOI silicon film thickness, VDIs the drain voltage. VDThe drain voltage refers to the voltage of one of the probes, and the voltage of the other probe is the source voltage, and is selected to be ground.
Further, when the accumulation region is operated, for the MOSFET operated in the ohmic region, the accumulation layer current may be approximated as: i isacc=-fGμP,SCOX（（VG-VFB）VD/（1+θacc（VG-VFB））），μaccIs the carrier interfacial mobility, θaccAs a degeneration factor, COXIs a capacitance per unit area of silicon oxide, VGIs the gate voltage, VFBIs a flat band voltage. Based on the above description, based on the drain current at that time and the applied gate voltage, the carrier interface mobility μ can be thus characterizedacc。
As an example, a first pressure at which the first probe contacts the top silicon is between 25g-35 g; the second pressure at which the second probe is in contact with the top silicon is between 25g and 35 g; the first pressure is the same as the second pressure, and may be selected to be 30g, for example.
As an example, the material of the first probe comprises tungsten carbide, and the material of the second probe comprises tungsten carbide; the first probe and the second probe have a spacing therebetween.
As an example, as shown in fig. 7, the top silicon includes several test silicon units, and the adjacent test silicon units have a spacing between 100nm and 1 micron.
As an example, the insulator to be tested has an active impurity concentration of between 1018 cm-3~1019 cm-3May be 2 x 10, for example18 cm-3、3*1018 cm-3、4*1018 cm-3、5*1018 cm-3。
The specific embodiment is as follows: according to the previous analysis, the dummy MOS transistor can be used to construct a junction-free transistor on the ultra-thin heavily doped SOI. Based on the above, the invention provides a method for characterizing an ultrathin heavily doped SOI by using a pseudo MOS tube, which comprises the following specific implementation modes:
1) in order to prevent the edge leakage of the SOI, the SOI wafer is made into square silicon islands (the side length is more than 5 cm);
2) placing the SOI silicon island on a metal platform, wherein in order to ensure that metal is well contacted with a substrate, an air hole is arranged in the middle of the metal platform, and a vacuum pump is connected with the air hole to fix the SOI silicon island on the metal platform;
3) two pressure probes are vertically placed in the center of the SOI silicon island and are given proper pressure; in order to avoid the short channel effect and the influence of the area of the silicon island, the distance between the two metal probes is 1mm, and of course, other values larger than 1.5mm can be set according to the size of the silicon island;
4) connecting the metal platform and the connecting probe to a semiconductor parameter tester; in order to enable the pseudo MOS to work in an ohmic region, a source end is grounded, a drain end is connected with low voltage (0.1V-0.2V), and a metal platform provides grid voltage for scanning;
5) in order to avoid the history effect, the grid voltage is scanned from 0 to positive direction or negative direction, the establishing time is more than 5 seconds, and the delay time is 20 milliseconds;
6) repeating 1) -5) to obtain a plurality of results to confirm the obtained current-voltage transmission characteristic curve of the junctionless transistor, thereby obtaining the parameters of the silicon-on-insulator to be tested based on the obtained current-voltage transmission characteristic curve and the above relation.
In summary, the characterization method based on the junctionless transistor of the present invention realizes the junctionless transistor based on the dummy MOS transistor; the characterization of the ultrathin heavily doped SOI material can be realized based on the junctionless transistor; the junctionless transistor can simultaneously realize the characterization of the active impurity concentration, the bulk mobility and the interface mobility of p-type and n-type doped SOI. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A method of characterization based on a junctionless transistor, the method comprising the steps of:
providing silicon on an insulator to be tested, wherein the silicon on the insulator to be tested sequentially comprises a substrate, a middle buried oxide layer and top silicon;
placing a first probe and a second probe on the top layer silicon, wherein a space is formed between the first probe and the second probe, the first probe forms a first port, the second probe forms a second port, and the substrate forms a third port;
adjusting a bias voltage applied to the substrate based on the third port to enable the silicon-on-insulator to be tested to work in an accumulation region and obtain an accumulation region drain current, wherein the obtaining of the accumulation region drain current comprises: i isD accumulation= Ivol accumulation+ Iacc，Ivol accumulationIs body current, IaccIs the accumulation layer current;
adjusting a bias voltage applied to the substrate based on the third port to cause the silicon-on-insulator to be tested to operate in a partially depleted region and obtain a partially depleted region drain current, wherein obtaining the partially depleted region drain current comprises: i isPartial depletion of D= IPartial depletion of vol，IPartial depletion of volIs a body current, wherein the body mobility is set to be constant when the partially depleted region is operated, the body current IPartial depletion of volComprises the following steps: i isPartial depletion of vol=qfGμP,volNA,D(Tsi-WD)VDWherein q is an electronic charge, fGIs a geometric factor, muP,volFor body carrier mobility, NA,DIs the acceptor (p-type doping) or donor (n-type doping) doping concentration, TsiIs the thickness of the top silicon layer, VDIs the drain voltage, WDIs the depletion layer width; and
characterizing parameters of the silicon-on-insulator under test based on the accumulation region drain current, the partially depleted region drain current, and voltages applied to the first port, the second port, and the third port.
2. The crystal according to claim 1, which is based on a crystal of no junction typeMethod for characterization of a body tube, characterized in that the depletion layer width WDComprises the following steps: wD =（COX/（qNA,D））（VG-VFB) Wherein, COXIs the capacitance per unit area of silicon oxide, q is the electron charge, NA,DIs the acceptor (p-type doping) or donor (n-type doping) doping concentration, VGIs the gate voltage, VFBIs a flat band voltage.
3. The method of claim 2, wherein the W is based on the depletion layer widthDAnd the body current IPartial depletion of volThe following can be obtained: i isPartial depletion of vol=-fGμP,volCOX (VG-V0)VD(a) Wherein V is0=VFB+（qNA,D/ COX）Tsi（b），V0And (3) obtaining the mobility of the silicon body region on the insulator to be tested based on the slope of the formula (a) for the voltage of the pseudo MOS body region which is just completely exhausted, and calculating the concentration of the activated impurity based on the formula (b).
4. The method of claim 1, wherein the body current I is measured while the accumulation region is operatingvol accumulationComprises the following steps: i isvol accumulation=qfGμvolNA,DTsiVD(c) Wherein q is an electronic charge, fGIs a geometric factor, muvolFor body carrier mobility, NA，DIs the acceptor (p-type doping) or donor (n-type doping) doping concentration, TsiIs the thickness of the top silicon layer, VDIs the drain voltage.
5. The method of claim 4, wherein the accumulation layer current I is measured while the accumulation region is operatingaccComprises the following steps: i isacc=-fGμP,SCOX（（VG-VFB）VD/（1+θacc（VG-VFB）））（d），μP,sAs carrier interfacial mobility, COXIs the capacitance per unit area of silicon oxide, thetaaccAs a degeneration factor, VGIs the gate voltage, VFBObtaining the interface mobility mu of the silicon on insulator to be tested based on the formula (c) and the formula (d) for flat band voltageP,S。
6. The method for characterization based on no-junction transistor according to claim 1, wherein the first pressure at which the first probe contacts the top silicon is between 25g-35 g; the second pressure at which the second probe is in contact with the top silicon is between 25g and 35 g; the first pressure is the same as the second pressure.
7. The method of claim 1, wherein the top silicon comprises a plurality of test silicon units, and the adjacent test silicon units have a pitch between 100nm and 1 micron; the material of the first probe comprises tungsten carbide, and the material of the second probe comprises tungsten carbide.
8. The method of claim 1, wherein the silicon-on-insulator device under test is placed on a conductive support for testing, and the voltage applied to the substrate is adjusted based on the conductive support and the third port.
9. The characterization method according to claim 8, wherein the conductive support platform further comprises an air hole and an air pump connected to the air hole, and the SOI is disposed on the air hole.
10. The method of characterization based on no-junction transistor according to any of claims 1-9, wherein the top silicon of the insulator under test has an active impurity concentrationBetween 1018 cm-3-1019 cm-3In the meantime.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011242826.0A CN112151403A (en) | 2020-11-10 | 2020-11-10 | Characterization method based on junctionless transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011242826.0A CN112151403A (en) | 2020-11-10 | 2020-11-10 | Characterization method based on junctionless transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112151403A true CN112151403A (en) | 2020-12-29 |
Family
ID=73887251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011242826.0A Pending CN112151403A (en) | 2020-11-10 | 2020-11-10 | Characterization method based on junctionless transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112151403A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112461900A (en) * | 2021-02-04 | 2021-03-09 | 微龛(广州)半导体有限公司 | InGaAs geometric factor characterization method and system based on pseudo MOS |
| CN112994615A (en) * | 2021-02-04 | 2021-06-18 | 微龛(广州)半导体有限公司 | SOI wafer quality detection method and system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5519336A (en) * | 1992-03-03 | 1996-05-21 | Honeywell Inc. | Method for electrically characterizing the insulator in SOI devices |
| US20020102751A1 (en) * | 2001-01-26 | 2002-08-01 | International Business Machines Corporation | Method of determining electrical properties of silicon-on-insulator wafers |
| CN1687800A (en) * | 2005-04-15 | 2005-10-26 | 中国科学院上海微系统与信息技术研究所 | Electrical parameter characterization method of silicon on insulation body |
| CN1734277A (en) * | 2005-08-31 | 2006-02-15 | 中国科学院上海微系统与信息技术研究所 | A kind of quick characterization method of charge density of buried oxide layer of silicon-on-insulator |
| JP6172102B2 (en) * | 2014-09-26 | 2017-08-02 | 信越半導体株式会社 | Method for evaluating SOI substrate |
-
2020
- 2020-11-10 CN CN202011242826.0A patent/CN112151403A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5519336A (en) * | 1992-03-03 | 1996-05-21 | Honeywell Inc. | Method for electrically characterizing the insulator in SOI devices |
| US20020102751A1 (en) * | 2001-01-26 | 2002-08-01 | International Business Machines Corporation | Method of determining electrical properties of silicon-on-insulator wafers |
| CN1687800A (en) * | 2005-04-15 | 2005-10-26 | 中国科学院上海微系统与信息技术研究所 | Electrical parameter characterization method of silicon on insulation body |
| CN1734277A (en) * | 2005-08-31 | 2006-02-15 | 中国科学院上海微系统与信息技术研究所 | A kind of quick characterization method of charge density of buried oxide layer of silicon-on-insulator |
| JP6172102B2 (en) * | 2014-09-26 | 2017-08-02 | 信越半導体株式会社 | Method for evaluating SOI substrate |
Non-Patent Citations (1)
| Title |
|---|
| F.Y. LIU ET AL: ""Characterization of heavily doped SOI wafers under pseudo-MOSFET configuration"", 《SOLID-STATE ELECTRONICS》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112461900A (en) * | 2021-02-04 | 2021-03-09 | 微龛(广州)半导体有限公司 | InGaAs geometric factor characterization method and system based on pseudo MOS |
| CN112994615A (en) * | 2021-02-04 | 2021-06-18 | 微龛(广州)半导体有限公司 | SOI wafer quality detection method and system |
| CN112994615B (en) * | 2021-02-04 | 2022-07-05 | 微龛(广州)半导体有限公司 | SOI wafer quality detection method and system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Deen et al. | Electrical characterization of semiconductor materials and devices | |
| US6900652B2 (en) | Flexible membrane probe and method of use thereof | |
| US7288446B2 (en) | Single and double-gate pseudo-FET devices for semiconductor materials evaluation | |
| US9064842B2 (en) | Semiconductor device including graphene layer and method of making the semiconductor device | |
| Hovel | Si film electrical characterization in SOI substrates by the HgFET technique | |
| CN101529592B (en) | Method for evaluating semiconductor wafer | |
| CN112151403A (en) | Characterization method based on junctionless transistor | |
| Deen et al. | Electrical characterization of semiconductor materials and devices | |
| US20070170934A1 (en) | Method and Apparatus for Nondestructive Evaluation of Semiconductor Wafers | |
| CN112461900B (en) | InGaAs geometric factor characterization method and system based on pseudo MOS | |
| US7989232B2 (en) | Method of using electrical test structure for semiconductor trench depth monitor | |
| US7633305B2 (en) | Method for evaluating semiconductor wafer and apparatus for evaluating semiconductor wafer | |
| US7521946B1 (en) | Electrical measurements on semiconductors using corona and microwave techniques | |
| US7327155B2 (en) | Elastic metal gate MOS transistor for surface mobility measurement in semiconductor materials | |
| CN113257790B (en) | Electric leakage test structure and electric leakage test method | |
| Uchida et al. | Short-channel a-Si thin-film MOS transistors | |
| EP1610373A2 (en) | Method and apparatus for determining generation lifetime of product semiconductor wafers | |
| CN112994615B (en) | SOI wafer quality detection method and system | |
| Kushner et al. | Low-frequency-noise spectroscopy of SIMOX and bonded SOI wafers | |
| CN103745941B (en) | The testing method of the electric property of gate medium | |
| Liu | Ge (Sn)-based vertical gate-all around nanowire MOSFETs and inverters for low power logic | |
| Sato | Modeling the propagation of ac signal on the channel of the pseudo-MOS method | |
| Elbaz et al. | Transport characterization of CMOS-based devices fabricated with isotopically-enriched 28 Si for spin qubit applications | |
| González | Electrical characterization of reliability in advanced silicon-on-insulator structures for sub-22nm technologies | |
| Murthy et al. | Mechanisms underlying leakage current in inverted staggered a-Si: H thin film transistors |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20201229 |
|
| RJ01 | Rejection of invention patent application after publication |