JP2007218809A - Material testing machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the sampling rate of testing force, and to provide a material testing machine capable of improving the measurement precision. <P>SOLUTION: The detected data x which are obtained by amplifying and digitizing the out put of the load cell 2 are outputted, the correction circuit of a hard ware for operating a deviation amount e from a straight line P which is relating the detected data x to a test force value F is provided by using a previously set correction function. The conversion to the test force value F by the operation control part 4 which is mainly CPU 41 is constituted that the deviation amount e is performed after adding the deviation amount e to the detected data x, the measurement value of the test force can be made high precision while improving the sampling rate etc., of the detected data x without loading CPU 41. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a material testing machine, and more particularly to a material testing machine capable of accurately measuring a test force acting on a specimen.

  In material testing machines, in general, a load such as tension or compression is applied to a specimen, and the test force acting on the specimen and the elongation of the specimen are measured momentarily to measure the test force and elongation. From the results, the material characteristics of the specimen are investigated, and the measurement results of the test force are often used as detection signals for feedback control of the load mechanism.

  The test force is measured by using a load cell as a detector, and the output is usually amplified by an amplifier and digitized to obtain test force detection data. At this time, in order that the obtained test force detection data correctly represents the actual test force, a known force is applied in advance using a force meter (verifier), the amplification factor of the amplifier, and the arithmetic control unit mainly composed of the CPU A calibration operation is performed to determine the coefficient used for the calculation for conversion to the test force at. This calibration is generally performed using an amplified output at a load of 0 and an amplified output at a full scale load (see, for example, Patent Document 1).

Also, for the purpose of measuring the test force more strictly, conventionally, each amplified output when a plurality of loads are loaded using a force meter is sampled, and the output value-load value is plotted in a line on the graph. It is also known to perform so-called straight line correction calculation in which straight lines are connected, each straight line is stored as an equation, and the measured data is corrected by software calculation by the CPU (see, for example, Patent Document 2). ). In this method, the detection data obtained by amplifying and digitizing the output of the load cell is x, the corrected test force is F, and a _i , b _i (i = 1, 2,...) Are coefficients in each section. Then,
F = a _i x + b _i
Is calculated by the CPU.

In addition, a correction table for test force measurement data is stored in place of the straight line correction by the calculation of the above formula, and corrected data is picked up from the correction table.
JP 2005-331256 A Japanese Patent Laying-Open No. 2005-69868

  By the way, in order to improve the measurement accuracy of the test force, not only the magnification (amplification factor) is determined using the load 0 and the full scale, but also data collection is performed by applying some intermediate test force. It is necessary to correct the output value at each point.

  Moreover, in the correction calculation by software and the correction using the correction table, processing is performed by the CPU, but processing is performed by so-called case division, and the sampling rate of the test force is improved, and It is difficult to improve the measurement accuracy of the test force. In other words, if the sampling rate is increased, the calculation possible time is limited, and the calculation processing is limited. Therefore, the sampling rate is restricted by the calculation capacity of the CPU. In addition, when straight line correction is performed, a refraction point is created in data that is originally a smooth curve.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a material testing machine capable of improving the sampling rate of the test force and improving the measurement accuracy of the test force.

  In order to solve the above problems, a material testing machine according to the present invention includes a load mechanism that applies a load to a specimen, a load cell that detects a test force acting on the specimen by the load, and amplifies the output of the load cell. Amplification / digitization circuit means for digitizing and outputting as test force detection data, and calculation control comprising a CPU that takes the test force detection data and performs calculations including conversion into test force values In a material testing machine equipped with a section, hardware for inputting the test force detection data and calculating a deviation amount from a straight line of the relationship of the detection data to the test force value using a preset correction function The conversion to the test force value is characterized by adding the deviation amount to the detection data (Claim 1).

  Here, in the present invention, a configuration using programmable hardware (Claim 2) can be suitably employed as the correction arithmetic circuit.

  Further, in the present invention, the calculation of the deviation amount from the straight line using the correction function is less than the number of bits of detection data by the amplification / digitization means and the number of bits of calculation in the calculation control unit. It is preferable to adopt the configuration (Claim 3) performed in (1).

As a specific example of the correction function in the present invention, when the test force detection data by the amplifying / digitizing circuit means is x, the data value at full scale is L, and k ₁ is a coefficient, the correction function f (X)
f (x) = k ₁ x (x−L) (1)
(Claim 4) or when the detected data is x and the data values at full scale are L, k ₁ and k ₂ as coefficients, the number of correction functions f (x a), f (x) = k 1 x (x-L) + k 2 x (x-L) (x-L / 2) ·· (2)
Further, when the detection data is x and the data values at full scale are L, k ₁ , k ₂ and k ₃ as coefficients, the correction function The number f (x) is
f (x) = k ₁ x (x−L) + k ₂ x (x−L) (x−L / 2) + k ₃ x ² (x−L) ² ... (3)
(Claim 6) Further, similarly to the above, the detected data is x, the data value at full scale is L, k ₁ and k ₂ are coefficients, and g (x) is x, (x −L) and (x−L / 2) n-order polynomials, the correction function is
f (x) = k ₁ x (x−L) + k ₂ x (x−L) (x−L / 2) + g (x) (4) (Claim 7).

  In the present invention, in order to correct the linearity of the output characteristics of the load cell, the test force is not immediately obtained from the data after amplification and digitization of the output of the load cell by software, but the amount of deviation from the straight line of the detected data, In other words, when the test force is F, the detection data obtained by amplifying and digitizing the load cell output is x, a, and b are coefficients, the deviation from F = ax + b is calculated by a hardware correction calculation circuit, and the calculation result Is to solve the problem by adding to the detection data.

  That is, as illustrated in FIG. 2A, the relationship between the detection data x and the test force F from the appropriately amplified and digitized load cell, that is, the detection data x-test force characteristics includes a, b , Each of which is a coefficient, it is not strictly on the straight line P represented by ax + b, and is usually a curve as shown. In the present invention, this curve is not calculated from the detection data x, but the deviation e with respect to the straight line P is calculated. In addition, a hardware correction arithmetic circuit is used for this calculation. This makes it possible to increase the sampling rate and improve the measurement accuracy of the test force as compared with the conventional method in which processing is performed by dividing the case in the CPU.

  Since the output-test force characteristics of the load cell are different from each other (instrumental difference), it is necessary to change the correction function for calculating the deviation from the straight line according to the load cell to be used. Therefore, as in the invention according to claim 2, by using programmable hardware such as FPGA or DSP as the hardware used for such digital correction calculation, the CPU is used for calculating the coefficient in the correction function. By setting the calculated coefficient or the like in the hardware, the setting operation can be simplified.

  Since the deviation from the straight line is sufficiently smaller than the test force detection data itself, that is, ax + b >> e, the correction calculation is performed with the number of bits smaller than the number of bits of the measurement data. Can be expected to facilitate the calculation process.

As a specific example of the correction function, a function like that of the invention according to claims 4 to 7 can be used. Among these, the function f (x) = k ₁ x (x−L) in the invention according to claim 4 is used.
The load cell test force-output characteristic can correspond to a monotonically increasing function characteristic as shown in FIG. 3, and the polynomial function in the inventions according to claims 5 to 7 has an inflection point in the curve. In particular, the function f (x) = k ₁ x (x−L) + k ₂ x (x−L) (x−L / 2) + k _{3 of the} invention according to claim 6 can be accommodated. It has been confirmed that x ² (x−L) ² can correspond to almost all characteristics by a relatively simple calculation using three coefficients. The polynomial function in the invention according to claim 7 can be corrected more strictly by increasing the order n.

  According to the present invention, the deviation from the straight line of the detection data by the load cell is calculated and corrected by a simple calculation by the correction arithmetic circuit of the hardware as compared with the correction including the case classification by the CPU based on the correction table. Therefore, there is no burden on the CPU for correction calculation, and both high speed sampling rate and high accuracy of test force measurement results can be achieved.

  In addition, since the amount of deviation of the detected data from the straight line is sufficiently small, it is sufficient to calculate the number of bits smaller than the number of bits of the detected data for the calculation. This makes it possible to measure the test force with high accuracy with low cost and short calculation time.

  Further, by using a polynomial as the correction function as in the inventions according to claims 5 to 7, even if the output characteristic of the load cell has an inflection point, the correction of linearity is performed accordingly. It can be carried out.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a configuration diagram of an embodiment of the present invention, and is a diagram illustrating a schematic diagram showing a mechanical configuration and a block diagram showing an electrical configuration.

  The testing machine main body 1 includes a drive mechanism 1a, a pair of screw rods 1c and 1d that extend vertically on the table 1b and are given rotation by driving the drive mechanism 1a, and the table 1b by rotation of the screw rods 1c and 1d. The test body W is mainly composed of a cross head 1e that moves in the vertical direction and a pair of upper and lower gripping tools 1f and 1g mounted on the table 1b and the crosshead 1e, respectively. It is subjected to the test in a gripped state.

  A load cell 2 is interposed between the upper gripping tool 1g and the crosshead 1e, and a test force acting on the test body W is detected by the load cell 2. An extensometer 3 is attached to the test body W, and the elongation of the test body W is detected by the extensometer 3.

  The outputs of the load cell 2 and the extensometer 3 are amplified by the load amplifier 2a and the strain amplifier 3a, respectively, and digitized by the AD converters 2b and 3b, respectively, and tested as test force detection data and elongation detection data, respectively. The data is taken into the calculation unit 40 of the machine controller 4.

  In addition to the CPU 41, ROM 42, and RAM 43, the arithmetic unit 40 includes an FPGA 44 and an EPROM 45 that stores logic to be set in the FPGA 44. The logic is obtained by the CPU 41 as will be described later using data in the calibration operation performed before the test.

  Further, the control unit 400 of the test machine controller 4 feeds back the amount set as the control amount to the separately set target value among the test force measurement value and the elongation measurement value obtained by the calculation unit 40. To control the drive mechanism 1a. The test force measurement value and the elongation measurement value obtained by the calculation unit 40 are also taken into the personal computer 5 for data processing.

  Of the test force detection data and the elongation detection data obtained by amplifying and digitizing the output of the load cell 2 and the output of the extensometer 3, respectively, the elongation detection data is subjected to a known calculation by the CPU 41 of the calculation unit 40 and stretched. The measured value is obtained. On the other hand, the test force detection data is subjected to calculation for linearity correction by the FPGA 44, and the CPU 41 obtains a measurement value of the test force.

  That is, the test force detection data x obtained by amplifying and digitizing the output of the load cell 2 is not normally in a linear relationship like the straight line P shown in FIG. The curve Q has a characteristic illustrated by a bold line.

Therefore, in this embodiment, the deviation e from the straight line P of the curve Q is calculated by using the correction function f (x) set in the FPGA 44 in advance by calculation using the test force detection data x. . If the relationship between the deviation amount e and the detected data x is shown in a graph, it becomes as shown in FIG. 2B, and the correction function f (x) is an approximate expression of the graph in FIG. (3) Formula, that is,
f (x) = k ₁ x (x−L) + k ₂ x (x−L) (x−L / 2) + k ₃ x ² (x−L) ² ... (3)
It is.

In this equation, L is detection data (output of the AD converter 2b) in a state where the output of the load cell 2 is full scale, and is stored at the time of calibration, and k ₁ , k ₂ , k ₃ are These are coefficients, which are calculated by the CPU 41 using the detection data of a plurality of points obtained at the time of calibration, and set as logic for calculating the expression (3) in the FPGA 44 through the EPROM 45. In calibration, the detection data x is set to 0 when the test force is 0 by adjusting the load amplifier 2a.

The feature of this embodiment is that the A-D converter 2b and the CPU 41 operate with 24 bits, whereas the FPGA 44 operates with 18 bits. That is, during the test, the AD converter 2b outputs the test force detection data x in 24 bits, and the FPGA 44 performs a correction function multiplication or the like using only the upper 18 bits of the 24-bit data x, The deviation amount f (x) from is obtained in 18 bits, and the digit is corrected and added to the original 24-bit data x. That means
y = x + f (x) (5)
The detection data y with the linearity corrected by the above is obtained, and the test force F is obtained by using A as a coefficient and F = Ay (6)
Calculated by

Here, in the above description, the method of correcting x has been described, but by substituting Equation (6) into Equation (5),
F = Ax + Af (x)
It is also possible to create a graph for directly calculating Af (x) by directly calculating Af (x) and correcting the digital value x or directly obtaining Af (x).

  Therefore, the measured value F of the test force thus obtained is an accurate value excluding the influence of the linearity error of the load cell 2.

Further, by performing the calculation of f (x) with 18 bits, correction can be performed with less cost and calculation time without reducing accuracy. That is, the deviation e from the straight line P is equal to the test force value F on the straight line P in FIG.
F >> e
The number of digits of e is actually smaller than x, and even if the number of bits for calculating e is smaller than x, the results obtained are substantially the same. It is.

Coefficient k ₁ to k ₃ in the above (3), based on the detection data taken during calibration using a force meter or the like as described above, CPU 41 automatically calculates accordance with a program written in the ROM42 And set in the FPGA 44 through the EPROM 45. The calculation method will be described below.

At the time of calibration, as shown in FIG. 2A, the relationship x _i −F _i between the detection data x _i and the test force value F _i is collected at n + 1 points (i = 0, 1,... N) and stored in the RAM 43. Remember. Here, the detection data x ₀ when the i = 0 is the data when the load 0, x _n is a data at full scale load load, F _n corresponds to L in equation (3).

Next, from these data,
e _i = (F _i · x _n / F _n ) −x _i ··· (7)
Seeking
e = f (x)
= K ₁ x (x−L) + k ₂ x (x−L) (x−L / 2) + k ₃ x ² (x−L) ²
(3)
K ₁ to k ₃ are estimated. For this estimation, for example, a regression analysis method can be used.

Substituting x _i (i = 1 to n−1) into equation (3),
a _i = k ₁ x (x−L)
b _i = k ₂ x (x−L) (x−L / 2)
c _i = k ₃ x ² (x−L) ²
far. And

When
Ak = E (8)
Multiplying A ^T on both sides,
A ^T Ak = A ^T E (9)
Multiply both sides by (A ^T A) ^-1
(A ^T A) ⁻¹ (A ^T A) k = (A ^T A) ⁻¹ A ^T E (10)
Here, since (A ^T A) ⁻¹ (A ^T A) is a unit matrix,
k = (A ^T A) ⁻¹ A ^T E (11)
K _{1 to} k ₃ can be obtained as follows.

The above procedure is written in the ROM 42, the obtained k ₁ to k ₃ are stored in the EPROM 45, and the logic of the FPGA 44 is set. As a result, every time the test force detection data x is sampled during the test, the FPGA 44 performs the calculation of equation (3) to obtain the deviation e = f (x) of the detection data x from the straight line P. The test force value F after every correction can be obtained by the equation (6).

In the above embodiment, the load amplifier 2a is adjusted during calibration so that the detection data x becomes 0 when the test force is 0, and the CPU 41 uses the equation (6) to obtain the test force value F. However, when the CPU 41 adds e = f (x) to the detected data x to calculate the corrected data y, the deviation is subtracted. Y = x + f (x) + B (12)
Of course, the above calculation may be performed.

  In the above embodiment, the function f (x) representing the deviation amount of the detection data x from the straight line P is described using the above-described equation (3). However, the above-described (1), (2 ) Or (4) may be used. However, in the equation (1), only the characteristic of a monotonically increasing function that does not have an inflection point on the way as illustrated in the graph of the detection data x-test force F in FIG. 3 can be dealt with.

In the block diagram of embodiment of this invention, it is the figure which writes together and shows the schematic diagram showing a mechanical structure, and the block diagram showing an electric structure. (A) is a graph which shows the example of the characteristic of the detection data x and the value of the test force F, (B) is a graph which represented the relationship by the relationship between the detection data x and the deviation | shift amount e from the straight line P. FIG. . It is a graph which shows the example of the load cell characteristic which can respond | correspond by Formula (1).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Test machine main body 1a Drive mechanism 1b Table 1c, 1d Screw rod 1e Cross head 1f, 1g Grasping tool 2 Load cell 2a Load amplifier 3 Extensometer 3a Strain amplifier 2b, 3b AD converter 4 Test machine controller 40 Arithmetic unit 400 Control Part 5 Personal computer W Specimen

Claims (7)

Amplification / digital that has a load mechanism that applies a load to the test body and a load cell that detects the test force acting on the test body by the load, and that outputs the load cell output after it is digitized and output as test force detection data In a material testing machine comprising a calculation circuit unit and a calculation control unit having a CPU that takes in the detection data of the test force and executes a calculation including conversion into a test force value,
Provided with a hardware correction calculation circuit that inputs the test force detection data and uses a preset correction function to calculate the deviation from the straight line of the relationship of the detection data to the test force value. A material testing machine characterized in that conversion to force value is performed after the deviation amount is added to the detection data.   2. The material testing machine according to claim 1, wherein the correction arithmetic circuit is configured by programmable hardware.   The amount of deviation from the straight line using the correction function is calculated with a number of bits smaller than the number of bits of detection data by the amplification / digitization means and the number of bits converted into test force values in the calculation control unit. The material testing machine according to claim 1 or 2, wherein When the detection data of the test force by the amplification / digitization circuit means is x, the value of the detection data at full scale of the load cell output is L, and k ₁ is a coefficient, the correction function f (x) is
f (x) = k ₁ x (x−L)
The material testing machine according to claim 1, 2 or 3, wherein When the detection data of the test force by the amplifying / digitizing circuit means is x and the values of the detection data at full scale of the load cell output are L, k ₁ and k ₂ as coefficients, the correction function f (x) But,
f (x) = k ₁ x (x−L) + k ₂ x (x−L) (x−L / 2)
The material testing machine according to claim 1, 2 or 3, wherein When the detection data of the test force by the amplifying / digitizing circuit means is x and the values of the detection data at the full scale of the load cell output are L, k ₁ , k ₂ and k ₃ as coefficients, the correction function f (X) is
_{f (x) = k 1 x} (x-L) + k 2 x (x-L) (x-L / 2) + k 3 x 2 claims, characterized in that a (x-L) ² 1,2 Or the material testing machine of 3. The test force detection data by the amplifying / digitizing circuit means is x, the value of the load cell output at full scale is L, k ₁ and k ₂ are coefficients, g (x) is x, (x− L) and (x−L / 2) n-order polynomial, the correction function is
f (x) = k ₁ x (x−L) + k ₂ x (x−L) (x−L / 2) + g (x)
The material testing machine according to claim 1 or 3, wherein:

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