JP2007201124A - Substrate for evaluation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate for evaluation used for evaluating CMP conditions that is performed to form a plurality of wires in upper and lower directions in a semiconductor element. <P>SOLUTION: The substrate is manufactured, which has an evaluation pattern including a recess that is formed on the substrate and occupies 0.1-90% of a chip area while the depth ranges from 5 to 300 nm, a wiring groove formed on the recess, and a barrier film 6 and a Cu film 7 provided in the wiring groove. The CMP polishing of the substrate is made, the presence or absence of polishing remainder is evaluated electrically, and optimum polishing time is obtained. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention particularly relates to an evaluation substrate used for studying CMP conditions in CMP (Chemical Mechanical Polishing) of a Cu film in a damascene wiring structure.

  In the CMP process of Cu and barrier film used for LSI multilayer wiring formation, even if there is dishing or erosion of the lower layer wiring, polishing residue that causes a short circuit between wirings does not occur, and dishing and erosion are reduced. It is required to control the film thickness of the Cu wiring within a certain range. Also, in the case of overplating where the plating film thickness of the fine wiring portion becomes thicker than the portion without the pattern, it causes a polishing residue, and thus the same control is required. Therefore, in the CMP of the multilayer wiring, it is necessary to set a CMP condition having a sufficient margin for these fluctuation factors.

  In the Cu wiring formation process, a Cu diffusion barrier film and a Cu seed film are sequentially formed on a substrate on which a wiring groove is formed, and then the Cu film is formed by a plating method to a wiring groove depth of 1.5-3. About twice as thick. Then, in the CMP process, first, the Cu film other than the portion that becomes the wiring is polished and removed using the slurry for Cu, and when the lower barrier film is exposed, the polishing is temporarily stopped. Generally, a method of polishing and removing a barrier film using a slurry for different barrier films is used. This technique requires that the Cu film and barrier film other than the wiring are completely removed after CMP of the Cu film and barrier film, and that dishing and erosion are small. That is, if the Cu film and the barrier film other than the wiring are not completely removed, a short circuit between the wirings occurs and the yield decreases. If dishing or erosion is large, the wiring resistance increases and the performance of the LSI deteriorates.

  By the way, when a single-layer wiring is formed on a flat substrate and the Cu film and the barrier film are subjected to CMP, the reason for the Cu film and the barrier film remaining in the space between the wiring is that before CMP. Variations in the film thickness of the Cu film can be considered. When the Cu film is formed by plating, the Cu film thickness of the fine L & S pattern part is about 1.1 to 1.5 times the film thickness of the flat part without the pattern. This phenomenon is so-called overplating. Although attempts have been made to reduce overplating by examining the additives of the plating solution, it is considered difficult to eliminate overplating completely. In addition, overplating becomes more prominent as the wiring becomes finer. If overplating has occurred, the Cu film overpolishing time by CMP must be lengthened in order to remove the Cu film at that portion.

  In the case of forming a multilayer wiring, there is a tendency that a Cu film or a barrier film tends to remain in a recess formed by dishing or erosion of the lower layer wiring. In particular, when a fine L & S pattern is laminated on the concave portion and the overplating of the Cu plating film occurs, the possibility that the remainder of the Cu film or the barrier film occurs is further increased. Therefore, in order to prevent a short circuit between the wirings, it is necessary to take a sufficiently long overpolishing time for the Cu film by CMP in accordance with the depth of the recess by the lower layer wiring and the overplating scale of the Cu plating film.

However, it has not been possible to evaluate how much overpolishing time is actually required with an evaluation substrate in which a single-layer wiring is formed on a flat substrate as in the prior art.
For example, in an example of Japanese Unexamined Patent Publication No. 2001-7114 “Semiconductor Device and Manufacturing Method Thereof”, a substrate is proposed in which a wiring groove is formed on a flat substrate and a metal film is formed thereon. However, in the evaluation using this substrate, it is not possible to evaluate the influence of unevenness due to the lower layer wiring during the multilayer wiring formation as described above.

  In other words, the wafer with an evaluation wiring pattern that has been used in the past for studying CMP conditions is a single-layer wiring formed on a flat silicon substrate, and is affected by dents due to dishing or erosion of the lower layer wiring. Cannot be evaluated. Therefore, it was not possible to evaluate when a fine L & S pattern was laminated on the depression formed by the lower layer wiring and overplating of the plating film occurred.

Therefore, in order to evaluate the influence of the depression of the lower layer wiring, a method of forming a multilayer wiring is used. In this method, after the CMP of the first layer wiring is performed, the second layer wiring is formed. It is necessary to perform CMP again. For this reason, it takes a long time to optimize the CMP conditions, and the development efficiency of the CMP conditions and slurry is lowered. Furthermore, in this method, since it is difficult to freely change the depth of the dent due to dishing or erosion, it is also difficult to confirm the margin of how large the dent of the base is allowed.
JP2001-7114

  Therefore, the problem to be solved by the present invention is to make it possible to easily evaluate the influence of the depression due to the lower layer wiring and the overplating of the fine wiring in the CMP process for forming the wiring of the semiconductor element. It is to improve the development efficiency. This makes it possible to reduce variations in flatness for each wiring in the manufacture of LSI, leading to improvement in LSI performance and yield.

The above-described problem is an evaluation substrate used for evaluating the conditions of CMP performed to form a plurality of wirings in the vertical direction of a semiconductor element,
A substrate,
A recess formed in the substrate;
A wiring groove formed on the recess;
It solves by the board | substrate for evaluation characterized by comprising the wiring material provided in the said wiring groove | channel.

  That is, by forming a recessed region on a flat substrate, forming a wiring groove on the upper portion so as to at least partially overlap the recessed region, and using an evaluation substrate fabricated by embedding a wiring material, The influence of dishing and overplating on CMP processing can be evaluated by a single CMP.

  In the evaluation substrate of the present invention, the recess is preferably a recess having a depth of 5 to 300 nm. Furthermore, a recess having a depth of 5 to 60% of the depth of the wiring groove formed in the upper layer is preferable. Further, the recess is preferably a recess having a size of 0.1 to 90% of the chip area.

  It is desirable that the wiring groove depth be approximately the same as the LSI wiring thickness. The wiring thickness of the LSI is about 100 nm to 2 μm, and varies depending on the design rule and the applied wiring (lower layer, middle layer, upper layer). Therefore, it is preferable to select appropriately according to the target LSI.

  By performing CMP of the Cu film and barrier film of the substrate configured as in the present invention, the influence of overplating can be easily evaluated without forming a multilayer wiring. Further, CMP conditions and slurry development efficiency are improved. In addition, since it is possible to confirm the allowable range of the dent amount due to the lower layer wiring, which cannot be achieved by the conventional method, it is possible to select a condition with a wide margin for the remaining Cu. Therefore, in manufacturing the LSI, the variation in flatness for each wiring can be reduced, and the performance and yield of the LSI can be improved.

  The evaluation substrate according to the present invention is an evaluation substrate used for evaluating the conditions of CMP performed for forming a plurality of wirings in the vertical direction of a semiconductor element. And it comprises a board | substrate, the recessed part formed in the said board | substrate, the wiring groove | channel formed on the said recessed part, and the wiring material provided in the said wiring groove | channel. The recess has a depth of 5 to 300 nm (particularly 10 nm or more and 200 nm or less). Furthermore, it is 5 to 60% (especially 10% or more and 50% or less) of the depth of the wiring groove formed in the upper layer. The size (expansion) is 0.1 to 90% of the chip area (substrate area) (particularly 1% or more, further 10% or more, and 60% or less). The wiring groove depth is approximately the same as the LSI wiring thickness. For example, the wiring thickness of the LSI is about 100 nm to 2 μm. The wiring width is about 1 to 1000 μm.

This will be described in more detail as follows.
Here, one unit of an evaluation substrate (TEG) in which an evaluation wiring pattern is provided on a wafer (substrate) is referred to as a chip. The evaluation depends on which concave portion and wiring pattern for evaluation are formed on the chip.

1A and 1B are a partial cross-sectional view and a plan view of an evaluation substrate according to the present invention.
Here, in order to make the structure as close as possible to the actual wiring structure, a structure in which a cap film is laminated on a low k film (low dielectric constant insulating film) is used as the insulating film of the trench assuming wiring. The material for the low k film is not particularly limited, and any material may be used. Further, the low k material is not necessarily used. Furthermore, the cap film may not be laminated. That is, after the base step insulating film 1 for forming the recess is provided on the substrate, the base step insulating film 1 is etched to form the recess. Thereafter, the insulating film 2, the etching stopper film 3, the low k film 4, and the cap film 5 are laminated in this order. Then, a photoresist film is provided on the cap film 5, exposed and developed to form a wiring pattern, and then a groove (wiring groove) is formed by etching and ashing. As the low-k film 4, either a coating type insulating film or a plasma CVD (Chemical Vapor Deposition) film may be used as necessary. When the coating type insulating film is used, the effect of flattening the unevenness by the lower layer wiring by the coating type insulating film can be evaluated. There is no particular limitation on the type of insulating film in the wiring, and it is not necessary to have a structure in which the cap film 5 is laminated on the low k film 4 as shown in FIG. In FIG. 1, 6 is a Cu diffusion barrier film, and 7 is a Cu film.

FIG. 2 shows a process for forming an evaluation substrate.
First, as shown in FIG. 2A, an insulating film 12 having the same thickness as the depth of the shallowest recess among the recesses to be formed is formed on the Si substrate 11. Subsequently, as shown in FIG. 2B, a photoresist film 13 is provided by coating, and is exposed and developed to form a predetermined pattern. Thereafter, as shown in FIG. 2C, the recess 14 is formed by plasma etching. As an etching condition, a condition with a high etching selectivity with respect to the Si substrate 11 is used. As a result, the depth of the recess 14 can be made substantially the same as that of the insulating film 12, and variations in the groove depth in the substrate surface can be reduced. After that, as shown in FIG. 2D, the remaining photoresist film 13 is removed by ashing, and cleaning for removing the residue is performed.

  Next, as shown in FIG. 2E, an insulating film 15 having a difference between the depth of the second shallowest recess and the thickness of the insulating film 12 is formed. The insulating film 12 and the insulating film 15 are of the same type. Thereafter, as shown in FIG. 2 (f), a photoresist film 16 is provided by coating, and exposure and development are performed so that a concave portion is formed in a region where the concave portion is not formed by the first etching, and a predetermined photoresist is formed. Form a pattern. Next, as shown in FIGS. 2G and 2H, recesses are formed by etching and ashing, and the photoresist film 16 is removed.

  In the same manner, the same process is repeated so that a recess having a required depth is formed. In addition, when forming the recessed part of several depth in the same chip | tip, it is necessary to prepare several masks. When the number of masks is limited, a pattern having a required depth may be formed by changing the depth of the recess for each wafer. There is no particular limitation on the pattern step formation method, and methods other than those described above may be used as long as a pattern of recesses having different required depths can be formed.

  By the way, in the present invention, the proportion of the manufactured recesses in one chip is preferably 90% or less with respect to the chip area. That is, if the area of the recess exceeds 90%, the influence of the recess in CMP becomes small and is not suitable for evaluation. As for the size of the region of the recess, the length and width are preferably 0.001 to 5 mm. That is, if one concave portion becomes too large, the influence of the concave portion in CMP becomes small and it is not suitable for evaluation. On the other hand, in a pattern whose length and width are smaller than 0.001 mm, since dishing and erosion are usually small, such a recess is not suitable as an evaluation pattern. Further, the depth of the recess is preferably about the same as the depth of the recess by wiring dishing or erosion, and is preferably in the range of 5% to 60% of the depth of the wiring groove.

  After forming necessary concave portions, an insulating film, an etching stopper film, and an insulating film are formed in this order, a wiring pattern is formed with a photoresist, and a wiring groove is formed by etching and ashing. Then, following the cleaning step, a barrier film for preventing Cu diffusion and a Cu seed film are formed by a sputtering method, and then a Cu film is formed by a plating method and hydrogen annealing is performed. In addition, Cu film thickness is about 1.5 to 3 times the depth of the groove | channel which normally assumed wiring.

  The evaluation wiring pattern is produced by dividing it into blocks having a constant wiring width (L) and a space between wirings (S). As for the size of the block, the size of one side is desirably 3 mm or less. That is, if the area of the block is too large, when the electrical characteristics are evaluated, it is easily affected by processes other than the remaining Cu film and barrier film by CMP, and is difficult to be evaluated. The area of the L & S pattern with respect to the chip area is suitably 90% or less. That is, if the area of the L & S pattern is too large, the influence of overplating is mitigated, making it difficult to be suitable for evaluation. In the case where the concave portion and the block of the L & S pattern are overlapped, it is sufficient that at least a part of the block of the L & S pattern overlaps the region of the concave portion.

  In general, the adverse effect of overplating of the Cu plating film increases when both the wiring width (L) and the inter-wiring space (S) are 0.5 μm or less. The width of the fine wiring that may be realized in the future is about 0.02 μm. Accordingly, the wiring width and inter-wiring space of the L & S pattern superimposed on the recess is generally 0.02 to 0.5 μm.

  FIG. 3 shows a CMP apparatus. The head holding the substrate to be polished is pressed against the platen to which the polishing pad is attached, and polishing is performed while rotating the head and the platen in the same direction while supplying slurry to the pad surface. A commercially available polyurethane foam pad can be used as the pad. There are two slurry supply systems, and two types of slurry can be supplied. Pressing a disk with diamond grains embedded on the surface against the polishing pad and rotating the disk and platen to scrape off the pad surface prevents clogging of the pad surface due to abrasives from reactants and slurry from polishing. it can. This can be done during polishing or between polishings as required. The film thickness change of the Cu film during polishing can be detected by an eddy current type end point detector installed on the platen. As a result, it is possible to polish to a certain film thickness under the first condition, stop the polishing once, and then perform polishing under the second polishing condition. Further, it is possible to detect the end point when the Cu film is removed and the Cu diffusion barrier is exposed, and it is possible to control the time of the subsequent over polishing to be constant.

  Since this polishing apparatus performs Cu diffusion barrier polishing following Cu polishing, it has a platen and a head different from those for Cu polishing. Using this, barrier polishing can be carried out with a slurry for barrier. If necessary, Cu polishing and barrier polishing can be continuously processed by automatic conveyance, or only Cu polishing or only barrier polishing can be performed alone. In addition, after polishing, chemical cleaning, ultrasonic cleaning, and the like are performed as necessary by automatic conveyance, and then the substrate is spin-dried to complete the processing.

After the CMP, a Cu diffusion barrier film and a protective film are formed, and a photoresist film is provided for etching and ashing in order to open an electrode portion for electrical measurement. Next, cleaning for removing the residue is performed to form a film of Ti and Al. Thereafter, a photoresist pattern for processing the electrode is formed, and Ti and Al are etched. Finally, an unnecessary resist film is removed by ashing, and an Al electrode is formed.
In order to determine whether or not the Cu film and the barrier film other than the wiring are removed after the predetermined CMP is performed, a comb pattern as shown in FIG. 1B is formed by the L & S pattern. The method for measuring the leakage current or dielectric strength between wirings is accurate and effective. In observation with an optical microscope, it is necessary to detect a color difference or the like, which is difficult to judge.

  An auto prober is used to measure electrical characteristics. By measuring the entire surface of the wafer and evaluating the ratio of patterns without short-circuiting between wirings (hereinafter referred to as yield), it is possible to evaluate the margin for the remaining Cu under CMP conditions.

Hereinafter, the present invention will be described with specific examples.
As a substrate, a 300 mmφ Si wafer was used, and an evaluation substrate as shown in FIG. 1 was produced. As a mask for pattern formation, one mask for forming a wiring groove and two masks for forming a lower layer recess were used, and an evaluation substrate having recesses of two different depths in one chip was produced.

That is, first, a recess forming insulating film (SiCN film) 1 having a thickness of 20 nm was formed on a 300 mmφ Si substrate by plasma CVD. Then, after forming a resist film having a predetermined pattern using the mask for forming recesses X, recesses M having a depth of 20 nm were formed by etching using the resist film as a mask. Etching was performed in a gas system mainly composed of CF ₄ . The etching rate ratio between Si and SiCN at this time is about 1: 5, and a sufficient selection ratio is obtained. After the etching, the remaining resist film was removed by ashing, and residue removal was washed. Thereafter, a SiCN film having a thickness of 20 nm is further formed, a resist film having a predetermined pattern is formed at a position different from the position of the concave portion M using the concave portion forming mask Y, and etching using the resist film as a mask is performed. Thus, a recess N having a depth of 40 nm was formed. After the etching, the remaining resist film was removed by ashing and cleaning for removing the residue was performed. Accordingly, a recess having a depth of 20 nm and a recess having a depth of 40 nm are formed. After this, a 500 nm thick SiO film (insulating film) 2 is provided on the recesses M and N, a 50 nm thick SiCN film (etching stopper film) 3 is provided, and a 150 nm thick SiOC film (Low k film) 4 is provided. Further, a 50 nm thick SiO film (cap film) 5 was laminated. These films were formed by the plasma CVD method. Next, a resist film having a predetermined pattern is formed using a wiring formation mask, and a wiring groove having a predetermined pattern (FIG. 1B) is formed in the regions of the recesses M and N by etching using the resist film as a mask. Formed. Thereafter, ashing and washing were performed. Then, a Cu diffusion barrier film 6 was formed by providing a 10 nm thick TaN film and a 10 nm thick Ta film by sputtering. After the formation of the Cu diffusion barrier film 6, the wafer was conveyed in vacuum, and a Cu seed film was continuously provided by a 60 nm thick sputtering method. Thereafter, a Cu film 7 having a thickness of 540 nm was provided by a plating method. Then, a hydrogen annealing treatment was performed at 220 ° C. for 60 seconds. As a result, the evaluation substrate A in which the wiring of the comb-teeth pattern shown in FIG. The wiring width and space width in this evaluation substrate A were both 90 nm and the overplating amount was 200 nm.

  Then, CMP was performed as follows. As the slurry, a commercially available slurry for Cu using silica-based abrasive grains was used. When performing Cu polishing, a hydrogen peroxide solution having a concentration of 30 wt% was previously mixed with the slurry. The polishing conditions are as follows. Polishing pressure: 7 kPa, platen rotation speed: 60 rpm, head rotation speed: 61 rpm, slurry flow rate: 300 cc / min. Polishing was performed using a slurry in which the mixing ratio of the slurry and the hydrogen peroxide solution was 8: 2 from the start of polishing until the Cu remaining film thickness became 300 nm (half). The supply of slurry was stopped when the Cu remaining film thickness reached 300 nm (half), and the slurry on the pad was once washed with pure water, and then the mixing ratio of the slurry and the hydrogen peroxide solution in terms of weight ratio. Polishing was performed by supplying a slurry of 4: 6. When the mixing ratio of the slurry and the hydrogen peroxide solution is 8: 2, the pattern dependency of the polishing rate is small, and the uniformity of the polishing rate within the wafer surface is good. On the other hand, when the mixing ratio is 4: 6, the pattern dependency of the polishing rate is large, but the step resolution is good and the dishing increase during over-polishing is small. Thereby, it becomes possible to achieve both good flatness and Cu remaining elimination. The polishing rate of the Cu blanket film at a mixing ratio of 8: 2 is 400 nm / min, and the polishing rate of the Cu blanket film at a mixing ratio of 4: 6 is about 300 nm / min.

  During polishing of the Cu film, the remaining Cu film thickness was monitored by an eddy current end point detector. From the output from the end point detector, it can be seen when the Cu remaining film thickness is 300 nm and when the Cu film is removed and the underlying barrier film is almost exposed. FIG. 4 shows the output of the end point detector during polishing. After the unnecessary Cu film is almost removed, the output from the end point detector becomes almost constant. Accordingly, during the polishing under the second polishing condition, the slope of the output from the end point detector, that is, when the differential value becomes 0, is set as the end point, and the subsequent polishing time is set as the over polishing time. Over-polishing was continuously performed under the second polishing conditions. After polishing, the slurry on the pad and the substrate surface was washed away with pure water. Subsequently, the substrate was automatically conveyed to a platen for barrier polishing, and barrier film polishing was performed using a commercially available barrier slurry. The following conditions were used for the polishing conditions. Polishing pressure: 14 kPa, platen rotation speed: 60 rpm, head rotation speed: 61 rpm, slurry flow rate: 200 cc / min. Under these conditions, the polishing rate of the barrier film is 80 nm / min for both Ta and TaN, and the polishing rate ratio is barrier film: SiO film: Cu film = 2: 1: 0.2. After polishing, the pad and the substrate surface slurry are washed away with pure water, then the substrate is automatically transported to a cleaning device, brush cleaning using a commercially available chemical solution, ultrasonic cleaning is performed, followed by water cleaning and spin drying. .

  In Cu CMP, at the end point where the differential value of the output of the eddy current detector becomes 0, there is a possibility that an extremely thin Cu film remains on the barrier film. In particular, when there is a recess in the overplating or the base, Cu tends to remain, and it is necessary to remove it by overpolishing. At this time, if the over-polishing time is too short, there is a possibility that the Cu residue cannot be completely removed. Conversely, if it is too long, dishing and erosion increase.

  Next, an evaluation substrate A was used to examine the optimum polishing time when a fine wiring L & S pattern was provided in the recess and overplating of the Cu plating film occurred.

  In the above, the substrate A was polished by setting the over polishing time of the Cu film to 40 seconds, 60 seconds, and 80 seconds. The barrier polishing time was 30 seconds and 40 seconds. After CMP, an Al electrode for measuring electrical characteristics was formed as follows. First, a SiCN film 30 nm was formed as a Cu diffusion barrier film, and a SiO film 500 nm was formed as a protective film. Next, in order to open the electrode portion, a photoresist pattern was formed and opened by plasma etching. Subsequently, unnecessary photoresist was removed by ashing. Thereafter, cleaning for removing the residue was performed, and a Ti film having a thickness of 70 nm and an Al film having a thickness of 1000 nm were formed by sputtering. In order to form an Al electrode, a photoresist pattern was formed, and the Al film and the Ti film were etched with a chemical solution. After the etching, unnecessary resist was removed by ashing.

And about the wafer in which Al electrode was formed, the leak current between the wiring of L & S pattern was measured using the auto prober. FIG. 5 shows an overview of a pattern in which the inter-wiring leakage current is measured. A plurality of patterns having different widths W of the recessed regions were formed, and measurements were performed on them. The wiring width and space width of the L & S pattern are 90 nm. FIG. 6 shows the chip arrangement on the wafer and the chip whose electrical characteristics were measured. For each L & S pattern, the leakage current was measured in the range where the electric field strength between the wirings was 0 to 3.5 MV / cm. By dividing the measurement result by the facing length and the wiring groove depth, it is converted into a leakage current density. If the leakage current density at an electric field strength of 3 MV / cm exceeds 1E-4 A / cm ² , it is determined that a short circuit between the wirings has occurred.

  Tables 1 to 4 show the results obtained by performing CMP of the Cu film and the barrier film under the above six types of CMP conditions and measuring the electrical characteristics. Tables 1 to 4 show the ratio (yield) of chips in which a short circuit between wirings does not occur for each CMP condition. Table 1 has a recess depth of 20 nm and a width of 3 μm, Table 2 has a recess depth of 20 nm and a width of 10 μm, and Table 3 has a recess depth of 20 nm and a width of 100 μm. Has a recess depth of 20 nm and a width of 1000 μm.

表−２（深さ２０ｎｍ幅１０μｍでの電気特性歩留まり）

表−３（深さ２０ｎｍ幅１００μｍでの電気特性歩留まり）

表−４（深さ２０ｎｍ幅１０００μｍでの電気特性歩留まり）

Table 1 (Electrical property yield at 20 nm depth and 3 μm width)

Table 2 (Electrical property yield at 20 nm depth and 10 μm width)

Table 3 (Electrical property yield at a depth of 20 nm and a width of 100 μm)

Table 4 (Electrical property yield at 20 nm depth and 1000 μm width)

  Based on these results, when the Cu over polishing time is 80 seconds and the barrier polishing time is 40 seconds, the electrical property yield is 90% or more for all the patterns with W = 3 to 1000 μm, and the remaining polishing amount is less than the remaining polishing amount. It can be judged that there is a sufficient margin.

  Also, with the conditions of Cu over polishing time of 80 seconds and barrier polishing time of 30 seconds, and the conditions of Cu over polishing time of 60 seconds and barrier polishing time of 40 seconds, a yield of 80% or more is obtained in the pattern of W = 100, 1000 μm. Therefore, it is considered that the margin for the polishing residue is relatively good. The substrate A used in the experiment has an overplating of Cu plating of about 200 nm. However, if the overplating is reduced, it can be determined that a sufficient margin can be obtained even under these conditions.

  As a result of performing the same measurement on a pattern having a recess depth of 40 nn, the yield was less than 70% under most conditions. If the Cu over polishing time and the barrier polishing time are excessively increased, the wiring resistance is remarkably increased. Therefore, it is not preferable to increase the polishing time further. Therefore, it can be determined that the depth of the concave portion due to dishing erosion of the lower layer wiring is within a range of about 20 to 30 nm.

  For comparison, the same pattern for measuring electrical characteristics was formed in a portion having no recessed area, and the same measurement was performed. That is, an evaluation substrate B as shown in FIG. 7 was prepared and performed in the same manner as described above. As a result, a yield of about 100% was obtained in all the six types of CMP conditions and in all the L & S patterns, and the influence of the unevenness of the lower layer wiring could not be evaluated. In addition, in order to perform the same examination by the conventional method of forming the two-layer wiring, it is necessary to form the upper layer wiring after performing the CMP of the lower layer wiring, and perform the CMP again. I can't. Further, in the conventional method, since it is difficult to arbitrarily control the depth of dishing and erosion depending on the CMP conditions, to what extent the recess amount due to erosion and dishing of the lower layer wiring is allowed as in the present invention. However, it was not possible to confirm the margin and to set appropriate polishing conditions.

Illustration of evaluation pattern according to the present invention Evaluation pattern formation procedure Schematic diagram of CMP equipment Illustration of output of eddy current end point detector Wiring leakage current measurement pattern Explanation of chip layout and electrical characteristic measurement chip on wafer Illustration of evaluation pattern to be compared

Explanation of symbols

1 Insulating film 2 for forming recesses Insulating film 3 Etching stopper film 4 Low k film 5 Cap film 6 Cu diffusion barrier film 7 Cu film

Representative Katsumi Udaka

Claims (4)

An evaluation substrate used for evaluating conditions for CMP performed to form a plurality of wirings in a vertical direction in a semiconductor element,
A substrate,
A recess formed in the substrate;
A wiring groove formed on the recess;
An evaluation board comprising: a wiring material provided in the wiring groove.   The evaluation substrate according to claim 1, wherein the recess is a recess having a depth of 5 to 300 nm.   3. The evaluation substrate according to claim 1, wherein the recess is a recess having a depth of 5 to 60% of the depth of the wiring groove. 4. The evaluation substrate according to claim 1, wherein the recess is a recess having a size of 0.1 to 90% of a chip area.

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