JP4400795B2 - Evaluation substrate and CMP condition evaluation method - Google Patents

Description

  The present invention particularly relates to an evaluation substrate used for studying CMP conditions in CMP (Chemical Mechanical Polishing) of a Cu film in a damascene wiring structure, and an evaluation method for determining (evaluating) CMP conditions using the evaluation substrate. About. In particular, the present invention relates to a technique for providing a damascene wiring structure having a multi-layered wiring film that is excellent in flatness and Cu remaining removability.

  In the CMP process of Cu and barrier film used for the formation of multilayer wiring of LSI, the film thickness of Cu wiring is controlled within a certain range over a wide range from fine wiring of 0.1 μm or less to global wiring of about 100 μm. It is demanded. Further, the dishing and erosion of Cu and the barrier film generated in the CMP process are large fluctuation factors of the Cu wiring film thickness, and therefore, a CMP method for reducing these amounts is required.

  By the way, in the Cu wiring formation process, first, a Cu diffusion barrier film is formed on a substrate on which a wiring groove is formed, and then a Cu seed film is formed, and then the Cu film is formed to a wiring groove depth by plating. A thickness of about 1.5 to 3 times is formed. Thereafter, unnecessary films are polished and removed by CMP. That is, first, a Cu film other than a portion to be a wiring is polished and removed using a slurry for Cu. Then, the polishing is temporarily stopped when the underlying Cu diffusion barrier film is exposed. Next, the Cu diffusion barrier film is polished and removed using a slurry different from that for Cu. In such a technique, when the Cu film is removed and the Cu diffusion barrier film is exposed, the deterioration of flatness due to dishing and erosion is small, and excess Cu other than the portion that becomes the wiring is completely removed. It is important that

  In such a technique, a method is proposed in which a Cu film is partially left in a state after Cu polishing, and the remaining Cu film is simultaneously polished at the time of barrier polishing. In this case, the barrier film and the Cu film are used. It is necessary to make the polishing rate of about 1: 1. However, when CMP is performed in this manner, the amount of Cu polishing during polishing of the Cu diffusion barrier film increases, leading to a decrease in flatness and an increase in wiring resistance.

  In forming a multilayer wiring film of an LSI, the base is often relatively flat when the first (lowermost) wiring film is formed. However, in the formation of wiring films in the second and subsequent layers (layers above the first layer), irregularities are formed by dishing and erosion caused by CMP of the Cu film and Cu diffusion barrier film for forming the lower wiring film. It is necessary to form a wiring film on such irregularities.

  By the way, in the CMP of the second layer and subsequent Cu films, it is necessary to completely remove excess Cu in the concave portion due to the formation of the lower wiring film in order not to cause a short circuit between the wirings. Then, in order to remove the local Cu residue for the concave portion, it is necessary to perform over-polishing after the Cu film is removed and the underlying barrier film is exposed. However, depending on the CMP conditions of the Cu film, it may be necessary to perform overpolishing for a longer time than when there is no unevenness in the lower layer wiring. However, dishing increases as the overpolishing time increases. In the polishing method in which the over-polishing time is increased as the layer progresses, the dishing increases as the upper layer increases, and when the number of wiring layers is large, it is difficult to form a multilayer wiring film. In addition, it is necessary to set an over-polishing time for each wiring layer, and there is a problem that process management becomes complicated.

  As a method for avoiding such a problem, a method has been proposed in which a thick insulating film is formed in the middle of a multi-layer wiring forming process, and the underlying film is flattened by CMP. However, this method increases the number of steps and increases the cost.

  By the way, in the example of Japanese Patent Application Laid-Open No. 2001-7114 “Semiconductor Device and Method of Manufacturing the Same”, as a study of CMP, a substrate in which a wiring groove is formed on a flat substrate and a metal film is formed thereon is used. Yes.

  However, in the evaluation using such a substrate, the influence of unevenness due to the lower wiring film at the time of forming the multilayer wiring film as described above is not taken into consideration.

As described above, a wafer with an evaluation wiring pattern that has been proposed in the past is merely a single-layer wiring formed on a flat silicon substrate. Therefore, the wafer is used for examination of conditions during CMP. However, the influence of unevenness due to dishing or erosion of the lower layer wiring has not been evaluated. Therefore, in order to evaluate the influence of the unevenness of the lower wiring film, a method of actually forming a multilayer wiring film can be considered. However, in this method, it is necessary to perform the CMP again in order to form the second-layer wiring film after performing the CMP for forming the first-layer wiring film. For this reason, since it takes a long time to obtain the optimum CMP conditions, the development efficiency is lowered. Furthermore, in the above method, it has not been possible to confirm the margin of how deep Cu can be removed by the recesses formed by the lower wiring film. Therefore, it was not possible to select a CMP condition having a sufficient margin for removing Cu remaining in the recess by the lower wiring film.
JP2001-7114

  Therefore, if an evaluation substrate and an evaluation method that can easily evaluate the influence of unevenness due to the lower layer wiring are developed, the development efficiency of the slurry for CMP and the CMP process is greatly improved. In the manufacture of LSI, the yield is improved by using CMP conditions with a wide margin.

  Therefore, the problem to be solved by the present invention is to provide a damascene wiring structure having a multi-layered wiring film excellent in flatness and Cu removability removal. Among other things, it is to provide a CMP technique for obtaining a damascene wiring structure having the above features.

The above-described problem is an evaluation substrate used for evaluating the conditions of CMP performed to form a plurality of wiring films in the vertical direction of a semiconductor element,
A substrate,
A first groove having a depth A formed in the substrate;
A second groove having a depth B formed on the substrate from the same reference surface as the first groove;
A wiring film material provided in the first groove and the second groove;
The depth B of the second groove is solved by a substrate for evaluation characterized by being shallower than the depth A of the first groove.

In particular, an evaluation substrate used for evaluating the conditions of CMP performed to form a plurality of wiring films in a vertical direction in a semiconductor element,
A substrate,
A first groove having a depth A formed in the substrate;
A second groove having a depth B formed on the substrate from the same reference surface as the first groove;
A wiring film material provided in the first groove and the second groove;
The depth B of the second groove is 5 to 60% of the depth A of the first groove, which is solved by the evaluation substrate.

  In addition, the above-described evaluation substrate can be solved by the evaluation substrate characterized in that (depth of the second groove) ≧ (depth of dishing in the first groove). The

In addition, the evaluation substrate further includes a groove similar to the second groove except for a different depth,
The groove is solved by an evaluation substrate characterized in that the depth is 5 to 60% of the depth A of the first groove.

  Further, in the above-described evaluation substrate, the groove is solved by the evaluation substrate characterized in that the planar shapes thereof are substantially the same.

  In addition, the above-described evaluation substrate is solved by the evaluation substrate characterized in that the first groove corresponds to a wiring film forming groove in a semiconductor element.

  Further, in the above-described evaluation substrate, the groove is solved by the evaluation substrate characterized in that the pattern is an L & S pattern or an isolated pattern.

Also, a CMP process for CMPing the evaluation substrate,
Whether the wiring film material provided in the second groove is removed at the depth of the dishing of the wiring film material provided in the first groove after the CMP process or deeper than the depth of the dishing. It is solved by a CMP condition evaluation method characterized by comprising a determination step for determining whether or not.

  That is, the present invention is configured by forming two or more grooves having different depths on a substrate and providing a film to be polished (a wiring film, for example, a conductor film such as Cu) on the substrate to bury the grooves. The present invention relates to a CMP evaluation substrate having a patterned pattern, and a method for determining (evaluating) whether or not the CMP is appropriate by performing CMP on the substrate. That is, after CMP of the Cu film and the Cu diffusion barrier film of the substrate, Cu having a groove depth equal to or deeper than the dishing depth in the pattern portion corresponding to the wiring film is removed. The conditions for the CMP are set. That is, by setting CMP conditions so that the above conditions are satisfied and performing CMP under these conditions on a film having a plurality of wiring films, polishing without problems is performed. That is, troubles such as excessive polishing or insufficient polishing do not occur.

  When the present invention is used for studying the CMP process for forming a Cu wiring film, the planar shape of the pattern provided on the substrate includes L & S (Line & Space) patterns with various groove widths and groove occupation ratios, and isolated patterns with various groove widths. Can be used. The occupation ratio of the L & S pattern is defined by (groove pattern width (L) / groove pattern pitch (L + S)) × 100%. In the CMP of the Cu film, dishing becomes the largest when the wiring width is wide and the wiring occupation ratio is large. If such a wiring film is in the lower layer, Cu residue is likely to occur in the upper CMP. Since the maximum wiring width in a normal LSI is considered to be about 100 μm, it is suitable to use several types of patterns having a wiring width of about 100 μm and different wiring occupation ratios. It is also possible to use several types of isolated patterns having different wiring widths. In this case, the wiring width is preferably about 1 to 1000 μm.

  It is desirable that the groove depth of the pattern assuming the wiring film (Cu wiring film formation) is approximately the same as the thickness of the wiring film of the element (LSI). The thickness of the wiring film in the LSI is about 150 nm to 2 μm. Note that the depth of the groove is appropriately selected according to the target LSI because it differs depending on the design rule and the layer (lower layer, middle layer, upper layer) of the applied wiring film. The groove depth of the pattern assuming the depression due to the lower layer wiring is 5 to 60% (especially 7.5%) of the wiring groove depth because the target of dishing amount is about 10% of the thickness of the wiring film. The above range is preferably 10% or more, and 50% or less, and more preferably 40% or less. The number of grooves having a depth within such a range may be one, or two or more. Preferably, 2 to 6 grooves having different depths in the above range are formed. That is, by forming a plurality of grooves as described above, more appropriate CMP conditions can be evaluated.

  Evaluation (determination) of CMP conditions is performed by comparing the dishing amount of the pattern assuming wiring and the remaining Cu state of the pattern assuming depression due to the lower layer wiring after CMP of Cu or Cu diffusion barrier film. . The comparison at this time is a comparison of grooves having the same shape (the same planar shape) except for the depth. As a result of comparison and examination, it has been found that a condition in which there is no Cu residue in a pattern having a groove depth equal to or deeper than the dishing amount is suitable as a CMP condition for multilayer wiring. That is, when CMP is performed from the first layer (lowermost layer) wiring film under the above-described conditions, the CMP of Cu at the same time as the first layer is also performed in the CMP of the second and subsequent wiring films. By over-polishing, the remaining Cu in the recesses due to the lower layer wiring is removed. At this time, dishing of the wirings after the second layer is maintained at the same level as the first layer because the over-polishing time of Cu CMP is constant. Therefore, such CMP conditions are extremely effective for forming a multilayer wiring film. Conversely, under the CMP conditions in which Cu residue is generated in a pattern having a groove depth shallower than the dishing amount, if the second layer CMP is performed under the same conditions, Cu residue is generated due to the underlying recess. If the over-polishing time is made longer than the CMP condition of the first layer in order to remove this Cu residue, the dishing amount of the second-layer wiring film becomes larger than the dishing of the first-layer wiring film. Such CMP conditions are considered to be unsuitable as CMP conditions for multilayer wiring films because dishing increases and wiring resistance increases as the upper wiring film is formed. Further, in such a case, the upper layer wiring film becomes more uneven on the surface of the substrate, so that it is expected that a fine pattern using a photoresist becomes difficult.

  By performing CMP on a pattern having a Cu diffusion barrier film or Cu film for grooves having different depths and evaluating the remaining Cu, it is known whether or not the CMP is appropriate CMP. I can do it. That is, it is possible to evaluate the influence of the underlying irregularities due to the lower wiring film.

  Further, it is necessary to perform a cumbersome work of forming and evaluating an actual multilayer wiring film having a plurality of layers. Therefore, for example, the development efficiency of the slurry for CMP and the CMP process is greatly improved.

  Furthermore, since it is possible to confirm the margin for the Cu remaining in the recessed portion due to the lower wiring film, which cannot be achieved by the conventional method, it is possible to select a condition with a wide margin for the Cu remaining. Therefore, the manufacturing yield and performance of LSI can be improved.

  An evaluation substrate according to the present invention is an evaluation substrate used for evaluating the conditions of CMP performed to form a plurality of wiring films in a vertical direction in a semiconductor element, and is formed on the substrate and the substrate. A first groove having a depth of A, a second groove having a depth of B formed on the substrate from the same reference plane as the first groove, and the first and second grooves. The depth B of the second groove is shallower than the depth A of the first groove. In particular, the depth B of the second groove is 5 to 60% of the depth A of the first groove. Especially, it is 7.5% or more, Furthermore, it is 10% or more. In particular, it is 50% or less, further 40% or less. Preferably, (depth of the second groove) ≧ (depth of dishing in the first groove) is satisfied. Preferably, the groove further includes a groove similar to the second groove except that the depth is different, and the depth of the groove is 5 to 60% of the depth A of the first groove. In particular, it is 7.5% or more, and further 10% or more. In particular, it is 50% or less, further 40% or less. The grooves preferably have substantially the same planar shape. The first groove corresponds to a groove for forming a wiring film in the semiconductor element. The groove has an L & S pattern or an isolated pattern.

  The CMP condition evaluation method according to the present invention includes a CMP process for CMPing the evaluation substrate, a dishing depth of the wiring film material provided in the first groove after the CMP process, or a depth of the dishing. And a determination step of determining whether or not the material of the wiring film provided in the second groove is removed at a deep depth.

This will be described in more detail as follows.
FIG. 1 is a cross-sectional view of a part of the evaluation substrate.
Here, in order to make the structure as close as possible to the actual wiring film structure, a structure in which a cap film is laminated on a low k film (low dielectric constant insulating film) is used as the insulating film of the trench assuming the wiring film. That is, after a base step insulating film 1 for forming a groove assuming a base step is provided on the substrate, the base step insulating film 1 is etched to form a groove. Thereafter, the insulating film 2, the etching stopper film 3, the low k film 4, and the cap film 5 are laminated in this order. Then, a photoresist film is provided on the cap film 5, exposed and developed to form a wiring film pattern, and then a groove is formed by etching and ashing. As the low k film 4, a coating type insulating film, plasma CVD (Chemical
Either a Vapor Deposition film may be used. When the coating type insulating film is used, the effect of flattening the unevenness by the lower layer wiring by the coating type insulating film can be evaluated. There is no particular limitation on the type of insulating film in the wiring film, and it is not necessary to have a structure in which the cap film 5 is laminated on the low k film 4 as shown in FIG. In FIG. 1, the pattern on the right side is for investigating the influence of the base step, and the pattern on the left side is a pattern corresponding to the wiring film. In FIG. 1, 6 is a Cu diffusion barrier film, and 7 is a Cu film.

FIG. 2 shows a process for forming an evaluation substrate.
First, as shown in FIG. 2A, an insulating film 12 having the same thickness as that of the shallowest groove to be manufactured is formed on the Si substrate 11. Subsequently, as shown in FIG. 2B, a photoresist film 13 is provided by coating, and is exposed and developed to form a predetermined pattern. Thereafter, as shown in FIG. 2C, a groove 14 is formed by plasma etching. As an etching condition, a condition with a high selectivity with respect to the Si substrate 11 is used. As a result, the depth of the groove 14 can be made substantially the same as that of the insulating film 12, and the variation of the groove depth in the substrate surface can be reduced. After that, as shown in FIG. 2D, the remaining photoresist film 13 is removed by ashing, and cleaning for removing the residue is performed.

  Next, as shown in FIG. 2E, an insulating film 15 having a thickness that is the difference between the depth of the second shallowest groove and the thickness of the insulating film 12 is formed. The insulating film 12 and the insulating film 15 are of the same type. Thereafter, as shown in FIG. 2 (f), a photoresist film 16 is provided by coating, and exposure and development are performed so that grooves are formed in a region where grooves are not formed by the first etching, and a predetermined photoresist is formed. Form a pattern. Next, as shown in FIGS. 2G and 2H, grooves are formed by etching and ashing, and the photoresist film 16 is removed.

  In the same manner, the same process is repeated so that a groove having a required depth is formed. In addition, since it is necessary to form the pattern of the same planar shape so that it may not overlap in the same chip | tip with respect to each groove depth, it is necessary to prepare a some mask. When the number of masks is limited, a pattern having a required groove depth may be formed by changing the groove depth for each wafer. There is no particular limitation on the pattern step forming method, and a method other than the above may be used as long as grooves of a predetermined pattern can be formed at different depths.

FIG. 3 is an example of an evaluation pattern.
Although there are no particular restrictions on the shape and size of the pattern, as already mentioned, an L & S pattern with a wiring width of about 100 μm, a pattern in which isolated wirings with a wiring width of 1 to 1000 μm are arranged, etc. It is preferable to simulate a wiring pattern.

  After forming the necessary grooves, following the final ashing cleaning step, a barrier film for preventing Cu diffusion is provided, and after forming a Cu seed film by a sputtering method, a Cu film is formed by a plating method, Perform hydrogen annealing. The Cu film thickness to be provided is normally about 1.5 to 3 times the depth of the groove assuming wiring.

  The unevenness on the surface of the Cu film is affected by the unevenness of the base, and as shown in FIG. 1, the unevenness of the lower layer wiring and the unevenness of the wiring are different. By forming this with the same evaluation pattern and performing CMP at the same time, favorable (optimum) conditions for good flatness and no Cu residue can be obtained.

  FIG. 4 shows a CMP apparatus. The head holding the substrate to be polished is pressed against the platen to which the polishing pad is attached, and polishing is performed while rotating the head and the platen in the same direction while supplying slurry to the pad surface. A commercially available polyurethane foam pad can be used as the pad. There are two slurry supply systems, and two types of slurry can be supplied. Pressing a disk with diamond grains embedded on the surface against the polishing pad and rotating the disk and platen to scrape off the pad surface prevents clogging of the pad surface due to abrasives from reactants and slurry from polishing. it can. This can be done during polishing or between polishings as required. The film thickness change of the Cu film during polishing can be detected by an eddy current type end point detector installed on the platen. As a result, it is possible to polish to a certain film thickness under the first condition, stop the polishing once, and then perform polishing under the second polishing condition. Further, it is possible to detect the end point when the Cu film is removed and the Cu diffusion barrier is exposed, and it is possible to control the time of the subsequent overpolishing to be constant.

  Since this polishing apparatus performs Cu diffusion barrier polishing following Cu polishing, it has a platen and a head different from those for Cu polishing. Using this, barrier polishing can be carried out with a slurry for barrier. If necessary, Cu polishing and barrier polishing can be continuously processed by automatic conveyance, or only Cu polishing or only barrier polishing can be performed alone. In addition, after polishing, chemical cleaning, ultrasonic cleaning, and the like are performed as necessary by automatic conveyance, and then the substrate is spin-dried to complete the processing.

  For measuring the flatness after CMP, a stylus-type step gauge can be used. After polishing the Cu film and the Cu diffusion barrier film, the pattern flatness is measured assuming wiring. In the flatness measurement of the L & S pattern, the dishing amount is measured for each block having a certain wiring occupation ratio. The definition of the flatness of the L & S space pattern is shown in FIG. FIG. 5 shows a state in which the insulating film between the wirings has been removed by barrier polishing. FIG. 6 shows the definition of the flatness of the isolated wiring. For isolated wiring, the dishing amount is measured for each wiring.

  The remaining Cu is observed with an optical microscope. In the case of the L & S pattern, the presence or absence of Cu is observed for each block. In the case of an isolated pattern, the presence or absence of Cu is observed for each wiring width. The number of chips to be observed is not particularly limited, but it is desirable to observe at least one row of chips in the diameter direction.

Hereinafter, the present invention will be described with specific examples.
A 300 mmφ Si wafer was used as the substrate, and an evaluation substrate having a cross-sectional structure as shown in FIG. 1 was produced. As a mask for pattern formation, one mask is used for forming a wiring groove and two masks are used for forming a recess by a lower layer wiring so that three different depth grooves can be formed in one chip. Then, using these masks, two types of evaluation substrates with different groove depths of patterns assuming a depression due to the lower layer wiring were produced. Note that the substrates for evaluation of two types of specifications are substrate A and substrate B. The groove depth of the pattern assuming the wiring film in the substrate A and the substrate B is the same. A SiCN film was used as an insulating film for forming a step in a pattern assuming a depression due to a lower layer wiring. The etching rate ratio between the Si substrate and SiCN when etching was performed with a gas mainly containing CF ₄ was about 1: 5, and a sufficient selection ratio was obtained.

  The evaluation substrate A was produced as follows. First, a 20 nm-thick underlying step insulating film (SiCN film) 1 was formed on a 300 mmφ Si substrate by plasma CVD. Then, after forming a resist film having a predetermined pattern using the recess forming mask X, a groove M having a depth of 20 nm was formed by etching using the resist film as a mask. After the etching, the remaining resist film was removed by ashing and cleaning for removing the residue was performed. Thereafter, an SiCN film (insulating film for base step) having a thickness of 20 nm is further formed, and a resist film having a predetermined pattern is formed at a position different from the position of the groove M by using a recess forming mask Y. A groove N having a depth of 40 nm was formed by etching using the resist film as a mask. After the etching, the remaining resist film was removed by ashing and cleaning for removing the residue was performed. Accordingly, a groove (step) having a depth of 20 nm and a groove (step) having a depth of 40 nm are formed. Thereafter, an SiO film (insulating film) 2 having a thickness of 500 nm is provided on the grooves M and N, an SiCN film (etching stopper film) 3 having a thickness of 50 nm is further provided, and an SiOC film (Low k film) having a thickness of 150 nm is provided. 4) Furthermore, a 50 nm thick SiO film (cap film) 5 was laminated. These films were formed by the plasma CVD method. Next, a resist film having a predetermined pattern is formed at a position different from the grooves M and N by using a mask for forming a wiring film, and a groove (groove) for the wiring film having a predetermined pattern is formed by etching using the resist film as a mask. Depth: 200 nm). Thereafter, ashing and cleaning were performed. Then, a Cu diffusion barrier film 6 was formed by providing a 10 nm thick TaN film and a 10 nm thick Ta film by sputtering. After the formation of the Cu diffusion barrier film 6, the wafer was conveyed in vacuum, and a Cu seed film was continuously provided by a 60 nm thick sputtering method. Thereafter, a Cu film 7 having a thickness of 540 nm was provided by a plating method. Then, a hydrogen annealing treatment was performed at 220 ° C. for 60 seconds. As a result, an evaluation substrate A having a predetermined wiring film (wiring film constituting groove depth: 200 nm) pattern and predetermined groove M (depth: 20 nm), N (depth: 40 nm) pattern was produced. .

  An evaluation substrate B was produced in the same manner as the evaluation substrate A. Note that the depths of the grooves M and N of the evaluation substrate A were 20 nm and 40 nm, whereas the evaluation substrate B was different in that grooves having a depth of 60 nm and 80 nm were formed. (That is, the difference is that the thickness of the SiCN film provided first is 60 nm in order to form a groove having a depth of 60 nm). Substrate B was produced.

  Then, CMP was performed as follows. As the slurry, a commercially available slurry for Cu using silica-based abrasive grains was used. When performing Cu polishing, a hydrogen peroxide solution having a concentration of 30 wt% was previously mixed with the slurry. The polishing conditions are as follows. Polishing pressure: 7 kPa, platen rotation speed: 60 rpm, head rotation speed: 61 rpm, slurry flow rate: 300 cc / min. Polishing was performed using a slurry in which the mixing ratio of the slurry and the hydrogen peroxide solution was 8: 2 from the start of polishing until the Cu remaining film thickness became 300 nm (half). Slurry supply was stopped when the Cu remaining film thickness reached 300 nm (half), and the slurry on the pad was once washed away with pure water, and then the mixing ratio of the slurry and hydrogen peroxide solution was 4 by weight. : The slurry made into 6 was supplied and it grind | polished. The condition that the mixing ratio of the slurry and the hydrogen peroxide solution is 8: 2 is a condition that the pattern dependency of the polishing rate is small and the uniformity of the polishing rate within the wafer surface is good. On the other hand, when the mixing ratio is 4: 6, the pattern dependency of the polishing rate is large, but the step resolution is good and the dishing increase during over-polishing is small. This makes it possible to achieve both good flatness and Cu residue elimination. The polishing rate of the Cu blanket film at a mixing ratio of 8: 2 is 400 nm / min, and the polishing rate of the Cu blanket film at a mixing ratio of 4: 6 is about 300 nm / min.

  During polishing of the Cu film, the remaining Cu film thickness was monitored by an eddy current end point detector. From the output from the end point detector, it can be seen when the Cu remaining film thickness is 300 nm and when the Cu film is removed and the underlying barrier film is almost eliminated. FIG. 7 shows the output of the end point detector during polishing. After the unnecessary Cu film is almost removed, the output from the end point detector becomes almost constant. Accordingly, during the polishing under the second polishing condition, the slope of the output from the end point detector, that is, when the differential value becomes 0, is set as the end point, and the subsequent polishing time is set as the over polishing time. Over-polishing was continuously performed under the second polishing conditions. After polishing, the slurry on the pad and the substrate surface was washed away with pure water. Subsequently, the substrate was automatically conveyed to a platen for barrier polishing, and barrier film polishing was performed using a commercially available barrier slurry. The following conditions were used for the polishing conditions. Polishing pressure: 14 kPa, platen rotation speed: 60 rpm, head rotation speed: 61 rpm, slurry flow rate: 200 cc / min. Under these conditions, the polishing rate of the barrier film is 80 nm / min for both Ta and TaN, and the polishing rate ratio is barrier film: SiO film: Cu film = 2: 1: 0.2. After polishing, the pad and the substrate surface slurry are washed away with pure water, then the substrate is automatically transported to a cleaning device, brush cleaning using a commercially available chemical solution, ultrasonic cleaning is performed, followed by water cleaning and spin drying. .

  In Cu CMP, at the end point where the differential value of the output of the eddy current detector becomes 0, there is a possibility that an extremely thin Cu film remains on the barrier film. In particular, when there is unevenness on the base, Cu tends to remain in the recesses, and it is necessary to remove it by overpolishing. At this time, if the over-polishing time is too short, there is a possibility that the Cu residue cannot be completely removed. Conversely, if it is too long, dishing increases. Therefore, in order to examine the optimum over-polishing time when there is unevenness due to the lower wiring film, the above-described evaluation substrates A and B are used.

  CMP was performed with Cu film overpolishing times of 20 seconds, 40 seconds, 60 seconds, and 80 seconds on the evaluation substrates A and B. The polishing time for the Cu diffusion barrier film was 20 seconds and 30 seconds. Then, the flatness of the Cu wiring film pattern was measured and the remaining Cu in the dent pattern was observed. As the evaluation pattern, the L & S pattern having a wiring width of 100 μm shown in FIG. FIG. 8 shows the chip arrangement on the wafer, the flatness measurement position, and the Cu remaining observation chip. Tables 1 to 3 show the flatness measurement results of the substrates A and B subjected to CMP of the Cu film and the Cu diffusion barrier film under the above eight conditions, and the observation results of the remaining Cu. The dishing amount indicates an average value of the measurement results of the substrates A and B. The state of remaining Cu is observed for each L & S pattern having a constant wiring occupancy and groove depth, and it is determined that there is no remaining Cu in all 11 chips shown in FIG. If Cu remains even in one of 11 chips, it is determined that there is Cu remaining. Tables 1 to 3 show the maximum groove depths of the recess patterns with no Cu residue. In any polishing condition and pattern, Cu is removed in the recess pattern shallower than the groove depth, and conversely, Cu residue is generated in the recess pattern deeper than this. Tables 1 to 3 show the evaluation results for patterns with pattern occupancy rates of 10%, 50%, and 91%. Since the groove depth of the shallowest concave pattern among the produced patterns is 20 nm, when Cu residue is generated in the pattern, it is a lower step that the Cu residue is removed. Therefore, in this case, <20 is indicated.

表−２（パターン占有率５０％のＬ＆Ｓの平坦性とＣｕ残り評価結果）

表−３（パターン占有率９１％のＬ＆Ｓの平坦性とＣｕ残り評価結果）

Table 1 (L & S flatness with 10% pattern occupancy and Cu remaining evaluation result)

Table-2 (L & S flatness with 50% pattern occupancy and Cu remaining evaluation results)

Table 3 (L & S flatness of pattern occupancy 91% and Cu remaining evaluation result)

  In all pattern occupancy ratios shown in Table-1 to Table-3, the maximum groove depth of the concave pattern having no Cu residue is equal to or larger than the dishing amount because the Cu over polishing time is 60 seconds or more, It can be seen that the barrier polishing time is 20 seconds and 30 seconds. Then, CMP under such polishing conditions is appropriate (optimal) CMP. In particular, under the CMP conditions with a barrier polishing time of 30 seconds, the Cu residue of the recessed pattern larger than the dishing amount by 10 nm or more is removed, and it is considered that the margin is large with respect to the Cu remaining removal property of the recessed portion by dishing of the lower layer wiring. It is done.

  From the results shown in Tables 1 to 3, it is considered that the longer the Cu over polishing time and the barrier polishing time, the wider the margin with respect to the remaining Cu. However, the longer the polishing time, the greater the amount of chipping of the Cu wiring film, leading to an increase in wiring resistance. Therefore, it is considered that the CMP condition for removing the Cu residue in the groove having the step amount of about 1.0 to 1.6 as the dishing amount is most suitable.

  As described above, when the above-described CMP conditions are applied to the formation of the multilayer wiring film, the over-polishing time for each layer is constant, so that the dishing of the wiring film in each layer is kept substantially constant. Further, since the Cu residue of the recessed pattern deeper than the dishing depth of the lower wiring film can be removed, it is considered that there is a sufficient margin with respect to the Cu residue.

  Then, by performing CMP with the above optimal Cu over-polishing time and Cu diffusion barrier film polishing time, whether or not a multilayer wiring film can be formed is actually confirmed. From the 90 nm / 90 nm L & S to 25 μm / As a result of forming a 6-layer wiring film having various L & S patterns up to 25 μm L & S and measuring the dielectric breakdown voltage between the wirings of the 6th layer wiring, there is no short circuit between the wirings, and the yield is 100% good. Results were obtained.

  On the other hand, in order to perform the same examination with the conventional method, it is necessary to form the upper layer wiring film after CMP of the lower layer wiring film, and perform CMP again, so that quick evaluation can be performed. Absent. In addition, since it is impossible to confirm a margin that indicates how deep Cu can be removed in comparison with the dishing amount of the lower wiring film, it is not possible to set appropriate polishing conditions.

Cross-sectional structure of evaluation pattern Step formation procedure for evaluation pattern Example of evaluation pattern Schematic diagram of CMP equipment Definition of flatness of L & S pattern Definition of flatness of isolated patterns Output of eddy current end point detector Flatness measurement position and Cu remaining observation tip position

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Insulating film 2 for base level | step differences Insulating film 3 Etching stopper film 4 Low k film 5 Cap film 6 Cu diffusion barrier film 7 Cu film

Representative Katsumi Udaka

Claims (8)

An evaluation substrate used for evaluating the conditions of CMP performed to form a plurality of wiring films in a vertical direction in a semiconductor element,
A substrate,
A first groove corresponding to a groove for forming a wiring film in a semiconductor element having a depth of A formed in the substrate;
A second groove having a depth B formed on the substrate from the same reference surface as the first groove;
A wiring film material provided in the first groove and the second groove;
The evaluation substrate, wherein the depth B of the second groove is 5 to 60% of the depth A of the first groove. The evaluation substrate according to claim 1, wherein the depth B of the second groove is 10 to 40% of the depth A of the first groove . The evaluation substrate according to claim 1 or 2, wherein the first groove and the second groove do not overlap in the vertical direction . Further comprising a groove similar to the second groove except for the depth,
4. The evaluation substrate according to claim 1, wherein the groove has a depth of 5 to 60% of a depth A of the first groove. The evaluation substrate according to any one of claims 1 to 4, wherein the first groove and the second groove have the same planar shape. The evaluation substrate according to any one of claims 1 to 5, wherein the first groove and the second groove are L & S patterns or isolated patterns. The evaluation substrate according to any one of claims 1 to 6, wherein the second groove is formed beside the first groove . A CMP step of CMPing the evaluation substrate according to claim 1;
Whether the wiring film material provided in the second groove is removed at the depth of the dishing of the wiring film material provided in the first groove after the CMP process or deeper than the depth of the dishing. A CMP condition evaluation method comprising: a determination step of determining whether or not.

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