JP2007109989A - Cmp method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low-cost method for both reducing dishing after a CMP of a Cu wiring film and removing residual Cu. <P>SOLUTION: This CMP method comprises a first step of conducting the CMP under the condition of a ratio (V1/V2) between a polishing speed V1 in a concavo-convex region, and a polishing speed V2 in a flat region, in a CMP initial stage with large surface irregularity ranging from 0.8 to 1.1; and a second step after the first step for conducting the CMP under the condition of the ratio (V1/V2) between the polishing speed V1 in the concavo-convex region and the polishing speed V2, in the flat region ranging not less than 1.2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a CMP method. In particular, the present invention relates to a CMP method used for forming a wiring film structure (damascene wiring film structure) of a semiconductor device. Furthermore, the present invention relates to a CMP method capable of providing a semiconductor device having a Cu damascene wiring structure satisfying both excellent flatness and Cu remaining removal performance in a polished region at a low cost.

  In the CMP (Chemical Mechanical Polishing) process for Cu and barrier film used in the formation of LSI multilayer wiring, the film thickness of the Cu wiring film is increased over a wide range from fine wiring of 0.1 μm or less to global wiring of about 100 μm. There is a demand for constant control. That is, the dishing and erosion of Cu and the barrier film generated in the CMP process are important fluctuation factors of the Cu wiring film thickness, and therefore a CMP technique for reducing these amounts is required.

  In the Cu wiring film forming process, a Cu diffusion barrier film is provided on the substrate on which the wiring groove is formed, and then a Cu seed film is formed. Subsequently, the Cu film is formed by a plating method to a wiring groove depth of 1.5-3. It is about twice as thick. Thereafter, a Cu wiring film is formed using a CMP technique. In this CMP step, the Cu film other than the portion that becomes the wiring is first polished and removed using a slurry for Cu, and once the lower barrier film is exposed, the polishing is temporarily stopped. A method of polishing and removing the barrier film using a different slurry is common. In such a CMP technique, when the Cu film is removed and the barrier film is exposed, the deterioration of flatness due to dishing and erosion is small, and excess Cu other than the portion that becomes the wiring is completely removed. This is very important.

  Although a method has been proposed in which the Cu film is partially left in the state after Cu polishing and the Cu film remaining at the time of barrier polishing is simultaneously polished, in this case, the polishing rate of the barrier film and the Cu film is increased. It is necessary to set the ratio to 1: 1, which increases the amount of Cu polishing during barrier polishing, resulting in deterioration in flatness and increase in wiring resistance.

Incidentally, the flatness and the removability of the remaining Cu are usually in a trade-off relationship.
It is becoming more and more difficult to make these two characteristics compatible as LSIs become finer. And so far, although device manufacturers, equipment manufacturers, material manufacturers, etc. have studied each, a technology that achieves both characteristics has not been proposed yet.

For example, Japanese Patent Laid-Open No. 2000-301454 “Chemical Mechanical Polishing Process and its Components” proposes a method for reducing dishing by polishing an insulating film under the barrier film simultaneously in polishing the barrier film. .
However, it is necessary to increase the depth of the wiring groove in accordance with the dishing amount at the stage when Cu polishing is completed. If the dishing amount is large, the load on the film forming and etching processes increases, and the process cost is increased. Increase. Also, since the dishing amount usually varies depending on the groove width, if the insulating film is polished until the dishing of the wide wiring portion becomes small, the wiring portion becomes convex with respect to the insulating film in the narrow wiring portion and becomes flat. Sexuality is impaired. For this reason, it is difficult to obtain good flatness with different wiring widths.

Also, US Patent 6,602,724 B2 “Chemical
“Mechanical Polishing of a Metal Layer With Polishing Rate Monitoring” proposes a method in which a Cu film is polished to a certain thickness and then polished at a lower polishing rate.
However, with this technique, a significant improvement in dishing amount cannot be expected, and it is difficult to achieve the dishing amount required for miniaturized LSIs.

Also, Japanese Patent Laid-Open No. 2001-85378 “Conductor device and manufacturing method thereof” proposes a technique for polishing a Cu film using several types of slurry having different dispersibility of abrasive grains in accordance with the surface state of a wafer. ing.
According to this technique, in the stage where the unevenness of the surface at the initial stage of polishing is large, the surface is flattened by removing the convex portion by a physical action using a slurry having low dispersibility of the abrasive grains, and then the dispersibility is It is said that a good surface state can be obtained by polishing with a large slurry using a small physical action.
However, as a result of investigations by the present inventors, when polishing is performed in a state where the mechanical action is strong at the stage where the surface unevenness is large, the difference in the polishing rate due to the depth and density of the surface unevenness increases, resulting in barrier It has been found that Cu remains partially thick when the film is exposed, and Cu residue is likely to occur after polishing. It has also been found that if the underlying barrier film is exposed during polishing with a weak mechanical action, dishing of the Cu wiring film increases. Therefore, it is difficult to obtain good flatness with this technique.
JP 2000-301454 A US Patent 6,602,724 B2 JP 2001-85378 A

  As described above, with the miniaturization of LSI, it is required to reduce the dishing after CMP of the Cu wiring film, but as the dishing is reduced, the trade-off with Cu residual removal becomes remarkable, It was difficult to achieve both the target dishing amount and the Cu residual removal ability.

Therefore, the problem to be solved by the present invention is to solve the above problems.
That is, it is to provide a technique that realizes both the reduction of dishing after CMP of the Cu wiring film and the removal of residual Cu at a low cost.

  Now, in general, CMP of Cu proceeds by removing the reaction layer formed on the Cu surface by friction with abrasive grains and pads. In the present specification, the mechanical action means the action of removing the reaction layer by friction with such abrasive grains and pads. By the way, the hardness of the reaction layer formed on the Cu surface varies depending on the slurry. When the reaction layer is strong, a strong mechanical action is required to remove the reaction layer. In this case, the stronger the mechanical action, the faster the removal rate of the reaction layer and the higher the polishing rate. When a wafer having irregularities on the surface is polished under such conditions, the polishing rate of the convex portions in the region having the concavo-convex pattern is faster than the polishing rate in the region having no concavo-convex pattern. On the contrary, the polishing rate of the concave portion in the region where the concave / convex pattern is present is slower than the region where the concave / convex pattern is present, but when the reaction layer is strong, the polishing rate of the convex portion in the region where the concave / convex pattern is present is The effect of increasing the speed is superior, and the average polishing rate in the region where the uneven pattern is present is faster than the polishing rate in the region where the uneven pattern is not present. In this case, an L & S (Line and Space) having a wiring width / space width of about 10 μm / 10 μm is assumed as a pattern of the region having the uneven pattern. The state where the polishing rate is higher in the region with the concavo-convex pattern than the region without such a concavo-convex pattern, in the sense that the dependency of the polishing rate on the mechanical action is strong, `` the state where the mechanical action dependency is strong '' I will call it.

  As the strength of the surface reaction layer changes from a strong state to a weak state, the polishing rate difference between the convex portions in the region without the uneven pattern and the region with the uneven pattern decreases. Even if the polishing rate of the convex part is higher than the polishing rate of the region without the concave / convex pattern, the average polishing rate in the concave / convex pattern region is no uneven pattern as long as it is offset by the slow polishing rate of the concave part. The polishing rate in this region is almost the same. Such a state in which the strength of the surface reaction layer is slightly weak and the polishing rate of the region having no concavo-convex pattern and the region having the concavo-convex pattern is substantially the same is referred to as a “mechanical action-dependent state”. To do.

  When the strength of the surface reaction layer is further weakened, the reaction layer is removed by a very weak mechanical action, so the polishing rate of the protrusions and recesses in the area where there is no uneven pattern and the area where the uneven pattern is present is almost the same. become. Also in this case, the polishing rate in the region with the concavo-convex pattern is almost the same as the polishing rate in the region without the concavo-convex pattern. However, if the polishing is performed in this state, the polishing proceeds without any surface irregularities being eliminated, and the flatness is extremely deteriorated. Therefore, normal CMP is not performed in such a state.

  Whether the dependence of the polishing rate on the mechanical action is large or small depends on the balance between the strength of the reaction layer on the Cu surface and the strength of the mechanical action received from the abrasive grains and the pad. Accordingly, it is considered that the strength of the mechanical action dependency varies depending on the chemical component of the slurry, the type and amount of abrasive grains, the hardness of the pad, and the like.

  In order to reduce the difference in the polishing rate due to the unevenness of the surface, it is necessary to polish in a state where the mechanical action dependency is weak. Under these conditions, the difference in polishing rate due to the unevenness on the surface is small, but the difference in polishing rate between the recesses and the protrusions in the uneven pattern is also smaller than in the state where the mechanical action dependency is strong, so the level difference resolution is poor. Therefore, when polishing is performed under this condition, the underlying barrier film is exposed while the level difference due to the surface irregularities is not sufficiently eliminated, and as a result, flatness is impaired. In order to compensate for the lack of step resolution, it is necessary to increase the film thickness of Cu, but the film formation time and CMP time become longer and the cost increases. When polishing is performed until the underlying barrier film is exposed under such conditions, local Cu residue is unlikely to occur. However, since the difference in polishing rate between the concave and convex portions in the uneven pattern region is small, the increase in dishing due to over polishing after the base is exposed increases. The situation of this problem is shown in FIG.

  In order to improve the level difference elimination with respect to fine irregularities, it is necessary to polish in a state where the mechanical action dependency is strong. In this state, the difference in polishing rate between the concave and convex portions in the concave and convex pattern region is large, so that the level difference elimination is improved. However, if polishing is performed in this state from the initial stage of polishing with a large surface unevenness, the difference in polishing rate due to the surface unevenness is large, so the Cu film thickness becomes non-uniform. That is, when polishing is performed until the underlying barrier film begins to be exposed under such conditions, a thick Cu residue is locally generated in a region where the polishing rate is low. It has been clarified by the inventor's examination that the removal of the locally thick Cu residue by over-polishing increases the wiring dishing in the region where the barrier film has been previously exposed. This malfunction situation is shown in FIG. And in the state where the mechanical action dependence is strong, the polishing rate difference between the concave and convex portions in the concave and convex pattern region is large, so the increase in dishing during over polishing should be suppressed to a small level, but remained locally. When the Cu film is thick, it is difficult to completely remove the Cu residue while suppressing an increase in dishing.

  Now, polishing conditions with a small difference in polishing speed due to unevenness of the surface and polishing conditions with good step resolution are a state where the mechanical action dependency is weak and a state where the mechanical action dependency is strong, respectively. Balancing is considered difficult. This is considered to be an essential cause until now, in Cu CMP, it has been difficult to achieve both dishing reduction and Cu remaining removability.

  As a result of further intensive investigations based on the above knowledge, a two-step polishing method using the first polishing condition and the second polishing condition described below has good flatness and Cu It has been found that it is extremely effective as a means for achieving balance with the remaining removability.

  Here, the first polishing condition is a polishing condition in which the mechanical action dependency is weak. The step resolution in a state where the mechanical action dependency is weak is inferior to that in the state where the mechanical action dependence is strong, but at the initial stage of polishing where the level difference is large, sufficient level difference resolution is exhibited. Thereby, it is possible to eliminate the level difference while keeping the difference in polishing rate due to the unevenness of the surface small.

  The second polishing condition is a polishing condition in which the mechanical action dependency is strong. Under this condition, the difference in polishing rate between the concave and convex portions in the concave / convex pattern region is large, so that a minute step that is not flattened under the first condition can be eliminated. At this stage, since the unevenness on the wafer surface is reduced to some extent by polishing under the first polishing condition, the difference in the polishing rate due to the unevenness on the surface is kept small even when polishing is performed with a strong mechanical action dependency. Be drunk. Further, even after the barrier film is exposed, the difference in polishing rate between the concave and convex portions in the concave and convex pattern region is large, so unnecessary Cu is removed while suppressing an increase in dishing. The polishing situation under such conditions is shown in FIG.

  Then, by polishing using the first and second polishing conditions, the difference in polishing rate due to surface irregularities is always kept small from the initial stage of polishing until the barrier film is exposed. As a result, the variation of the Cu film thickness within the wafer surface when the barrier film begins to be exposed is small, and local thick Cu residue does not occur. That is, when the base barrier film begins to be exposed, the step amount can be reduced without generating a local thick Cu residue. Therefore, Cu residue can be completely removed by short-time overpolishing. Note that the second polishing condition has a large polishing rate difference between the concave and convex portions in the concavo-convex pattern region, so that the fine level difference that has not been flattened under the first polishing condition is eliminated. Unnecessary Cu can be removed while suppressing the increase. That is, in the over polishing, the Cu residue can be completely removed by polishing for a short time under the condition that the dishing is difficult to increase. Therefore, both the removal of the Cu residue and the reduction of the dishing can be achieved.

The present invention has been made based on the above findings.
That is, the above-mentioned problem is in the CMP method.
A first step of performing CMP under conditions of a substantially uniform polishing rate over the entire surface;
After the first step, the present invention is solved by a CMP method comprising: a second step of performing CMP under a condition in which the unevenness unevenness elimination property is excellent.

In the CMP method,
A first step of performing CMP under a condition where the difference between the polishing rate V1 in the uneven region and the polishing rate V2 in the flat region is small;
After the first step, there is provided a second step in which CMP is performed under a condition in which the difference between the polishing rate V1 in the uneven region and the polishing rate V2 in the flat region is larger than the polishing rate difference in the first step. It is solved by the CMP method characterized by the above.

In the CMP method,
A first step in which CMP is performed under a condition where the ratio (V1 / V2) of the polishing rate V1 in the uneven region to the polishing rate V2 in the flat region is 0.8 to 1.1;
After the first step, there is provided a second step in which CMP is performed under a condition where the ratio (V1 / V2) of the polishing rate V1 in the uneven region to the polishing rate V2 in the flat region is 1.2 or more. This is solved by the CMP method.
In particular, in the CMP method,
CMP is performed under the condition where the ratio (V1 / V2) of the polishing rate V1 in the uneven region to the polishing rate V2 in the flat region is 0.9 to 1.1 (among these, 0.95 or more and 1.05 or less). The first step;
After the first step, the ratio (V1 / V2) between the polishing rate V1 in the uneven region and the polishing rate V2 in the flat region is 1.2 to 10 (in particular, 1.25 or more, especially 1.3 or more. The second step of performing CMP under the conditions of 1.5 or more, 5 or less, particularly 3 or less, 2 or less, and even 1.85 or less. This is solved by the CMP method.

In the CMP method,
In the initial stage of polishing (first step) where the surface irregularities are large, polishing is performed until the Cu film has a constant film thickness under the first polishing condition where the polishing rate difference due to the depth and density of the irregularities is small
Thereafter (second step), in order to flatten the fine irregularities on the surface, the problem is solved by a CMP method characterized by polishing under a second polishing condition with good step resolution.

Also, the above CMP method,
The first step is solved by a CMP method characterized in that the step is performed until the step becomes 1/10 to 2/3 (more preferably, ½ or less) of the step initial value.

Also, the above CMP method,
The first step is solved by a CMP method characterized in that the first step is performed in a CMP initial stage having a large degree of surface irregularity.

  Further, the problem is solved by the above-described CMP method, which is used when forming a wiring film structure of a semiconductor device.

  According to the present invention, it is possible to reduce the dishing of the Cu wiring film after CMP and to remove the Cu residue. Moreover, since the technical means for this purpose is simple, it can be carried out at a low cost. Moreover, it can also be carried out using a conventional CMP apparatus. That is, there is no need for extensive equipment renewal. Therefore, a high-performance semiconductor device can be obtained at a low cost.

  The CMP method of the present invention (in particular, the CMP method used for forming a wiring film structure of a semiconductor device) includes a first step of performing CMP under conditions of a substantially uniform polishing rate over the entire surface, and a step after the first step. And a second step of performing CMP under the condition that the unevenness unevenness elimination property is excellent. Alternatively, the first step of performing CMP under a condition where the difference between the polishing rate V1 in the uneven region and the polishing rate V2 in the flat region is small, and after the first step, the polishing rate V1 in the uneven region and the polishing rate in the flat region. And a second step of performing CMP under a condition where the difference from V2 is larger than the polishing rate difference in the first step. Alternatively, the ratio (V1 / V2) between the polishing rate V1 in the uneven region and the polishing rate V2 in the flat region is 0.8 to 1.1 (in particular, 0.9 or more, especially 0.95 or more. The ratio (V1 / V2) between the polishing rate V1 in the uneven region and the polishing rate V2 in the flat region is 1.2 or more after the first step in which CMP is performed under the condition of 05 or less. Among them, 1.25 or more, especially 1.3 or more, further 1.5 or more, and 10 or less, especially 5 or less, especially 3 or less, further 2 or less, and further 1.85. The second step of performing CMP under the following conditions). Alternatively, in the initial stage of polishing (first step) with large surface irregularities, polishing is performed until the Cu film reaches a certain thickness under the first polishing condition where the difference in polishing rate due to the depth and density of the irregularities is small. (2nd step) In order to flatten the fine irregularities on the surface, polishing is performed under the second polishing conditions with good step resolution. The first step is performed until the step becomes 1/10 to 2/3 (particularly, ½ or less) of the step initial value. The first step is performed in the initial stage of CMP having a large surface irregularity.

  This will be described in more detail below.

  FIG. 4 is a schematic view of a CMP (Chemical Mechanical Polishing) apparatus used in the practice of the present invention. That is, the head holding the substrate to be polished is pressed against the platen to which the polishing pad is attached, and the polishing is performed while rotating the head and the platen in the same direction while supplying the slurry to the pad surface. Yes. A commercially available polyurethane foam pad can also be used as the pad. There are two slurry supply systems, and two types of slurry can be supplied. Pressing a disk with diamond grains embedded on the surface against the polishing pad and rotating the disk and platen to scrape off the pad surface prevents clogging of the pad surface due to abrasives from reactants and slurry from polishing. it can. This can be done during polishing or between polishings as required. The film thickness change of the Cu film during polishing can be detected by an eddy current type end point detector installed on the platen. As a result, the film is polished to a certain film thickness under the first condition, and once the polishing is stopped, the polishing can be performed under the second polishing condition. Further, the end point when the Cu film is removed and the barrier is exposed can be detected, and the time of the subsequent overpolishing can be controlled to be constant.

  This polishing apparatus has a platen and a head different from those for Cu polishing for performing barrier polishing following Cu polishing. Using this, barrier polishing can be carried out with the slurry for the barrier. If necessary, Cu polishing and barrier polishing can be continuously processed by automatic conveyance, or only Cu polishing and barrier polishing can be performed alone. In addition, after polishing, chemical cleaning, ultrasonic cleaning, and the like are performed as necessary by automatic conveyance, and then the wafer is spin-dried to complete the processing.

  FIG. 5 is a cross-sectional view of the substrate to be polished. In this substrate, an etch stopper layer and an insulating film layer are formed on a Si substrate, and after forming a photoresist pattern, a wiring groove is formed by etching. After etching, the remaining photoresist is removed by ashing, and cleaning is performed to remove the residue. Subsequently, after forming a Cu barrier film and a Cu seed film by a sputtering method, a Cu film is formed by a plating method. Then, hydrogen annealing is performed. The Cu film thickness is usually about 1.5 to 3 times the wiring groove depth, and is also in the present invention.

FIG. 6 is a schematic view of a TEG (Test Element Group) chip formed on the surface of the substrate to be polished. The chip size is 32 mm long and 26 mm wide. In the chip, flatness measurement L & S (Line) with various wiring widths and wiring densities
and Space) pattern, electrical characteristic measurement pattern, film thickness measurement region, and the like. The film thickness measurement region is composed of two regions, a region without a wiring pattern (uneven pattern) and a region with a wiring pattern (uneven pattern). Each region is a rectangle of 6 mm length and 12 mm width, and is a 4-probe sheet. The Cu film thickness can be measured with a resistance meter. The film thickness measurement region is used to measure the difference in Cu polishing rate depending on the presence or absence of a wiring pattern. An L & S having a wiring width of 10 μm and a space width of 10 μm was formed on the entire surface in the wiring pattern area. In the L & S having a wiring width and a space width of 1 μm or less, since the recessed portion is narrow, the depth of the unevenness on the surface after plating is smaller than the wiring groove depth. Further, when the wiring width and the space width are about 100 μm, the width of the convex portion and the concave portion is wide, so that the wiring pattern is almost absent and the influence of the mechanical action is considered to be small. Therefore, it is considered that the difference in the polishing rate from the non-patterned region due to the surface unevenness is L & S of about 5 to 50 μm.

  In an actual LSI, various irregularities exist because the wiring from 0.1 μm or less to about 100 μm is irregularly arranged. For the above reason, the polishing speed depends on the mechanical action dependence of the polishing speed. It is expected that the variation becomes large when there is unevenness having a width of about 5 to 50 μm.

  CMP polishing is performed until the polishing rate is measured using an eddy current type end point detector, and the remaining Cu film thickness reaches a predetermined film thickness. FIG. 7 shows the output of the eddy current type end point detector. Polishing can be automatically terminated when the output of the detector reaches an output value corresponding to a certain film thickness. The polishing rate was calculated by dividing the difference in film thickness before and after polishing between the region with and without the wiring pattern measured with a 4-probe sheet resistance measuring instrument by the time required for polishing. The alignment direction of the four-probe needles in the measurement of the region with the wiring pattern was perpendicular to the length direction of the wiring. There are no particular restrictions on the direction of needle alignment during measurement, but it is desirable to have the same orientation before and after polishing. The amount of polishing at the time of measuring the polishing rate is not particularly limited as long as it is about 0.5 to 2 times the wiring groove depth. However, it is desirable that the polishing amount when measuring the step resolution is about 1 to 2 times the wiring groove depth.

  Various L & S patterns in the TEG chip can be used for measuring the flatness. A stylus type step meter is used as the measuring device. Since the dishing after polishing becomes larger as the wiring width is wider, the dishing of a pattern having a wiring width of 100 μm and a space width of 100 μm was measured. A normal LSI is considered to have the maximum wiring width. An overview of the L & S pattern used for the measurement is shown in FIG. In the pattern of FIG. 8, the definition of flatness when the underlying barrier film is exposed and when it is not exposed is shown in FIG.

  Hereinafter, specific examples will be described.

[Example]
A 300 mmφ Si wafer was used as the substrate, and the required number of substrates to be polished having the cross-sectional structure shown in FIG. The etch stopper film was a 50 nm thick SiCN film, and the insulating film was a two-layer structure in which a 50 nm thick SiO film was laminated on a 150 nm thick SiOC film. The Cu barrier film has a two-layer structure in which 10 nm thick Ta is laminated on 10 nm thick TaN. Then, a Cu seed film having a thickness of 60 nm was formed on the Cu barrier film by a sputtering method, and then a Cu film having a thickness of 540 nm was formed by a plating method. Then, a hydrogen annealing process was performed at 220 ° C. for 60 seconds. The substrate thus obtained is designated as substrate 1.

  As the slurry, a commercially available slurry for Cu using silica-based abrasive grains was used. When performing Cu polishing, hydrogen peroxide water was mixed with the slurry in advance.

  The polishing conditions are a polishing pressure of 7 kPa, a platen rotation speed of 60 rpm, a head rotation speed of 61 rpm, and a slurry flow rate of 300 cc / min. The film thickness change during polishing was monitored by an eddy current type end point detector, and the polishing was terminated when the remaining Cu film thickness was about 300 nm. After polishing, the slurry on the pad and wafer surface was washed away with pure water, and then the substrate was automatically transported to a cleaning device, followed by brush cleaning and ultrasonic cleaning using a commercially available chemical solution, followed by water cleaning and spin drying.

  The substrate 1 was polished using a slurry in which the mixing ratio of the hydrogen peroxide solution having a concentration of 30 wt% and the slurry was mixed in a weight ratio of 2: 8 to 7: 3. The Cu film thickness before and after polishing was measured, and the polishing rate was calculated. The remaining Cu film thickness was measured at 12 points each in the diametrical direction and linearly, with and without the wiring pattern. The arrangement of TEG chips on the substrate and the film thickness measurement points are shown in FIG. Using the same substrate, the step amount of the L & S pattern of 100 μm / 100 μm was measured. The level difference was measured for five patterns with distances from the wafer center of 1 cm, 6 cm, 11 cm, 13.5 cm, and 14.5 cm. The average value of the measurement results is shown in Table-1.

表−１の結果から、２段階の研磨をする場合、最初の第１の研磨条件としては、凹凸パターン在り領域の研磨速度と凹凸パターン無し領域の研磨速度との差が小さい条件１や条件２が適しており、後の第２の研磨条件としては、段差解消性が良い条件４〜６が適していると考えられる。条件１，２は、凹凸パターン在り領域の研磨速度と凹凸パターン無し領域の研磨速度差が小さい（研磨速度比がほぼ１）ことから、機械的作用依存性が弱い状態になっている。そして、過酸化水素水の混合割合が大きくなるに伴って、研磨速度比が大きくなることから、機械的作用依存性が強い状態に変わると考えられる。又、過酸化水素水の混合割合が大きくなるに伴って、段差解消性が良くなる。このことからも、機械的作用依存性が強い状態に変わることが判る。第１の条件としては、或る程度の段差解消性が必要であるが、条件１，２では、初期段差２００ｎｍに対して研磨後の段差量は５５ｎｍ，２５ｎｍであり、十分な段差解消性を有すると考えられる。 Table-1

From the results shown in Table 1, when performing two-step polishing, the first first polishing condition is condition 1 or condition 2 in which the difference between the polishing rate in the region with the uneven pattern and the polishing rate in the region without the uneven pattern is small. It is considered that Conditions 4 to 6 having good step resolution are suitable as the subsequent second polishing conditions. Conditions 1 and 2 are in a state where the dependency on the mechanical action is weak because the difference between the polishing rate in the region with the uneven pattern and the polishing rate in the region without the uneven pattern is small (the polishing rate ratio is approximately 1). As the mixing ratio of the hydrogen peroxide solution increases, the polishing rate ratio increases, so that the mechanical action dependency is considered to change to a strong state. Further, as the mixing ratio of the hydrogen peroxide solution is increased, the step resolution is improved. This also indicates that the mechanical action dependency is changed to a strong state. As the first condition, a certain level of level difference elimination is necessary, but in conditions 1 and 2, the level difference after polishing is 55 nm and 25 nm with respect to the initial level 200 nm, and sufficient level difference resolution is achieved. It is thought to have.

  Further, two-stage polishing was performed using the unpolished substrate 1. Using condition 1 as the first polishing condition, polishing was performed until the Cu remaining film thickness reached 300 nm. Thereafter, in order to temporarily stop polishing, the supply of slurry was stopped, and the slurry on the pad was washed away with pure water. Subsequently, using condition 4 as the second polishing condition, polishing was performed until the barrier film was exposed. After the barrier film was exposed, overpolishing was performed for 20 seconds under the same conditions. The time when the remaining Cu film thickness reached 300 nm and the time when the barrier film was exposed were detected by an eddy current end point detector. FIG. 11 shows the output of the end point detector during polishing. After the unnecessary Cu film is almost removed, the output from the end point detector becomes almost constant. Accordingly, during polishing under the second polishing condition, the slope of the output from the end point detector, that is, the time when the differential value becomes 0 is set as the end point, and the subsequent polishing time is set as the over polishing time. At the end point when the differential value becomes 0, there is a possibility that an extremely thin Cu film remains on the barrier film. In order to remove it, overpolishing was performed. After over polishing, the slurry on the pad and the substrate surface was washed away with pure water. Subsequently, the substrate was automatically conveyed to a cleaning apparatus, and after brush cleaning and ultrasonic cleaning using a commercially available chemical solution, it was washed with water and spin-dried.

  Similarly, the substrate 1 was polished using Condition 1 as the first polishing condition and Conditions 5 and 6 as the second polishing condition.

As a result of measuring the flatness of the substrate 1 polished under the above three conditions (polishing conditions using conditions 4 to 5 as the second polishing conditions), the average value of the dishing amount of the 100 μm / 100 μm L & S pattern of each wafer is 20 to 20 Good results of 30 nm were obtained. Moreover, as a result of observing the substrate surface using visual observation and an optical microscope, it was confirmed that there was no Cu residue. Further, after polishing to the remaining Cu film thickness of 400 nm (polishing amount 200 nm) and 200 nm (polishing amount 400 nm) according to the first polishing condition (condition 1), polishing is performed under the second polishing condition (condition 4). In both cases, almost the same results were obtained.
Therefore, it has been found that there is no particular limitation if the polishing amount under the first polishing condition is in the range of 1 to 2 times the wiring groove depth.

Further, when the remaining Cu film thickness is polished to 400 nm by polishing under the first polishing conditions, the step amount of the 100 μm / 100 μm L & S pattern is 90 nm, and when the Cu remaining film thickness is polished to 200 nm, 100 μm. The step amount of the L & S pattern of / 100 μm was 40 nm.
Therefore, it has been found that it is sufficient that the amount of step difference is reduced to 1/2 or less of the initial step amount by polishing under the first polishing condition.

  Next, using a platen for barrier polishing, using a commercially available barrier slurry, barrier polishing of the substrate polished with Cu under the above three conditions (polishing conditions using conditions 4 to 5 as the second polishing conditions) was performed. did. After polishing, the slurry on the surface of the pad and the substrate was washed away with pure water, and then the substrate was automatically transported to a cleaning device, followed by brush cleaning and ultrasonic cleaning using a commercially available chemical solution, followed by washing with water and spin drying. As a result of measuring the flatness after polishing, the average dishing amount of the 100 μm / 100 μm L & S pattern was 10 to 20 nm. The polishing rate ratio between the barrier film, the insulating film, and the Cu film under the barrier polishing conditions used is about 2: 1: 1, and the barrier film polishing rate is higher than the Cu film polishing rate. The dishing is smaller than after Cu polishing. The target value of flatness is about 10% or less of the wiring groove depth, and is 20 nm or less in this case. The above results meet this goal. In addition, it was confirmed that the same flatness can be obtained even when Cu polishing and barrier polishing are successively processed.

  In order to measure the electrical characteristics of the Cu wiring, Cu polishing was performed under the above three conditions, and a substrate that was continuously subjected to barrier polishing was produced. After forming a Cu diffusion barrier film and a passivation film on the substrate, the pad portion was opened, and a Ti and Al film was formed and etched to form an Al pad. Thereafter, electrical characteristics were measured using an auto prober. As a result of measuring the wiring resistance of the folded pattern with a wiring length of 92 cm on all the 64 chips in the wafer surface with the L & S of 90 nm / 90 nm, the conduction yield was 100% and the width of the variation of the wiring resistance was 10%. In addition, as a result of performing a short check of a comb pattern with a facing length of 92 cm on 64 chips with 90 nm / 90 nm L & S, it was confirmed that the yield was 100% and there was no short circuit between wiring due to Cu remaining in the fine wiring part.

  As the first polishing condition in the two-stage polishing, a condition with a small polishing rate difference due to surface irregularities is suitable, but there has been no appropriate method for evaluating such a polishing rate difference. From this study, it was found that the method of measuring and comparing the polishing rate of the region having the concavo-convex pattern and the region having no concavo-convex pattern created in the chip is suitable as a method for evaluating the influence of the surface unevenness on the polishing rate. As the second polishing condition, a polishing condition having a strong mechanical action dependency is suitable. As a method for evaluating the dependency of the polishing rate on the mechanical action, a method of measuring the amount of level difference on the surface after polishing a certain thickness of Cu has been used. However, this method is not an effective method because it is easily affected by fluctuations in the polishing film thickness, and it takes time to measure, so it is difficult to increase the number of measurement points, and there are large variations in measurement results. . Further, it was found from this example that there is a correlation between the polishing rate in the region with the uneven pattern / the polishing rate in the region without the uneven pattern and the strength of the polishing rate on the mechanical action. In measuring the polishing rate ratio, since there is no problem like the method using the step measurement, it is considered to be extremely effective as a method for evaluating the dependency of the polishing rate on the mechanical action.

Similar results were obtained when condition 2 was used instead of condition 1 as the first polishing condition of the above three conditions. From this, the first polishing condition that requires a small difference in polishing rate due to unevenness on the surface is (polishing rate in the region with the uneven pattern) / (polishing rate in the region without the uneven pattern) as described above. When a simple polishing rate measuring method is used, polishing conditions that are in the range of 0.8 to 1.1 (among others 0.9 or more, especially 0.95 or more and 1.05 or less) are suitable. . In addition, as the first polishing condition, a certain level of step resolution is required. Under conditions 1 and 2, when the Cu film thickness is 300 nm with respect to the initial step of 200 nm, the step elimination amounts are 145 nm and 175 nm, respectively. Therefore, in the L & S of 100 μm / 100 μm, when Cu having a thickness of 1.5 times the initial step amount is polished, the step resolving property is sufficient if a step of 1/2 or more of the Cu polishing amount is eliminated. It is believed that there is.
Then, the step amounts after the Cu remaining film thickness is polished to 300 nm with respect to the initial step amount of 200 nm under the conditions 1 and 2 are 55 nm and 25 nm, respectively. If the level difference elimination property is too good, the polishing rate difference due to the unevenness of the pattern becomes large. Therefore, considering the above results, the level difference after polishing under the first polishing condition is 1/2 to the initial level difference. It is considered preferable to be eliminated to 1/10.

  Next, since favorable results were obtained by using the conditions 4 to 6 as the second polishing condition, the second polishing condition that requires step resolution is (polishing of the region with the uneven pattern). (Speed) / (Polishing speed of the region having no concave / convex pattern) is 1.2 or more (in particular, 1.25 or more, especially 1.3 or more. The polishing conditions are in the range of 0.5 or more, 10 or less, especially 5 or less, especially 3 or less, more preferably 2 or less, and even more preferably 1.85 or less.

  In the above embodiment, the first and second polishing conditions are different from each other in the mixing ratio of the hydrogen peroxide solution of the same slurry. However, if the characteristics required for the first and second polishing conditions are obtained. It is also possible to use different slurries for the first polishing condition and the second polishing condition. In that case, if two types of slurries are used on the same platen, and adverse effects on the process such as agglomeration of abrasive grain components are expected, the first polishing condition and the first polishing condition can be obtained using an apparatus having three platens. It is desirable to perform barrier polishing with a third platen after performing Cu polishing under the second polishing condition with a different platen. Even when one type of slurry is used with different mixing ratios of oxidizing agents as in this embodiment, Cu polishing under the first and second polishing conditions is performed on different platens using an apparatus having three platens. In that case, the throughput can be improved. Further, as in this embodiment, when one type of slurry is used with the mixing ratio of the oxidizing agent changed, even if the first and second polishing are performed with the same platen, there is no adverse effect on the process. Absent. Note that the use of only one type of slurry is advantageous in terms of process control and material cost.

  Next, for comparison, Cu polishing was performed only under Condition 1 until the barrier film was exposed. As a result, although no Cu residue was observed, the dishing of the 100 μm / 100 μm L & S pattern was as large as 60 nm.

  Further, as a result of polishing only under condition 5, it was found that the Cu residue could not be removed even after over-polishing for 40 seconds.

  Further, Cu polishing was performed only under conditions 2, 3 and 4. In either case, neither dishing reduction nor Cu remaining removal could be achieved.

Explanatory diagram of progress of CMP according to the present invention Description of the situation of defects in conventional CMP Description of the situation of defects in conventional CMP Schematic diagram of CMP equipment Cross section of substrate Schematic diagram of TEG chip Output of eddy current detector in film thickness measurement Schematic of L & S pattern for flatness measurement Illustration of flatness Arrangement of TEG chip on substrate and explanation of film thickness measurement points Output explanation diagram of eddy current detector in two-stage polishing Katsumi Utaka

Claims (6)

In the CMP method,
A first step of performing CMP under conditions of a substantially uniform polishing rate over the entire surface;
A CMP method comprising: a second step of performing CMP under the condition that the unevenness unevenness elimination property is excellent after the first step. In the CMP method,
A first step of performing CMP under a condition where the difference between the polishing rate V1 in the uneven region and the polishing rate V2 in the flat region is small;
After the first step, there is provided a second step in which CMP is performed under a condition in which the difference between the polishing rate V1 in the uneven region and the polishing rate V2 in the flat region is larger than the polishing rate difference in the first step. A CMP method characterized by the above. In the CMP method,
A first step in which CMP is performed under a condition where the ratio (V1 / V2) of the polishing rate V1 in the uneven region to the polishing rate V2 in the flat region is 0.8 to 1.1;
After the first step, there is provided a second step in which CMP is performed under a condition where the ratio (V1 / V2) of the polishing rate V1 in the uneven region to the polishing rate V2 in the flat region is 1.2 or more. CMP method.   4. The CMP method according to claim 1, wherein the first step is performed until the step becomes 1/10 to 2/3 of the step initial value.   5. The CMP method according to claim 1, wherein the first step is performed in an initial stage of CMP having a large surface roughness. 6. The CMP method according to claim 1, which is used for forming a wiring film structure of a semiconductor device.

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