JP2007188072A - Digital drive type display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive circuit having high reliability from a viewpoint of drive timing control in a display device employing a gradation expression by digital signals which are substantially free from problems of accuracy. <P>SOLUTION: A synchronizing circuit is fabricated by directly inputting the same clock signals to the all memory elements used for capturing external video signals, and an edge trigger flip-flop is employed to the memory element and is connected in series to configure a shift register. By subsequently inputting video signals of one row from an initial stage of the shift register, each flip-flop constituting the shift register synchronizes with rising (or falling) of a clock edge to capture data. Even when an operational frequency of a signal line drive circuit increases, timing of capturing video signals can be relatively easily controlled. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a digital drive type display device. In particular, the present invention relates to a configuration of a signal line driver circuit which writes a digital signal line-sequentially into a pixel portion in a digital drive display device.

  In order to perform multi-gradation display using an electro-optic element, it is necessary to express the gradation by some physical value and to control the element with appropriate means. For example, gradation is expressed by applying an analog voltage in a liquid crystal element and flowing an analog current in an organic EL element. However, the method using an analog value has a limit in its accuracy. In particular, in an active matrix display device using an organic EL element that has been actively developed in recent years, an analog current value is controlled using a TFT, and therefore variations in TFT characteristics directly affect display characteristics.

  On the other hand, a method has been proposed in which time is used as a physical value for expressing a gradation and the gradation is expressed using a kind of pulse width modulation. In other words, this is a method of expressing gradation with the light emission time of the electro-optic element. In this method, since the electro-optical element has only two states of light emission and non-light emission, there is essentially no problem of accuracy as in the case of controlling with an analog voltage or an analog current. Also, regarding the light emission time, if the gradation is expressed with a discrete value that is an integral multiple of a predetermined unit time, the electro-optical element can be driven without an analog value.

  When the method is realized, typically, gradation data is expressed in binary code, a holding period having a length proportional to the weight is set for each digit, and then a sub period consisting of a writing period and a holding period is set. A frame is formed for each digit. Then, each subframe is sequentially executed to form one frame, and gradation expression is realized with an integral value of the light emission time in one frame period.

  In addition, a method of using the light emitting area of the electro-optic element as a physical value expressing gradation is also proposed. In this method, a plurality of subpixels having different emission areas are provided, and one pixel is formed by a set of subpixels. The role of the subpixel in this method corresponds to the role of the subframe in the method using time. Then, the gradation expression is realized with the sum of the light emitting areas.

  In the case of these methods for expressing gradation with light emission time and light emission area, it is possible to handle a video signal consistently as a digital value from external capture to writing to a pixel portion. For this reason, the gradation expression using the digital signal is an excellent method in terms of display accuracy. However, a disadvantage is that the frequency of writing video signals per pixel increases, so that the operating frequency of the drive circuit increases. As a result, in the conventional signal line driving circuit (see Patent Document 1) adopting the dot sequential writing method, the writing time to the pixel portion is insufficient, and a display defect may occur.

In addition, in a signal line driving circuit of a display device that performs analog driving, a configuration in which a digital video signal is directly input to a shift register and serial-parallel conversion is proposed (see Patent Documents 2 and 3).
JP 2000-259132 A JP 2001-31243 A US Pat. No. 5,589,847

  As a solution to the dot sequential driving, there is a line sequential writing method. In other words, two storage elements are provided per signal line, and two operations of capturing an external video signal and writing the video signal to the pixel portion are pipelined, and the video signal is sent in parallel to the pixel groups belonging to the same row. Write.

  FIG. 5 shows a block diagram of a typical signal line driving circuit adopting such a line sequential method. In the figure, D-latch (0) 501, D-latch (1) 502, and D-latch (2) 503 all mean level sensitive latches.

  A D-latch (1) 502 is a storage element used for an external video signal capturing operation, and a D-latch (2) 503 is a storage element used for a video signal writing operation to the pixel portion. . The D-latch (0) 501 is a storage element for controlling the timing of capturing a video signal into the D-latch (1) 502, and is configured by a group of D-latch (0) 501 connected in series. In the shift register, a start pulse signal (also referred to as SSP) 504 that becomes active once per row of the pixel portion is digitally delayed by a clock signal (also referred to as SCK) 505 and a clock inversion signal (also referred to as SCKB) 506. The data is sequentially taken into the D-latch (1) 502 group. It is assumed that a video signal corresponding to the timing of the start pulse signal 504 is input to the input terminal DATA 507 in the drawing.

  After appropriate video signals are stored in all D-latch (1) 502, the video signals held by all D-latch (1) 502 are simultaneously stored in D-latch (2) 503 at an appropriate timing. It is captured and written in parallel to the pixel group belonging to the same row. While the video signal of D-latch (2) 503 is being written to the pixel, D-latch (1) 502 captures the next row of data.

As described above, by adopting the line-sequential writing method, it is possible to solve the problem related to insufficient writing time. However, with regard to the external video signal capturing operation, as long as the number of data to be captured is increased, a high operating frequency is still required.
Therefore, the problem remains that D-latch (1) 502 in FIG. 5 malfunctions without taking in appropriate data. After all, the adoption of the line-sequential writing method is merely a transfer from the pixel portion to the memory element in the signal line driver circuit where the operation is most difficult to control in terms of timing.

  On the other hand, a solution to parallelize the video signal capturing operation from the outside, that is, increase n in FIG. 5, is conceivable. However, in reality, the parallelism is increased by limiting the interface with the outside. There is a limit.

  The present invention has been made in view of the above-described problems, and even in a display device that employs a gradation representation by a digital signal that has essentially no problem of accuracy, it is highly reliable in terms of operation timing control. The object is to provide a circuit.

  The above problem is due to the fact that whether or not the video signal can be captured by the D-latch (1) 502 in FIG. 5 is determined by the timing of the output pulse of the D-latch (0) 501. That is, since the video signal capturing timing in the D-latch (1) 502 is an asynchronous circuit that is affected by variations in characteristics of the circuits constituting the D-latch (0) 501, the D-latch (0) It is a problem whether the output delay of 501 is too early or too late. In particular, TFTs used in an active matrix display device that employs organic EL or liquid crystal have a larger characteristic variation than transistors using single crystal Si, and thus are greatly affected by the characteristic variation.

  Further, the clock signal 505 and the clock inversion signal 506 are alternately input to the D-latch (0) 501 group, but considering that the clock inversion signal 506 is an inversion of the clock signal 505, D-latch ( 1) 502 indicates that both edges at the rising edge and falling edge of the clock are used for determining the timing of capturing the video signal. In general, it is known that the frequency of the clock signal can be controlled, but the duty ratio easily changes. Therefore, in the case of the circuit shown in FIG. 5, even if there is no characteristic variation in the D-latch (0) 501 group, even-numbered D-latch (1) 502 group and odd-numbered D-latch (1) 502 group. There is a possibility that there will be a difference in the timing of capturing data.

  In this way, several uncertain factors are entangled, making it difficult to control the video signal capture timing.

  In view of the above problems, the present invention makes a synchronous circuit by directly inputting the same clock to all the storage elements used for the external video signal capturing operation, and the storage elements are both edge trigger flip-flops (D-FF). The D-FFs are connected in series to form a shift register, and one row of video signals are sequentially input from the first stage of the shift register, so that each D-FF constituting the shift register has a clock edge. Data is fetched in synchronization with the rising edge (or falling edge) of.

  One embodiment of the present invention includes a shift register having a plurality of flip-flop circuits, a signal line driver circuit having a latch circuit connected to each flip-flop circuit, a signal line connected to each latch circuit, In the shift register, the video signal is sequentially input to each flip-flop circuit according to the clock signal, and the latch circuit uses the signal input from the shift register as the signal line. This is a digital drive type display device characterized by outputting.

  Another embodiment of the present invention is a signal line driver circuit including a shift register having a plurality of flip-flop circuits, a first latch circuit and a second latch circuit connected to each flip-flop circuit, The first signal line connected to each latch circuit, the second signal line connected to the second latch circuit, and the shift register sequentially input video signals to each flip-flop circuit in accordance with the clock signal. The first latch circuit outputs the signal input from each flip-flop circuit to the first signal line according to the first latch pulse, and the second latch circuit outputs the signal input from each flip-flop circuit. A digitally driven display device that outputs to a second signal line in accordance with a second latch pulse.

  In the present invention, the video signal from the outside may be a digital signal.

  In the present invention, the flip-flop circuit may be a D-type flip-flop.

  In the present invention, the latch circuit may be a level sensitive latch.

  In the present invention, the pixel portion includes a pixel portion to which a signal from the signal line driver circuit is input through the signal line, and the pixel portion includes a signal line, a scanning line provided to intersect the signal line, and a signal line In addition, a structure having a switching element, a driving element connected to the switching element, and a light emitting element connected to the driving element in a region intersecting with the scanning line may be used.

  According to the present invention, it is possible to control the timing of capturing a video signal relatively easily even if the operating frequency is increased by adopting gradation representation by a digital signal in an active matrix display device.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment, a structure of a signal line driver circuit is described.

  FIG. 1 shows a signal line driving circuit for performing line-sequential writing when adopting gradation representation by a digital signal in an active matrix display device having m × n signal lines.

  Each of D-latch 101 and D-FF 102 in FIG. 1 represents a storage element that statically holds an n-bit digital signal. Of these, the D-FF 102 is an edge trigger flip-flop. The D-latch 101 may be either a level sensitive latch or an edge trigger flip-flop, but here it is a level sensitive latch.

  The level sensitive latch may be any circuit that realizes its function. For example, as shown in FIG. 2, an inverter (also referred to as inv) 201, a clocked inverter (also referred to as clkinv) 202, a data input terminal (also referred to as D) 203, a clock signal input terminal (also referred to as CK) 204, a data output terminal (Also referred to as Q) 205 is configured. A clock signal (also referred to as SCK) output from the clock signal input terminal 204 is supplied to the clocked inverter 202 together with a clock inverted signal (also referred to as SCKB) output from the clock inverted signal input terminal (also referred to as CKB) 206. . However, the inputs of the clock signal of the other clock inverter 202 to one clocked inverter 202 are in an inverted relationship with each other. That is, when the output signal of one clocked inverter has a high impedance, the other clocked inverter operates as an inverter. That is, as a whole, a clock output from the clock signal input terminal 204 includes an operation of transferring the signal of the data input terminal 203 to the data output terminal 205 and an operation of holding the signal of the data output terminal 205 by the positive feedback of the two inverters. It has a function of switching according to the signal level.

  The edge trigger flip-flop may be any circuit that realizes its function, but a typical example is a level sensitive latch (for example, one shown in FIG. 2) as shown in FIG. There is a master-slave type flip-flop which is connected in series, and one clock signal input uses a clock inversion signal input to the other. A data input D (also referred to as D) 301 is connected to the data input D of the master latch 302. The data output terminal (also referred to as Q) 303 is connected to the data output Q of the slave latch 304. The data output D of the master latch 302 is connected to the data input D of the slave latch 304. One of the clock signal input terminal 305 and the clock inverted signal input terminal 306 is connected to the clock signal input CK of the master latch 302, and the other is connected to the clock signal input CK of the slave latch 304. That is, when one latch transfers data, the other latch holds data. That is, as a whole, the data input terminal 301 is transmitted to the data output terminal 303 when the clock signal input from the clock signal input terminal 305 rises (or falls), and then the clock output from the clock signal input terminal 305 next time. Until the signal rises (or falls), the data output from the data output terminal 303 is held over one clock cycle (regardless of the value of data input from the data input terminal 301).

  In executing line sequential writing, the D-FF 102 has a function of capturing an external video signal, and the D-latch 101 has a function of writing data to a signal line (that is, a selected pixel group).

  Here, as indicated by the dotted line in FIG. 1, storage elements used for external video signal capturing operation are connected in series to form the shift register 103, and the video signal is only in the first stage of the shift register 103. It is a feature of the present invention that it is input. The video signal input from the DATA terminal (also simply referred to as DATA) 104 is sequentially input in an appropriate order in synchronization with the clock signal 105, so that data is stored in the D-FF 102 after m clocks. At this time, the D-FF 102 is supplied with the common clock signal 105 and the clock inverted signal 106 and operates as a synchronization circuit. Therefore, whether or not the video signal can be captured depends on the transition of the output of the D-FF 102 with respect to the transition of the clock signal 105. It depends only on the delay time. Therefore, according to the present invention, display defects caused by the asynchronous operation of the signal line driver circuit can be eliminated.

  According to the present invention, it is possible to control the timing of capturing a video signal relatively easily even if the operating frequency is increased by adopting gradation representation by a digital signal in an active matrix display device. This is because whether or not a video signal can be captured is determined only by the characteristics of the D-FF 102 constituting the shift register 103, and in particular, it is not necessary to consider the case where the delay time of the D-FF 102 is earlier than expected.

(Embodiment 2)
In this embodiment, a structure of a signal line driver circuit which is different from that in the above embodiment is described.

  FIG. 4 shows a block diagram when the number of D-FFs 102 in the first embodiment shown in FIG. 1 is reduced to half. The D-FF 401 used for taking in the video signal from the outside shares the function as a storage element with two signal lines. That is, the output of one D-FF 401 is connected to the input of two D-latches 402. Of these two D-latches 402, one uses a first latch pulse (also referred to as SLAT1) 403, and the other uses a second latch pulse (also referred to as SLAT2) 404 to control the data capture timing. Except for the items described above, the circuit configuration is the same as that of the first embodiment. Since the overall storage capacity of the shift register related to the external video signal capturing operation is halved, the data transfer to the D-latch 402 group, that is, the pixel writing operation is scheduled in two steps, and sequentially Execute. Specifically, the control signal that determines the data capture timing in the D-latch 402 group is divided into two systems, a first latch pulse 403 and a second latch pulse 404, and pulse signals that become active at different timings are supplied. To do.

  With such a circuit configuration, the circuit scale can be reduced instead of reducing the parallelism of the writing operation to the pixel.

The storage capacity of the shift register is m × n bits in the first embodiment and m × n / 2 bits in the second embodiment. However, the storage capacity is not limited to this, and can be arbitrarily set. is there. Therefore, it is desirable to optimize the storage capacity of the shift register in consideration of a trade-off between two factors, that is, the circuit scale and the parallelism of the writing operation to the pixel.
For example, FIG. 1 of Patent Document 2 shows a circuit configuration in the case where a memory element of a signal line driver circuit is shared by four signal lines. An object of the invention described in Patent Document 2 is to employ analog driving for writing an analog signal to a pixel and to reduce a circuit area. In particular, the present invention is different from the present invention in that a latch that drives a signal line is shared by a plurality of signal lines by using a multiplexer that is effective in sharing a DAC having a large exclusive area by a plurality of signal lines. However, the purpose of reducing the circuit scale is also applicable to a signal line driving circuit that employs digital driving as in the present invention. In this case, in the present invention, a latch is prepared for each signal line. This is because in the case of digital drive, the drive frequency is high, and if there is a signal line that enters a high impedance state by sharing a latch, there is a risk of malfunction due to the influence of noise.

  According to the present invention, it is possible to control the timing of capturing a video signal relatively easily even if the operating frequency is increased by adopting gradation representation by a digital signal in an active matrix display device. This is because whether or not a video signal can be captured is determined only by the characteristics of the D-FF constituting the shift register, and in particular, it is not necessary to consider the case where the delay time of the D-FF is earlier than expected. However, whether or not a video signal can be captured is determined only by the characteristics of the D-FFs constituting the shift register, but accurately includes clock skew. However, in the case of the display device targeted by the present invention, the clock skew is usually negligible. In addition, with the circuit configuration of this embodiment, the circuit scale can be reduced instead of reducing the parallelism of the writing operation to the pixel.

(Embodiment 3)
In this embodiment, a structure of an active display device that can include a signal line driver circuit is described with reference to FIGS.

  A thin film transistor is formed over a substrate 401 (hereinafter referred to as an insulating substrate) having an insulating surface with an insulating layer interposed therebetween. A thin film transistor (also referred to as a TFT) is connected to a semiconductor layer processed into a predetermined shape, a gate insulating layer covering the semiconductor layer, a gate electrode provided on the semiconductor layer via the gate insulating layer, and an impurity layer in the semiconductor film Source electrode or drain electrode. The material used for the semiconductor layer is a semiconductor material containing silicon, and the crystalline state may be any of an amorphous state, a microcrystalline state, and a crystalline state. For the insulating layer typified by the gate insulating film, an inorganic material is preferably used, and silicon nitride or silicon oxide can be used. The gate electrode, the source electrode, or the drain electrode may be formed using a conductive material, and includes tungsten, tantalum, aluminum, titanium, silver, gold, molybdenum, copper, and the like. The active display device can be broadly divided into a pixel portion 615 and a driver circuit portion 618. A thin film transistor 603 provided in the pixel portion 615 serves as a switching element (a switching TFT), and a thin film transistor 604 provided in the driver circuit portion includes Used as a CMOS circuit. In order to be used as a CMOS circuit, it is composed of a P-channel TFT and an N-channel TFT. The thin film transistor 603 can be controlled by the thin film transistor 604 provided in the driver circuit portion 618. The switching TFT and the driving TFT are referred to as a driving element.

  An insulating layer having a stacked structure or a single layer structure is formed so as to cover the thin film transistor. The insulating layer can be formed from an inorganic material or an organic material. As the inorganic material, silicon nitride or silicon oxide can be used. As the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane, or polysilazane can be used. Siloxane has a skeletal structure composed of a bond of silicon (Si) and oxygen (O), and an organic group containing at least hydrogen (such as an alkyl group or aromatic hydrocarbon) is used as a substituent. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Polysilazane is formed using a liquid material containing a polymer material having a bond of silicon (Si) and nitrogen (N) as a starting material. When formed using an inorganic material, the surface is in a state of following the unevenness on the lower side. When formed using an organic material, the surface is flattened. For example, in the case where flatness is required for the insulating layer 605, an organic material may be used. In addition, even if it is an inorganic material, flatness can be provided by thickening.

  The source electrode or the drain electrode is manufactured by forming a conductive layer in an opening provided in the insulating layer 605 or the like. At this time, a conductive layer functioning as a wiring over the insulating layer 605 can be formed. The capacitor 614 can be formed using the conductive layer of the gate electrode, the insulating layer 605, and the conductive layer of the source or drain electrode.

  Then, a first electrode 606 connected to either the source electrode or the drain electrode is formed. The first electrode 606 is formed using a light-transmitting material. Examples of the light-transmitting material include indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), and zinc oxide added with gallium (GZO). Further, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, alloys containing these (Mg: Ag, Al: Li, Mg: In, etc.), and compounds thereof (calcium fluoride, In addition to calcium nitride), even non-transparent materials such as rare earth metals such as Yb and Er can be made translucent by having a very thin film thickness. May be used for the first electrode 606.

  An insulating layer 610 is formed so as to cover an end portion of the first electrode 606. The insulating layer 610 can be formed in a manner similar to that of the insulating layer 605. In order to cover the end portion of the first electrode 606, an opening is provided in the insulating layer 610. The end face of the opening may have a taper shape, and a layer formed thereafter can be prevented from being disconnected. For example, when a non-photosensitive resin or a photosensitive resin is used for the insulating layer 610, a taper can be provided on the side surface of the opening depending on exposure conditions.

  Thereafter, an electroluminescent layer 607 is formed in the opening of the insulating layer 610. The electroluminescent layer has a layer having each function, specifically, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer. Moreover, the boundary of each layer is not necessarily clear, and some of them may be mixed.

As a specific example of the material for forming the light emitting layer, when red light emission is desired, 4-dicyanomethylene-2-isopropyl-6- [2- (1,1,7,7-tetra Methyljulolidin-9-yl) ethenyl] -4H-pyran (abbreviation: DCJTI), 4-dicyanomethylene-2-methyl-6- [2- (1,1,7,7-tetramethyljulolidine-9- Yl) ethenyl] -4H-pyran (abbreviation: DCJT), 4-dicyanomethylene-2-tert-butyl-6- [2- (1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] -4H-pyran (abbreviation: DCJTB), periflanthene, 2,5-dicyano-1,4-bis [2- (10-methoxy-1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] Benze , Bis [2,3-bis (4-fluorophenyl) Kinokisarinaito] iridium (acetylacetonate) (abbreviation: Ir _[Fdpq] 2 acac), or the like can be used. However, the present invention is not limited to these materials, and a substance exhibiting light emission having an emission spectrum peak from 600 nm to 700 nm can be used.

When green light emission is desired, N, N′-dimethylquinacridone (abbreviation: DMQd), coumarin 6, coumarin 545T, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), or the like is used for the light emitting layer. Can do. However, the present invention is not limited to these materials, and a substance exhibiting light emission having an emission spectrum peak from 500 nm to 600 nm can be used.

  In order to obtain blue light emission, 9,10-bis (2-naphthyl) -tert-butylanthracene (abbreviation: t-BuDNA), 9,9′-bianthryl, 9,10-diphenyl is used in the light-emitting layer. Anthracene (abbreviation: DPA), 9,10-bis (2-naphthyl) anthracene (abbreviation: DNA), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-gallium (abbreviation: BGaq), bis ( 2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq) or the like can be used. However, the present invention is not limited to these materials, and a substance exhibiting light emission having an emission spectrum peak from 400 nm to 500 nm can be used.

When white light emission is desired, TPD (aromatic diamine), 3- (4-tert-butylphenyl) -4-phenyl-5- (4-biphenylyl) -1,2,4-triazole (abbreviation) : TAZ), tris (8-quinolinolato) aluminum (abbreviation: _Alq 3), can be used a configuration in which laminated by the _Alq 3, Alq ₃ doped with Nile red which is a red light emitting pigment deposition method.

  After that, the second electrode 608 is formed. The second electrode 608 can be formed in a manner similar to that of the first electrode 606. A light-emitting element 609 including the first electrode 606, the electroluminescent layer 607, and the second electrode 608 can be formed.

  At this time, since the first electrode 606 and the second electrode 608 have a light-transmitting property, light can be emitted from the electroluminescent layer 607 in both directions. Such an active display device that can emit light in both directions can be called a double-sided light emitting display device.

  After that, the insulating substrate 601 and the counter substrate 620 are attached to each other with a sealing material 628. In this embodiment, since the sealing material 628 is provided over part of the driver circuit portion 618, a narrow frame can be achieved. Needless to say, the arrangement of the sealing material 628 is not limited thereto, and may be provided outside the driver circuit portion 618.

  An inert gas such as nitrogen is sealed in the space formed by the bonding, and the space is filled with a resin material having a light-transmitting property and a high hygroscopic property. As a result, intrusion of moisture or oxygen that is a cause of deterioration of the light-emitting element 609 can be prevented. In order to maintain a distance between the insulating substrate 601 and the counter substrate 620, a spacer may be provided or the spacer may be hygroscopic. The spacer has a spherical or columnar shape.

The counter substrate 620 can be provided with a color filter or a black matrix.
The color filter enables full color display even when a monochromatic light emitting layer, for example, a white light emitting layer is used. Even when each of the RGB light emitting layers is used, by providing a color filter, the wavelength of the emitted light can be controlled and a beautiful display can be provided. Further, the black matrix can reduce reflection of external light due to wiring or the like.

  After that, an optical film 635 such as a polarizing plate or a circularly polarizing plate is provided outside the insulating substrate 601, and an optical film 625 such as a polarizing plate or a circularly polarizing plate is provided outside the counter substrate 620. With such an optical film, black display can be sunk and the contrast ratio can be increased. In addition, reflection due to wiring or the like can be prevented.

  In this embodiment mode, the driving circuit portion is also formed over the insulating substrate 601, but an IC circuit formed from a silicon wafer may be used as the driving circuit portion. In that case, a video signal or the like from the IC circuit can be input to the thin film transistor 603 through a connection terminal or the like.

  This embodiment can be combined with any of the above embodiments as appropriate.

  In such an active display device, by applying the signal line driving circuit of the present invention, even when the operating frequency is increased by adopting gradation representation by a digital signal, the timing of capturing a video signal is relatively simple. Can be controlled.

(Embodiment 4)
In this embodiment mode, a structure of an active display device including a signal line driver circuit, a pixel portion, and the like of the present invention is described.

  FIG. 7 is a block diagram illustrating a state where the scan line driver circuit 723 and the signal line driver circuit 722 are provided around the pixel portion 700.

  The pixel portion 700 includes a plurality of pixels, and each pixel is provided with a light emitting element and a switching element.

  The scan line driver circuit 723 includes a shift register 701, a level shifter 704, and a buffer 705. A signal is generated based on the start pulse (GSP) and the clock pulse (GCK) input to the shift register 701 and input to the buffer 705 via the level shifter 704. In the buffer 705, the signal is amplified and input to the pixel portion 700. The pixel portion 700 is provided with a light-emitting element and a switching element for selecting the light-emitting element, and a signal from the buffer 705 is input to a gate line included in the switching element. Then, a switching element of a predetermined pixel is selected.

  The signal line driver circuit 722 includes a shift register 711, a latch circuit 713, a level shifter 714, and a buffer 715. A data signal (DATA) and a clock pulse (SCK) are input to the shift register 711, and a latch pulse (SLAT) is input to the latch circuit 713. The latch circuit 713 holds DATA for one row and inputs it to the pixel portion 700 all at once.

  The signal line driver circuit 722, the scan line driver circuit 723, and the pixel portion 700 can be formed using semiconductor elements provided over the same substrate. For example, the thin film transistor can be formed using the thin film transistor provided over the insulating substrate described in the above embodiment mode.

  This embodiment can be combined with any of the above embodiments as appropriate.

  In such an active display device, by applying the signal line driving circuit of the present invention, even when the operating frequency is increased by adopting gradation representation by a digital signal, the timing of capturing a video signal is relatively simple. Can be controlled.

(Embodiment 5)
In this embodiment mode, a pixel circuit of an active display device including the signal line driver circuit of the present invention will be described with reference to FIGS.

  FIG. 8A illustrates an example of an equivalent circuit diagram of a pixel. A signal line 6114, a power supply line 6115, a scanning line 6116, a light-emitting element 6113, transistors 6110 and 6111, and a capacitor element 6112 in an intersection region thereof. Have A digital video signal (also referred to as a video signal) held by the D-latch in the signal line driver circuit as shown in FIGS. 1 and 4 is input to the signal line 6114 directly or via a level shifter, a buffer, or the like. . At this time, the signal line driver circuit of the present invention does not include a DAC. The transistor 6110 can control supply of the potential of the video signal to the gate of the transistor 6111 in accordance with a selection signal input to the scan line 6116. The transistor 6111 can control supply of current to the light-emitting element 6113 in accordance with the potential of the video signal. The capacitor 6112 can hold a voltage between the gate and the source of the transistor 6111 (also referred to as a gate-source voltage). Note that although the capacitor 6112 is illustrated in FIG. 8A, the capacitor 6112 is not necessarily provided when it can be covered by the gate capacitance of the transistor 6111 or other parasitic capacitance.

  FIG. 8B is an equivalent circuit diagram of a pixel in which a transistor 6118 and a scan line 6119 are newly provided in the pixel shown in FIG. With the transistor 6118, the gate and the source of the transistor 6111 can be set to the same potential, so that a state where no current flows through the light-emitting element 6113 can be forcibly created.

  FIG. 8C is an equivalent circuit diagram of a pixel in which a transistor 6125 and a wiring 6126 are newly provided in the pixel illustrated in FIG. The potential of the gate of the transistor 6125 is fixed by the wiring 6126. The transistor 6111 and the transistor 6125 are connected in series between the power supply line 6115 and the light-emitting element 6113. Therefore, in FIG. 8C, the value of the current supplied to the light-emitting element 6113 is controlled by the transistor 6125, and the presence or absence of the current supplied to the light-emitting element 6113 can be controlled by the transistor 6111.

  This embodiment can be combined with any of the above embodiments as appropriate. In particular, when the digital driving method is employed as in the present invention, there is no need for a compensation circuit for the variation in transistor electrical characteristics required when the analog driving method is employed. A pixel configuration having four to four transistors can be obtained. Note that a compensation circuit for variation in TFT characteristics required when the analog driving method is adopted is constituted by transistors in one pixel, so that the number of transistors in one pixel increases.

  By applying the present invention to an active display device having such a pixel circuit, even if the operating frequency increases by adopting gradation expression by digital signal, the timing of capturing the video signal can be relatively easily determined. It becomes possible to control.

(Embodiment 6)
As electronic devices according to the present invention, portable information such as a television device (also simply referred to as a television or a television receiver), a digital camera, a digital video camera, a cellular phone device (also simply referred to as a cellular phone or a cellular phone), a PDA, etc. Examples include a terminal, a portable game machine, a computer monitor, a computer, an audio playback device such as a car audio, and an image playback device equipped with a recording medium such as a home game machine. A specific example will be described with reference to FIG.

  A portable information terminal device illustrated in FIG. 9A includes a main body 9201, a display portion 9202, and the like. The display device of the present invention can be applied to the display portion 9202. As a result, it is possible to provide a portable information terminal device that employs gradation representation using a digital signal with high display accuracy and is highly reliable in terms of operation timing control.

  A digital video camera shown in FIG. 9B includes a display portion 9701, a display portion 9702, and the like. The display device of the present invention can be applied to the display portion 9701. As a result, it is possible to provide a digital video camera that employs gradation expression using a digital signal with high display accuracy and is highly reliable in terms of operation timing control.

  A cellular phone shown in FIG. 9C includes a main body 9101, a display portion 9102, and the like. The display device of the present invention can be applied to the display portion 9102. As a result, it is possible to provide a mobile phone that employs gradation expression using a digital signal with high display accuracy and is highly reliable in terms of operation timing control.

  A portable television device illustrated in FIG. 9D includes a main body 9301, a display portion 9302, and the like. The display device of the present invention can be applied to the display portion 9302. As a result, it is possible to provide a portable television device that employs gradation expression using a digital signal with high display accuracy and is highly reliable in terms of operation timing control. In addition, the present invention can be applied to a wide variety of television devices, from a small one mounted on a portable terminal such as a cellular phone to a medium-sized one that can be carried and a large one (for example, 40 inches or more). The display device can be applied.

  A portable computer shown in FIG. 9E includes a main body 9401, a display portion 9402, and the like. The display device of the present invention can be applied to the display portion 9402. As a result, it is possible to provide a portable computer that employs gradation representation using a digital signal with high display accuracy and has high reliability in terms of operation timing control.

  A television device illustrated in FIG. 9F includes a main body 9501, a display portion 9502, and the like. The display device of the present invention can be applied to the display portion 9502. As a result, it is possible to provide a television apparatus that employs gradation expression using a digital signal with high display accuracy and that is highly reliable in terms of operation timing control.

  As described above, the display device of the present invention can provide an electronic device with a high contrast ratio.

It is a circuit diagram showing a signal line drive circuit of the present invention FIG. 3 is a circuit diagram illustrating a level sensitive latch according to the present invention. It is the circuit diagram which showed the edge trigger flip-flop of this invention. It is the circuit diagram which showed another embodiment of the signal line drive circuit of this invention. It is a circuit diagram showing a conventional signal line drive circuit. It is sectional drawing which showed the display apparatus of this invention. It is the block diagram which showed the display apparatus of this invention It is a circuit diagram which shows the pixel circuit of the display apparatus of this invention. It is the figure which showed the electronic device of this invention

Explanation of symbols

101 D-latch
102 D-FF
103 Shift register 104 DATA terminal 105 Clock signal 106 Clock inverted signal 201 Inverter 202 Clocked inverter 203 Data input terminal 204 Clock signal input terminal 205 Data output terminal 206 Clock inverted signal 214 Capacitance element 301 Data input terminal 302 Master latch 303 Data output terminal 304 Slave latch 305 Clock signal input terminal 306 Clock inversion signal input terminal 401 D-FF
402 D-latch
403 First latch pulse 404 Second latch pulse 501 D-latch (0)
502 D-latch (1)
503 D-latch (2)
504 Start pulse signal 505 Clock signal 506 Clock inversion signal 601 Insulating substrate 603 Thin film transistor 604 Thin film transistor 605 Insulating layer 606 Electrode 607 Electroluminescent layer 608 Electrode 609 Light emitting element 610 Insulating layer 614 Capacitance element 615 Pixel unit 618 Drive circuit unit 620 Counter substrate 625 Optical Film 628 Sealing material 635 Optical film 700 Pixel portion 701 Shift register 704 Level shifter 705 Buffer 711 Shift register 713 Latch circuit 714 Level shifter 715 Buffer 722 Signal line driver circuit 723 Scan line driver circuit 6110 Transistor 6111 Transistor 6112 Capacitance element 6113 Light emitting element 6114 Signal Line 6115 Power line 6116 Scan line 6118 Transistor 6119 Scan line 6125 Transistor 126 wiring 9101 body 9102 display unit 9201 body 9202 display unit 9301 body 9302 display unit 9401 body 9402 display unit 9501 body 9502 display unit 9701 display unit 9702 display unit

Claims (6)

A shift register having a plurality of flip-flop circuits;
A latch circuit connected to each flip-flop circuit, and a signal line driver circuit,
Each having a signal line connected to the latch circuit,
In the shift register, a video signal is sequentially input to the flip-flop circuits according to a clock signal,
The digital driving display device, wherein the latch circuit outputs a signal input from the shift register to the signal line in accordance with a latch pulse. A shift register having a plurality of flip-flop circuits;
A signal line driver circuit having a first latch circuit and a second latch circuit respectively connected to each flip-flop circuit;
A first signal line connected to the first latch circuit and a second signal line respectively connected to the second latch circuit;
In the shift register, a video signal is sequentially input to each flip-flop circuit according to a clock signal,
The first latch circuit outputs a signal input from each flip-flop circuit to the first signal line according to a first latch pulse,
The digitally driven display device, wherein the second latch circuit outputs a signal input from each flip-flop circuit to the second signal line in accordance with a second latch pulse. In claim 1 or claim 2,
The digital drive type display device, wherein the video signal is a digital signal. In any one of Claim 1 thru | or 3,
The digitally-driven display device, wherein the flip-flop circuit is a D-type flip-flop. In any one of Claims 1 thru | or 4,
The digitally driven display device, wherein the latch circuit is a level sensitive latch. In any one of Claims 1 thru | or 5,
A pixel portion to which a signal from the signal line driver circuit is input via the signal line;
The pixel portion includes a scanning line provided to intersect the signal line;
A switching element provided in an intersection region between the signal line and the scanning line;
A driving element connected to the switching element;
And a light emitting element connected to the driving element.

Images