KR100602347B1 - Light emitting display device capable of changing scanning direction - Google Patents

Abstract

The present invention relates to a light emitting display device capable of switching the screen display direction. A light emitting display device according to the present invention includes a scan driver for supplying a scan signal to a scan line and a light emission control signal to a light emission control line, a data driver for supplying a data signal to a data line, a scan line, a light emission control line and a data line And an image display unit having a plurality of pixels electrically connected to the scan drive unit, wherein the scan driver sequentially transfers the scan signal and the light emission control signal in either of two directions selected.

Display device, screen display switching, scan driver, data driver, shift register

Description

Light emitting display device capable of changing the screen display direction             

1 is a conceptual diagram of a general organic light emitting device.

2 is a circuit diagram illustrating a general pixel circuit used in a conventional organic light emitting display device.

3 is a block diagram illustrating a light emitting display device according to an exemplary embodiment of the present invention.

4 is a circuit diagram illustrating a pixel circuit of a light emitting display device according to an exemplary embodiment of the present invention.

5 is a diagram illustrating a scan driver of a light emitting display device according to an embodiment of the present invention.

6A is a diagram illustrating a logic operation result by the gate unit of FIG. 5.

6B is a circuit diagram of another example of the gate part of the scan driver of FIG. 5.

6C is a diagram illustrating a logic operation result by the gate part of FIG. 6B.

7 is a diagram illustrating a shift register of a scan driver of a light emitting display device according to an exemplary embodiment of the present invention.

8 is a driving timing diagram of a forward mode of a scan driver of a light emitting display device according to an exemplary embodiment of the present invention.

9 is a driving timing diagram for the reverse mode of the scan driver of the light emitting display device according to the exemplary embodiment.

10 is a diagram illustrating a data driver of a light emitting display device according to an embodiment of the present invention.

FIG. 11 is a drive waveform diagram for the data driver shown in FIG. 10.

<Description of the symbols in the main part of the drawing>

100: image display unit 110: pixels

200: scan driver 210: shift register

212: signal transmission unit 214: signal processing unit

220: switching unit 230: gate portion

240: buffer unit 300: data driver

400: control unit

The present invention relates to a light emitting display device, and more particularly, to an organic light emitting display device in which a screen display direction is changed.

Background Art In recent years, various portable electronic devices have been widely used due to technological developments in the fields of electricity, electronics, semiconductors, and communication. In particular, portable electronic devices have been manufactured so that a user can use the device more conveniently by mounting a flat panel display such as a TFT-LCD.

For example, among portable electronic devices, an electronic device such as a folding-type portable terminal is usually made so that the display screens of the inner display window and the outer display window of the terminal are inverted from each other so that the user can conveniently use the information on the screen. . Therefore, the user checks the information such as the reception status, the date and the time of the message through the outer display window while the folding portable terminal is folded, and confirms the message received through the inner display window while the folding portable terminal is opened or calls There is an advantage in that it is convenient to use services such as call and text message transmission.

However, a portable electronic device such as a folding portable terminal forms an inner layer display window and an outer display window by using two flat panel display devices such as a TFT-LCD to display an image on the inside and the outside of the device. In this case, the portable electronic device becomes thick and heavy, making it uncomfortable to carry.

On the other hand, in the technical field related to the recent flat panel display device, research on a light emitting display device having excellent brightness and a wide viewing angle using a self-luminous element has been continuously conducted. Such a light emitting display device displays an image by electrically exciting a light emitting layer made of a fluorescent or phosphorescent organic or inorganic compound in the light emitting device.

The light emitting device may be classified into an organic light emitting device using an organic compound as a light emitting layer and an inorganic light emitting device using an inorganic compound as a light emitting layer. The organic light emitting device has a higher luminous efficiency than the inorganic light emitting device and has excellent characteristics as a display device such as color reproducibility.

1 is a conceptual diagram of a general organic light emitting device.

Referring to FIG. 1, the organic light emitting diode may include anode and cathode electrodes on both sides as transparent electrodes for light emission on both sides. In addition, the organic light emitting device has a hole injecting layer (HIL), a hole transporting layer (hole transporting layer), an emitting layer (EML), an electron transporting layer (electron transporting layer) between the transparent electrode (ITO) on both sides and The electron injecting layer (EIL) may be formed in a multilayer structure.

By using the above-described organic light emitting device, an organic light emitting display device having excellent characteristics as a display device and capable of displaying on both sides of the screen can be manufactured. The conventional organic light emitting display device is used as a display device of various electronic devices such as a folding portable terminal or a camcorder due to its excellent display characteristics.

The above-described conventional light emitting display device is driven by an active matrix addressing method that is programmed to supply a predetermined current to a light emitting device for a frame time with a predetermined current source in a pixel. 2 illustrates a general pixel circuit used in the active matrix addressing light emitting display device.

2 is a circuit diagram illustrating a general pixel circuit used in a conventional organic light emitting display device. In the pixel circuit of FIG. 2, an emission control line for transmitting an emission control signal for limiting an emission period of the light emitting element is formed.

Referring to FIG. 2, a pixel circuit 12 of a conventional organic light emitting display device controls an electroluminescence device (hereinafter, referred to as “EL”) in a pixel 10. In addition, the pixel circuit 12 controls the light emission period of the light emitting element by a light emission control signal transmitted through the light emission control line En.

Specifically, the first transistor M1 in the recovery circuit 12 has a source, a drain, and a gate, the source is connected to a first power line for transmitting a first pixel voltage VDD, and the drain is a third transistor. It is connected to the source of M3, the gate is connected to the first electrode of the capacitor (C). In addition, the first transistor M1 supplies a predetermined current to the anode electrode of the light emitting device EL from the first pixel voltage VDD on the first power line in correspondence with the voltage applied to the gate as the driving transistor. Here, the second pixel voltage VSS is applied to the cathode of the light emitting device EL. The cathode of the light emitting device EL to which the second pixel voltage VSS is applied may be commonly connected to the cathode of the other light emitting device EL. The second transistor M2 has a source, a drain, and a gate, the source is connected to the data line Dm, the drain is connected to the gate of the first transistor M1, and the gate is connected to the scan line Sn. . In addition, the second transistor M2 samples the data voltage so that the data voltage applied to the data line Dm is transferred to the gate of the first transistor M1 in response to the scan signal of the scan line Sn. The third transistor M3 has a source, a drain and a gate, a source is connected to the drain of the first transistor M1, a drain is connected to the anode electrode of the light emitting element EL, and the gate is a light emission control line ( En). In addition, the third transistor M3 selectively blocks the current supplied from the first transistor M1 to the light emitting element EL in response to the light emission control signal of the light emission control line En, whereby the light emitting element EL Luminous period is limited. The capacitor C stores a voltage corresponding to the data voltage transmitted to the gate of the first transistor M1 through the second transistor M2, thereby predetermining a voltage between the gate and the source of the first transistor M1. Keep at the level voltage.

However, in the above-described conventional light emitting display device, since the light emission control line for transmitting the light emission control signal together with the scan line is formed in the pixel circuit, when the screen display direction of the light emitting display device is changed, the scan signal transmitted through the scan line is transmitted. The relationship between the light emission control signal transmitted through the light emission control line and the light emission display device may not operate properly.

In other words, in the light emitting display device having the scan line and the light emission control line, the scan signal and the light emission control signal transmitted to the pixel must always have the same order in the reverse mode opposite to the forward mode and the forward mode. Otherwise, the scanning signal and the light emission control signal are inverted with each other in the forward mode and the reverse mode, so that either image is not displayed properly. Therefore, in the light emitting display device having both the scan line and the light emission control line, it is necessary to control the scan signal and the light emission control signal to be applied to each pixel in a predetermined manner or order.

In addition, in the conventional light emitting display device, since the threshold voltage of the driving transistor for supplying current to the light emitting element is slightly different for each manufacturing process and for each position on the wafer, driving is performed for each pixel to maintain a constant current supplied to the light emitting element. It is manufactured to include a circuit (not shown) capable of compensating for the nonuniformity of the threshold voltage of the dragon transistor. Accordingly, the pixel circuit of most conventional light emitting display devices includes at least two scan lines for transmitting at least two different scan signals. In this case, when the screen display direction of the light emitting display device is changed, the application order of two different scanning signals is changed, and thus the light emitting display device may not operate normally.

As described above, in the conventional light emitting display device, when the plurality of scan signals are used or when the scan signals and the light emission control signals are used, it is difficult to change the screen display direction.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a light emitting display device having a light emission control line in which the screen display direction is switched.

Another object of the present invention is to provide a scan driving circuit which can easily switch the screen display direction in a light emitting display device in which a light emitting section is controlled by a light emission control signal.

In order to achieve the above object, according to an aspect of the present invention, a scan driver for supplying a scan signal to the scan line, a light emission control signal to the light emission control line, a data driver for supplying a data signal to the data line; And an image display unit having a plurality of pixels electrically connected to the scan line, the light emission control line, and the data line, wherein the scan driver sequentially transmits the scan signal and the light emission control signal in any one direction selected from both directions. Is provided.

Preferably, the scan driver may include a shift register for shifting the start signal in a direction selected by the direction control signal and sequentially outputting the shift signal; a switching unit transferring a signal selected by the direction control signal among the signals output from the shift register; The gate unit may include a gate unit configured to logically perform a first signal output from the shift register and a second signal transmitted through the switching unit, and sequentially output the scan signal. In this case, the first signal corresponds to the emission control signal.

In addition, the switching unit of the scan driver selectively transfers two signals output from the second output line adjacent in the first direction and the third output line adjacent in the second direction with respect to the specific first output line of the shift register according to the emission control signal. do. In addition, the switching unit of the scan driver may be arranged with the second output line disposed in the first direction with the at least one other output line interposed therebetween, and the at least one further output line in the second direction. Two signals output from the third output line to be selectively transmitted according to the light emission control signal. The switching unit of the scan driver may include a first transistor that transmits a signal on a second output line to a gate part in response to the first emission control signal among the emission control signals, and a third in response to the second emission control signal among the emission control signals. And a second transistor for transmitting a signal on the output line to the gate portion. Here, the start signal may be implemented as a staff pulse.

The scan driver may further include a buffer configured to buffer the first output signal and the third output signal and transmit the buffers to the image display unit.

In addition, the data driver may include a sheet register in which a direction of the output signal is switched in a third direction and a fourth direction opposite to the third direction.

According to another aspect of the present invention, a shift register for sequentially outputting a first signal obtained by shifting a start signal in a direction selected by a direction control signal, and selected by a direction control signal from among first signals output from the shift register; There is provided a scan driver including a switching unit for transmitting a signal, and a gate unit for sequentially outputting a scan signal by performing a logic operation on the first signal and the second signal. In this case, the first signal corresponds to the emission control signal.

Preferably, the shift register includes a plurality of signal transfer units configured to logically output the direction control signal and the start signal, and a plurality of the shift registers sequentially output in the first or second direction by shifting the start signal transmitted through each signal transfer unit. The scan driver of the light emitting display device includes a signal processing unit of which a start signal output from each signal processing unit is sequentially input to each signal transfer unit adjacent to the signal processing unit in the first direction or the second direction.

The signal transfer unit may include a first NAND gate having two inputs of a first direction control signal and a start signal in a first direction, a second NAND gate having two inputs of a second direction control signal and a start signal in a second direction; And a third NAND gate that logically computes each output of the first and second NAND gates and transfers the outputs to the signal processing units. Here, the second direction control signal may be implemented as an inverted signal of the first direction control signal.

In addition, the signal processor may implement a flip-flop for selectively maintaining a high level and a low level according to a clock signal.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, when a part is connected to another part, it includes not only the case where it is directly connected but also the case where it is electrically connected with another element between them. In the drawings, parts not related to the present invention will be omitted for convenience of description, and like reference numerals denote like parts throughout the specification.

3 is a block diagram illustrating a light emitting display device according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the light emitting display device includes an image display unit 100, a scan driver 200, a data driver 300, and a controller 400.

The image display unit 100 includes M * N pixels 110. The pixel 110 includes a light emitting device (not shown) and a pixel circuit (not shown) for controlling the light emitting device. The light emitting device includes an organic light emitting device in which the light emitting layer is made of an organic material. The pixel circuit includes a plurality of data lines D1, D2, D3, ..., Dm-1, Dm extending in the column direction and a plurality of scanning lines S1, S2, S3, ... extending in the row direction. , Sn-1, Sn) and a plurality of emission control lines E1, E2, E3, ..., En-1, En. In this embodiment, the pixel circuit may be implemented as the pixel circuit shown in FIG. 2.

 In addition, the image display unit 100 is connected to the first power supply unit 500 and the second power supply unit 600 that supply the first pixel voltage VDD and the second pixel voltage VSS to each pixel 110. . The first and second power supply units 500 and 600 may be implemented as DC-DC converters.

The scan driver 200 supplies a scan signal to the plurality of scan lines S1, S2, S3, ..., Sn-1, Sn, respectively. In addition, the scan driver 200 supplies light emission control signals to the plurality of light emission control lines E1, E2, E3, ..., En-1, En. The scan signal and the light emission control signal are applied to the pixels at the same time or sequentially. The scan signal may be a selection signal for selecting a pixel, and the emission control signal may be a signal for controlling the emission period of the selected pixel. The scan driver 200 may include a separate emission driver for supplying a emission control signal.

In addition, the scan driver 200 has at least a forward mode and a reverse mode. For example, the forward mode indicates a mode in which the scanning signal is applied in the first direction from the top of the image display part 100 to the bottom direction, and the reverse mode scans in the second direction from the bottom of the image display part 100 to the upward direction. Indicates the mode in which the signal is applied. In other words, the scan driver 200 may sequentially supply the scan signal and the light emission control signal in the first direction and in the second direction opposite to the first direction.

In this case, the scan driver 200 according to the present exemplary embodiment includes a configuration in which the order of the scan signal and the emission control signal applied to each pixel 110 is maintained in the forward mode and the reverse mode. This configuration will be described later.

The data driver 300 applies a data signal to each of the data lines D1, D2, D3,..., Dm-1, and Dm during one horizontal period in which at least one scan signal is applied to the pixels of at least one row line. Supply. The data signal represents a voltage level or a current level that allows each pixel 110 of the image display unit 100 to emit a predetermined amount of light.

In addition, the data driver 300 may sequentially apply the data signal in both the left and right directions of the image display unit 100 using the shift register mounted in the scan driver 200. In this case, the data driver 300 may sequentially apply the data signal from the left to the right or the right to the left to the pixel 110 during one horizontal period in which the scan signal is applied to the at least one scan line.

The controller 400 supplies control signals such as a start signal, a clock signal, a vertical synchronization signal, a horizontal synchronization signal, and a direction control signal to the scan driver 200 and / or the data driver 300. To this end, the controller 400 may include a start signal generator (not shown) and a timing controller (not shown). By the above-described configuration, the controller 400 controls the scan driver 200 and / or the data driver 300 so that the screen display direction of the image display unit 100 is switched up, down, left, and right.

As described above, in the light emitting display device according to the embodiment of the present invention, even when the scan line and the light emission control line for transmitting the scan signal and the light emission control signal to the pixel circuit, the screen display direction in the up and down and / or left and right directions Can be switched. This configuration will be described in more detail below.

4 is a circuit diagram of a pixel circuit of a light emitting display device according to an embodiment of the present invention. In the pixel circuit of FIG. 4, the transistor is formed of a P type transistor.

Referring to FIG. 4, the pixel circuit 114 of the light emitting display device controls the light emitting element EL in the pixel 110. The pixel circuit 114 includes a circuit for compensating for the nonuniformity of the threshold voltage of the driving transistor. To this end, the pixel circuit 114 includes first, second, third, fourth, and fifth transistors M1, M2, M3, M4, and M5 and first and second capacitors C1 and C2. .

The first transistor M1 has a source, a drain, and a gate, the source is connected to a first power line for transmitting the first pixel voltage VDD, and the drain is connected to a source of the fifth transistor M5. The gate is connected to the first electrode of the second capacitor C2. In addition, the first transistor M1 supplies a predetermined current to the anode electrode of the light emitting device EL from the first pixel voltage VDD on the first power line in correspondence with the voltage applied to the gate as the driving transistor. Here, the second pixel voltage VSS is applied to the cathode of the light emitting device EL. The cathode electrode of the light emitting device EL to which the second pixel voltage VSS is applied may be commonly connected to the cathode electrode of the other light emitting device EL.

The second transistor M2 has a source, a drain, and a gate, the source is connected to the data line Dm, the drain is connected to the second electrode of the second capacitor C2, and the gate is the first scan line Sn. ) In addition, the second transistor M2 transfers the data voltage applied to the data line Dm to the second electrode of the second capacitor C2 in response to the scan signal of the first scan line Sn.

The third transistor M3 has a source, a drain and a gate, the source is connected to the first power line, the drain is connected to the second electrode of the second capacitor C2, and the gate is the second scan line Sn-. Connected to 1). In addition, the third transistor M3 transfers the first pixel voltage VDD to the second electrode of the second capacitor C2 in response to a scan signal applied to the second scan line Sn-1.

The fourth transistor M4 has a source, a drain, and a gate, the source is connected to the drain of the first transistor M1, the drain is connected to the gate of the first transistor M1, and the gate is connected to the second scan line ( Sn-1). In addition, the fourth transistor M4 diode-connects the first transistor M1 in response to a scan signal applied to the second scan line Sn-1.

Due to the above-described configuration of the third and fourth transistors M3 and M4, the second capacitor C2 may have a first transistor (1) before the data voltage is transferred from the data line Dm through the second transistor M2. The voltage corresponding to the threshold voltage of M1) is stored. Therefore, the pixel circuit 114 according to the present exemplary embodiment includes a circuit for compensating the threshold voltage of the first transistor M1.

The fifth transistor M5 has a source, a drain, and a gate, a source is connected to the drain of the first transistor M1, a drain is connected to the anode electrode of the light emitting element EL, and the gate is a light emission control line ( En). In addition, the third transistor M3 selectively blocks the current supplied from the first transistor M1 to the light emitting element EL in response to the light emission control signal of the light emitting control line En, whereby the light emitting element EL Limit the light emission period.

The first capacitor C1 has a first electrode and a second electrode, the first electrode is connected to the drain of the second transistor M2, and the second electrode is connected to the first power line. In addition, the first capacitor C1 may have a voltage difference between the data voltage transferred through the second transistor M2 and the first pixel voltage VDD on the first power line while the scan signal is applied to the first scan line Sn. And stores the voltage corresponding to the voltage between the gate and the source of the first transistor M1 at a predetermined level. In this case, the voltage between the gate and the source of the first transistor M1 becomes a voltage across the series circuit of the first capacitor C1 and the second capacitor C2.

The second capacitor C2 has a first electrode and a second electrode, the first electrode is connected to the gate of the first transistor M1, and the second electrode is connected to the first electrode of the first capacitor C1. do. In addition, the second capacitor C2 stores a voltage substantially corresponding to the threshold voltage of the first transistor M1 while the scan signal is applied to the second scan line Sn-1.

On the other hand, when the pixel circuit 114 of FIG. 4 described above is employed as the pixel 110 of the light emitting display device of FIG. 3, the second scan line Sn-1 of the pixel circuit 114 is the first scan line Sn. It may be implemented as a previous or previous scan line to which the scan signal is applied during the horizontal period before at least one period before the scan signal is applied to.

5 is a diagram illustrating a scan driver of a light emitting display device according to an embodiment of the present invention.

Referring to FIG. 5, the scan driver 200 of the light emitting display device according to the present exemplary embodiment may include a scan signal (eg, a scan signal) according to the start signal SP1 of the controller and the first and second direction control signals CTD and CTU. S1, S2, S3, ..., Sn-1, Sn and light emission control signals E1, E2, E3, ..., En-1, En are supplied. To this end, the scan driver 200 includes a shift register 210, a switching unit 220, a gate unit 230, and a buffer unit 240.

The shift register 210 sequentially uses the signals SR [0], SR [1], in a first direction from the top to the bottom of the image display unit or in a second direction opposite to the first direction using the start signal SP1. SR [2], SR [3], ..., SR [n-1], SR [n], SR [n + 1]) are output. Here, the output signals SR [0], SR [1], SR [2], SR [3],…, SR [n-1], SR [n], SR [n + 1] of the shift register 210. ] Is used as the light emission control signals E1, E2, E3, ..., En-1, En. In Fig. 5, two output signals SR [0] and SR [n + 1] of the shift register 210 are used as dummy signals which are not substantially transmitted to the image display portion.

The switching unit 220 transmits a signal selected by the direction control signal among the signals output from the shift register 210 to the gate unit 230. For example, the switching unit 220 may be output from a second output line b adjacent to a specific first output line of the shift register 210 in a first direction and a third output line a adjacent to a second direction. The two signals are selectively transmitted to the gate unit 230 according to the direction control signal CTD or CTU. As another example, the switching unit 220 may include at least one second output line and at least one second output line disposed in a first direction with respect to a specific first output line of the shift register 210. Two signals output from the third output line arranged with another output line interposed therebetween can be selectively transmitted to the gate unit 230 according to the direction control signal.

In addition, in the forward mode in which the scan signal and the emission control signal are sequentially transmitted in the first direction, the switching unit 220 may output the specific output signal SR [of the shift register 210 in response to the first direction control signal CTD. 2]) is transferred to one input of the specific gate 233 and to one input of the other specific gate 235. On the other hand, the switching unit 220 is a specific output of the shift register 210 in response to the second direction control signal (CTU) in the reverse mode in which the scan signal is sequentially transmitted in the second direction opposite to the first direction The signal SR [2] is transmitted to one input of the specific gate 233 while being transmitted to one input of the other specific gate 231.

In addition, the switching unit 220 may include a switching circuit (not shown) formed of a transistor. For example, the switching circuit may be implemented as an N-type transistor or a P-type transistor having an on state in response to high and / or low level first and second direction control signals, respectively.

The gate unit 230 is configured to output signals SR [0], SR [1], SR [2], SR [3], ..., SR [n-1], SR [n], which are output from the shift register 210. SR [n + 1]) and the signal transmitted through the switching unit 220 are received and logically operated to sequentially output the scan signals S1, S2, S3, ..., Sn-1, Sn. In other words, the gate unit 230 combines a specific output signal of the shift register 210 with another output signal preceding this output signal to sequentially output the plurality of gate signals 231, 233, 235, and 237. , 239).

Each of the gates 231, 233, 235, 237, and 239 described above is negatively multiplied by a first input (/ c) and a second input (a) inverting one input (c). As shown in FIG. 6A, each gate 231, 233, 235, 237, 239 has a low level output when both inputs a and c are 1 and 0, respectively. Here, two output signals of the shift register are used for the two inputs a and c, and one input a of the two inputs is used as the light emission control signals E1, E2, E3, ..., En-1, En. The low level output of each gate is used as scan signals S1, S2, S3, ..., Sn-1, Sn.

Each of the gates 231, 233, 235, 237, and 239 of the gate unit 230 described above may be implemented using NAND gates that are easy to implement in a semiconductor process. However, the gate portion 230 may be formed by an inverter or another gate such as a NOT gate, a OR gate, a NOR gate, or a combination thereof. For example, as shown in FIG. 6B, the gate unit 230 has two inputs, an inverter for inverting one output signal of the shift register, and an output signal of the interleaver and the other signal transmitted through the switching unit. It may be implemented as a circuit 232 including an OR gate. The result of the logic operation by the gate portion of FIG. 6B is shown in FIG. 6C.

The buffer unit 240 includes the signals SR [1], SR [2], SR [3], ..., SR [n-1], SR [n] and the gate unit 230 output from the shift register 210. ), The light emission control signals E1, E2, E3, ..., En-1, En and the scan signals S1, S2, S3, ..., Sn-1 on the light emission control line and the scan line extending to the image display unit. And Sn) are supplied sequentially. At this time, the emission control signals E1, E2, E3, ..., En-1, En and the scan signals S1, S2, S3, ..., Sn-1, Sn are opposite to the first direction and the first direction. In a second direction or in a certain manner.

Thus, according to this embodiment, even when the direction of the output signal of the shift register is switched, the transfer direction of the scan signal and the transfer direction of the emission control preference are kept constant by the switching unit connected to the shift register, whereby The light emitting display device can display an image normally. As described above, the light emitting display device according to the exemplary embodiment may switch the screen display direction even when the scan line and the light emission control line are provided.

Next, a shift register of a light emitting display device according to an embodiment of the present invention will be described in detail below. 7 is a diagram illustrating a shift register employable in a light emitting display device according to an embodiment of the present invention.

Referring to FIG. 7, the shift register 210 according to the exemplary embodiment of the present invention may output the output signals SR [0] and SR [in the first or second direction according to the direction control signals CTD and CTU of the controller. 1], SR [2], SR [3], ..., SR [n-1], SR [n], SR [n + 1]). To this end, the shift register 210 includes a plurality of signal transfer units 212 and a plurality of signal processing units 214.

The signal transfer unit 212 includes a plurality of forward NAND gates RN0, RN1, RN2, ..., RNn-1, RNn, RNn + 1, and a plurality of reverse NAND gates LN0, LN1, LN2, ..., LNn-1, LNn, LNn + 1 and a plurality of NAND gates N0, N1, N2, ..., Nn-1, Nn, Nn + 1. The signal processor 214 includes a plurality of flip-flops F-F from 0th to N + 1th.

In the following detailed description, the first direction or the forward mode includes the N-1 th flip-flop, the N th flip-flop, and the N + 1 after the start signal SP1 passes from the zero flip-flop to the first flip-flop, the second flip-flop, and the like. And a second direction or a reverse mode, in which a signal passes from an N + 1 th flip flop to an N th flip flop, an N-1 th flip flop, a second flip flop, a first flip flop, and It represents the direction to be delivered to the zero flip-flop.

Specifically, the start signal SP1 and the first direction control signal CTD are input to the forward zero NAND gate RN0. The second direction control signal CTU and the signal at the output terminal of the first flip-flop are input to the reverse zero NAND gate LN0. The outputs of the forward and reverse zero NAND gates RN0 and LN0 are input to the zero NAND gate N0. The output of the zero NAND gate NO is input to the zero flip flip flop 0th F-F.

The signal of the output terminal of the zero flip-flop and the first direction control signal CTD are input to the first forward NAND gate RN1. The second direction control signal CTU and the signal of the output terminal of the second flip-flop are input to the reverse first NAND gate LN1. Outputs of the forward and reverse first NAND gates RN1 and LN1 are input to the first NAND gate N1. The output of the first NAND gate N1 is input to the first flip-flop 1st F-F.

The signal of the output terminal of the first flip-flop and the first direction control signal CTD are input to the second forward NAND gate RN2. The second direction control signal CTU and a signal of an output terminal of a third flip-flop (not shown) are input to the reverse second NAND gate LN2. Outputs of the forward and reverse second NAND gates RN2 and LN2 are input to the second NAND gate N2. The output of the second NAND gate N2 is input to the second flip-flop 2nd F-F.

The signal of the output terminal of the n-2nd flip-flop (not shown) and the first direction control signal CTD are input to the forward n-1th NAND gate RNn-1. A signal from the output terminal of the second direction control signal CTU and the nth flip-flop Nth F-F is input to the reverse n-1th NAND gate LNn-1. The outputs of the forward and reverse n-1 th NAND gates RNn-1 and LNn-1 are input to the n-1 th NAND gate Nn-1. The output of the n-1 th NAND gate Nn-1 is input to the n-1 th flip-flop N-1th F-F.

The signal of the output terminal of the n−1 th flip-flop and the first direction control signal CTD are input to the forward n-th NAND gate RNn. A signal from an output terminal of the second direction control signal CTU and the n−1 th flip-flop N-1th F-F is input to the reverse n-th NAND gate LNn. The outputs of the forward and reverse nth NAND gates RNn and LNn are input to the nth NAND gate Nn. The output of the nth NAND gate Nn is input to the nth flip-flop Nth F-F.

The signal of the output terminal of the nth flip-flop and the first direction control signal CTD are input to the forward n + 1th NAND gate RNn + 1. The second direction control signal CTU and the start signal SP1 are input to the reverse n + 1th NAND gate LNn + 1. The outputs of the forward and reverse n + 1th NAND gates RNn + 1 and LNn + 1 are input to the n + 1th NAND gate Nn + 1. The output of the n + 1th NAND gate Nn + 1 is input to the n + 1th flip-flop N + 1th F-F.

By the above-described configuration, the shift register 210 outputs the signals SR [0], SR [1], SR [2], SR [3], ..., SR [n-1 in the first direction or the second direction. ], SR [n], SR [n + 1]) in order. In this manner, the light emitting display device according to the present invention can easily switch the display direction of the screen by using the scan signal and the light emission control signal by providing the shift register having the above-described structure in the scan driver and / or the data driver.

On the other hand, the shift register of this embodiment may be implemented as a shift register in the data driver. In this case, the light emitting display device may not only change the screen display direction in the vertical direction by the scan driver, but also change the screen display direction in the left and right directions.

Next, driving timings of the scan driver of the light emitting display device according to the exemplary embodiment will be described. 8 is a driving timing diagram of a scan driver of a light emitting display device according to an exemplary embodiment of the present invention. In the present embodiment, an operation of sequentially outputting the scan signal and the light emission control signal in the first direction will be described.

First, a NAND gate outputs a high level signal regardless of another input signal when one input signal is low level, and outputs a signal having an inverted level with respect to another input signal when one input signal is high level. do. Therefore, when the first direction control signal CTD is at a high level and the second direction control signal CTU is at a low level under a first direction, that is, a forward operating condition, the reverse NAND gates always output a high level output signal. do.

Specifically, referring to FIGS. 5, 7 and 8, the high level first direction control signal CTD is configured to forward NAND gates RN0, RN1, RN2,..., RNn-1, RNn, and RNn + 1. The low level second direction control signal CTU is applied to the reverse NAND gates LN0, LN1, LN2, ..., LNn-1, LNn, LNn + 1, and is forward zero NAND gate RN0. ) And the start signal SP1 is applied to the reverse N + 1th NAND gate LNn + 1, the outputs of the reverse NAND gates LN0, LN1, LN2, ..., LNn-1, LNn, LNn + 1 High level, the output of the forward NAND gates RN0, RN1, RN2, ..., RNn-1, RNn, RNn + 1 becomes the inverted signal of the start signal SP1. Then, the outputs of the NAND gates N0, N1, N2, ..., Nn-1, Nn, Nn + 1 are reversed NAND gates LN0, LN1, LN2, ..., LNn-1, LNn, LNn + 1. Since the input from the high level is high, it becomes the start signal SP1 inverting the input from the forward NAND gates RN0, RN1, RN2, ..., RNn-1, RNn, RNn + 1.

With the above-described configuration, the shift register 210 sequentially outputs signals in the first direction every one frame period, and outputs the signals SR [0], SR [1], SR [2], The SR [3], ..., SR [n-1], SR [n], SR [n + 1] are formed through the buffer unit 240 to emit light control signals E1, E2, E3, ..., En-1, En) are sequentially output in the first direction. In addition, each output signal sequentially output in the first direction of the shift register 210 is selectively switched by the first direction control signal CTD applied to the switching unit 220 and combined by the gate unit 230. do. The scan signals S1, S2, S3,..., Sn-1, and Sn are sequentially output in the first direction through the gate unit 230.

9 is a driving timing diagram of a scan driver of a light emitting display device according to an exemplary embodiment of the present invention. In the present embodiment, an operation of sequentially outputting the scan signal and the light emission control signal in the second direction will be described.

First, a NAND gate outputs a high level signal regardless of another input signal when one input signal is low level, and outputs a signal having an inverted level with respect to another input signal when one input signal is high level. do. Therefore, when the first direction control signal CTD is at a low level and the second direction control signal CTU is at a high level under a second direction, that is, a reverse operating condition, the forward NAND gates always output a high level output signal. do.

Specifically, referring to FIGS. 5, 7 and 9, the low level first direction control signal CTD is configured to forward NAND gates RN0, RN1, RN2,..., RNn-1, RNn, and RNn + 1. The second direction control signal CTU of high level is applied to the reverse NAND gates LN0, LN1, LN2, ..., LNn-1, LNn, LNn + 1, and the forward zero NAND gate RN0. When the start signal SP1 is applied to the reverse N + 1th NAND gate LNn + 1, the outputs of the forward NAND gates RN0, RN1, RN2, ..., RNn-1, RNn, RNn + 1 are high. Level, the output of the reverse NAND gates LN0, LN1, LN2, ..., LNn-1, LNn, LNn + 1 becomes the inverted signal of the start signal SP1. Then, the outputs of the NAND gates N0, N1, N2, ..., Nn-1, Nn, Nn + 1 are forward NAND gates RN0, RN1, RN2, ..., RNn-1, RNn, RNn + 1. Since the input from the high level is high, it becomes the start signal SP1 inverting the input from the reverse NAND gates LN0, LN1, LN2, ..., LNn-1, LNn, LNn + 1.

With the above-described configuration, the shift register 210 sequentially outputs signals in the second direction every one frame period, and outputs the signals SR [n + 1], SR [n], and SR [n. -[1], ..., SR [3], SR [2], SR [1], SR [0] through the buffer unit 240 emit light control signals En, En-1, ..., E3, E2, E1) is sequentially output in the second direction. In addition, each output signal sequentially output in the second direction of the shift register 210 is selectively switched by the second direction control signal CTU applied to the switching unit 220 and combined by the gate unit 230. do. The scan signals Sn, Sn-1, ..., S3, S2, and S1 are sequentially output in the second direction through the gate unit 230.

10 is a diagram illustrating a data driver of a light emitting display device according to an embodiment of the present invention. FIG. 11 is a driving waveform diagram of the data driver shown in FIG. 10.

10 and 11, the data driver 300 of the light emitting display device according to an exemplary embodiment supplies a data signal to a data line extending in the image display unit. To this end, the data driver 300 includes a shift register 310, a first latch 320, a second latch 330, and a D / A converter 340. In FIG. 10, the first latch 320 and the second latch 330 are illustrated as sampling latches and holding latches, respectively.

Specifically, the shift register 310 may be implemented with the shift register shown in FIG. 5 above. However, in the above-described case, the shift register 310 operates according to the predetermined start signal SP2 and the control signal from the control unit for proper input and output of the data signal. Here, the control signal includes a clock signal CLK, a synchronization signal Hsync, a first direction control signal CTD, and a second direction control signal CTU. The first direction control signal CTD and the second direction control signal CTU represent the same control signals as the first and second direction control signals CTD and CTU of the scan driver.

In addition, the shift register 310 controls the first latch 320 according to the clock signal CLK and the synchronization signal Hsync.

The first latch 320 is a sequential control signal SR [0], SR [1], SR [2], ..., SR [n-1], SR [n], SR [n of the shift register 310. +1]) is sequentially sampled and output in parallel the amount of data to be provided to one row line of the image display unit. The second latch 330 receives and stores data stored in the first latch 320 according to a predetermined control signal. The second latch 330 outputs the data stored in the D / A converter 340 according to the control signal.

The D / A converter 340 converts a data signal input as a digital signal into an analog signal and outputs the analog signal. The D / A converter 340 may be implemented to process the output signal as an analog signal or a digital signal.

As described above, the present invention can easily switch the screen display direction in the up-down direction and / or the left-right direction even in a light emitting display device having pixels controlled by the scan signal and the light emission control signal. In particular, in the light emitting display device capable of double-sided display, the convenience of the user may be greatly improved by changing the screen display direction according to the position of the user viewing the screen.

Meanwhile, the above-described data driver and / or scan driver may be electrically connected to an image display unit including a plurality of pixels arranged in a matrix form, or may be adhesively and electrically connected to the image display unit. It can be mounted in the form of a chip. On the other hand, the data driver and / or the scan driver may be mounted on a flexible printed circuit (FPC), a film, or the like that is bonded and electrically connected to the pixel unit. On the other hand, the data driver and / or the scan driver may be replaced by a driving circuit mounted directly on the glass substrate of the pixel portion or formed of the same layers as the thin film transistors, data lines, and scan lines on the glass substrate.

As mentioned above, although preferred embodiment of this invention was described in detail, this invention is not limited to the said embodiment, A various deformation | transformation by a person of ordinary skill in the art within the scope of the technical idea of this invention is carried out. This is possible.

According to the present invention, the display direction of the screen can be easily switched in the light emitting display device including the scanning line and the light emission control line. Therefore, there is an advantage that the electronic device equipped with the display device becomes convenient to use.

In addition, by controlling the screen display direction by using a scan driver having a simple structure, there is an advantage that a light emitting display device which is very suitable for mass production while the screen display direction is switched can be provided.

Claims (24)

A scan driver for supplying a scan signal to the scan line and a light emission control signal to the light emission control line; A data driver supplying a data signal to the data line; And An image display unit having a plurality of pixels electrically connected to the scan line, the light emission control line, and the data line; And the scan driver sequentially transfers the scan signal and the emission control signal in one of two directions. The method of claim 1, The scan driver, A shift register for sequentially outputting a first signal obtained by shifting a start signal in the direction selected by the direction control signal; A switching unit transferring a second signal selected by the direction control signal among the first signals output from the shift register; And And a gate unit configured to logically operate the first signal and the second signal to sequentially output a scan signal. The method of claim 2, The light emitting display device corresponds to the first signal. The method of claim 2, And a signal selected by the direction control signal and input to the switching unit is a signal output from an output line adjacent to a first output line of the shift register for outputting the first signal. The method of claim 4, wherein The switching unit, And two signals output from the second output line adjacent to the first output line in the first direction and the third output line adjacent to the second direction in accordance with the light emission control signal. The method of claim 5, The switching unit, A first transistor configured to transfer a signal on the second output line to the gate in response to a first emission control signal among the emission control signals; And And a second transistor configured to transfer a signal on the third output line to the gate part in response to a second emission control signal among the emission control signals. The method of claim 6, The first transistor and the second transistor are formed of a transistor of the same type. The method of claim 7, wherein And the second emission control signal is an inverted signal of the first emission control signal. The method of claim 6, The first transistor and the second transistor are formed of different types of transistors, And a signal input to a control terminal of one of the first and second transistors is inverted by an inverter. The method of claim 2, The signal selected by the direction control signal and input to the switching unit is a signal output from an output line arranged with at least one other output line interposed from a first output line of the shift register for outputting the first signal. Light emitting display device. The method of claim 10, The switching unit, A second output line disposed in the first direction with the at least one other output line interposed therebetween, and a third output line disposed in the second direction with the at least one other output line interposed therebetween; A light emitting display for selectively transmitting two signals output from an output line in accordance with the light emission control signal. The method of claim 2, And the gate part negatively multiplies and outputs a third signal obtained by inverting the second signal and the first signal. The method of claim 2, And the gate part negatively ORs the third signal in which the first signal is inverted and the second signal. The method of claim 2, The scan driver further includes a buffer unit configured to supply the first signal and the scan signal to the emission control line and the scan line. The method of claim 2, The direction control signal, A first direction control signal for controlling a shift direction of the shift register in the first direction; And And a second direction control signal for controlling the shift direction of the shift register in the second direction. The method of claim 15, And the second direction control signal is an inverted signal of the first direction control signal. The method of claim 1, The pixel, A light emitting element having a first electrode and a second electrode, the second electrode being commonly connected to a first power supply line; A first transistor having a first electrode, a second electrode, and a gate, wherein the first electrode is connected to a second power line; A capacitor having a first electrode and a second electrode, wherein the first electrode is connected to a gate of the first transistor, and the second electrode is connected to the first electrode of the first transistor; A second electrode having a first electrode, a second electrode, and a gate, wherein the first electrode is connected to a data line, the second electrode is connected to the gate of the first transistor, and the gate is connected to a scan line transistor; And A first electrode, a second electrode, and a gate, wherein the first electrode is connected to the second electrode of the first transistor, the second electrode is connected to the first electrode of the light emitting device, and the gate And a third transistor connected to the emission control line. The method of claim 1, And the data driver includes a sheet register in which an output signal is switched in a third direction and a fourth direction opposite to the third direction. A shift register for sequentially outputting a first signal obtained by shifting a start signal in a direction selected by a direction control signal among a first direction and a second direction opposite to the first direction; A switching unit transferring a second signal selected by the direction control signal among the first signals output from the shift register; And A gate unit configured to logically operate the first signal and the second signal to sequentially output a scan signal, And the first signal corresponds to a light emission control signal. The method of claim 19, The shift register, A plurality of signal transfer units configured to logically output the direction control signal and the start signal; And It includes a plurality of signal processing unit for shifting the start signal transmitted through each of the signal transmission unit sequentially output in the first direction or the second direction, And each start signal output from each of the signal processing units is sequentially input to each of the signal transmission units of the adjacent signal processing unit in the first direction or the second direction. The method of claim 20, The signal transmission unit A first NAND gate having two inputs of the first direction control signal and the start signal in the first direction; A second NAND gate having two inputs of the second direction control signal and the start signal in the second direction; And And a third NAND gate for performing logical operation on the respective outputs of the first and second NAND gates, and for transferring the outputs to the signal processing units. The method of claim 21, If the first direction control signal is the enable level, the start signal is shifted in the first direction by the output of the first NAND gate, and if the second direction control signal is the enable level, the output of the second NAND gate is output. And the start signal is shifted in the second direction. The method of claim 22, And the second direction control signal is an inverted signal of the first direction control signal. The method of claim 20, And the signal processor is a flip-flop for selectively maintaining a high level and a low level according to a clock signal.

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