JP2007188072A5

JP2007188072A5 -

Info

Publication number: JP2007188072A5
Application number: JP2006337704A
Authority: JP
Filing date: 2006-12-15
Publication date: 2010-01-28

Claims

A shift register, and the signal line driver circuit having a respective flip-flop circuits one by one which are electrically connected to the latch circuits having a plurality of flip-flop circuit,
A signal line electrically connected to each latch circuit one by one ,
The shift register sequentially inputs a video signal to each flip-flop circuit according to the clock signal,
The latch circuit receives the video signal input to each flip-flop circuit, and then outputs the captured video signal to the signal line as a digital signal according to a latch pulse. apparatus.

a shift register having m (m is a natural number) flip-flop circuits, and a signal line driver circuit having m latch circuits electrically connected to the flip-flop circuits one by one;
M signal lines electrically connected to the respective latch circuits one by one,
The shift register sequentially inputs video signals to the flip-flop circuits according to a clock signal,
The latch circuit captures the video signal input to each flip-flop circuit and then outputs the captured video signal as a digital signal to the signal line according to a latch pulse. apparatus.

A shift register, and the signal line driver circuit having a respective one by two flip-flop circuits which are electrically connected to La Tchikai path having a plurality of flip-flop circuit,
Before it has a Kira latch circuit to signal Line that are electrically connected one by one, the,
The shift register sequentially inputs a video signal to each flip-flop circuit according to the clock signal,
Before Kira latch circuit after taking the video signal the input to the flip-flop circuit according to a latch pulse, and outputs before relaxin Route the video signal taken as a digital signal Digitally driven display device.

a shift register having m / 2 (m is a natural number of 2 or more) flip-flop circuits, and a signal line driver circuit having m latch circuits electrically connected to each flip-flop circuit two by two;
M signal lines electrically connected to the latch circuit one by one,
The shift register sequentially inputs video signals to the flip-flop circuits according to a clock signal,
The latch circuit captures the video signal input to each flip-flop circuit and then outputs the captured video signal as a digital signal to the signal line according to a latch pulse. apparatus.

In any one of Claims 1 thru | or 4,
The digital signal display device, wherein the signal line driver circuit writes the video signal to the pixel portion in a line sequential manner.

In any one of Claims 1 thru | or 5 ,
The digital drive type display device, wherein the video signal is a digital signal.

In any one of Claims 1 thru | or 6 ,
The digitally driven display device, wherein the flip-flop circuit is a D-type flip-flop.

In any one of Claims 1 thru | or 7 ,
The digitally driven display device, wherein the latch circuit is a level sensitive latch.

In any one of Claims 1 thru | or 8 ,
A pixel portion to which the video signal from the signal line driver circuit is input via the signal line
The pixel portion includes a scanning line provided to intersect the signal line;
A first transistor electrically connected to the signal line and the scan line;
A second transistor electrically connected to the first transistor ;
And a light-emitting element electrically connected to the second transistor .