JP2007179605A - Semiconductor storage - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage capable of reducing areas of a row decoder and control circuit by integrating a plurality of memories. <P>SOLUTION: The storage is provided with columns I/O 103 and 105 having column selectors 124 and 130 which differ in the number of bit lines to be selected or has sense amplifiers 127 and 132 connected to the different number of the column selectors 124 or individually connected to the column selectors 124, and is provided with the columns I/O 103 and 105 having sense amplifying selecting circuits which differ in the number of sense amplifiers to be selected according to the number of sense amplifiers 127 and 132. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device (memory) embedded in a system LSI. In particular, a technology that integrates multiple memories and replaces them with a single memory, thereby reducing the area occupied by the semiconductor storage device mounted on the system LSI and enabling individual functions after integration before integration. It is about.

  Various memories are mounted on the system LSI. FIG. 24 shows a block diagram of a system LSI before memory integration. In FIG. 24, reference numeral 171 denotes a first memory macro before integration, reference numeral 172 denotes a second memory macro before integration, and reference numeral 174 denotes commands and commands for the first memory macro 171 and the second memory macro 172. A logic circuit for giving an address is shown. The first memory macro 171 has a configuration of 32 word lines and 8 pairs of bit lines, and the second memory macro 172 has a configuration of 64 word lines and 8 pairs of bit lines.

  The technology for integrating the memories disclosed this time is a technology for integrating a plurality of memories, that is, a first memory macro 171 and a second memory macro 172, which are controlled by a conventional logic circuit 174, as shown in FIG. Conventionally, in the system LSI, as shown in FIG. 24, when the configuration such as the capacity and the number of words is different, the memory is mounted on the system LSI as individual memory macros, that is, as the first memory macro 171 and the second memory macro 172. Thus, the logic circuit 174 has been controlled.

Further, in the technology for integrating the memory, the memory array unit includes a memory array in which the first memory array unit and the second memory array unit are integrated together, and the first memory array unit and the second memory array unit are separately addressed. Is possible. A first access means is provided for addressing the first memory array unit using address data received from outside, and using the received control data as an address signal to the second memory array unit Second access means is provided for accessing the second memory array section. A method for integrating different memories in this manner is described in Patent Document 1.
Japanese Patent Laid-Open No. 7-281943

  However, in the conventional semiconductor memory device, when a plurality of memories are mounted on the system LSI when they are mixedly mounted on the system LSI, a control circuit and a row decoder exist for each of the plurality of memories, and the area increases. There was a problem. In the configuration described in Patent Document 1, the first memory array unit and the second memory array unit are integrated, but the row decoder unit exists separately.

  Accordingly, an object of the present invention is to provide a semiconductor memory device that can reduce the area of a row decoder, a control circuit, etc. by integrating a plurality of memories having different numbers of words and different capacities.

  In order to solve the above problems, a semiconductor memory device according to claim 1 of the present invention comprises a plurality of types of data input / output circuits having bit line selection circuits having different numbers of selection target bit lines.

  According to this configuration, even if the number of words is different for each data input / output circuit, it is possible to integrate a plurality of memory arrays by matching the number of word lines. Has the effect of reducing.

  In order to solve the above-described problem, a semiconductor memory device according to claim 2 of the present invention is configured so that different numbers of bit line selection circuits, sense amplifiers individually connected to the bit line selection circuits, and the bit line selection circuits are individually provided. And a write buffer selection having a number of selection target write buffers different depending on the number of the write buffers and a sense amplifier selection circuit having a number of selection target sense amplifiers different depending on the number of the sense amplifiers And a plurality of types of data input / output circuits.

  According to this configuration, even if the number of words is different for each data input / output circuit, it is possible to integrate a plurality of memory arrays by matching the number of word lines. Has the effect of reducing.

  In order to solve the above-mentioned problem, a semiconductor memory device according to claim 3 of the present invention is the semiconductor memory device according to claim 1 or 2, wherein the first data input / output circuit among the plurality of data input / output circuits is used. The corresponding first memory cell array has bit lines connected to all the memory cells, and the second memory cell array corresponding to the second data input / output circuit partially includes memory cells to which no bit lines are connected.

  According to this configuration, since the second memory cell array corresponding to the second data input / output circuit includes a part of the memory cells to which the bit lines are not connected, it is possible to reduce the load on the bit lines. In addition to the same effect as 1 or 2, it has the effect of improving data read characteristics.

  In order to solve the above problems, a semiconductor memory device according to a fourth aspect of the present invention is the semiconductor memory device according to the first or second aspect, wherein the first data input / output circuit among the plurality of data input / output circuits is used. The corresponding first memory cell array and the second memory cell array corresponding to the second data input / output circuit have different memory capacities.

  According to this configuration, the first memory array corresponding to the first data input / output circuit and the second memory array corresponding to the second data input / output circuit have different memory capacities. The load can be reduced, and in addition to the same function and effect as those of the first or second aspect, the data reading characteristic is improved.

  In order to solve the above-described problem, the semiconductor memory device according to claim 5 of the present invention is the semiconductor memory device according to claim 1 or 2, wherein the address commonly used in the plurality of data input / output circuits is the same as the external address. An address that is connected and not used in common by a plurality of data input / output circuits is connected to an external address as the highest address.

  According to this configuration, an address commonly used by a plurality of data input / output circuits is directly connected to an external address, and an address not commonly used by a plurality of data input / output circuits is connected to an external address as the highest address. In addition to the operational effects similar to those of the first or second aspect, the logical address space within the common capacity is unified to facilitate the inspection.

  In order to solve the above problem, according to a sixth aspect of the present invention, in the semiconductor memory device according to the first or second aspect, any one of the plurality of data input / output circuits includes a latency circuit. Prepare.

According to this configuration, since any one of the plurality of data input / output circuits includes the latency circuit, the latency circuit among the plurality of data input / output circuits includes the latency circuit. The provided data input / output circuit has an effect that the read cycle is delayed but the data read time is earlier than that of the data input / output circuit not provided with the latency circuit.

  In order to solve the above problems, according to a seventh aspect of the present invention, in the semiconductor memory device according to the first or second aspect, any one of the plurality of data input / output circuits includes a redundant circuit. Prepare.

  According to this configuration, since any one of the plurality of data input / output circuits includes the redundant circuit, the defective portion can be remedied by the redundant circuit. In addition to the same effects as those of the first or second aspect, It has the effect of improving the yield.

  In order to solve the above problems, according to an eighth aspect of the present invention, in the semiconductor memory device according to the first or second aspect, the plurality of data input / output circuits are connected to control signals having different control timings. Is done.

  According to this configuration, in addition to the operational effect similar to that of the first or second aspect, it has the operational effect of enabling fine adjustment of the readout time.

  In order to solve the above problems, a semiconductor memory device according to claim 9 of the present invention is the semiconductor memory device according to claim 1 or 2, wherein the semiconductor memory device is arranged between a plurality of data input / output circuits and controlled by a control circuit. A control delay circuit that delays a signal, and a word line delay circuit that is disposed between a plurality of memory arrays corresponding to a plurality of data input / output circuits and delays a signal of a word line that is an output of a row decoder. A first data input / output circuit of the data input / output circuits is connected to a control signal output from the control circuit, and a second data input / output circuit of the plurality of data input / output circuits is connected to the control delay circuit. The first memory array of the plurality of memory arrays connected to the output and corresponding to the plurality of data input / output circuits is connected to the word line, and the second memory array of the plurality of memory arrays is It is connected to a lead wire delay circuit.

  According to this configuration, by providing the control delay circuit and the word line delay circuit, the cycle time is the same, and a plurality of memories with operation timings out of phase are integrated to reduce the area of the row decoder, the control circuit, etc. It has the effect of reducing, unifying the logical address space within a common capacity, and facilitating the inspection.

  In order to solve the above problem, a semiconductor memory device according to claim 10 of the present invention is the semiconductor memory device according to claim 9, wherein both the control delay circuit and the word line delay circuit have inverter elements of the same number of stages. .

  According to this configuration, since both the control delay circuit and the word line delay circuit are provided with the same number of inverter elements, the cycle time is the same, and a plurality of memories having operation phases shifted in phase are integrated to adjust the phase. This reduces the area of the row decoder and the control circuit, unifies the logical address space within the common capacity, and facilitates the inspection.

  As described above, according to the present invention, it is possible to integrate a plurality of memories and reduce the area of a row decoder, a control circuit, and the like. In addition, it is possible to unify the logical address space within a common capacity and facilitate inspection. Furthermore, individual functions can be realized for each integrated memory.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
The semiconductor memory device according to the first embodiment of the present invention will be described below with reference to the drawings. Note that the same members are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. Here, a data input / output circuit having two configurations of a 4-bit line pair and an 8-bit line pair will be described, but the same applies to a case where a data input / output circuit having another configuration is provided. Further, the number of word lines, bit lines, and data inputs / outputs in the memory array is not necessarily the number in the embodiment.

  FIG. 1 is a block diagram of the semiconductor memory device according to the first embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a row decoder, and reference numeral 102 denotes a control circuit. Reference numeral 103 indicates a four-column I / O unit, and reference numeral 104 indicates one 4-column I / O constituting the four-column I / O unit 103. Reference numeral 105 denotes an 8-column I / O section, and reference numeral 106 denotes an 8-column I / O constituting the 8-column I / O section 105. Reference numeral 107 denotes a row predecoder, reference numeral 108 denotes a precharge control circuit, reference numeral 109 denotes a column decoder (bit line selection circuit), reference numeral 110 denotes a control unit, and reference numeral 111 denotes an address latch.

  Reference numeral 121 denotes a memory array, and reference numeral 122 denotes a memory cell array corresponding to a 4-bit line pair, which constitutes the memory array 121. Reference numeral 123 denotes a precharge circuit A corresponding to a 4-bit line pair, reference numeral 124 denotes a column selector A corresponding to a 4-bit line pair, reference numeral 125 denotes a write buffer, reference numeral 126 denotes an input data latch, Reference numeral 127 represents a sense amplifier, and reference numeral 128 represents an output circuit. Reference numeral 129 indicates a precharge circuit B corresponding to an 8-bit line pair, and reference numeral 130 indicates a column selector B corresponding to the 8-bit line pair.

  Symbols WL0 to WL63 indicate word lines, and symbols B0 to B3, NB0 to NB3, B80 to B87, and NB80 to NB87 indicate bit line pairs.

  FIG. 2 shows a specific configuration of the memory array 121 shown in FIG. In FIG. 2, reference numeral 120 denotes a memory cell.

  FIG. 3 shows a specific configuration of the memory cell 120 included in the memory cell array 122 shown in FIG. In FIG. 3, symbol P1 indicates a PMOS transistor, symbols N1 and N1 indicate NMOS transistors, symbols B and NB indicate bit line pairs, and symbol WL indicates a word line.

  FIG. 4 shows a specific configuration of the precharge circuit A123 and the column selector A124 shown in FIG. In FIG. 4, symbols P2 and P3 indicate PMOS transistors, symbol N3 indicates an NMOS transistor, and symbols I1 and I2 indicate inverters. Symbols DBUS and NDBUS indicate a data line pair. Symbols CAD0 to CAD3 indicate column decode signals. Symbol PCG indicates a precharge signal.

  FIG. 5 shows a specific configuration of the precharge circuit B129 and the column selector B130 shown in FIG. In FIG. 5, symbols CAD0 to CAD7 indicate column decode signals.

  FIG. 6 shows a specific configuration of the write buffer 125 shown in FIG. In FIG. 6, symbol N4 indicates an NMOS transistor, symbols I3 and I4 indicate inverters, and symbol NA1 indicates a NAND circuit. Symbol WD indicates an input data latch signal, and symbol WEN indicates a write buffer activation signal.

  FIG. 7 shows a specific configuration of the sense amplifier 127 shown in FIG. In FIG. 7, symbols P4 to P6 indicate PMOS transistors, symbol N5 indicates an NMOS transistor, symbols I5 and I6 indicate inverters, and symbol CI1 indicates a clocked inverter. Symbol RD indicates a sense amplifier output, and symbol SAE indicates a sense amplifier activation signal.

  FIG. 11a shows a connection diagram between the address latch 111 and the external pin PIN shown in FIG. In FIG. 11a, reference numeral 111a indicates a column address latch circuit, and reference numeral 111b indicates a row address latch circuit. Symbols A0 to A8 indicate external input addresses, symbol ADCn indicates a column address latch signal, symbol ADRn indicates a row address latch signal, and symbol INTCLK indicates an address latch activation signal.

  FIG. 13 shows a specific configuration of the output circuit 128 shown in FIG. In FIG. 13, reference numerals I7 to I10 denote inverters. Symbols RD and RD8 indicate sense amplifier outputs, and symbol DOx indicates output data.

  As shown in FIG. 1, the memory array 121 and the row decoder 101 are connected by word lines WL0 to WL63, and the memory array 121 and the precharge circuit A123 are connected by bit line pairs B0 to B3 and NB0 to NB3. 121 and the precharge circuit B129 are connected by bit line pairs B80 to B87 and NB80 to NB87. The row decoder 101 and the row predecoder 107 are connected by a row predecode signal RADn, the row predecoder 107 and the address latch 111 are connected by a row address latch signal ADRn, and the row predecoder 107 and the control unit 110 are main pulses. Connected by signal MP.

  The precharge circuit A123 and the precharge control circuit 108 are connected by a precharge signal PCG, and the precharge circuit A123 and the column selector A124 are connected by bit line pairs B0 to B3 and NB0 to NB3.

  The precharge circuit B129 and the precharge control circuit 108 are connected by a precharge signal PCG, and the precharge circuit B129 and the column selector B130 are connected by bit line pairs B80 to B87 and NB80 to NB87.

  The column selector A 124 and the write buffer 125 are connected by a data line pair DBUS, NDBUS, the column selector A 124 and the column decoder 109 are connected by a column decode signal CADn, and the column selector A 124 and the sense amplifier 127 are connected by a data line pair. Connected by DBUS and NDBUS.

  The column selector B130 and the write buffer 125 are connected by data line pairs DBUS8 and NDBUS8, the column selector B130 and the column decoder 109 are connected by a column decode signal CADn, and the column selector B130 and the sense amplifier 127 are connected by a data line pair. Connected by DBUS8 and NDBUS8.

  The column decoder 109 and the address latch 111 are connected by a column address latch signal ADCn.

  The write buffer 125 and the input data latch 126 are connected by an input data latch signal WD, and the write buffer 125 and the control unit 110 are connected by a write buffer activation signal WEN.

  The sense amplifier 127 and the output circuit 128 are connected by a sense amplifier output RD, and the sense amplifier 127 and the controller 110 are connected by a sense amplifier activation signal SAE.

  The input data latch 126 and the control unit 110 are connected by a data latch activation signal DICLK, and the input data latch 126 and the outside are connected by input data DIx.

  Further, the output circuit 128 and the outside are connected by output data DOx.

  The precharge control circuit 108 and the control unit 110 are connected by a precharge activation signal PR, and the address latch 111 and the control unit 110 are connected by an address latch activation signal INTCLK.

  The address latch 111 and the outside are connected by an address signal, and the control unit 110 and the outside are connected by a clock signal CLK and a write enable signal NWE.

  FIG. 2 shows the internal structure of the memory array 121. Each memory cell 120 arranged in a matrix is composed of a pair of a plurality of bit line pairs B0 to B3, NB0 to NB3, B80 to B87, and NB80 to NB87, and a plurality of word lines WL0 to WL63. It is connected with one of these.

  FIG. 11a shows a connection diagram between the address latch 111 and the external pin PIN shown in FIG. 1. The external address signal and INTCLK from the control unit are input, and the address latch signals ADRn and ADCn are output inside.

  24 shows a system LSI before memory integration, symbol 171 indicates a memory macro with 32 word lines, symbol 172 indicates a memory macro with 64 word lines, and symbol 174 indicates a logic circuit.

  FIG. 25 shows a system LSI after memory integration, symbol 173 indicates a memory macro after integration of 64 word lines, and the memory macro after integration of symbol 173 indicates the semiconductor according to the first embodiment of the present invention in FIG. A storage device is shown.

  The operation of the first embodiment of the present invention configured as described above will be described below.

  When writing is performed from the outside, the write enable signal NWE becomes “L” level and the external clock signal CLK becomes “H” level. At this time, the control unit 110 in the control circuit 102 outputs the address latch start signal INTCLK and the data latch start signal DICLK, the external address is latched by the address latch 111, the row address latch signal ADRn and the column address latch signal ADCn. Are output. The input data DIx is latched by the input data latch 126, and the input data latch signal WD is output. Further, the precharge activation signal PR is stopped by the controller 110, the precharge signal PCG is stopped by the precharge control circuit 108, the precharge circuit A123 and the precharge circuit B129 are stopped, and the precharge operation is finished. Further, the column decoder 109 receives the column address latch signal ADCn, outputs the column decode signal CADn at the column decoder 109, receives the column decode signal CADn, and selects one bit line pair at each of the column selector A124 and the column selector B130. .

  Further, a main pulse signal MP is output from the control unit 110, a row predecode signal RADn is output from the row predecoder 107, a desired word line is selected by the row decoder 101, and a signal is output from the desired word line. The Further, a write buffer activation signal WEN is output from the control unit 110, and data is output from the write buffer 125 to the data line pair DBUS and NDBUS.

  This data is written into the memory cell connected to the previously selected word line through each bit line pair in column selector A 124 and column selector B 130 selected previously.

  Thereafter, the main pulse signal MP is stopped from the control unit 110, the signal of the word line is stopped, the write buffer start signal WEN is stopped, the precharge start signal PR is further output, the bit line pair is precharged, and the write operation is performed. The operation ends.

  Next, when a read operation is performed from the outside, the write enable signal NWE becomes "H" level and the external clock signal CLK becomes "H" level. At this time, the control unit 110 in the control circuit outputs the address latch start signal INTCLK and the data latch start signal DICLK, the address is latched by the address latch 111, and the row address latch signal ADRn and the column address latch signal ADCn are output. Is done. Further, the precharge activation signal PR is stopped by the control unit 110, the precharge signal PCG is stopped by the precharge control circuit 108, the precharge circuit A123 and the precharge circuit B129 are stopped, and the precharge operation is finished. Also, the column decoder 109 receives the column address latch signal ADCn, and the column decoder 109 outputs the column decode signal CADn. The column decoder A124 and the column selector B130 select one bit line pair. The

  Further, the main pulse signal MP is output from the control unit 110, the row predecode signal RADn is output from the row predecoder 107, the desired word line is selected by the row decoder 101, and the signal of the desired word line is output. The At this time, data is read out from the memory cell connected to the previously selected word line through each bit line pair in the previously selected column selector A124 and column selector B130, and further controlled. The sense amplifier activation signal SAE is output from the unit 110, the data read by the sense amplifier 127 is amplified, the data is latched by the output circuit 128, and the output data DOx is output to the outside.

  In the first embodiment of the present invention configured as described above, 4 column I / O 104 for selecting one bit line pair from 4 bit line pairs and one bit line from 8 bit line pairs in one memory macro. Since there is an 8-column I / O 106 for selecting a pair, an appropriate number of words can be selected for each of the 4-column I / O unit 103 and the 8-column I / O unit 105, which are arranged individually as shown in FIG. The memory macros can be integrated as shown in FIG. 25 to reduce the area of the row decoder and the control circuit, the area of the control line from the logic circuit, etc., and its practical effect is great.

(Embodiment 2)
Next, a second embodiment of the present invention will be described below with reference to the drawings.

  FIG. 8 is a block diagram of the semiconductor memory device according to the second embodiment of the present invention. This semiconductor memory device includes a precharge circuit A123 instead of the precharge circuit B129, a column selector A124 instead of the column selector B130, and a write buffer 131 instead of the write buffer 125 in the 8-column I / O 106. In addition, a sense amplifier 132 is provided instead of the sense amplifier 127. The write buffer 131 includes a write buffer selection circuit 131a, and the sense amplifier 132 includes a sense amplifier selection circuit 132a (see FIGS. 9 and 10).

  The memory cell array 122, the precharge circuit A123, and the column selector A124 in the memory array 121 corresponding to the 8-column I / O 106 are connected by bit line pairs B80 to B87 and NB80 to NB87, and the column selector A124 and the write buffer 131 are connected. And the sense amplifier 132 are connected by data line pairs DBUS81 to DBUS82 and NDBUS81 to NDBUS82, and the column decoder 109, the write buffer selection circuit 131a in the write buffer 131, and the sense amplifier selection circuit 132a in the sense amplifier 132 are address-decoded. Connected by a line SADn, the write buffer selection circuit 131a and the control unit 110 are connected by a write buffer activation signal WEN, and the sense amplifier selection circuit 132a and the control unit 110 are sense amplifier activation signals. Are connected by AE, the write buffer 131 and the input data latch 126 is connected with the input data latch signal WD8, a sense amplifier 132 and the output circuit 128 is connected with the sense amplifier output RD8.

  FIG. 9 shows a specific configuration of the write buffer 131 shown in FIG. In FIG. 9, symbol N4 indicates an NMOS transistor, symbols I3 and I4 indicate inverters, symbol NA1 indicates a NAND circuit, symbol 131a indicates a write buffer selection circuit, and symbol A1 indicates an AND circuit.

  FIG. 10 shows a specific configuration of the sense amplifier 132 shown in FIG. 10, symbols P4 to P6 indicate PMOS transistors, symbol N5 indicates an NMOS transistor, symbols I5 and I6 indicate inverters, symbol CI1 indicates a clocked inverter, symbol 132a indicates a sense amplifier selection circuit, Symbol A2 indicates an AND circuit.

  Other configurations are the same as those of the first embodiment of the present invention.

  In the second embodiment of the present invention, the input data latch signal WD8 is written only in the write buffer 131 selected by the address decode line SADn. At the time of reading, the signal is amplified only by the sense amplifier 132 selected by the address decode line SADn.

  In this embodiment, since the column selector A124 is provided instead of the column selector B130, the load capacity of the column selector is small at the time of bit line data transfer, and only the column selector A124 is provided. Thus, as in the first embodiment, the appropriate number of words can be selected for each of the 4-column I / O unit 103 and the 8-column I / O unit 105, and the area of control lines from the row decoder, control circuit, and logic circuit can be selected. Can be reduced, and its practical effect is great.

(Embodiment 3)
Next, a semiconductor memory device according to a third embodiment of the present invention will be described below with reference to the drawings.

  FIG. 11b shows a connection diagram between the address latch 111 and the external pin PIN. The difference from FIG. 11a is that the addresses that can use the column address in common are the same connection, and the addresses that cannot be shared are connected to the top of all the addresses including the row address.

  Table 1 shows the logical address mapping for the connection of FIG. 11a.

  Table 2 shows the logical address mapping for the connection of FIG. 11b.

他の構成は本発明の実施の形態１と同様である。

Other configurations are the same as those of the first embodiment of the present invention.

  In the third embodiment of the present invention, the logical memory mapping is a memory mapping in which only the highest address is changed in units of 4 columns, and the logical address space within a common capacity can be unified, It is possible to reduce the area of the control lines from the row decoder, the control circuit, and the logic circuit as in the first embodiment after enhancing the ease of pattern creation and facilitating the inspection. The practical effect is great.

(Embodiment 4)
Next, a semiconductor memory device according to a fourth embodiment of the present invention will be described with reference to the drawings.

  FIG. 12 is a block diagram of the semiconductor memory device according to the fourth embodiment of the present invention. In this semiconductor memory device, the 8-column I / O 106 includes an output circuit 133. Control unit 110 and output circuit 133 are connected by a latency control clock L2CLK.

  FIG. 14 shows a specific configuration of the output circuit 133. In FIG. 14, symbol P7 indicates a PMOS transistor, symbol N6 indicates an NMOS transistor, and symbols I7 to I13 indicate inverters. Symbol L2CLK indicates a latency control clock.

  Other configurations are the same as those of the second embodiment of the present invention.

  In the fourth embodiment of the present invention, after latching the sense amplifier output RD8, the output circuit 133 receives the latency control clock L2CLK in the next cycle and outputs data. For this reason, the area of the control lines from the row decoder, the control circuit, and the logic circuit is reduced as in the first embodiment, and any one of the plurality of data input / output circuits includes a latency circuit. The data input / output circuit having the latency circuit has a read cycle slower than the data input / output circuit not having the latency circuit, but the data read time is faster, and its practical effect is great.

(Embodiment 5)
Next, a semiconductor memory device according to a fifth embodiment of the present invention will be described with reference to the drawings.

  FIG. 15 is a block diagram of the semiconductor memory device according to the fifth embodiment of the present invention. In this embodiment, the 8-column I / O 106 includes a redundant circuit 134 and the redundant relief unit 141 is provided at the last portion of the 8-column I / O 106. Redundant circuit 134 and input data latch 126 are connected by input data latch signal WDATA8, redundant circuit 134 and write buffer 131 are connected by input data latch signal WD8A, and redundant circuit 134 and sense amplifier 132 are sense amplifier output RD8A. The redundant circuit 134 and the output circuit 133 are connected by the sense amplifier output RDATA8, and the input data latch signal WD8B in the redundant circuit 134 is an input data latch in the redundant circuit 134 in the next 8-column I / O. It is connected to the signal WD8A and connected to the write buffer 131 in the next 8-column I / O. The sense amplifier output RD8B in the redundant circuit 134 is connected to the sense amplifier output RD8A in the redundant circuit 134 in the next-stage 8-column I / O, and is connected to the sense amplifier 132 in the next-stage 8-column I / O. . The redundancy signal RAA in the redundancy circuit 134 is connected to the redundancy signal RA in the redundancy circuit 134 in the next 8-column I / O, the redundancy signal 134 in the first stage is grounded, and the redundancy circuit 134 is reset. Connected.

  FIG. 16 shows details of the redundant circuit. In FIG. 16, symbols N7 and N8 indicate NMOS transistors, symbols I14, I15, and I16 indicate inverters, and symbol F1 indicates a fuse.

  FIG. 17 shows details of the redundant relief unit. In FIG. 17, symbol 142 indicates 8-column redundancy I / O. The 8-column redundant I / O 142 is not provided with an input data latch and an output circuit. The output RD8B of the sense amplifier 132 in the 8-column redundancy I / O 142 is connected to the RD8B in the redundancy circuit 134 in the previous 8-column I / O, and the input WD8B of the write buffer 131 in the 8-column redundancy I / O 142 is the previous stage. Are connected to the WD 8B in the redundant circuit 134 in the 8-column I / O.

  Other configurations are the same as those of the second embodiment of the present invention.

  In the fifth embodiment of the present invention, when there is no defect, the fuse F1 is not cut in the redundant circuit 134 of FIG. 16, so that the node A becomes “H” level after inputting the reset signal, and WDATA8-WD8A is written. Writing is performed through the path RD8, and reading is performed through the path RD8A-RDATA8 during reading. When there is a defect, the fuse F1 is cut, and after the reset signal is input, the node A becomes “L” level, writing is performed through the path WDATA8-WD8B, and writing is performed through the path RD8B-RDATA8. Reading is performed. For this reason, it is possible to reduce the area of the row decoder, the control circuit, the control line from the logic circuit, etc., as in the first or second embodiment, and further improve the yield. large.

(Embodiment 6)
Next, a semiconductor memory device according to a sixth embodiment of the present invention will be described with reference to the drawings.

  FIG. 18 is a block diagram of the semiconductor memory device according to the sixth embodiment of the present invention. The semiconductor memory device includes a memory cell array 122 corresponding to the 4-column I / O unit 103 and the 4-column I / O unit 103, a memory cell array 122 corresponding to the 8-column I / O unit 105 and the 8-column I / O unit 105, and A control signal delay circuit 135 and a word line delay circuit 136 are provided. The 4-column I / O unit 103 and the control signal delay circuit 135 are directly connected to the control signals PCG, CADn, SAE, WEN, and DICLK from the control circuit 102, and the 8-column I / O unit 105 and the control signal delay. The circuit 135 is connected by delayed control signals PCGA, CADnA, SAEA, WENA, DICLKA. The memory cell array 122 corresponding to the 4-column I / O unit 103, the row decoder 101, and the word line delay circuit 136 are connected by word lines WL0 to WL63, and the memory cell array 122 corresponding to the 8-column I / O unit 105 is connected to the memory cell array 122. The word line delay circuit 136 is connected by delay word lines WL0A to WL63A.

  FIG. 19 shows details of the control signal delay circuit 135. FIG. 19 shows an inverter for delaying symbols I17 to I20.

  FIG. 20 shows details of the word line delay circuit 136. In FIG. 20, symbols I21 to I24 indicate inverters for delay.

  Other configurations are the same as those of the first embodiment of the present invention.

  In the sixth embodiment of the present invention, the memory cell array 122 corresponding to the 8-column I / O unit 105 and the 8-column I / O unit 105 corresponds to the 4-column I / O unit 103 and the 4-column I / O unit 103. All signals are delayed equally with respect to the memory cell array 122. For this reason, the area of the row decoder, the control circuit, the control line from the logic circuit, etc. is reduced as in the first embodiment, and each column I / O unit in one memory is different, that is, four column I / O. It is possible to realize control with different operation cycles for each of the unit 103 and the 8-column I / O unit 105, and its practical effect is great.

  In other words, by providing the control delay circuit 135 and the word line delay circuit 136, the cycle time is the same and a plurality of memories having operation timings that are out of phase are integrated to reduce the area of the row decoder, the control circuit, and the like. The logical address space within a common capacity can be unified and inspection can be facilitated.

  In the configuration in which both the control delay circuit 135 and the word line delay circuit 136 have the same number of inverter elements, the cycle time is the same, and a plurality of memories having operation timings shifted in phase are integrated to adjust the phase. This makes it easy to reduce the area of the row decoder, the control circuit, etc., unify the logical address space within the common capacity, and facilitate the inspection.

(Embodiment 7)
Next, a semiconductor memory device according to a seventh embodiment of the present invention will be described with reference to the drawings.

  FIG. 21 is a block diagram of the semiconductor memory device according to the seventh embodiment of the present invention. In this embodiment, a delay circuit 137 is provided in the control circuit 102. The delay circuit 137 and the control unit 110 are connected by a sense amplifier activation signal SAE, and the delay circuit 137 and the sense amplifier 127 of the 8-column I / O 106 are connected by a sense amplifier activation signal SAE1.

  Other configurations are the same as those of the first embodiment of the present invention.

  In the seventh embodiment of the present invention, the 8-column I / O unit 105 is controlled by the 4-column I / O unit 103 to control the delayed sense amplifier activation signal SAE1. For this reason, as in the first embodiment, the area of the row decoder, the control circuit, the control line from the logic circuit, etc. is reduced, and the read time for each of the 4-column I / O unit 103 and the 8-column I / O unit 105 is reduced. Can be finely adjusted, and data can be read at a more reliable timing, which has a great practical effect.

(Embodiment 8)
Next, a semiconductor memory device according to an eighth embodiment of the present invention will be described below with reference to the drawings.

  FIG. 22 shows a configuration of a memory array in the semiconductor memory device according to the eighth embodiment of the present invention. In this embodiment, only the necessary memory cells are connected to the bit line pair in the memory cell array 151, the bit lines are disconnected between the necessary memory cells and the unnecessary memory cells, and the unnecessary memory cells are connected to one node. (Bit line) is grounded.

  Other configurations are the same as those of the first embodiment of the present invention.

  In the eighth embodiment of the present invention, the 8-column I / O unit 105 has a shorter bit line length than the 4-column I / O unit 103 and accesses only the necessary memory. It is also possible to increase the speed. Therefore, as in the first embodiment, the area of the control lines from the row decoder, control circuit, and logic circuit is reduced, and more reliable timing is provided for each of the four column I / O units and the eight column I / O units. Thus, it is possible to realize data reading, and its practical effect is great.

(Embodiment 9)
Next, a semiconductor memory device according to a ninth embodiment of the present invention will be described below with reference to the drawings.

  FIG. 23 shows a configuration of a memory array in the semiconductor memory device according to the ninth embodiment of the present invention. In this embodiment, only necessary memory cells 120 are arranged in the memory cell array 151.

  Other configurations are the same as those of the first embodiment of the present invention.

  In the ninth embodiment of the present invention, the 8-column I / O unit 105 has a shorter bit line length than the 4-column I / O unit 103, and only necessary memory is arranged, so that the read timing is high. The area can also be reduced. Therefore, as in the first embodiment, the area of the control lines from the row decoder, control circuit, and logic circuit is reduced, and the 4-column I / O unit 103 and the 8-column I / O unit 105 are more reliable. It is possible to read data at an appropriate timing, and its practical effect is great.

  The technology for integrating memories according to the present invention includes a plurality of input / output circuits having different circuits for selecting bit line pairs in one memory, integrating a plurality of memories, and providing one row decoder and one control circuit. Thus, not only the area can be reduced, but also the wiring connected to the memory can be reduced, which is useful for reducing the area of the memory on the system LSI.

1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a specific configuration of a memory array 121 shown in FIG. 1. FIG. 3 is a circuit diagram showing a specific configuration of a memory cell 120 included in the memory cell array 122 shown in FIG. 2. FIG. 2 is a circuit diagram showing specific configurations of a precharge circuit A123 and a column selector A124 shown in FIG. FIG. 2 is a circuit diagram showing specific configurations of a precharge circuit B129 and a column selector B130 shown in FIG. FIG. 2 is a circuit diagram showing a specific configuration of a write buffer 125 shown in FIG. 1. FIG. 2 is a circuit diagram showing a specific configuration of a sense amplifier 127 shown in FIG. 1. It is a block diagram which shows the structure of the semiconductor memory device of Embodiment 2 of this invention. FIG. 9 is a circuit diagram showing a specific configuration of a write buffer 131 in FIG. 8. FIG. 9 is a circuit diagram illustrating a specific configuration of a sense amplifier 132 in FIG. 8. FIG. 2 is a circuit diagram showing a connection between an address latch 111 and an external pin PIN in FIG. 1. It is a circuit diagram which shows the connection of the address latch 111 and external pin PIN in Embodiment 3 of this invention. It is a block diagram which shows the structure of the semiconductor memory device of Embodiment 4 of this invention. FIG. 2 is a circuit diagram showing a specific configuration of an output circuit 128 shown in FIG. 1. FIG. 13 is a circuit diagram showing a specific configuration of the output circuit 133 shown in FIG. 12. It is a block diagram which shows the structure of the semiconductor memory device of Embodiment 5 of this invention. FIG. 16 is a circuit diagram showing a specific configuration of redundant circuit 134 in FIG. 15. FIG. 16 is a circuit diagram showing a specific configuration of a redundant relief unit 141 in FIG. 15. It is a block diagram which shows the structure of the semiconductor memory device of Embodiment 6 of this invention. FIG. 19 is a circuit diagram showing a specific configuration of a control signal delay circuit 135 in FIG. 18. FIG. 19 is a circuit diagram showing a specific configuration of a word line delay circuit 136 in FIG. It is a block diagram which shows the structure of the semiconductor memory device of Embodiment 7 of this invention. It is a circuit diagram which shows the structure of the memory array in the semiconductor memory device of Embodiment 8 of this invention. It is a circuit diagram which shows the structure of the memory array in the semiconductor memory device of Embodiment 9 of this invention. It is a block diagram which shows the system LSI before memory integration. It is a block diagram which shows the system LSI after memory integration.

Explanation of symbols

101 Row Decoder 102 Control Circuit 103 4 Column I / O Unit 104 4 Column I / O
105 8-column I / O section 106 8-column I / O
107 row predecoder 108 precharge control circuit 109 column decoder 110 control unit 111 address latch 111a column address latch circuit 111b row address latch circuit 120 memory cell 121 memory array 122 memory cell array 123 precharge circuit A
124 Column selector A
125 Write buffer 126 Input data latch 127 Sense amplifier 128 Output circuit 129 Precharge circuit B
130 Column selector B
131 Write Buffer 131a Write Buffer Selection Circuit 132 Sense Amplifier 132a Sense Amplifier Selection Circuit 133 Output Circuit 133a Latency Circuit 134 Redundancy Circuit 135 Control Signal Delay Circuit 136 Word Line Delay Circuit 137 Delay Circuit 141 Redundancy Relief Unit 151 Memory Cell Array 152 Memory Cell Array 161 Memory Array 162 Memory array 171 Memory 1 before integration
172 Memory 2 before integration
173 Memory after integration 174 Logic circuit A1 to A2 AND circuit NA1 NAND circuit I1 to I24 Inverter CI1 Clocked inverter P1 to P7 PMOS transistor N1 to N8 NMOS transistor

Claims (10)

  A semiconductor memory device comprising a plurality of types of data input / output circuits having bit line selection circuits having different numbers of selection target bit lines.   There are different numbers of bit line selection circuits, sense amplifiers individually connected to the bit line selection circuits, and write buffers individually connected to the bit line selection circuits, and selected according to the number of the sense amplifiers. A semiconductor memory device comprising a plurality of types of data input / output circuits having a sense amplifier selection circuit having a different number of target sense amplifiers and a write buffer selection circuit having a different number of selection target write buffers in accordance with the number of write buffers.   Of the plurality of data input / output circuits, the first memory cell array corresponding to the first data input / output circuit has bit lines connected to all the memory cells, and a second data input / output circuit corresponding to the second data input / output circuit. 3. The semiconductor memory device according to claim 1, wherein a part of the memory cell array includes memory cells to which bit lines are not connected.   Among the plurality of data input / output circuits, the first memory cell array corresponding to the first data input / output circuit and the second memory cell array corresponding to the second data input / output circuit have different memory capacities. Item 3. The semiconductor memory device according to Item 1 or 2.   5. An address commonly used by the plurality of data input / output circuits is directly connected to an external address, and an address not commonly used by the plurality of data input / output circuits is connected to an external address as the highest address. The semiconductor memory device according to any one of the above.   The semiconductor memory device according to claim 1, wherein any one of the plurality of data input / output circuits includes a latency circuit.   The semiconductor memory device according to claim 1, wherein any one of the plurality of data input / output circuits includes a redundant circuit.   The semiconductor memory device according to claim 1, wherein the plurality of data input / output circuits are connected to control signals having different control timings. A control delay circuit disposed between the plurality of data input / output circuits for delaying a control signal of the control circuit; and a row decoder disposed between a plurality of memory arrays corresponding to the plurality of data input / output circuits. A word line delay circuit for delaying a signal of a certain word line,
A first data input / output circuit of the plurality of data input / output circuits is connected to a control signal output from the control circuit, and a second data input / output circuit of the plurality of data input / output circuits is A first memory array of a plurality of memory arrays connected to an output of the control delay circuit and corresponding to the plurality of data input / output circuits is connected to the word line, and a first memory array of the plurality of memory arrays 3. The semiconductor memory device according to claim 1, wherein two memory arrays are connected to the word line delay circuit.   The semiconductor memory device according to claim 9, wherein both the control delay circuit and the word line delay circuit include inverter elements having the same number of stages.

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