JP2005116173A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device easily realizing a desired data width only by changing, e.g., the connection of metal wiring, without changing circuitry or layout. <P>SOLUTION: Data read through a main bit line MBL from a memory block 2 having a memory cell array constituted of a dynamic type storage element are amplified by a sense amplifier circuit and latched by a latch circuit 12, and only one of outputs from a plurality of tristate buffers 13 to receive the output of the latch circuit is set so as to become a state to be outputted. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device using a dynamic RAM (hereinafter referred to as “DRAM”). In particular, the present invention relates to a technique that is characterized by means for easily setting an optimum data input / output width according to an applied system, and that is effective for reducing the power and speed of a DRAM.

  In recent years, DRAM has become a macrocell, and a microprocessor and an ASIC (Application Specific IC: hereinafter referred to as “logic”) are formed on a single semiconductor substrate.

  By embedding DRAM, compared with the case of using external DRAM, restrictions due to the number of pins of DRAM can be eliminated, so the data input / output data width can be expanded, and data between DRAM and logic can be expanded. The transfer speed can be dramatically increased, and the integration between the DRAM and logic can be achieved by short-distance connection between the DRAM and logic by using metal wiring, so the parasitic capacitance of the input / output wiring can be remarkably reduced and the power consumption can be reduced. The advantage of being realizable is well known.

  On the other hand, in the basic operation of the DRAM, as the first operation period (hereinafter referred to as “RAS cycle”), data in a memory cell in a predetermined area is temporarily activated to read and hold the data. As an operation period (hereinafter referred to as “CAS cycle”), an operation of dividing data held in the sense amplifier into predetermined units and writing data output to the outside or input data from the outside in time series to the sense amplifier; 3 operation periods (hereinafter, referred to as “precharge cycle”), an operation for setting a precharge state in preparation for the next operation cycle.

  In a single DRAM product in practical use, DRAMs of various specifications such as a high-speed page method, EDO method, and synchronous method are generally used, but all are configured based on such basic operations and are mixed. The specifications of the DRAM macro cell to be performed are also configured based on any of these specifications.

  Furthermore, in DRAM macrocells to be embedded, the storage capacity and the input / output data width are changed in predetermined units according to the product application in accordance with the specifications of the applied semiconductor device.

By the way, there are a wide variety of fields in which semiconductor devices on which DRAMs are embedded are used, and the performance required for DRAMs varies depending on the application. For example, when applied to a system that processes graphics image data, it is required to increase the data transfer rate using a high-speed clock of 100 MHz or higher. For this reason, a wide page length and a high data transfer rate are required in the page mode or a mode equivalent thereto. (For example, see Patent Documents 1 to 3)
When applied to a system such as a portable device or a consumer device, the data transfer rate is mainly used in a random access mode with a clock frequency of about several tens of MHz or an access mode with a relatively short page length of about several pages. Lower power consumption is required than higher speed.

The page operation of the DRAM is an operation of sequentially reading (or writing) data of the sense amplifier activated in the first operation period every predetermined unit in the second operation period. Therefore, the page length is the activation region. The longer it is, the longer it can be configured. On the other hand, the power consumption of the DRAM greatly depends on the number of activated memory cell regions and the number of sense amplifiers, and the power consumption can be reduced as the activated region is reduced.
Japanese Patent Laid-Open No. 9-245474 Japanese Patent Laid-Open No. 10-83672 Japanese Patent Laid-Open No. 11-110963

  In general, a semiconductor device in which a DRAM is embedded has different input / output data widths depending on the application of the system used. However, in a conventional semiconductor device using a DRAM, it is necessary to change a circuit configuration or a layout configuration according to a required data width in order to be embedded in a semiconductor device for various uses.

  In order to overcome the above-described problems, an object of the present invention is to provide a semiconductor device that can easily realize a desired data width without changing the circuit configuration or layout configuration, for example, only by changing the connection of metal wiring. .

  In order to achieve the above object, a semiconductor device according to the present invention includes a memory cell composed of a dynamic memory element and a memory cell connected at the intersection of orthogonal word lines and bit lines arranged in a matrix. A memory cell array, a first sense amplifier circuit for amplifying the potential of the bit line, a main bit line arranged in a direction parallel to the bit line, and an output between the first sense amplifier circuit and the main bit line A memory block array in which memory blocks each having a desired storage capacity are arranged so that main bit lines in the same column are connected to each other, and a main bit. A second sense amplifier circuit that amplifies line data, a latch circuit that latches output data of the second sense amplifier circuit, and a latch circuit. A tri-state buffer that receives an output of the circuit, a first decoder circuit that selects and designates a word line and a second sense amplifier belonging to one or a plurality of memory blocks among a plurality of arranged memory blocks, and a plurality of A second decoder circuit for selecting and instructing a switch circuit belonging to one of the arranged memory blocks; an address predecoder circuit for controlling the first decoder circuit and the second decoder circuit; In a semiconductor device composed of a decoder circuit, a second sense amplifier circuit, a latch circuit, and a control signal generation circuit for controlling a tristate buffer, only one of outputs from a plurality of tristate buffers can be output. It is characterized by setting to.

  According to the above configuration, the outputs of a plurality of tristate buffers can be easily set to a desired data width without changing the circuit configuration or layout by connecting them with, for example, metal wiring.

  A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic layout diagram of a DRAM macrocell in a semiconductor device according to the present invention.

  In FIG. 1, 1 indicates a DRAM macro cell, 2 indicates a memory block obtained by blocking a memory cell array and a sense amplifier into one basic unit, and 2a indicates a sense amplifier circuit. 3 represents a row decoder, 4 represents an address predecoder circuit, 5 represents a main amplifier circuit block, and 6 represents a control signal generation circuit.

  In FIG. 1, the memory block 2 is composed of an array of a total of 512 Kbits arranged in 256 rows in the row direction and 2048 bits in the column direction, and an arbitrary storage capacity is realized by arranging a desired number of the memory blocks 2. can do. The main input / output signals to / from the DRAM macro cell 1 include a clock (CLK), a row address strobe signal (/ RAS), a column address strobe signal (/ CAS), a write enable signal (/ WE), and an address input signal ( A (i)), data output signal (Do (k)), and data input signal (Di (k)). “/” Is an identifier indicating negative logic. The DRAM macrocell 1 shown in FIG. 1 has a storage capacity of 4M (mega) bits and data input / output of 64 bits.

  FIG. 2 is a detailed configuration diagram of a part of the memory block 2, the main amplifier circuit block 5, and the row decoder 3 in the DRAM macrocell 1. In FIG. 2, 1024 sense amplifier circuits 2a are arranged in one column, and one main bit line MBL is shared by two sense amplifier circuits 2a. It is assumed that 512 input / output circuits are provided. In addition, what is indicated by “*” in the explanatory text indicates any of these 512 pieces.

  In FIG. 2, reference numeral 7 denotes a memory cell connected to the word line WL and the bit line BL, and the sense amplifier circuit 2a generally shares one sense amplifier circuit 2a with the bit line pair BL and BLB arranged on the left and right sides thereof. It is configured by a publicly known shared method.

  Reference numeral 8 denotes a transfer gate formed of an N-type MOS transistor, MBL (1), MBL (2),... Denotes a main bit line formed of a third metal, and the complementary output of the sense amplifier circuit 2a is the transfer gate 8 Are connected to the main bit lines MBL (i) and MBL (i + 1) selected via (i = 0 to 1023).

  Reference numeral 9 denotes a decoder composed of a 4-input AND circuit for selecting and instructing the opening and closing of the transfer gate 8. The first input is connected to the MBT signal for instructing the opening and closing timing of the transfer gate 8, and the second and third Are input to the address decode signals PA (0) to PA (3) and PB (0) to PB for instructing which sense amplifier circuit 2a is connected to the main bit line pair MBL (i), MBL (i + 1). (3) is program-connected, and the fourth input is ORed between the block selection signals BLK (0) to BLK (7) for selecting and instructing the memory block 2 to be activated. A logical sum of the circuits 9a is connected.

  Further, in the main amplifier circuit block 5, reference numeral 10 denotes a column decoder circuit composed of an N-type MOS transistor Q1, and an OR circuit 9b ORs the address decode signals PA (0) and PA (2) at its gate. Signals obtained by ORing the address decode signals PA (1) and PA (3) by the OR circuit 9b are alternately connected.

  11 is a main amplifier circuit that receives the outputs MA (*) and MB (*) of the column decoder 10, 12 is a latch circuit controlled by a latch signal DLCH, and 13 is an output enable signal OE (j). Is a controlled tristate buffer, and finally read data from the memory cell 7 is output from the data output terminal Do (k) (j = 0 to 7, k = 0 to 63).

  On the other hand, data is written from the data input terminal Din (k) via the inverter 15 and the tristate buffer 14 controlled by the write enable signal WE (j), and the outputs MA (*) and MB (*) of the column decoder 10. It is connected to the.

  Of the input signals of this circuit, MBT is supplied from the control signal generation circuit 6, and the address decode signals PA (0) to PA (3) and PB (0) to PB (3), the block selection signal BLK (0). ) To BLK (7) are supplied from the address predecoder circuit.

  FIG. 3 is a detailed circuit diagram of the main amplifier circuit 11 and the latch circuit 12. In FIG. 3, reference numeral 11a denotes an input signal precharge circuit, which is composed of P-type MOS transistors Q2 and Q3 having a main bit line precharge signal / MPR as a gate input. An output signal precharge circuit 11b is composed of P-type MOS transistors Q4 and Q5 having the main amplifier enable signal MSE as a gate input. Reference numeral 11c denotes an amplifier circuit, which is composed of a P-type MOS transistor Q6 and N-type MOS transistors Q7, Q8, and Q9, and is formed of a cross-coupled amplifier whose output is connected to the gates of the P-type MOS transistor Q6. . Further, the output signals MA (*) and MB (*) of the column decoder 10 are connected to the gate of the N-type transistor Q7, and the output of a latch circuit 12 described later is connected to the gate of the N-type MOS transistor Q8. A main amplifier enable signal MSE is connected to the gate of the type MOS transistor Q9.

  The latch circuit 12 includes a tristate inverter composed of P-type MOS transistors Q10 and Q11 and N-type MOS transistors Q12 and Q13 connected in series, inverters 16 and 17, a P-type MOS transistor Q14, and an N-type MOS transistor Q15. It consists of a transfer gate consisting of The latch circuit 12 is controlled by a latch signal DLCH, its complementary output is connected to the N-type MOS transistor Q8 of the amplifier circuit 11c, and one output Mout (*) is connected to the tristate buffer 13 shown in FIG. . Note that the input signals / MPR, MSE, and DLCH of this circuit are all supplied from the control signal generation circuit 6.

  FIG. 4 is a detailed circuit diagram of an input circuit among the circuits constituting the address predecoder circuit 4. In FIG. 4, 18 is a selector circuit, 19 is a load / hold type D-FF circuit, 20 and 21 are inverters, and 22 is a program circuit that is fixed at "H" level or "L" level.

  The selector circuit 18 has a RACF signal for enabling address input in the RAS cycle connected to the A port, a CACF signal for enabling address input in the CAS cycle is connected to the B port, and the selector port S has a program circuit. 22 outputs are connected, and one of the A port input and the B port input is output to the output port Y. The selector circuit 18 outputs the data of the A port to the port Y when the input level of the S port is “L” level, and the data of the B port when the input level of the S port is “H” level. Output to Y.

  In the load / hold type D-FF circuit 19, the output of the selector circuit 18 is connected to the load / hold port LH, the address signal A (i) is connected to the data input port D, and the clock signal CLK is connected to the clock port CK. Are connected, and positive and negative logic signals AP (i) and AN (i) are output via inverters 20 and 21.

  The program circuit 22 is connected to one of the power supply wiring and the ground wiring by metal wiring for each address according to the page length specification of the semiconductor device to which the DRAM macrocell 1 is applied. Of the input signals of this circuit, RACF, CACF, and CLK are supplied from the control signal generating circuit 6.

  5 to 7 are circuit diagrams of an address predecode circuit related to the selection of the main bit line among the circuits constituting the address predecoder circuit 4. FIG. FIG. 5 is a circuit diagram of a block selection predecoder circuit for selecting and instructing one of the eight memory blocks 2. FIGS. 6 and 7 select and instruct the main bit line MBL (i) and the sense amplifier circuit 2a. It is a circuit diagram of an address decoding circuit. The output signal of any circuit is input to the row decoder 3.

  Reference numerals 23, 25, and 26 denote AND circuits, and reference numeral 24 denotes a program circuit that is connected to either a power supply line or an address signal by a metal wiring. Any address signal is connected to the output of the input circuit described in FIG.

  FIG. 8 is a signal generation circuit related to the control of the main amplifier block 5 and the main bit line shown in FIG. 2 or 3 among the circuits constituting the control signal generation circuit 6. Reference numeral 30 is a reference pulse generation circuit for generating an output MPULSE composed of a clock CLK and an enable terminal, 31 is a pulse generation circuit generated based on a signal from the reference pulse generation circuit 30, and 32 is input with / RAS and / CAS. NOR circuit 33, D-FF circuit, 34a to 34c are inverters, 35 is a NAND circuit, 36 is an inverter circuit, 37 is either the output B of the NOR circuit 32 or the output A of the inverter 36 as a reference pulse generation circuit This is a program circuit connected to 30 enable terminals with metal. The reference pulse generation circuit 30 is configured to generate a pulse MPULSE having a predetermined width in synchronization with the rising edge of the clock CLK input during the period when the “H” level is input to the enable terminal.

  FIG. 9 is a circuit diagram of a predecode circuit for output enable signals OE (0) to OE (7) for controlling the tristate buffer 13 shown in FIG. 2 among the circuits constituting the address predecoder circuit 4. Reference numeral 27 denotes a 4-input AND circuit which receives a data output timing control signal OE and column address signals AN (13) to AN (15) and AP (13) to AP (15). Each address signal is connected to the output of the input circuit described in FIG. 4, and the timing control signal OE is supplied from the control signal generation circuit 6.

  FIG. 10 is a connection diagram of the tristate buffer 13 shown in FIG. The DRAM macro cell 1 has a tri-state buffer 13 that operates in parallel for 512 bits. In order to convert the DRAM macro cell 1 into a 64-bit output configuration, the outputs of the adjacent tri-state buffers 13 are connected in common with metal in units of eight. Yes. Further, the output enable signal OE (j) described in FIG. 9 is connected to each output.

  Next, a setting method and operation of the semiconductor device configured as described above will be described with reference to the drawings. FIG. 11 is a timing chart relating to the read control method of the DRAM macrocell 1.

  In FIG. 11, the operation of the DRAM macrocell 1 is controlled in synchronization with the rising edge of the clock CLK. First, at time t0, the row address strobe / RAS is at "L" level and the column address strobe / CAS is at "H" level, and the row address A (i) is fetched. Next, column address A (i) is fetched in response to the fact that both row address strobe / RAS and column address strobe / CAS are at "L" level at time t1. Thereafter, after the elapse of tA in the same cycle, the data at the corresponding address is output from the data output terminal Do. Next, when the next column system address is input at time t2, similarly, after the elapse of tA, data corresponding to that address is output.

  Thereafter, this page mode operation is repeated in the column address space within the set page length. When both the row address strobe / RAS and the column address strobe / CAS are set to “H”, the precharge operation is started at the timing synchronized with the “H” edge of the clock CLK.

  FIG. 12 is a correspondence diagram of page length and address assignment. Since this DRAM macrocell 1 has a storage capacity of 4 Mbits and a 64-bit configuration, the required address is 16 bits A0 to A15.

  As shown in FIG. 12A, when the maximum page length required for the DRAM macrocell 1 by a semiconductor device incorporating DRAM is 8 pages or less, 13 bits A0 to A12 are fetched in the RAS cycle (at time t0 in FIG. 11). Timing) is set, and only 3 bits A13 to A15 are captured in the CAS cycle (timing after time t1 in FIG. 11). Specifically, among the program circuits 22 shown in FIG. 4, the “L” level is set for those corresponding to A0 to A12, and the “H” level is set for those corresponding to A13 to A15. Further, the program circuits 24 shown in FIG. 5 are all set on the address signal lines AN (j) and AP (j) side as shown in FIG. Further, all the program circuits 24 shown in FIG. 7 are set on the power supply line side. Further, the program circuit 37 shown in FIG. 8 is set on the terminal A side shown in FIG.

  When the maximum page length required for the DRAM macrocell 1 is 9 pages or more and 32 pages or less in a semiconductor device incorporating DRAM as shown in FIG. 12 (2), 11 bits A0 to A10 are captured in the RAS cycle (FIG. 11). (Timing at time t0) is set, and 5 bits A11 to A15 are captured in the CAS cycle (timing after time t1 in FIG. 11). Specifically, among the program circuits 22 shown in FIG. 4, the “L” level is set for those corresponding to A0 to A10, and the “H” level is set for those corresponding to A11 to A15. 5 are all set on the address signal lines AN (j) and AP (j) as shown in FIG. 5, and all the program circuits 24 shown in FIG. 7 are set on the power supply line side. Keep it. Further, the program circuit 37 shown in FIG. 8 is set on the terminal B side shown in FIG.

  As shown in FIG. 12 (3), when the maximum page length required for the DRAM macrocell 1 by the semiconductor device incorporating DRAM is 33 pages or more and 64 pages or less, 10 bits A0 to A9 are captured in the RAS cycle (FIG. 11). (Timing at time t0) is set, and 6 bits A10 to A15 are captured in the CAS cycle (timing after time t1 in FIG. 11). As a specific setting method, “L” level setting is performed for those corresponding to A0 to A9 in the program circuit 22 shown in FIG. 4, and “H” level setting is performed for those corresponding to A10 to A15. Further, the program circuit 24 shown in FIG. 5 sets the address signal lines AN (10) and AP (10) to the power supply line side, and the program circuit 24 shown in FIG. 7 has the power supply lines only for AN (9) and AP (9). Set to the side. Further, the program circuit 37 shown in FIG. 8 is set on the terminal B side shown in FIG.

  As shown in FIG. 12 (4), when the maximum page length required for the DRAM macrocell 1 in a semiconductor device incorporating DRAM is 65 pages or more and 128 pages or less, 9 bits A0 to A8 are captured in the RAS cycle (FIG. 11). (Timing at time t0) is set, and the 7 bits A9 to A15 are captured in the CAS cycle (timing after time t1 in FIG. 11). Specifically, among the program circuits 22 shown in FIG. 4, the “L” level is set for those corresponding to A0 to A8, and the “H” level is set for those corresponding to A9 to A15. Further, all the program circuits 24 shown in FIG. 5 are set on the power supply line side, and all the program circuits 24 shown in FIG. 7 are set on the address signal lines AN (j) and AP (j) side. Further, the program circuit 37 shown in FIG. 8 is set on the terminal B side shown in FIG.

  As shown in FIG. 1, the DRAM macrocell 1 includes 8 blocks of memory cell arrays and 9 rows of sense amplifier rows. FIG. 13 is a view showing an example of regions activated by one read or write operation for each page length setting.

  When the page length is set to 8 pages or 32 pages, the output signals BLK (0) to BLK (7) of the block selection predecoder circuit shown in FIG. 5 as shown in FIG. Since only one is selected, only one of the eight blocks of the memory cell array and two sense amplifier columns on both sides thereof, that is, 2048 sense amplifier circuits 2a are activated.

  When the page length is set to 64 pages, two output signals BLK (0) to BLK (7) of the block selection predecoder circuit shown in FIG. 5 as shown in FIG. 13 (2) are selected for the address input. Therefore, 2 blocks of the 8 blocks of the memory cell array and 4 sense amplifier columns on both sides thereof, that is, 4096 sense amplifier circuits 2a are activated.

  When the page length is set to 128 pages, four output signals BLK (0) to BLK (7) of the block selection predecoder circuit shown in FIG. 5 as shown in FIG. 13 (3) are selected for the address input. Therefore, 4 blocks of the 8 blocks of the memory cell array and 8 sense amplifier columns on both sides thereof, that is, 8192 sense amplifier circuits 2a are activated.

  Next, the timing operation of the internal signal will be described. FIG. 16 shows the operation of the reference pulse generation circuit 30 shown in FIG. 8 when the enable terminal is connected to the terminal A side (that is, when the page length is set to 8 pages) and when it is connected to the terminal B side (that is, the page length is 32). (In case of setting more than page).

  In FIG. 16, the output of the NOR circuit 32 is “H” level while both / RAS and / CAS are “L” level. Therefore, when connected to the terminal B side, the reference pulse MPULSE is generated every time during that period in synchronization with the rising edge of the clock CLK.

  On the other hand, the output of the D-FF circuit 33 is a signal obtained by sampling the output of the NOR circuit 32 with the clock CLK, and further becomes a negative phase signal obtained by delaying the output through the inverters 34a, 34b, and 34c. The output of the inverter 36 is outputted at the “H” level only for a predetermined period after the clock first rises from the timing when both / RAS and / CAS are set to the “L” level. Therefore, when connected to the terminal A side, the reference pulse MPULSE is generated only once in synchronization with the rising edge of the clock CLK.

  FIG. 14 shows the operation of the DRAM macrocell 1 when the page length is set to 8 pages. First, a row-related address is taken in at the timing of time t0, and the word line WL and the sense amplifier column designated by the block selection signal BLK (*) are activated accordingly, and the amplification operation of the bit line pair BL, BLB is performed. Is called.

  Next, along with the column address fetch at the timing of time t1, the reference pulse MPULSE is generated only once by the reference pulse generation circuit 30 as described above, and accordingly, the transfer gate control signal MBT, the latch signal DLCH, the main bit are generated. The line precharge signal / MPR and the main amplifier enable signal MSE are generated by the pulse generation circuit 31 with the timing relationship described below.

  First, the latch signal DLCH is set to the “L” level, and the latch circuit 12 enters the through state. Thereafter, the main bit line precharge signal / MPR is set to "H" level, and the precharge operation of the main bit line is completed. At the same time, the transfer gate control signal MBT is set to the “H” level. Since address decode signals PA (0) to PA (3) and PB (0) to PB (3) have been determined up to that point, sense amplifier 2a corresponding to the designated address and main bit line MBL (i) , MBL (i + 1) are connected. Thereafter, the main amplifier enable signal MSE is set to the “H” level, the main amplifier 11 is activated, and the data of the sense amplifier 2a is read. Thereafter, the latch signal DLCH is set to the “H” level and the data read by the main amplifier 11 is latched, and then the main amplifier is deactivated, the transfer gate is closed, and the main bit line is precharged. Further, the data of the corresponding latch circuit 12 is output from the output terminal Do (k) according to the instruction of the output enable signal OE (j) and the column address.

  At the timing after t2, the operation of the main amplifier 11 and the like is not performed, and the data latched in the cycle of t1 by the latch circuit 12 is only enabled for the tristate buffer 13 indicated by the column addresses A13 to A15. Is output. In the case of this setting, since the activation of the minimum sense amplifier row and the main bit line are only operated once, the power consumption can be reduced.

  FIG. 15 shows the operation of the DRAM macrocell 1 when the page length is set to 32 pages or more. The difference from the case where the page length is set to 8 pages in FIG. 14 is that the row address and the column address are allocated and the read operation of the main amplifier is performed every time after t1.

  In general, a semiconductor device in which a DRAM is embedded has different input / output data widths depending on the application of the system used. FIG. 17 shows the connection state of the output section of the tristate buffer 13 described in FIG. 2 for various data widths.

  As described with reference to FIG. 10, in the case of a 64-bit output configuration, among the 512 tristate buffers 13 arranged, the outputs of eight adjacent tristate buffers 13 are commonly connected by metal, and this terminal is connected to a DRAM macro cell. 1 output terminal Do (k) (k = 0 to 63).

  In the case of a 128-bit output configuration, among the 512 tristate buffers 13 arranged, the outputs of four adjacent tristate buffers 13 are commonly connected by metal, and this terminal is connected to the output terminal Do (k) of the DRAM macrocell 1. (K = 0 to 127).

  In the case of a 256-bit output configuration, among the 512 tristate buffers 13 arranged, the outputs of two adjacent tristate buffers 13 are commonly connected by metal, and this terminal is connected to the output terminal Do (k) of the DRAM macrocell 1. (K = 0 to 255).

  In the 512-bit output configuration, the outputs of 512 tristate buffers 13 are directly used as the output terminals Do (k) of the DRAM macro cell 1 (k = 0 to 511).

  FIG. 18 shows a circuit diagram of a predecode circuit for the output enable signals OE (0) to OE (7). A program circuit 40 is added to the same configuration as the predecode circuit shown in FIG.

  In the case of a 64-bit output configuration, programming is performed on the AN (13) to AN (15) and AP (13) to AP (15) sides as shown in FIG. As a result, only one of the eight outputs OE (0) to OE (7) is selected.

  In the case of a 128-bit output configuration, AN (15) and AP (15) are programmed to the power supply line side. As a result, one of the four outputs OE (0) to OE (3) and one of the four outputs OE (4) to OE (7) are selected.

  In the case of a 256-bit output configuration, AN (14), AP (14), AN (15), and AP (15) are programmed on the power supply line side. As a result, one of the two outputs OE (0) to OE (1), one of the two outputs OE (2) to OE (3), and the two outputs OE (4) to OE (5) One of the two outputs OE (6) to OE (7) is selected.

  In the case of a 512-bit output configuration, AN (13) to AN (15) and AP (13) to AP (15) are all programmed on the power supply line side. As a result, all eight outputs are selected in conjunction with the movement of the OE.

  The program circuits 22, 24, and 40 have a method of bypassing the signal line by metal wiring, but a program by contact connection or a method of providing a switch by a transistor instead of the metal wiring may be used.

  The selector circuit 18 and the program circuit 22 shown in FIG. 4 are provided for all address inputs A0 to A15, but are provided only for required address inputs (A9 to A12 when the page length = 8 pages). May be.

  In FIG. 8, when the page length is 8 pages, the reference pulse MPULSE is connected to the A terminal and is generated only once in the CAS cycle. However, when the purpose of simplifying the circuit and the page mode itself is not used. Alternatively, the signal on the terminal B side may be substituted.

  Furthermore, the specification of the DRAM macro cell 1 described in FIG. 11 and the like is a method similar to a generally known EDO method, but is similarly applied to a synchronous method or a DRAM having a plurality of banks. it can.

  As described above, according to the present embodiment, the activation area and page length of the DRAM macro cell can be freely set. Therefore, in the large-capacity data requiring the page length, the activation area is continuously set. By securing it, the data transfer speed can be increased. On the other hand, in the case of normal data that does not require a page length, processing is performed with the minimum activation area without generating a useless activation area. Thus, power saving can be achieved. In addition, by connecting the outputs of the plurality of tristate buffers with metal, it is possible to change the data width to a desired value only by changing the connection of the metal wiring without changing the circuit configuration or layout.

  According to the semiconductor device of the present invention, the optimum data width can be set according to the system to be applied without changing the circuit configuration and layout, which is useful for reducing the power and speed of the DRAM.

Schematic layout of a DRAM macro cell to which the present invention is applied Detailed configuration diagram of DRAM macrocell Detailed circuit diagram of main amplifier circuit and latch circuit Detailed circuit diagram of input circuit Circuit diagram of address predecode circuit Circuit diagram of address predecode circuit Circuit diagram of address predecode circuit Control signal generation circuit diagram of main amplifier block etc. Circuit diagram of predecode circuit for output enable signal Tri-state buffer connection diagram Timing diagram for DRAM macrocell read control method Relationship between page length and address assignment Illustration of memory cell array and sense amplifier row activation region Timing diagram for page length = 8 pages Timing diagram for page length = 32 pages or more Timing chart of reference pulse generator Connection state diagram of tristate buffer output Circuit diagram of predecode circuit for output enable signal

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 DRAM macrocell 2 Memory block 2a Sense amplifier circuit 3 Row decoder 4 Address predecoder circuit 5 Main amplifier circuit block 6 Control signal generation circuit 7 Memory cell 8 Transfer gate 9 Decoder 10 Column decoder circuit 11 Main amplifier circuit 12 Latch circuit 13, 14 Tri-state buffer 15, 16, 17, 20, 21, 34a, 34b, 34c Inverter 18 Selector circuit 19 Load / hold type D-FF circuit 22, 24, 37, 40 Program circuit 23, 25, 26, 27 AND circuit 30 Reference pulse generation circuit 31 Pulse generation circuit 32 NOR circuit 33 D-FF circuit 35 NAND circuit 36 Inverter circuit

Claims (1)

A memory cell composed of a dynamic memory element;
A memory cell array in which a predetermined number of memory cells connected to the intersections of orthogonal word lines and bit lines are arranged in a matrix;
A first sense amplifier circuit for amplifying the potential of the bit line;
A main bit line disposed in a direction parallel to the bit line;
The basic unit is a memory block composed of a switch circuit that controls conduction between the output of the first sense amplifier circuit and the main bit line,
A memory block array in which the memory blocks for a desired storage capacity are arranged so that the main bit lines in the same column are connected to each other;
A second sense amplifier circuit for amplifying data of the main bit line;
A latch circuit for latching output data of the second sense amplifier circuit;
A tri-state buffer that receives the output of the latch circuit;
A first decoder circuit for selecting and instructing the word line and the second sense amplifier belonging to one or a plurality of the memory blocks among a plurality of the memory blocks arranged;
A second decoder circuit for selecting and instructing the switch circuit belonging to one of the plurality of memory blocks,
An address predecoder circuit for controlling the first decoder circuit and the second decoder circuit;
In the semiconductor device including the second decoder circuit, the second sense amplifier circuit, the latch circuit, and a control signal generation circuit for controlling the tristate buffer,
A semiconductor device characterized in that only one of the outputs from the plurality of tristate buffers is set to an output enabled state.

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