JPH09204779A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device reducing a layout area of data bus wiring. SOLUTION: When the data are read out, the read-out data are latched to a data latch 123 by a first pulse signal, and an input/output buffer connection transfer gate 131 and an input/output line common bit line selection transfer gate 137 are turned on to be transferred to a data input/output buffer 129 through an input/output common bit line pair 141. When the data are written in, the input/output buffer connection gate 131 and the input/output line common bit line selection transfer gate 137 are turned on by the first pulse signal, and the written data are latched by the data latch 123 through the input/output line common bit line pair 141 to be written in a required memory cell MCx by a second pulse signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of reading and writing data.

[0002]

2. Description of the Related Art FIG. 10 shows a conventional asynchronous SRAM 10
FIG. 2 is a block diagram showing a configuration of a 00. Hereinafter, the same reference numerals indicate the same things.

Referring to FIG. 10, when a chip select state is set by a chip enable signal CE, an address signal Add input from the outside drives an address buffer 103. A part of the output signal of the address buffer 103 is transferred to the word line selection decoder 111, and the desired word line WLx is selected. Address buffer 10
The rest of the output signals of No. 3 are transferred to the bit line selection decoder 113, the bit line selection transfer gate (column selection gate) TGx is turned on, and the desired bit line pair BLx.
Is selected. The memory cell MCx at the intersection of the word line WLx and the bit line pair BLx thus selected is selected.

When the read state is set by the read / write setting signal R / W, the memory cell M is placed in the bit line pair BLx which has been boosted to a constant voltage in advance by the bit line load 115.
Read data is output from Cx, selected via the bit line selection transfer gate TGx and the input / output line pair 117 by the upper address of the bit line pair selection address, and
It is transferred to the sense amplifier 121 activated by the read mode setting signal output from the mode setting signal generation circuit 101. The read data further amplified by the sense amplifier 121 is transferred to the data input / output buffer 129 via the data bus 1001 and the data input / output terminal 13
3 is output.

On the other hand, when the write state is set by the read / write setting signal R / W, the write data input from the data input / output terminal 133 is the address for selecting the bit line pair via the data bus 1001. Selected by the upper address of
In addition, the write driver 127 activated by the write mode setting signal output from the mode setting signal generation circuit 101.
Is forwarded to Then, the write data is written from the write driver 127 to the input / output line pair 117, the selected bit line selection transfer gate TGx and the bit line pair BLx.
Is written to the desired memory cell MCx via.

By the way, Address T detecting that the address signal Add input from the outside has changed
position detector (hereinafter, ATD
A method of controlling the equalization of the bit line pair and the selection period of the word line or the bit line pair by the output pulse signal of the generation circuit 105 is generally adopted. Equalization of the bit line pair is performed to restore the potential of the bit line pair after the read / write operation, and normally, equalization is performed using a pulse signal output from ATD generation circuit 109 before word selection. . As a result, the potential of the bit line pair is quickly boosted to the precharge potential, so that the law of data transfer can be established. The selection period of the word line or bit line pair is controlled so that only the pulse width period of the output pulse signal of the ATD generation circuit 109 becomes the selection period. This is effective in reducing power consumption and improving other characteristics.

FIG. 11 is a block diagram showing a structure of a conventional asynchronous pipeline type SRAM 1100.

Referring to FIG. 11, in the asynchronous pipeline type SRAM 1100, when the chip select signal CE sets the chip selection state, the address signal Add and the read / write setting signal R / W input from the outside are set. At the rising edge of the external clock signal Ck, the address register 509 and the mode register 5
It is latched to 07. Latched address signal Add
Is transferred to the word line selection decoder 111, and the desired word line WLx is selected. The rest of the latched address signal Add is transferred to the bit line selection decoder 113, the bit line selection transfer gate TGx is turned on, and the desired bit line pair BLx is selected. The memory cell MCx at the intersection of the word line WLx and the bit line pair BLx thus selected is selected.

When the read state is set by the read / write setting control R / W, the memory cell M is placed in the bit line pair BLx which has been boosted to a constant voltage by the bit line load 115 in advance.
The read data is output from Cx, the sense amplifier 12 selected by the upper address of the bit line pair selection address and activated by the output signal of the mode register 509 via the bit line selection transfer gate TGx and the input / output line pair 117.
Transferred to 1. The read data further amplified by the sense amplifier 121 is latched in the data register 505 via the data bus 1001. Further, the latched read data is transferred to data input / output buffer 129 and output to data input / output terminal 133 in synchronization with the next rising edge of external clock signal Ck.

On the other hand, when the write state is set by the read / write setting signal R / W, the write data input from the data input / output terminal 133 is the address signal Add and the read / write setting signal R / W. At the rising edge of the external clock signal Ck similar to the above, it is latched in the data register 505 via the data input / output buffer 129. After that, the latched write data is transferred to the data bus 1
It is transferred to the write driver 127 selected via the upper address of the bit line pair selection address via 001 and activated by the output signal of the mode register 507. The write data output from the write driver is written into a desired memory cell MCx via the input / output line pair 117, the selected bit line selection transfer gate TGx and the bit line pair BLx.

In the case of a non-pipeline type synchronous SRAM without the data register 505, during data reading,
The read data output from the sense amplifier 121 is directly transferred to the data input / output buffer 129 via the data bus 1001 and read to the data input / output terminal 133. At the time of data writing, the write data input from the data input / output terminal 133 is passed through the data input / output buffer 129 as it is to the data bus 1001 and the write driver 1.
Since the data is written in the memory cell MCx via the input line 27, the input / output line pair 117, the bit line selection transfer gate TGx, and the bit line pair BLx, the control of the data register 505 by the external clock signal Ck becomes unnecessary.

FIG. 12 shows a pulse generation circuit 501 of FIG.
FIG. 4 is a circuit diagram showing an example of the embodiment. In the case of a synchronous SRAM such as the synchronous pipeline type SRAM 1100 shown in FIG. 11, the pulse generation circuit 501 shown in FIG. 12 is used for equalizing the bit line pair and controlling the selection period of the word line and the bit line pair. It is performed by the pulse signal output from. The pulse generation circuit 501 uses the external clock signal C
The desired pulse signal is generated in synchronization with the rising edge of k.

FIG. 13 shows a pulse generation circuit 501 of FIG.
6 is a timing chart showing a pulse signal output from the device.

The operation of the pulse generation circuit 501 of FIG. 12 will be described with reference to the timing chart of FIG.

The external clock signal Ck is the pulse generation circuit 5
When input to 01, the delay circuit 1201 and the NOT circuit 1
The complementary signal having a delay due to 203 is the NAND circuit 12
It is input to 05. From the NAND circuit 1205, the NAND circuit 1205 outputs NAND to the rising edge of the external clock signal Ck.
A pulse signal having a delay of the circuit 1205 and a delay of the pulse width of (delay circuit 1201 + NOT circuit 1203) is generated (). NAND circuits 1207 and 12
No. 07-243 when the power is turned on to the output node of 09.
An N-channel MOS transistor (hereinafter, referred to as an NMOS transistor) 1213 having a gate input of a power-on reset signal which becomes “H (logic high) level, as already known in 79, has an initial value of“ L (logic low). ) ”
Since it is set to the level, the NAND circuit 1207 has a delay due to the NAND circuits 1205 and 1207, and the pulse width is (NAND circuit 120
A pulse signal having a delay of 7 + NAND circuit 1209 × 2 + delay circuit 1211) is generated ().

The pulse signal thus generated is
Like the pulse signal output from the ATD generation circuit 105 of an asynchronous SRAM such as the asynchronous SRAM 1000 shown in FIG. 10, it is used for equalizing bit line pairs and controlling the selection period of word lines and bit line pairs. To be

As described above, the conventional asynchronous and synchronous SRAM has a data bus from the sense amplifier or write driver to the data input / output buffer.
In recent years, multi-bit memory has become the mainstream, and external data bus wiring has come to occupy a large layout area.

[0018]

However, with the reduction of the layout area of the memory cell, the sense amplifiers are alternately arranged on both sides of the memory cell area, and the use of the arrangement of external pins causes the memory cell area to be sandwiched. From the sense amplifier or write driver on the opposite side to the data input / output buffer, it is not uncommon for data bus wiring to be routed around the memory cell area, further increasing the area occupied by the layout area of the data bus wiring. There was a problem to do.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device having a reduced layout area of data bus wiring.

[0020]

A semiconductor memory device according to a first aspect of the present invention is provided with an input / output buffer, a plurality of bit lines, and an input / output line, each corresponding to one of the plurality of bit lines. , A plurality of column selection gates connected between the plurality of bit lines and the input / output lines, and a data latch connected to the input / output lines to latch data are provided, and the plurality of bit lines are provided with
An I / O line shared bit line is provided, an I / O line shared bit line selection gate connected to the I / O line shared bit line is provided at the plurality of column selection gates, and an I / O buffer and an I / O line shared bit line are provided. The input / output buffer connection gate connected between the column selection gate and the column selection gate corresponding to the input column address signal are turned on at the first timing during data reading, and the column selection gate turned on at the first timing is turned on at the first timing. The first gate control means which is turned off at the second timing later than the second timing, and the input / output line shared bit line selection gate and the input / output buffer connection gate at the time of data reading are the third timing later than the second timing. Turns on at the timing, and at the time of data writing, turns on the input / output buffer connection gate and the input / output line shared bit line select gate at the fourth timing A second gate control means for turning off the buffer connection gate and the input / output line supply bit line selection gate at a fifth timing later than the fourth timing is further provided, and the first gate control means is configured to write the data. At the time of writing, the column selection gate corresponding to the input column address signal is turned on at the sixth timing which is later than the fifth timing.

A semiconductor memory device according to a second aspect is the semiconductor memory device according to the first aspect, wherein the voltage of the bit line adjacent to the input / output line shared bit line is read at the second timing and when the data is written. The voltage fixing means for fixing the voltage to a constant voltage at the fourth timing when the switch is turned on is further provided.

According to another aspect of the semiconductor memory device of the present invention, an input / output buffer, a plurality of bit lines, and an input / output line are respectively provided.
A plurality of column selection gates provided corresponding to one of the plurality of bit lines and connected between the plurality of bit lines and the input / output lines; a data latch connected to the input / output lines and latching data; I / O line shared bit lines are provided for the plurality of bit lines, and I / O line shared bit line selection gates connected to the I / O line shared bit lines are provided for the plurality of column selection gates. A pulse for outputting an input / output buffer connection gate connected between the input / output line shared bit line, a first pulse signal, and a second pulse signal output after the inactivation of the first pulse signal Signal output means and in response to activation of the first or second pulse signal,
First gate control means for turning on the column selection gate corresponding to the inputted column address signal and turning off the turned-on column selection gate in response to the deactivation of the activated first or second pulse signal. In response to the activation of the first or second pulse signal, the input / output buffer connection gate and the input / output line shared bit line selection gate are turned on to disable the activation of the activated first or second pulse signal. Second gate control means for turning off the turned-on input / output buffer connection gate and the input / output line shared bit line select gate in response to activation, and a first pulse signal for controlling the first pulse signal during data reading. Means, the second pulse signal is transferred to the second gate control means, the first pulse signal is transferred to the second gate control means, and the second pulse signal is transferred to the first gate control means during data writing. Gate control And the pulse signal transfer means for transferring the stage, in which the provided.

According to a fourth aspect of the present invention, in the semiconductor memory device according to the third aspect, the voltage of the bit line adjacent to the input / output line shared bit line is constant when the first and second pulse signals are activated. Voltage fixing means for fixing the voltage is further provided.

A semiconductor memory device according to a fifth aspect is the semiconductor memory device according to any one of the first to fourth aspects, in which the first sense amplifier connected between the plurality of bit lines and the data latch, and the data latch. And a write driver connected between the bit line and the plurality of bit lines, and the input / output line sharing bit line is a bit line among the plurality of bit lines, among the input / output buffer, the first sense amplifier, and the write driver. It is the bit line that is the shortest distance from one.

According to another aspect of the semiconductor memory device of the present invention, an input / output buffer, a plurality of bit line pairs, and an input / output line are provided corresponding to one of the plurality of bit line pairs. A plurality of column selection gates connected between the bit line pair and the input / output line and a data latch connected to the input / output line for latching data are provided, and the plurality of bit line pairs are provided with the input / output line shared bit. A line pair is provided, and an I / O line shared bit line selection gate connected to the I / O line shared bit line pair is provided for a plurality of column selection gates, and is connected between the I / O buffer and the I / O line shared bit line pair. The input / output buffer connection gate and the column selection gate corresponding to the input column address signal are turned on at the first timing and the column selection gate turned on at the first timing is turned on at the first timing during data reading. The first gate control means which is turned off at the second timing, which is later than the second timing, and the input / output line shared bit line selection gate and the input / output buffer connection gate, at the time of data reading, at the third timing later than the second timing. When turned on and writing data, the input / output buffer connection gate and the input / output line shared bit line selection gate are turned on at the fourth timing, and the input / output buffer connection gate and the input / output line shared bit line selection gate are set to the fourth timing. Second gate control means which is turned off at a fifth timing later than the timing;
Further, the first gate control means turns on the column select gate corresponding to the input column address signal at the sixth timing later than the fifth timing at the time of data writing.

A semiconductor memory device according to a seventh aspect is the semiconductor memory device according to the sixth aspect, wherein the voltage of the bit line adjacent to the I / O line shared bit line pair is set at the second timing during data reading, and A voltage fixing means for fixing a constant voltage at a fourth timing when writing data is further provided.

According to another aspect of the semiconductor memory device of the present invention, an input / output buffer, a plurality of bit line pairs, and an input / output line are provided corresponding to one of the plurality of bit line pairs, respectively. A plurality of column selection gates connected between the bit line pair and the input / output line and a data latch connected to the input / output line for latching data are provided, and the plurality of bit line pairs are provided with the input / output line shared bit. A line pair is provided, and a plurality of column selection gates are provided with an input / output line shared bit line selection gate connected to the input / output line shared bit line pair, and a first pulse signal and a first pulse signal are provided.
Pulse signal output means for outputting a second pulse signal output after the pulse signal is inactivated, and the first or second pulse signal output means.
The column select gate corresponding to the input column address signal is turned on in response to the activation of the pulse signal of 1 and is turned on in response to the deactivation of the activated first or second pulse signal. The first gate control means for turning off the column selection gate, and the input / output buffer connection gate and the input / output line shared bit line selection gate are turned on and activated in response to the activation of the first or second pulse signal. Second gate control means for turning off the input / output buffer connection gate and the input / output line shared bit line selection gate in response to the inactivation of the activated first or second pulse signal; Transferring the first pulse signal to the first gate control means,
Pulse signal is transferred to the second gate control means, and at the time of data writing, the first pulse signal is transferred to the second gate control means and the second pulse signal is transferred to the first gate control means. And pulse signal transfer means.

A semiconductor memory device according to a ninth aspect is the semiconductor memory device according to the eighth aspect, wherein the voltage of the bit line adjacent to the I / O line shared bit line pair is set at the time of activation of the first and second pulse signals. Voltage fixing means to fix a constant voltage,
It is further provided.

A semiconductor memory device according to a tenth aspect of the present invention is the semiconductor memory device according to any one of the sixth to ninth aspects, in which the first sense amplifier connected between the plurality of bit line pairs and the data latch is connected to the data latch. A write driver connected between the latch and the plurality of bit line pairs is further provided, and the input / output line shared bit line is an input / output buffer, a first sense amplifier, and a write driver of the plurality of bit line pairs. The bit line that is the shortest distance from one of

According to an eleventh aspect of the present invention, in the semiconductor memory device according to any one of the third to fifth aspects or the eighth to tenth aspects, the pulse signal output means changes the address signal inputted from the outside. It detects and outputs the first and second pulse signals.

A semiconductor memory device according to a twelfth aspect of the present invention is the semiconductor memory device according to any one of the third to fifth aspects or the eighth to eleventh aspects, wherein the pulse signal output means is synchronized with a clock signal input from the outside. Then, the first and second pulse signals are output.

A semiconductor memory device according to a thirteenth aspect is the semiconductor memory device according to any one of the third to fifth aspects or the eighth to twelfth aspects, wherein the first pulse signal is inactivated and the second pulse signal is inactivated. Precharge / equalize multiple bit lines between activation of
Equalizing means is further provided.

A semiconductor memory device according to a fourteenth aspect is the semiconductor memory device according to any one of the first to thirteenth aspects, further comprising a second sense amplifier connected between the input / output buffer connection gate and the input / output buffer. It is further provided.

[0034]

Embodiments of the present invention will be described below with reference to the drawings.

(1) First Embodiment FIG. 1 is a block diagram showing an asynchronous SRAM 100 according to a first embodiment of a semiconductor memory device of the present invention.

Referring to FIG. 1, an asynchronous SRAM 100
, WLx, ... WLm (collectively referred to as WL. In the figure, WL1 and WLx are representative.
Is shown. ) And a plurality of bit line pairs BL1, ..., BLx, ..., BLy, ..., BLn (collectively referred to as BL. In the figure, BLx is representatively shown) intersecting the word line WL. , MCx, ..., MCy, which are connected to the word line WL and the bit line pair BL.
, ..., MCs (collectively referred to as MC. MCx and MCy are representatively shown in the figure), and the input chip enable signal CE and read / write setting signal R / W.
A mode setting signal generating circuit 101 for generating a mode setting signal for setting a mode of a chip based on the above, an address buffer 103 to which an address signal is input from the outside, and an AT for generating a pulse signal based on a change in the address signal.
The D generation circuit 105, the word line selection decoder 111 that selects the word line WL based on the row address signal input from the address buffer 103, and the address buffer 1.
A bit line selection decoder 113 for selecting the bit line pair BL based on the column address signal input from
Decode ATD selection circuit 107 that controls the pulse signal output from TD generation circuit 105 and outputs it to word line selection decoder 111 and bit line selection decoder 113, input / output line pair 117, bit line selection transfer gate TG1 ,. , TGx, ..., TGy, ..., TGn (collectively referred to as TG. In the figure, TGx is shown as a representative). The bit line pair BL includes an input / output line shared bit line pair 141 having a function similar to that of a conventional data bus, and the bit line selection transfer gate TG includes an input / output line shared bit line selection transfer gate 137.

The asynchronous SRAM 100 includes an input / output line shared bit line selection transfer gate control signal generation circuit 119 for generating a control signal for controlling the input / output line shared bit line selection transfer gate, and a sense amplifier 121.
And a data latch 1 for latching read or write data
23, an input / output line shared bit line pair and a data latch 123
Latch data transfer transfer gate 1 for connecting to
25, the pulse signal output from the ATD generation circuit, the input / output line shared bit line selection transfer gate control signal generation circuit 119, the latch data transfer transfer gate 125, and the input / output buffer connection transfer gate 1
31. Data transfer ATD selection circuit 1 for controlling and outputting
09, a bit line load 115 for precharging / equalizing the bit line pair BL, and a data input / output terminal 133.
And a data input / output buffer 129 for inputting / outputting data (Din / Dout), and an input / output buffer connection transfer gate 131 connecting the input / output line shared bit line and the data input / output buffer 129.

The mode setting signal generation circuit 101 includes an address buffer 103 and a decode ATD selection circuit 107.
A data transfer ATD circuit 109 and a sense amplifier 12
1 and the data input / output buffer 127. The address buffer 103 has an ATD generation circuit 105.
Are connected to the word line selection decoder 111 and the bit line selection decoder 113. ATD generation circuit 105
Is a decode ATD selection circuit 107 and a data transfer AT.
It is connected to the D selection circuit 109 and the bit line load 115. The decode ATD selection circuit 107 is connected to the word line selection decoder 111 and the bit line selection decoder 113. The data transfer ATD selection circuit 109 is connected to the input / output line shared bit line selection transfer gate control signal generation circuit 119, the latch data transfer transfer gate 125, and the input / output buffer connection transfer gate 131. The word lines WL and the bit line pairs BL are arranged so as to intersect with each other, and the memory cells MC are connected to each of the intersections to form a memory cell array.

The word line WL is the word line selection decoder 1
11, each bit line pair BL is connected to the input / output line pair 117 via the bit line load 65 and one bit line selection transfer gate TG provided corresponding to each bit line pair BL. It is connected to the. The input / output line pair 117 includes a sense amplifier 121 and a write driver 12
7 is connected.

One end of the I / O line shared bit line pair 141 is connected to the bit line load 115, and further connected to the data I / O buffer 129 via the I / O buffer connection transfer gate 131. The data input / output buffer 129 is connected to the data input / output terminal 133. The other end of the I / O line shared bit line pair 141 is connected to the sense amplifier 121, the data latch 123, and the write driver 127 via the I / O line shared bit line selection transfer gate 137. Further, the input / output line shared bit line selection transfer gate 137 connected to the input / output line shared bit line pair 141 is the input / output line shared bit line selection transfer gate control signal generation circuit 1.
It is connected to the bit line selection decoder 113 via 19. FIG. 2 is a timing chart for explaining the operation of the asynchronous SRAM 100 of FIG.

The operation of the asynchronous SRAM 100 of FIG. 1 will be described with reference to the timing chart of FIG.

When the chip enable signal CE is activated and the selected state of the chip is set, the address buffer 103 is driven by the address signal Add input from the outside. A pulse signal is generated when the detection signal in the ATD generation circuit 105 provided for each bit of the address signal Add changes the address signal Add even for one bit. Then, based on the generated pulse signal, the first pulse that changes first and the first pulse that changes first by setting the delay
Two kinds of pulse signals, that is, the second pulse signal that changes after the pulse of 1) are further generated inside the circuit.

When the read state is set by the read / write setting signal R / W (when the "H" level signal is input), the first pulse signal is passed through the decode ATD selection circuit 107. , A part of the output signal of the address buffer 103 is transferred to the word line selection decoder 111, and only the desired word line W is supplied during the input pulse width period.
Lx is selected. The third pulse signal output from the decode ATD selection circuit 107 and the address buffer 103
The rest of the output signals of (1) are transferred to the bit line selection decoder 113, the bit line selection transfer gate TGx is turned on only during the input pulse width period, and the desired bit line pair BLx is selected. In this way, the memory cell MCx connected to the intersection of the selected word line WLx and the bit line pair BLx is selected.

The bit line pair BL is previously boosted to a constant voltage by the bit line load 115, and the bit line pair BLx
The read data from the memory cell MCx output to the bit line select transfer gate TGx and the input / output line pair 1
17 and is transferred to the sense amplifier 121 selected by the upper address of the bit line pair selecting address and activated by the read mode setting signal output from the mode setting signal generating circuit 101. The read data further amplified by the sense amplifier 121 is temporarily stored in the data latch 12
Latched to 3. These operations are completed within the pulse width period of the first pulse.

After completion of this operation, the second pulse signal is
The latched data transfer transfer gate 125 and the input / output buffer connection transfer gate 131 which are transferred through the data transfer ATD selection circuit 109 are turned on, and the read data latched by the data latch 123 is input / output line shared bit line pair. The data is transferred to the data input / output buffer 129 via 141.

The data latch 123 and the input / output line pair 117 are arranged so that the complementary output signal of the read data output from the data latch 123 is in phase with the complementary output signal of the read data transferred through the input / output line pair 117. If and are connected, the potential of the read data remains in the input / output line pair 117, and the read data can be transferred at high speed.

The input / output line shared bit line selection transfer gate 137 corresponds to the bit line selection transfer gate of the input / output line shared bit line pair 141, and the input / output line shared bit line selection transfer gate control signal generation circuit 11 is provided.
The memory cells connected to the input / output line shared bit line pair 141 which is turned on by the memory cell 9 (for example, the memory cell M
Even when Cy) is selected, the I / O line shared bit line selection transfer gate control signal generation circuit 119 causes the I / O line shared bit line selection transfer gate 141, as in the case of other bit line selection transfer gates.
Is turned on, the same reading by the first pulse signal is possible. Input / output line shared bit line pair 1 in this case
41 and the input / output line shared bit line selection gate 137 are
It changes as shown by a dotted line in FIG.

As described above, the data input / output buffer 1
The read data transferred to 29 is the data input / output terminal 13
3 is output. The above operation is completed within the pulse width period of the second pulse signal.

Furthermore, when the first and second pulse signals are not generated, bit line load 115 precharges and equalizes bit line pair BL. If you send the second pulse signal, the first
After the generation of the pulse signal of, the input / output line shared bit line pair 1
Since precharging and equalization of 41 can be performed, activation of the word line WLx erases the potential due to the read data from the memory cell MCx output to the input / output line shared bit line 141, and the next data transfer. Can be performed at high speed.

On the other hand, when the write state is set by the read / write setting signal R / W (when the "L" level signal is input), a pulse signal is generated from the ATD generating circuit 105, and the first signal is generated. Pulse signal turns on the latch data transfer transfer gate 125 and the input / output buffer connection transfer gate 131 via the data transfer ATD selection circuit 109, and the data input from the data input / output terminal 133 to the data input / output buffer 129 is transferred. , And is transferred to the data latch 123 via the input / output line shared bit line pair 141. Also at this time, the input / output line shared bit line selection transfer gate 137 is turned on by the control signal output from the input / output line shared bit line selection transfer gate control signal generation circuit 119. When the above operation is completed within the pulse width period of the first pulse signal, the second pulse signal passes through the decoder ATD selection circuit 107 to the word line selection decoder 111 together with a part of the output signal of the address buffer 103. The desired word line WLx is selected only during the period of the pulse width that is transferred and input. The second pulse signal output from the decode ATD selection circuit 107 and the rest of the output signal of the address buffer 103 are transferred to the bit line selection decode 113, and the bit line selection transfer gate TGx is transferred only during the input pulse width period. When turned on, the desired bit line pair BLx is selected, and the memory cell MCx connected to the intersection with the selected word line WLx is selected. The write data transferred to the data latch 123 is the write driver 127 selected by the upper address of the bit line pair selection address.
From the input / output line pair 117, the bit line selection transfer gate TGx, and the bit line pair BLx that has been boosted to a constant voltage by the bit line load 115 in advance, to the memory cell MCx.

If the write driver 127 and the input / output line pair 117 are connected so that the complementary signal of the write data output from the write driver 127 has the same phase as the complementary signal of the input / output line pair 117. , The potential of the write data remains in the input / output line pair 117, and the write data can be written at high speed.

At this time, the memory cells connected to the input / output line shared bit line pair 141 (for example, the memory cell MC
Even when y) is selected, the I / O line sharing bit line selection transfer gate control signal generation circuit 119 is selected as in the case where other bit line selection transfer gates are selected.
As a result, the input / output line shared bit line selection transfer gate 137 is turned on, so that the same write operation can be performed with the second pulse signal. In this case, the input / output line shared bit line pair 141 and the input / output line shared bit line selection gate 137
Changes as shown by the dotted line in FIG.

Further, when the first and second pulse signals are not generated, the bit line load 115 precharges and equalizes the bit line pair BL, as in the data read operation. If the second pulse signal is sent, the precharge and equalization of the input / output line shared bit line pair 141 can be performed after the generation of the first pulse signal, so that the input / output lines left by the data transfer. The potential of the shared bit line pair 141 is erased,
At the time of writing the next data, it becomes possible to prevent an error in writing to the memory cell connected to the input / output line shared bit line pair 141.

FIG. 3 shows the mode setting signal generating circuit 1 of FIG.
01 partial circuit 101 ′, ATD generating circuit 105 partial circuit 105 ′, decode ATD selection circuit 107,
FIG. 6 is a detailed circuit diagram showing an example of a data transfer ATD selection circuit 109, a bit line selection decoder 113, and an input / output line shared bit line selection transfer gate control signal generation circuit 119.

Referring to FIG. 3, partial circuit 101 'of mode setting signal generating circuit 101 includes NOT circuit 303. The partial circuit 105 ′ of the ATD generation circuit 105 includes a delay circuit 303. The decoder ATD selection circuit 107
It includes NMOS transistors 305 and 307. The data transfer ATD selection circuit 109 includes an NMOS transistor 30
Including 9,311. The bit line selection decoder 113 has N
It includes an AND circuit 313 and a NOT circuit 315. The input / output line shared bit line selection transfer gate control signal generation circuit 119 includes NOT circuits 317 and 321 and a NOT circuit.
And a circuit 319.

In the decode ATD selection circuit 107, N
The source electrode of the MOS transistor 305 and the source electrode of the NMOS transistor 307 are connected to each other, and the NAs of the word line selection decoder 111 and the bit line selection decoder 113 are connected.
It is connected to the input node of the ND circuit 313. Further, in the data transfer ATD selection circuit 109, the NMO
The source electrode of the S transistor 309 and the source electrode of the NMOS transistor 311 are connected to each other, and the control node Na of the latch data transfer transfer gate 125 and the control node Nb of the data transfer transfer gate 131 are connected.
And an input node of the NOT circuit 321 of the input / output line shared bit line selection transfer gate control signal generation circuit 119. In the bit line selection decoder 113, the output signal from the address buffer 103 is applied to the other input node of the NAND circuit 313.
The output node of the NAND circuit 313 is the NOT circuit 315.
Connected to the input node of. The output node of the NOT circuit 315 is connected to the input node of the NOT circuit 317 of the input / output line shared bit line selection transfer gate control signal generation circuit 119. In the input / output line shared bit line selection transfer gate control signal generation circuit 119, the output nodes of the NOT circuits 317 and 321 are
It is connected to the input node of the NAND circuit 319. N
The output node of the AND circuit 319 is connected to the control node Nc of the input / output line shared bit line selection transfer gate 137.

In the partial circuit 105 ', the first pulse signal is generated without passing through the delay circuit 303, and the delay circuit 3'
The second pulse delayed from the first pulse signal via 03.
Pulse signals are generated. The first pulse signal is the NMOS transistor 30 of the decode ATD selection circuit 107.
5 and the drain electrode of the NMOS transistor 309 of the data transfer ATD selection circuit 109. The second pulse signal is the decode ATD selection circuit 1
It is input to the drain electrode of the NMOS transistor 307 of 07 and the drain electrode of the NMOS transistor 311 of the data transfer ATD selection circuit 109.

In the partial circuit 101 'of the mode setting signal generation circuit 101, the signal which becomes "H" level at the time of data read and "L" level at the time of data write is the delay circuit 303.
Via the gate electrode of the NMOS transistor 305 of the decode ATD selection circuit and the gate electrode of the NMOS transistor 311 of the data transfer ATD selection circuit 109, and the gate electrode of the NMOS transistor 307 and the NMOS via the NOT circuit 303. Transistor 31
1 gate electrode.

That is, at the time of data reading, the partial circuit 1
The read mode setting signal of "H" level output from 01 'is applied to the gate electrode of the NMOS transistor 305, and the NMOS transistor 305 is turned on. As a result, the first pulse signal output from the partial circuit 105 ′ passes through the NMOS transistor 305 and the NA of the word line selection decoder 111 and the bit selection decoder 113.
It is transferred to the ND circuit 313. The NAND circuit 313 has an address buffer 103 which becomes “H” level when selected.
Output signal is input, and the output of the NAND circuit 313 is at the “L” level during the pulse width period of the input first pulse signal. Therefore, the output of the NOT circuit 310 becomes "H" level. In the input / output line shared bit line selection transfer gate control signal generation circuit 119, when the input / output line shared bit line pair 141 is selected, NOT
The output of the circuit 317 is “L” level, and the NAND circuit 319
Output becomes "H" level and the input / output line shared bit line selection transfer gate 137 is turned on. Also,
Data latch 1 via I / O line shared bit line pair 141
When data is transferred from 23, in the input / output line shared bit line selection transfer gate control signal generation circuit 119, the output of the NOT circuit 321 is at "L" level and the output of the NAND circuit 319 is at "H" level. I / O line shared bit line selection transfer gate 1
37 is turned on.

On the other hand, the "H" level signal output from the partial circuit 101 'is the N level of the data transfer ATD selection circuit.
The MOS register 311 also turns on. As a result, the second pulse signal output from the partial circuit 105 'becomes N
The data is transferred to the latch data transfer transfer gate 125 and the input / output buffer connection transfer gate 131 via the MOS transistor 311, and the latch data transfer transfer gate 125 and the input / output buffer connection transfer gate 13 are transferred during the pulse width period of the second pulse signal.
1 and are turned on.

At the time of data writing, the "L" level write mode setting signal is inverted by the NOT circuit 303 of the partial circuit 101 'and is output at "H" level. This "H" level signal turns on the NMOS transistor 309 of the data transfer ATD selection circuit 109. As a result, the first pulse signal output from the partial circuit 105 ′ is transferred to the latch data transfer transfer gate 125 and the input / output buffer connection transfer gate 131 by meeting the NMOS transistor 309, and
During the pulse width period of the pulse signal, the latch data transfer transfer gate 125 and the input / output buffer connection transfer gate are turned on.

On the other hand, the decode ATD selection circuit 107 is also turned on by the "H" level signal output from the partial circuit 101 '. As a result, the delay circuit 303
And the second pulse signal output from the partial circuit 105 ′ passes through the NMOS transistor 307 and the word line selection decoder 111 and the bit line selection decoder 113.
Of the NAND circuit 313. NAND circuit 3
The output signal of the address buffer 103, which becomes “H” level at the time of selection, is input to 13, and the second input signal is input.
During the pulse width period of the pulse signal, the output of the NAND circuit 313 is at "L" level. Therefore, the output of the NOT circuit 315 becomes "H" level. As in the case of data reading, when the input / output line shared bit line pair 141 is selected as the bit line pair connected to the write memory, the input / output line shared bit line selection transfer gate control signal generation circuit 119 is used. , The output of the NOT circuit 317 becomes the “L” level and the output of the NAND circuit 319 becomes the “H” level, and the input / output line shared bit line selection transfer gate 1
37 is turned on. In addition, the input / output line shared bit line pair 14
When data is transferred to the data latch 123 via 1, the NOT circuit 3 in the I / O line shared bit line selection transfer gate control signal generation circuit 119 is transferred.
The output of 21 becomes "L" level, the output of the NAND circuit 319 becomes "H" level, and the input / output line shared bit line selection transfer gate 137 is turned on.

FIG. 4 shows the bit line load 115 of FIG.
7 is a circuit diagram showing an example of a bit line load control signal generation circuit 400 included in a partial circuit 105 ″ of the TD generation circuit 105. FIG.

Referring to FIG. 4, bit line load control signal generating circuit 400 includes NOR circuit 401, and the first or second pulse signal output from partial circuit 105 'shown in FIG. 3 is NOR. It is applied to the input node of the circuit 401.

The bit line load 115 includes a plurality of unit loads 115 'corresponding to the plurality of bit line pairs BL,
Correspondingly, FIG. 4 shows a unit load 115 'provided corresponding to a certain bit line pair BL. Unit load 115 '
Includes NMOS transistors 403, 405, 407, the drain electrodes of the NMOS transistors 403, 405 are connected to the Vcc power supply, and the gate electrodes are connected to the output node of the NOR circuit 401 of the bit line load control signal generation circuit 400. . The gate electrode of the NMOS transistor 407 is also connected to the output node of the NOR circuit 401, and the source / drain electrodes are connected to the source electrodes of the NMOS transistors 403 and 405 and the corresponding bit line BL.

In the bit line load control signal generation circuit 400, when the first or second pulse signal is not given from the NOR circuit 401 (no pulse change), NO
The output of the R circuit 401 becomes "H" level, and this output is the NMOS transistors 403, 4 of the bit line load 115.
05,407 gate electrodes. This allows
The NMOS transistors 403, 405, and 407 are turned on, and the NMOS transistor 407 causes the bit line pair BL
Is equalized with a complementary signal applied to the bit line and precharged to the power supply voltage Vcc by the Vcc power supply.

(2) Second Embodiment FIG. 5 is a block diagram showing a structure of a synchronous pipelined SRAM 500 according to a second embodiment of the semiconductor memory device of the present invention.

Referring to FIG. 5, a synchronous pipeline type SRAM 500 is shown in FIG.
An external clock input terminal 50 that includes a pulse generation circuit 501 instead of the TD generation circuit 105, and that is connected to the pulse generation circuit 501 and receives an external clock signal Ck.
3, data register 505, and mode register 507
And an address register 509 to which the address signal Add is input.

The other circuit configurations in the synchronous pipeline type SRAM 500 and their connection relationship are the same as those of the asynchronous SRAM 100 of FIG.

Synchronous pipeline type SRAM 501
Is a decode ATD selection circuit 107 and a data transfer AT.
It is connected to the D selection circuit 109 and the bit line load 115. The external clock input terminal 503 is connected to the pulse generation circuit 501, the data register 505, the mode register 507, and the address register 509. The mode register 507 has a chip enable signal C.
E and the read / write setting signal R / W are input, the decode ATD selection circuit 107 and the data transfer ATD circuit 1
09, the sense amplifier 121, and the write driver 127.
And a data input / output buffer 129.
The address register 509 is a word line selection decoder 11
1 and the bit line selection decoder 113. The data input / output buffer 129 is the data register 5
It is connected to the input / output buffer connection transfer gate 131 via 05.

FIG. 6 shows the synchronous pipeline system S of FIG.
6 is a timing chart for explaining the operation of the RAM 500.

The operation of the synchronous pipeline type SRAM 500 of FIG. 5 will be described with reference to the timing chart of FIG.

When the operating state of the chip is set by the chip enable signal CE, the address signal Add and the read / write setting signal R / W input from the outside are supplied to the address register 50 at the rising edge of the external clock Ck.
9 and the mode register 507, respectively. The external clock signal Ck is input to the pulse generation circuit 501 and a desired internal pulse signal is generated. This pulse signal is the AT in the asynchronous SRAM 100 of FIG.
It functions similarly to the pulse signal generated by the D generation circuit 105.

When the data read state is set, the bit line is synchronized with the rising edge of the first pulse signal generated by the pulse generating circuit 501 based on the first external clock signal Ck1 that has changed previously. The selection transfer gate TGx is turned on, the bit line pair BLx, the bit line selection transfer gate TGx, and the sense amplifier 121.
The read data from the desired memory cell MCx is latched in the data latch 123 via. Then, the latched data transfer transistor gate 125, the input / output line shared bit line selection transfer gate 137, and the second pulse signal, which is a delayed signal of the first pulse signal, rise.
And input / output buffer connection transfer gate 131
Are turned on, and the read data is transferred to the data register 505 via the I / O line shared bit line pair. Furthermore, the first
Of the data input / output buffer 1 from the data register 505 in synchronization with the rising edge of the second external clock signal Ck2 input after the falling of the external clock signal Ck1.
Data is transferred to 29 and read data is output from the data input / output terminal 133.

When the data write state is set, the first
Pulse generator circuit 50 based on the external clock signal Ck1 of
In synchronization with the rising edge of the first pulse signal generated at 1, the input / output buffer connection transfer gate 13
1, I / O line shared bit line selection transfer gate 1
37, and transfer gate 1 for latch data transfer
25 is turned on, the write data input from the data input / output terminal 133 is transferred via the data input / output buffer 129, the data register 505, and the input / output line shared bit line pair 141, and latched by the data latch 123. It
Then, the bit line selection transfer gate BLx is turned on in synchronization with the fall of the second pulse signal which is a delay signal of the first pulse signal, and the desired memory is passed through the write driver 127 and the bit line pair BLx. Cell MCx
Write data is written in.

In this way, the synchronous pipeline SR
In AM500, in response to an external clock signal,
A read / write operation similar to that of the asynchronous SRAM 100 of FIG. 1 is performed.

In the case of a non-pipeline type synchronous SRAM without the data register 505, at the time of data reading, the read data transferred via the input / output buffer connection transfer gate 131 is the data input / output buffer 129.
Is directly read from the data input / output terminal 133, and at the time of data writing, the write data input from the data input / output terminal 133 is the data input / output buffer 129, the input / output buffer connection transfer gate 131, the input / output line shared bit. Since it is taken into the data latch 123 via the line pair 141, the input / output line shared bit line selection transistor gate 137, and the latch data transfer transfer gate 125, the external clock signal Ck as shown in FIG. No control is needed.

The input / output buffer connection transfer gate 131 of the asynchronous SRAM 100 of FIG. 1 has two NMOS transistors 15 provided corresponding to the input / output line shared bit lines 143 and 145 of the input / output line shared bit line pair.
3,155.

One electrode of the source / drain electrode of the NMOS transistor 153 is connected to the input / output line shared bit line 143, and the other electrode thereof is connected to the input / output buffer 129. One electrode of the source / drain electrode of the NMOS transistor 155 is connected to the input / output line shared bit line 145, and the other electrode thereof is connected to the input / output buffer 129. The gate electrodes of the NMOS transistors 153 and 155 are both connected to the data transfer ATD selection circuit 109. Complementary signals of read data and write data are input shared bit line 143 and NMOS transistor 153, and input / output line shared bit line 145 and NMOS transistor 155.
Respectively transferred via.

(3) Third Embodiment FIG. 7 is a block diagram showing a structure of an asynchronous SRAM 700 corresponding to a single data bus of a third embodiment of a semiconductor memory device of the present invention.

Referring to FIG. 7, an asynchronous SRAM 700 compatible with a single data bus is an asynchronous SRAM of FIG.
Instead of the I / O line shared bit line pair 141 of 100, the I / O buffer connection transfer gate 131, and the latch data transfer transfer gate 125, only one I / O line shared bit line is provided, and one of the I / O line shared bit lines is input. Input / output buffer connection transfer gate 13 connecting output line shared bit line 145 and data input / output buffer 129
1 ', and of the input / output line pair 117, the latch data transfer for connecting the input / output line shared bit line 145 and the input / output line connected via the input / output line shared bit line selection transfer gate 137 to the data latch 123. And a transfer gate 125 '.

Asynchronous SRA for single data bus
The other circuit configuration and connection relationship of the M700 are the same as those of the asynchronous SRAM 100 of FIG.

In the asynchronous SRAM 700 of FIG. 7, the asynchronous SRAM 700 of FIG.
I / O line shared bit line pair 1 of the asynchronous SRAM 100
One of the I / O line shared bit lines 143 and 145 of 41 is used to transfer either the complementary signal of the read data or the write data. In FIG. 7, the input / output bit line 145 is used as the input / output line shared bit line, and the NMOS transistor 153 of the input / output buffer connection transfer gate 131 provided corresponding to the input / output line shared bit line 143 is removed. It is composed.

That is, at the time of data reading, one of the complementary signals of the read data latched by the data latch 123 is transferred to the latch data transfer transfer gate 125 'constituted by one NMOS transistor, and the input / output line is transferred. Shared bit line select transfer gate 1
37, the input / output line shared bit line 145, and the input / output buffer connection transfer gate 131 (NMOS transistor 155) to the input / output buffer 129. Here, turning on / off of the latch data transfer transfer gate 125 'is similar to that of the latch data transfer transfer gate 125 of FIG.

Further, one of the signals complementary to the read data output from the data latch 123 is input / output line pair 1
If they are connected so as to be in phase with the complementary signals of 17, the read data potential remains in the input / output line pair 117, so that the data can be reduced at high speed.

At the time of data writing, one of the complementary signals of the write data input to the input / output buffer 129 is transferred to the input / output buffer connection transfer gate 131 (NMOS transistor 155), the input / output line shared bit line 145, and the input / output line shared bit line 145. Output line shared bit line selection transfer gate 137,
And latch data transfer transfer gate 125 '
Via the data latch 123.

Further, the write data is fetched from the data latch 123 to the write driver 127, and one of the complementary signals output from the write driver 127 is in phase with the complementary signal of the input / output line pair 117. If it is connected to, the potential of the write data remains in the input / output line pair, so that the write data can be written at high speed.

The single data bus system described in the third embodiment can also be used in the semiconductor memory device of the second embodiment.

(4) Fourth Embodiment FIG. 8 is a block diagram showing the structure of an asynchronous SRAM 800 according to the fourth embodiment of the semiconductor memory device of the present invention.

Referring to FIG. 8, an asynchronous SRAM 800
In the asynchronous SRAM 100 of FIG. 1, a sense amplifier 801 is connected between the input / output buffer 129 and the input / output buffer connection transfer gate 131. The sense amplifier 801 is also connected to the mode setting signal generation circuit 101.

When the read mode setting signal is output from mode setting signal generating circuit 101, the read data transferred through input / output buffer connection transfer gate 131 is further amplified by sense amplifier 801.

Therefore, when data is read, the read data transferred via the input / output line shared bit line pair 141 has a sufficient amplitude due to the influence of the drain capacitance of the memory cell, the wiring capacitance of the pair of bit lines, and the like. Even if the error does not occur, it is possible to obtain the read data having a sufficiently large amplitude by amplifying the amplitude of the data by the sense amplifier.

The semiconductor memory devices of all the first to third embodiments can be provided with the same sense amplifier as that of the fourth embodiment.

(5) Fifth Embodiment FIG. 9 is a block diagram showing the structure of an asynchronous SRAM 900 according to the fifth embodiment of the semiconductor memory device of the present invention.

Referring to FIG. 9, an asynchronous SRAM 900
Is the input / output line shared bit line pair 141 of the asynchronous SRAM 100 of FIG. 1 (in the case of the asynchronous SRAM 700 corresponding to the single data bus shown in FIG. 7, the input / output shared bit line 1
45), and the potential fixing circuit 901 is connected to the bit line pair adjacent to (or in the vicinity of) 45).

In FIG. 9, the input / output line shared bit line pair 141
The potential fixing circuit 901 provided corresponding to the bit line pair BLy adjacent on one side is representatively shown. Although the potential of the bit line pair is fixed to the GND potential in FIG. 9, another potential may be used as long as it is a constant potential.

In FIG. 9, the potential fixing circuit 901 has N
Including the MOS transistors 903 and 905, the gate electrodes of the NMOS transistors 903 and 905 are both connected to the data transfer ATD selection circuit 109, and the drain electrodes are connected to one corresponding bit line of the bit line pair. The source electrodes are both implemented and are given a GND potential.

At the time of data transfer, the control signal from the data transfer ATD selection circuit 109, which is applied to the control node Nb of the input / output buffer connection transfer gate 131, is applied to the gate electrodes of the NMOS transistors 903 and 905 of the potential fixing circuit 901, When the output buffer connection transfer gate 131 turns on, the NMOS transistors 903 and 905 also turn on, and the bit line pair BLy becomes GND.
Potential.

Therefore, as described in the fourth embodiment, the data transferred via the input / output line shared bit line pair 141 does not have a sufficient amplitude because of the capacitance between the pair of bit line pairs. However, as described above, the capacitance between wirings is reduced by fixing the potential of the bit line pair 141 adjacent to the I / O line shared bit line pair 141 to a constant potential (for example, GND potential) during data transfer as described above. It becomes possible to do.

In all of the second to fourth embodiments, a potential fixing circuit for precharging / equalizing a bit line can be provided as in the fifth embodiment.

In all of the above embodiments,
By setting the bit line pair having the shortest distance from any of the data input / output circuits such as the data input / output buffer 129, the sense amplifier 121, and the write driver 127 as the input / output line shared bit line pair, the data transfer time can be reduced. It can be shortened.

As described above, in all the embodiments of the semiconductor memory device of the present invention, the timing margin at the time of data reading and writing is reduced, and the input / output line shared bit line is used without malfunction. Data can be transferred.

Therefore, the conventional data bus wiring becomes unnecessary, and it is possible to provide a semiconductor memory device in which the layout area of the data bus wiring is reduced. This also increases the degree of freedom in design.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an asynchronous SRAM according to a first embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a timing chart for explaining an operation of the asynchronous SRAM 100 of FIG.

3 is a partial circuit of the mode setting signal generation circuit of FIG.
Partial circuit of ATD generation circuit, decode ATD selection circuit,
FIG. 6 is a detailed circuit diagram showing an example of a data transfer ATD selection circuit, a bit line selection decoder, and an input / output line shared bit line selection transfer gate control signal generation circuit.

4 is a circuit diagram showing an example of a bit line load control signal generation circuit included in a partial circuit of the ATD generation circuit of the bit line load in FIG.

FIG. 5 is a block diagram showing a configuration of a synchronous pipelined SRAM according to a second embodiment of the semiconductor memory device of the present invention.

6 is a timing chart for explaining the operation of the synchronous pipeline type SRAM of FIG.

FIG. 7 is a block diagram showing a configuration of an asynchronous SRAM compatible with a single data bus according to a third embodiment of the semiconductor memory device of the present invention.

FIG. 8 is a block diagram showing a configuration of an asynchronous SRAM according to a fourth embodiment of a semiconductor memory device of the present invention.

FIG. 9 is a block diagram showing a configuration of an asynchronous SRAM according to a fifth embodiment of a semiconductor memory device of the present invention.

FIG. 10 is a block diagram showing a configuration of a conventional asynchronous SRAM.

FIG. 11 is a conventional asynchronous pipeline type SRAM.
FIG. 3 is a block diagram showing the configuration of FIG.

12 is a circuit diagram showing an example of the pulse generation circuit of FIG.

13 is a timing chart showing a pulse signal output from the pulse generation circuit of FIG.

[Explanation of symbols]

107 decode ATD selection circuit, 109 data transfer ATD selection circuit, 119 input / output line shared bit line selection transfer gate control signal generation circuit, 123 data latch, 125 latch data transfer transfer gate, 131 input / output buffer connection transfer gate, 137 input / output Line shared bit line selection transfer gate, 503 external clock input terminal, 505 data register, 507 mode register, 509 address register, 121, 801, sense amplifier, 141
I / O line shared bit line pair, 143, 145 I / O line shared bit line, 129 data I / O buffer, 113
Bit line selection decoder, 105 ATD generation circuit, WL
1, ..., WLx, ..., WLm (WL) Word line, BL
, ..., BLx, ..., BLy, ..., BLn (BL) bit line pair, MC1, ..., MCx, ..., MCy, ..., MC
s (MC) Memory cell.

Claims (14)

[Claims] 1. An input / output buffer, a plurality of bit lines, an input / output line, each of which is provided corresponding to one of the plurality of bit lines, and the plurality of bit lines and the input / output lines are provided. A plurality of column select gates connected to each other, and a data latch connected to the input / output line to latch data, wherein the plurality of bit lines include an input / output line shared bit line, The column selection gate includes an I / O line shared bit line selection gate connected to the I / O line shared bit line, and an I / O buffer connection connected between the I / O buffer and the I / O line shared bit line. At the time of data reading, the gate and the column selection gate corresponding to the input column address signal are turned on at a first timing, and the column selection gate turned on at the first timing is set to the first timing. The first gate control means which is turned off at a second timing later than the timing, and the input / output line shared bit line select gate and the input / output buffer connection gate at the time of data reading are later than the second timing. When the data is written, the input / output buffer connection gate and the input / output line shared bit line selection gate are turned on at a fourth timing, and the input / output buffer connection gate and the input / output line shared bit are turned on. A second gate control means for turning off the line selection gate at a fifth timing later than the fourth timing, the first gate control means further comprising: A semiconductor memory device which turns on the column select gate corresponding to an address signal at a sixth timing later than the fifth timing. 2. Fixing means for fixing the voltage of a bit line adjacent to the input / output line shared bit line to a constant voltage at the second timing when reading data and at the fourth timing when writing data. Claim 1 further comprising:
3. The semiconductor memory device according to claim 1. 3. An input / output buffer, a plurality of bit lines, an input / output line, each of which is provided corresponding to one of the plurality of bit lines, and the plurality of bit lines and the input / output lines are provided. A plurality of column select gates connected to each other, and a data latch connected to the input / output line to latch data, wherein the plurality of bit lines include an input / output line shared bit line, The column selection gate includes an I / O line shared bit line selection gate connected to the I / O line shared bit line, and an I / O buffer connection connected between the I / O buffer and the I / O line shared bit line. A gate, a pulse signal output means for outputting a first pulse signal, and a second pulse signal output after the first pulse signal is inactivated, and activation of the first or second pulse signal In response to
A first column selection gate that turns on the column selection gate corresponding to the input column address signal and turns off the turned-on column selection gate in response to the deactivation of the activated first or second pulse signal. Gate control means, and in response to activation of the first or second pulse signal,
The input / output buffer connection gate and the input / output line shared bit line selection gate turned on, and the input / output buffer connection gate turned on in response to the inactivation of the activated first or second pulse signal. And second gate control means for turning off the input / output line shared bit line selection gate, and transferring the first pulse signal to the first gate control means at the time of data reading, and the second pulse signal. To the second gate control means, and at the time of data writing, the first pulse signal is transferred to the second gate control means, and the second pulse signal is transferred to the first gate control means. A semiconductor memory device comprising: pulse signal transfer means for transferring. 4. The voltage fixing means for fixing the voltage of a bit line adjacent to the input / output line shared bit line to a constant voltage when the first and second pulse signals are activated. The semiconductor memory device according to 1. 5. A first sense amplifier connected between the plurality of bit lines and the data latch, and a write driver connected between the data latch and the plurality of bit lines. 2. The I / O line shared bit line is a bit line that is the shortest distance from one of the I / O buffer, the first sense amplifier, and the write driver among the plurality of bit lines. 5. The semiconductor memory device according to any one of 4 above. 6. An input / output buffer, a plurality of bit line pairs, and an input / output line, each of which is provided corresponding to one of the plurality of bit line pairs. A plurality of column selection gates connected to the output lines; and a data latch connected to the input / output lines to latch data, wherein the plurality of bit line pairs include an input / output line shared bit line pair. The plurality of column selection gates include an input / output line shared bit line selection gate connected to the input / output line shared bit line pair, and are provided between the input / output buffer and the input / output line shared bit line pair. The connected input / output buffer connection gate and the column selection gate corresponding to the input column address signal at the time of data reading are turned on at a first timing, and the column selection gate turned on at the first timing. The first gate control means for turning off the gate at a second timing later than the first timing, the I / O line shared bit line selection gate, and the I / O buffer connection gate at the time of data reading. Is turned on at a third timing later than the above timing, and at the time of data writing, the input / output buffer connection gate and the input / output line shared bit line selection gate are turned on at a fourth timing, and the input / output buffer connection gate is turned on. And second gate control means for turning off the input / output line shared bit line selection gate at a fifth timing later than the fourth timing, the first gate control means further comprising: At the time of input, the column selection gate corresponding to the input column address signal is turned on at a sixth timing later than the fifth timing. Conductor storage. 7. A voltage for fixing a voltage of a bit line adjacent to the I / O line shared bit line pair to a constant voltage at the second timing during data reading and at the fourth timing during data writing. 7. The semiconductor memory device according to claim 6, further comprising fixing means. 8. An input / output buffer, a plurality of bit line pairs, an input / output line, each of which is provided corresponding to one of the plurality of bit line pairs, and the plurality of bit line pairs and the input / output lines are provided. A plurality of column selection gates connected to the output lines; and a data latch connected to the input / output lines to latch data, wherein the plurality of bit line pairs include an input / output line shared bit line pair. The plurality of column selection gates includes an input / output line shared bit line selection gate connected to the input / output line shared bit line pair, and a first pulse signal and an inactivation of the first pulse signal. Pulse signal output means for outputting a second pulse signal to be output later, and in response to activation of the first or second pulse signal,
A first column turn-on gate corresponding to an input column address signal is turned on, and the turned-on column select gate is turned off in response to inactivation of the activated first or second pulse signal. Gate control means, and in response to activation of the first or second pulse signal,
The input / output buffer connection gate and the input / output line shared bit line selection gate are turned on, and in response to the deactivation of the activated first or second pulse signal, Second gate control means for turning off the input / output line sharing bit line selection gate, and transferring the first pulse signal to the first gate control means during data reading and transmitting the second pulse signal to the first gate control means. When the data is written, the first pulse signal is transferred to the second gate control means, the first pulse signal is transferred to the second gate control means, and the second pulse signal is transferred to the first gate control means. A semiconductor memory device comprising: 9. The voltage fixing means for fixing the voltage of a bit line adjacent to the input / output line shared bit line pair to a constant voltage when the first and second pulse signals are activated. 8. The semiconductor memory device according to item 8. 10. A first sense amplifier connected between the plurality of bit line pairs and the data latch; a write driver connected between the data latch and the plurality of bit line pairs. The input / output line shared bit line pair may further include: the input / output buffer and the first bit line pair among the plurality of bit line pairs.
10. The semiconductor memory device according to claim 6, which is a bit line pair located at the shortest distance from one of the sense amplifier and the write driver. 11. The pulse signal output means detects a change in an address signal input from the outside and outputs the first and second pulse signals, and the pulse signal output means outputs the first and second pulse signals. The semiconductor storage device according to any one of claims. 12. The pulse signal output means synchronizes with a clock signal inputted from the outside, and the first and second pulse signals are outputted.
12. The semiconductor memory device according to claim 3, wherein the pulse signal is output. 13. A bit line precharge / equalize means for precharging and equalizing the plurality of bit lines between inactivation of the first pulse signal and activation of the second pulse signal, The semiconductor memory device according to any one of claims 3 to 5 or 8 to 12, further comprising: 14. The semiconductor memory device according to claim 1, further comprising a second sense amplifier connected between the input / output buffer connection gate and the input / output buffer.