JP2007159201A - Power unit and recorder equipped with that power unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power unit suitable for downsizing, which is high in reliability, is inexpensive, and stably supplies power, and also to provide a recorder using the device. <P>SOLUTION: The power unit, which changes its set output voltage, based on an external input digital control signal, is equipped with the following constitution. That is, it is equipped with a time constant circuit which receives the input of a digital control signal, a D/A converter which receives a digital control signal distorted by the circuit, and a comparator which compares an output voltage value with a threshold of a voltage value outputted from there. It is also equipped with a controller which modulates its pulse width by the comparison results, and a switching element which is switched on or switched off by a control signal with its pulse width modulated, and converts input voltage into set output voltage prior to output. These components are mounted on the same board, and the time constant of the time constant circuit is determined in consideration of the cycle of the digital control signal and the frequency of the noise concerned with the switching operation of the switching element. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a power supply apparatus and a recording apparatus including the power supply apparatus, and more particularly to an ink jet recording apparatus provided with a power supply apparatus such as a DC / DC converter.

  2. Description of the Related Art Conventionally, a DC / DC converter that changes an output voltage value by a digital control signal input from the outside is known (see, for example, Patent Document 1).

  FIG. 7 is a block diagram showing a configuration example of a conventional DC / DC converter.

  According to FIG. 7, the output of the digital / analog converter (hereinafter referred to as D / A converter) 715 is used as the reference voltage of the error amplifier (comparator) 706 of the DC / DC converter, and the output voltage of the DC / DC converter Compare. The comparison result is fed back by the control circuit (CNTL) 705 to stabilize the output voltage.

  In FIG. 7, 701 is a voltage input terminal, 703 is a switch, 704 is a diode, 709 is an input side low pass filter (LPF), 710 is an output side LPF, 712 is a voltage output terminal, and 716 is a digital control signal input terminal. is there.

  However, since the DC / DC converter that changes the setting of the output voltage by this technique has a built-in D / A converter, the switching noise of the DC / DC converter itself is generated in the D / A converter. Wrapping around the board causes malfunction. As a result, there arises a problem that the set voltage changes.

  Even in the prior art, as a problem that often occurs in a DC / DC converter having a built-in D / A converter, several techniques for preventing malfunction due to switching noise are disclosed as follows.

  For example, Patent Document 2 discloses a so-called “single-point grounding” so as to reduce a common impedance with respect to routing of a power supply wiring pattern for preventing malfunction of circuit operation due to power supply noise when a DC / DC converter is built in the same printed circuit board. "Is proposed.

  Patent document 3 discloses a technique for preventing malfunctions by separating the circuit board of the analog part and the digital part and in particular noise caused by wraparound.

  The above two examples are proposals for noise prevention measures based on circuit mounting.

  As a technique for preventing malfunction of the electronic circuit itself due to noise, Patent Document 4 discloses a technique for configuring a so-called PLL (Phased Lock Loop) in the technical field of digital audio.

Patent Document 5 proposes the use of an integral filter as a circuit for preventing noise caused by chattering such as mechanical contacts.
JP-A-6-006969 Japanese Patent Laid-Open No. 9-062815 JP-A-7-170184 JP-A-8-055429 JP-A-8-237087

  However, the proposal shown in Patent Document 2 is effective for a case where there is a certain margin in the routing of the power supply wiring pattern, but cannot be applied when there is a great restriction on the routing of the power supply wiring pattern. For example, when the area of the substrate is greatly limited by design, such as a carriage substrate of a carriage on which a recording head used in an ink jet recording apparatus is mounted, this is not an effective solution.

  In addition, the proposal shown in Patent Document 3 cannot be applied when the size of the circuit board is limited.

  Furthermore, the proposal shown in Patent Document 4 also has a problem that the circuit configuration becomes complicated and the cost of the DC / DC converter increases. In addition, since the PLL circuit is mounted, an appropriate mounting area is required, which is difficult to apply.

  As described above, the cause of the noise related to the malfunction of the D / A converter in the DC / DC converter is the signal noise generated along with the transmission of the digital signal. Moreover, all the techniques disclosed in Patent Documents 2 to 4 are examples applied to a motherboard of a personal computer and a signal processing system of an audio device.

  Hereinafter, the problem to be solved which the DC / DC converter applied to the ink jet recording apparatus and the like will be described in detail.

  FIG. 8 is a diagram showing a voltage waveform by an oscilloscope at an input terminal of a D / A converter (M62342GP) manufactured by Renesas. In FIG. 8, the vertical axis represents voltage, the horizontal axis represents time, the voltage axis scale is 1 V, and the time axis scale is 1 μs. Thus, FIG. 8 represents a waveform in the range of approximately 10 μs.

  This D / A converter employs a serial data transfer method, and there are three input digital signals: a clock signal (CLK), a latch signal (LD), and a digital data signal (DI).

The observed waveform shown in FIG. 8 is obtained when the DC / DC converter is operating, and is a waveform when no voltage setting signal is exchanged from the D / A converter. In the waveform shown in the figure, it is observed that switching noise is present at the period of the switching frequency of the DC / DC converter on the terminal voltages of the CLK signal, the LD signal, and the DI signal that should be at the GND level. The switching frequency (f _sw ) is f _sw = 250 kHz.

  Now, since the logic voltage of this digital signal is 3.3V, the noise margin of about ± 1V is clearly less when considering various variations from the threshold voltage level (1.65V) of the logic voltage. It is in a state.

  FIG. 9 is a diagram showing waveforms when the DC / DC converter exchanges voltage setting signals from the D / A converter. The scale of the horizontal axis (time axis) shown in FIG. 9 is 100 μs, which is longer than that of FIG. Accordingly, FIG. 9 represents a waveform with a range of approximately 1 ms.

  Therefore, the switching noise shown in FIG. 8 is observed as a waveform having a shaded width like a cloud up and down from the GND level in FIG.

  According to FIG. 9, voltage setting data is written to the D / A converter through the three input terminals in the interval T1, the DC / DC converter is activated at time t = T2, and the output voltage Vo rises. Observe to go.

  FIG. 10 is a diagram showing the relationship between the output value of the D / A converter and the output value (Vo) of the DC / DC converter at the voltage setting timing.

  10A is a waveform when no malfunction occurs in the DC / DC converter, and FIG. 10B is a waveform when malfunction occurs.

  As shown in FIG. 10, after the output of the D / A converter is determined, it is observed that the output voltage value (Vo) increases with the start of the DC / DC converter operation. On the other hand, it can be observed that switching noise is superimposed on the CLK signal and the LD signal at the same timing.

  In particular, in FIG. 10B, it is observed that the output of the D / A converter drops to the GND level at time t = T3 when the switching noise is superimposed on the CLK signal and the LD signal. In connection with FIG. 8, it has been described that the noise margin is reduced when the switching noise is superimposed, but in the example shown in FIG. 10B, a malfunction actually occurs in the DC / DC converter.

  In this setting, since the control of the DC / DC converter is negative logic, control is performed so that the output voltage setting of the DC / DC converter becomes the maximum voltage, and the slope of the rising curve of the output voltage (Vo) is You can see that it is sudden.

  Further, when FIG. 10A is compared with FIG. 10B, the GND level of the input terminal of the CLK signal and the LD signal accompanying the start of the DC / DC converter is near the time t = T3 in FIG. 10B. It has also been observed that noise is increasing.

  As inferred from the actual operation waveform described above, for example, a DC / DC converter mounted on a carriage substrate of an ink jet recording apparatus (hereinafter referred to as a recording apparatus) has a large limitation on the mounting area, and the operation waveform is Extremely susceptible to noise.

  That is, since the switching noise generated with the switching operation of the DC / DC converter is larger than the noise level generated with the normal digital signal transmission, the D / A converter malfunctions and the set value of the output voltage is changed. It may change.

  Therefore, a DC / DC converter adopting a configuration in which a D / A converter that variably sets an output voltage according to an input digital control signal from the outside is mounted on a printed circuit board having a severe mounting area restriction such as a carriage board of a printing apparatus. It is difficult to apply the conventional technology.

  On the other hand, as a general solution to noise removal, it is widely known to use an integration circuit having a time constant of τ = CR. Therefore, a comparator having a hysteresis characteristic is used as a comparator of the DC / DC converter in order to eliminate the influence of noise.

  For example, the method disclosed in Patent Document 5 is an effective method for preventing chattering of mechanical contacts. However, the chattering of the mechanical contact used in Patent Document 5 is on the order of 1/1000 second, and the digit is different from the time constant in question here. The function of the integration circuit varies depending on the value of the time constant, and Cited Document 5 does not have a detailed disclosure on how to determine the time constant.

  The present invention has been made in view of the above-described conventional example, and an object of the present invention is to provide a power supply apparatus suitable for miniaturization that is highly reliable, inexpensive, and capable of stably supplying power, and a recording apparatus using the power supply apparatus. It is said.

  In order to achieve the above object, the power supply apparatus of the present invention has the following configuration.

  That is, a power supply device capable of changing a set output voltage based on an externally input digital control signal, the time constant circuit for inputting the digital control signal, and the digital control distorted by the time constant circuit A D / A converter for inputting a signal; a comparator for comparing the output voltage value with a voltage value output from the D / A converter as a threshold; a controller for performing pulse width modulation based on a comparison result from the comparator; A switching element that is turned on / off by a control signal pulse-width modulated by a controller, converts an input voltage to the set output voltage, and outputs the set voltage, the time constant circuit, the D / A converter, the comparator, the controller, The switching element is mounted on the same substrate, and the time constant of the time constant circuit is Characterized in that it is determined in consideration of the frequency of the switching noise of the switching operation of the period between the switching elements of the digital control signal.

  The switching element is a MOS-FET.

  The digital control signal is serially transferred and includes a clock signal, a latch signal, and a digital data signal. In this case, the time constant of the time constant circuit is determined in consideration of the cycle of the clock signal.

  Furthermore, it is desirable that the time constant circuit is disposed in the vicinity of the input terminal of the digital control signal.

The upper limit value of the time constant (τ) may satisfy τ <1 / 2πf _CLK with a frequency (f _CLK ) in which one cycle of the clock signal is a sine wave cycle as a cutoff frequency. On the other hand, the lower limit value is τ> √, where An is the positive maximum value of the noise component generated by the switching operation, V _{TH (Logic)} is the threshold value of the comparator, and f _Noise is the noise frequency at this time. It is preferable to satisfy {(An / V _{TH (Logic)} ) ² −1} / 2πf _Noise .

  The power supply device having the above configuration desirably takes the form of a DC / DC converter.

  According to another aspect of the invention, there is provided a recording apparatus using the power supply apparatus having the above-described configuration for supplying power to the recording head, the carriage having the built-in power supply apparatus and reciprocatingly mounted with the recording head. And a generating means for generating the digital control signal, a signal line for connecting the generating means and the carriage, transferring the digital control signal and a recording signal for the recording head, and a built-in flexible flat cable. A recording apparatus is provided.

  The recording head is preferably an ink jet recording head.

  Therefore, according to the present invention, there is an effect that it is possible to prevent the occurrence of a voltage setting error caused by the D / A converter caused by the noise accompanying the switching operation with an inexpensive, simple and suitable circuit configuration.

Accordingly, it is possible to provide a recording apparatus that supplies stable power and performs a stable recording operation.
According to a second invention relating to the present application, the DC / DC converter using the invention is used.

  Hereinafter, preferred embodiments of the present invention will be described more specifically and in detail with reference to the accompanying drawings.

  In this specification, “recording” (sometimes referred to as “printing”) does not represent only the case of forming significant information such as characters and graphics. In addition to this, an image, a pattern, a pattern, or the like is widely formed on a recording medium regardless of whether it is significant involuntary, or whether it is manifested so that a human can perceive it visually, or It also represents the case where the medium is processed.

  “Recording medium” refers not only to paper used in general recording apparatuses but also widely to cloth, plastic film, metal plate, glass, ceramics, wood, leather, and the like that can accept ink. Shall.

  Further, “ink” (sometimes referred to as “liquid”) should be interpreted widely as in the definition of “recording (printing)”. That is, by being applied on the recording medium, it is used for forming an image, pattern, pattern, etc., processing the recording medium, or processing the ink (for example, solidification or insolubilization of the colorant in the ink applied to the recording medium). It shall represent a liquid that can be made.

  Furthermore, unless otherwise specified, the “nozzle” collectively refers to an ejection port or a liquid channel communicating with the ejection port and an element that generates energy used for ink ejection.

<Description of Inkjet Recording Apparatus (FIG. 1)>
FIG. 1 is an external perspective view showing an outline of the configuration of an ink jet recording apparatus 1 which is a typical embodiment of the present invention.

  As shown in FIG. 1, an ink jet recording apparatus (hereinafter referred to as a recording apparatus) has a recording head 3 mounted on a carriage 2 for performing recording by discharging ink according to an ink jet system. A driving force generated by the carriage motor M1 is transmitted to the carriage 2 from the transmission mechanism 4, and the carriage 2 is reciprocated in the arrow A direction. At the time of recording, for example, a recording medium P such as recording paper is fed through the paper feeding mechanism 5 and conveyed to a recording position, and recording is performed by ejecting ink from the recording head 3 to the recording medium P at the recording position. Do.

  Further, in order to maintain the state of the recording head 3 satisfactorily, the carriage 2 is moved to the position of the recovery device 10 and the ejection recovery process of the recording head 3 is intermittently performed.

  In addition to mounting the recording head 3 on the carriage 2 of the recording apparatus 1, an ink cartridge 6 for storing ink to be supplied to the recording head 3 is mounted. The ink cartridge 6 is detachable from the carriage 2.

  The recording apparatus 1 shown in FIG. 1 is capable of color recording. For this reason, the carriage 2 contains four inks containing magenta (M), cyan (C), yellow (Y), and black (K) inks, respectively. An ink cartridge is installed. These four ink cartridges are detachable independently.

  Now, the carriage 2 and the recording head 3 can achieve and maintain a required electrical connection by properly contacting the joint surfaces of both members. The recording head 3 applies energy according to a recording signal to selectively eject ink from a plurality of ejection ports for recording. In particular, the recording head 3 of this embodiment employs an ink jet system that ejects ink using thermal energy. For this reason, the recording head 3 is provided with an electrothermal transducer for generating thermal energy. The electrical energy applied to the electrothermal converter is converted to thermal energy, and the ink is ejected from the discharge port using the pressure change caused by the growth and contraction of bubbles caused by film boiling caused by applying the thermal energy to the ink. To discharge. The electrothermal transducer is provided corresponding to each of the ejection ports, and ink is ejected from the corresponding ejection port by applying a pulse voltage to the corresponding electrothermal transducer in accordance with the recording signal.

  As shown in FIG. 1, the carriage 2 is connected to a part of the driving belt 7 of the transmission mechanism 4 that transmits the driving force of the carriage motor M <b> 1, and slides in the direction of arrow A along the guide shaft 13. It is guided and supported freely. Accordingly, the carriage 2 reciprocates along the guide shaft 13 by forward and reverse rotation of the carriage motor M1. A scale 8 is provided for indicating the absolute position of the carriage 2 along the direction of movement of the carriage 2 (the direction of arrow A). In this embodiment, the scale 8 uses a transparent PET film on which black bars are printed at the necessary pitch, one of which is fixed to the chassis 9 and the other is supported by a leaf spring (not shown). Yes.

  Further, the recording apparatus 1 is provided with a platen (not shown) facing the discharge port surface where the discharge port (not shown) of the recording head 3 is formed. Then, the carriage 2 on which the recording head 3 is mounted is reciprocated by the driving force of the carriage motor M1, and at the same time, a recording signal is given to the recording head 3 to eject ink, thereby conveying the recording medium P conveyed onto the platen. Recording is performed over the full width.

  Further, in FIG. 1, reference numeral 14 denotes a conveyance roller driven by a conveyance motor M2 to convey the recording medium P, and 15 denotes a pinch roller that abuts the recording medium P against the conveyance roller 14 by a spring (not shown). Reference numeral 16 denotes a pinch roller holder that rotatably supports the pinch roller 15, and reference numeral 17 denotes a conveyance roller gear fixed to one end of the conveyance roller 14. Then, the transport roller 14 is driven by the rotation of the transport motor M2 transmitted to the transport roller gear 17 through an intermediate gear (not shown).

  Further, reference numeral 20 denotes a discharge roller for discharging the recording medium P on which an image is formed by the recording head 3 to the outside of the recording apparatus, and is driven by transmitting the rotation of the transport motor M2. . The discharge roller 20 abuts on a spur roller (not shown) that presses the recording medium P by a spring (not shown). Reference numeral 22 denotes a spur holder that rotatably supports the spur roller.

  Furthermore, the recording apparatus 1 includes a recording head at a desired position (for example, a position corresponding to the home position) outside the range of reciprocal motion for recording operation of the carriage 2 on which the recording head 3 is mounted (outside the recording area). A recovery device 10 for recovering the ejection failure 3 is provided.

  The recovery device 10 includes a capping mechanism 11 for capping the ejection port surface of the recording head 3 and a wiping mechanism 12 for cleaning the ejection port surface of the recording head 3. In conjunction with capping of the ejection port surface by the capping mechanism 11, ink is forcibly discharged from the ejection port by a suction means (suction pump or the like) in the recovery device, and the viscosity in the ink flow path of the recording head 3 is increased. The ejection recovery process such as removing the ink and bubbles is performed.

  Further, when the recording head 3 is not in operation or the like, the ejection port surface of the recording head 3 is capped by the capping mechanism 11 to protect the recording head 3 and to prevent ink evaporation and drying. On the other hand, the wiping mechanism 12 is disposed in the vicinity of the capping mechanism 11 and wipes ink droplets adhering to the ejection port surface of the recording head 3.

  The capping mechanism 11 and the wiping mechanism 12 can keep the ink ejection state of the recording head 3 normal.

<Control Configuration of Inkjet Recording Apparatus (FIG. 2)>
FIG. 2 is a block diagram showing a control configuration of the recording apparatus shown in FIG.

  As shown in FIG. 2, the controller 600 includes an MPU 601, a special purpose integrated circuit (ASIC) 603, an interface 611, a motor driver 640, and the like. Here, a ROM (not shown) for storing a program corresponding to the recording control sequence, a required table, and other fixed data is connected to the MPU 601, and this program is read out on the RAM (not shown) and executed. The RAM is also used as a development area for image data. The ASIC 603 executes predetermined image processing and generates control signals for controlling the carriage motor M1, the conveying motor M2, and the recording head 3.

  In FIG. 2, a computer (or a reader for image reading, a digital camera, or the like) that is a generic source of image data collectively called a host device receives image data, commands, and the like via an interface (I / F) 611. Send and receive status signals.

  Further, reference numeral 630 denotes a sensor group for detecting the apparatus state, and is a temperature sensor provided at an appropriate position of the position sensor for detecting the home position h such as a photocoupler or a recording apparatus and used for detecting the environmental temperature. Consists of sensors and the like.

  Furthermore, a carriage motor M1 for reciprocating the carriage 2 in the direction of arrow A and a conveyance motor M2 for conveying the recording medium P are driven by a motor driver 640. Furthermore, the carriage printed board 644 mounted on the carriage 2 electrically connects the recording head 3 to the recording apparatus, supplies power from the recording apparatus, and transfers image signals and control signals.

  Note that all power for operating the recording apparatus is supplied from the power supply unit 650.

  Furthermore, in the figure, the portions indicated by bold lines are lines exchanged by a plurality of signal lines.

  The carriage printed board 644 is mounted with a DC / DC converter 31 and a sensor unit 32 such as a linear encoder that detects recording position information of the recording head 3.

  The recording apparatus 1 and the carriage 2 are connected by a flexible flat cable (hereinafter referred to as FFC) 20. Electrically, the FFC 20 connects the carriage printed board 644 and the controller 600, and is an assembly of wiring.

  Reference numeral 20-1 denotes a part of the wiring of the FFC 20, and represents a plurality of wirings that transmit the output voltage setting digital data (CLK signal, LD signal, DI signal) of the DC / DC converter 31 sent from the controller 600. Reference numeral 20-2 denotes a signal line group such as an on / off control signal of the DC / DC converter 31 other than the plurality of wirings 20-1, an output voltage monitor signal, and a status signal.

<Configuration of DC / DC converter (FIG. 3)>
FIG. 3 is a block diagram showing a detailed configuration of the DC / DC converter 31.

  In FIG. 3, reference numeral 100 denotes a MOSFET, and reference numeral 101 denotes an IC that performs power supply control of the DC / DC converter 31. The power supply control IC 101 includes a PWM controller 102 and an error amplifier (comparator) 103.

  Reference numeral 104 denotes a D / A converter that generates a reference voltage for the DC / DC converter 31 from an external voltage setting digital data signal.

  Furthermore, 105 is an inductor, 106 is a rectifier diode, 107 is a smoothing electrolytic capacitor, and 108 and 109 are voltage dividing resistors for detecting the output voltage value of the DC / DC converter 31, respectively.

  When the printed wiring board on which the DC / DC converter 31 is mounted has a large area restriction like the carriage printed board 644, it is necessary to pay close attention to the power supply wiring (particularly the GND wiring). Therefore, in this embodiment, the GND of the D / A converter 104 and the GND of the regulator 112 that supplies power to the D / A converter 104 are as close as possible to the negative (−) terminal of the electrolytic capacitor 107 of the DC / DC converter 31. Wire so that it branches off from. Further, the digital signal input LGND of the D / A converter 104 is connected to the GND terminal of the D / A converter 104.

  Reference numeral 110 denotes an integration time constant circuit including a resistor, a capacitor, and a comparator. The operation of this part will be described later with reference to FIG.

  Reference numeral 111 denotes a decoupling capacitor for the D / A converter 104, and 113 denotes an electrolytic capacitor on the input side of the DC / DC converter 31.

  In an actual circuit, a resistor and a noise removing capacitor are provided between the output of the D / A converter 104 and the input + terminal of the error amplifier 103 to eliminate the influence of the input current of the error amplifier 103. In addition, a resistor and a capacitor for phase compensation of the error amplifier 103 are also provided as constituent elements. However, since the drawing is complicated, these constituent elements are not directly related to the present invention and are omitted from the drawing. Similarly, the power supply control IC 101 of the DC / DC converter 31 and the decoupling capacitor for the regulator 112 are also omitted. In an actual circuit, this capacitor is connected between the power supply terminal and the GND terminal as close as possible to these two ICs.

  The DC / DC converter 31 of this embodiment is called a buck converter and can supply an output voltage (Vo) lower than the input voltage (Vi) by switching the MOSFET 100.

  Next, the operation of changing the output voltage setting of the DC / DC converter 31 in accordance with the external voltage setting digital signal in the above configuration will be briefly described.

  (1) First, when the MOSFET 100 is turned on, a current flows through the inductor 105 to charge the smoothing electrolytic capacitor 107.

  (2) The output voltage (Vo) increases, and the voltage value of the divided output detected by the resistors 108 and 109 also increases.

  (3) This voltage is compared with a voltage set in advance by the D / A converter 104 by the error amplifier (comparator) 103. As a result of the comparison, when the divided voltage becomes larger than the set voltage, a signal for turning off the MOSFET 100 is sent to the PWM controller 102, and the MOSFET 102 is turned off.

  (4) At this time, the inductor 105 generates an induced electromotive force so as to maintain the current that has been flowing so far, and the cathode side of the rectifier diode 106 falls below the GND potential.

  (5) Then, the rectifier diode 106 is turned on, and the inductor 105 releases a current to a load (not shown) while releasing the energy accumulated during the ON time.

  (6) At this time, since the smoothing electrolytic capacitor 107 also supplies energy to the load, the terminal voltage of the smoothing electrolytic capacitor 107 (that is, the output voltage (Vo)) decreases. This state continues until the voltage value of the divided output detected by the resistors 108 and 109 becomes smaller than the voltage set in the D / A converter 104 in advance.

  (7) When the voltage value of the divided output detected by the resistors 108 and 109 decreases, a signal for turning on the MOSFET 100 is sent from the error amplifier 103 to the PWM controller 102, and the MOSFET 102 is turned on again.

  As described above, by repeating the operations (1) to (7), the PWM controller 100 can maintain the output voltage (Vo) at the voltage set by the D / A converter 104 so that the ON / OFF signal from the error amplifier 103 can be maintained. Control the time. Thereby, the output voltage (Vo) is stabilized. Such control is called PWM control.

  This time, output voltage setting digital data (CLK, LD, DI signal) is sent from the controller 600 to the D / A converter 104 with the output voltage once stabilized.

  With this data, the reference voltage applied to the input (+) terminal of the error amplifier 103 changes.

  Then, compared to the divided output voltage (Vo) detected by the resistors 108 and 109 at this time, the PWM controller 102 turns off the MOSFET 100 when the reference voltage is high and turns on the MOSFET 100 when the reference voltage is low. Controls the pulse width. Then, as described above, the operations (1) to (7) are repeated. As a result, the output voltage becomes the newly set output voltage set value, and the output voltage (Vo) is stabilized.

<Integration time constant circuit (FIGS. 4 to 6)>
FIG. 4 is a circuit diagram showing a part of the integration time constant circuit 110 incorporated in the DC / DC converter. In FIG. 4, one of the integration time constant circuits 110 including the resistor R, the capacitor C, and the comparator 201 shown in FIG. 3 is extracted.

  This portion operates as an integration circuit having a time constant τ given by the product of the resistor R and the capacitor C.

  FIG. 5 is a signal waveform diagram showing the operation of the integrating circuit.

  As shown in FIG. 5, the integration circuit operates so as to blunt the rising and falling edges of the input signal pulse. This serves as a low-pass filter that limits the band of the high-frequency signal. The comparator 201 is characterized by having no hysteresis with half of the power supply voltage VDD as a threshold value.

  This is because the duty ratio of the input pulse is not lost, and if the duty ratio of the clock signal pulse or the like is lost, the operation timing of the digital circuit is inconvenient.

  When the integration circuit is used as in the “chattering prevention circuit” disclosed in Patent Document 5, the purpose is to extract the state of the original long pulse from the input pulse band-limited by the integration circuit. Information is not required.

  Therefore, the time constant is determined so that the amplitude of the short pulse is limited within the hysteresis range, and the hysteresis comparator is used as the input of the buffer circuit connected to the next stage.

  In this embodiment, if a hysteresis comparator is used, the pulse duty ratio is lost and the edge timing information is lost.

  As can be understood from FIGS. 8 to 10 described in the prior art, if noise is placed on the GND level at the timing when the logic level of the D / A converter must be originally low, the logic level of the D / A converter is increased. The threshold voltage for detecting the level is exceeded. This causes a malfunction. For this reason, output voltage setting digital data (CLK signal, LD signal, DI signal) input to the D / A converter logic at different timings, and an analog value that is not predetermined voltage setting data is output.

  In order to solve such a problem, in this embodiment, an integration circuit having a CR time constant as shown in FIG. 4 is inserted into each input terminal of the CLK signal, LD signal, and DI signal.

  Next, how to determine a value of a time constant necessary and sufficient to prevent malfunction will be described.

  Conventionally, the time constant is determined by taking a margin in the value determined by the actually measured waveform. However, if the time constant is simply set to a large value in order to enhance resistance to noise, the signal waveform necessary for the correct operation of the DC / DC converter will be dull. This leads to failure to maintain the logic timing necessary for the D / A converter, and causes malfunctions and malfunctions.

  It is more difficult to determine the lower limit of the time constant. Conventionally, the noise margin is determined by a value based on the evaluation result of the sample DC / DC converter used in the experiment. For this reason, some samples must be evaluated and their values determined by statistical processing, which always includes a risk factor based on the number of samples.

  In consideration of such problems, in this embodiment, an upper limit and a lower limit value of the time constant are obtained. Thus, if a time constant within the range is set, it is possible to reliably reduce malfunctions of the DC / DC converter.

  The procedure for determining the upper and lower limits of the time constant is shown below.

(1) Determination of upper limit value (τ _MAX ) of time constant τ To determine the upper limit value, consider how far the pulse can be dulled.

FIG. 5B shows a waveform when the time constant is the upper limit value. The upper limit value is a value that can maintain the peak value amplitude of the original pulse even if the pulse waveform is blunted while ensuring a noise margin as much as possible. This is defined by defining f _CLK as a frequency in which one cycle of the clock pulse signal of the D / A converter 104 (continuous part in the case of a burst) is a sine wave, and f _CLK is just the cut-off frequency. It is calculated | required by making the time constant into an upper limit. In FIG. 5B, a thin solid sine waveform corresponds to f _CLK .

  That is, a condition satisfying the following expression is satisfied.

τ _MAX = 1 / 2πf _CLK
The pulse dulled with the time constant value of CR is represented by the thick line in FIG. 5B, and it can be seen that the peak value amplitude of the original pulse is substantially maintained.

  Thereafter, in the comparator 201, if the high level threshold value of the logic signal is set to a value that is ½ of the peak value of the pulse, the duty relationship is reproduced in the information of the pulse waveform of the original clock signal. Is possible. As a result, it is possible to obtain a waveform that is delayed by the time Td.

  Therefore, as shown in FIG. 3, if all of the output voltage setting digital data (CLK signal, LD signal, DI signal) of the D / A converter 104 is dulled with the same time constant, the delay time Td is canceled out. I can do it. The delay time (Td) is sufficiently small with respect to the voltage setting timing of the DC / DC converter 31 and is not affected.

(2) Determination of the lower limit value (τ _MIN ) of the time constant τ When determining the lower limit value, it is necessary to consider how much the noise component can be reduced to eliminate the malfunction of the logic.

  In general terms, it is difficult to determine this value because the frequency of the noise component cannot be specified. Therefore, conventionally, it was handled on a case-by-case basis. That is, as described above, several samples are selected, experimental values are actually obtained, and the range of the values is determined by statistical processing. When a DC / DC converter is mass-produced, there are cases where parts of different lots enter and cause problems due to a noise distribution deviating from that initially considered in statistical processing.

  Therefore, the problem was analyzed once more in this example.

  As described with reference to FIG. 10, the cause of the malfunction of the DC / DC converter is that the logic signal is set to the high level in the section that should originally be the low level due to the noise component included in the output voltage setting digital data. It is.

  As shown in FIG. 8, attention is paid to the switching noise generated in association with the operation of the DC / DC converter when analyzing the problem. This noise waveform is obtained from oscilloscope measurements. Here, attention is paid to one period of the frequency component having the largest amplitude appearing at the beginning of the noise waveform.

  In FIG. 8, a sinusoidal component having a period of 400 ns can be observed.

In practice, distortion of a sine wave can be seen, but if this component is expanded by a Fourier series (that is, observed with a spectrum analyzer), it always appears as a harmonic component that is an integral multiple of the fundamental wave, and its amplitude is higher than the fundamental wave. Get smaller. Accordingly, a frequency in which the frequency component having the largest amplitude appearing at the beginning of the noise waveform is regarded as a sine wave is defined as f _Noise .

In the example shown in FIG. 8, _fNoise = 1/400 [ns] = 2.5 [MHz].

  Next, the positive maximum value based on the GND of the noise component in the worst state (occurrence of malfunction) is defined as An. Then, looking at the numerical value when the malfunction occurred from FIG. 10B, it was An = 2.5 [V].

Now, the logic threshold value of the comparator 201 is defined as V _{TH (Logic)} .

  In this embodiment, since the logic signal is 3.3V, the threshold value is half that of 1.65V. Then, the condition under which no malfunction occurs is given by equation (1).

V _{TH (Logic)} > An (1)
Actually, however, a malfunction may be caused in spite of V _{TH (Logic)} <An.

  Therefore, an attenuation rate (Kd: Kd ≦ 1) is considered.

  Then, the condition under which no malfunction occurs is as shown in Equation (2).

V _{TH (Logic)} > Kd x An (2)
That is, it can be seen that Kd <V _{TH (Logic)} / An.

At this time, Kd _(MAX) is given by Kd _(MAX) = _{VTH (Logic)} / An.

  In the case of an integral filter, the attenuation factor (Kd) is given by the partial pressure of the impedance, and is expressed as in equation (3).

Kd _(MAX) = V _{TH (Logic)} / An
= (1 / ωC) / √ {R ² + (1 / ωC) ² } (3)
Here, when ω = 2π × f _Noise and R × C = τ, the lower limit value (τ _MIN ) of the time constant to be obtained by arranging τ is as shown in Equation (4).

τ _MIN = √ {(An / V _{TH (Logic)} ) ² −1} / 2πf _Noise (4)
As described above, in this embodiment, it is determined that the noise component resulting from the switching operation of the DC / DC converter is the cause of the malfunction of the D / A converter, and within the carriage printed board on which the DC / DC converter is mounted. The time constant of the integration circuit to be used is determined. That is, the minimum value of the time constant of the integration circuit is determined by utilizing the fact that the noise component is the maximum level and the lowest low frequency component in terms of frequency. On the other hand, the maximum value is determined by considering how far the pulse band can be limited as digital transmission, and clarifying a numerical value that can provide a wide noise margin.

  As a result of performing a simulation using an electric circuit simulator with the conditions defined as follows based on this formula, the pulse response when the obtained time constant is the lower limit value is as shown in FIG. The pulse response at the time of value is as shown in FIG.

Simulation conditions Clock frequency: f _CLK = 1MHz
Noise frequency: f _Noise = 2.5MHz
Logic threshold level: V _{TH (Logic)} = 1.65V
Maximum positive amplitude of noise: An = 2.5V
Note that the time axis scale in FIG. 5 is 200 ns.

  FIG. 6 is a signal waveform diagram showing a simulation result.

In FIG. 6, a sine wave having a small amplitude represented by a thick line is a noise component equivalent waveform after passing through the integrating circuit. In this simulation, the resistance R = 362.5Ω, the capacitor C = 200 pF, and the lower limit time constant τ _MIN = 72.5 [ns].

  From this simulation result, a time constant τ larger than this value is adopted in an actual DC / DC converter. In addition, since the noise components that actually occur from the noise frequency of 2.5 MHz, which is the simulation condition, are all high in frequency and small in amplitude, the noise level can be reliably suppressed below the high level threshold of the logic signal. It becomes possible.

  Also, the integration circuit with the same time constant is used for all the input terminals of the CLK signal, LD signal, and DI signal of the D / A converter because the timing changes of the three input signals when the waveform is shaped by the comparator This is because there is an intention to arrange them. If the timing changes of the three signals are not severe, it is not necessary to align these values.

  In the above embodiment, the output impedance of the previous circuit is zero and the input impedance of the next circuit is infinite for the sake of clarity, but the effect is applied when applied to an actual circuit. It is necessary to set the resistance value and the capacitance value of the capacitor in consideration of

  Further, although the CR integration circuit has been described in the above embodiment, it is possible to replace with an inductor and a resistor having the same time constant τ as represented by the equation (5).

τ = CR = L / R (5)
As explained above, since it was not possible to identify which noise component caused the malfunction in the conventional technology, the design value of the integration circuit had to be determined by experiment, and for the noise component that did not appear during the experiment Could not deny the possibility of causing malfunction.

  However, in the embodiment described above, it is specified that the cause of the malfunction of the D / A converter is a noise component resulting from the operation of the DC / DC converter, and the minimum value of the time constant of the integrating circuit is taken into account that noise component. It was determined. On the other hand, the maximum value was determined by considering how far the pulse can be band-limited as digital transmission, and clarifying a numerical value that can provide a wide noise margin. By determining the time constant of the integration circuit based on the maximum value and the minimum value determined in this way, the DC / DC converter can realize a stable operation against noise.

  Further, since the frequency component of the switching noise of the DC / DC converter has been clarified, the time constant margin and the noise removal margin when the operation clock of the D / A converter is raised to the limit can be clarified.

  Here, returning to FIG. 2 again, the operation of the recording apparatus using the above-described DC / DC converter will be described.

  In order to change the voltage supplied from the controller 600 to the recording head 3 at a certain timing, the output voltage setting digital data is sent to the D / A converter 104 mounted on the DC / DC converter 31 via the wiring 20-1 of the FFC 20. Consider the case of sending.

  In this case, the DC / DC converter 31 changes the output voltage setting as described above based on the digital data. As a result, the recording head 3 performs the recording operation with the newly set voltage.

  As shown in FIG. 1, the serial type recording apparatus conveys the recording medium while reciprocating the carriage 2 repeatedly in the direction of arrow A on the recording medium. The FFC 20 usually has a length of about 50 to 80 cm depending on the type of the recording apparatus, and the voltage setting signal transmission line 20-1 of the DC / DC converter 31 is elongated. In addition, the image signal of each color component corresponding to the ink color must be transmitted to the recording head 3, and the number of signal lines that can be passed through the wiring of the FFC 20 is limited. Accordingly, the thickness of the wiring of the FFC 20 is naturally limited, and the wiring impedance becomes high and is easily affected by noise.

  However, since the DC / DC converter 31 as described above is used in this embodiment, it is strong against noise and does not malfunction in setting the output voltage. Accordingly, since stable power can be supplied to the recording head 3, stable recording is possible.

  Further, according to this embodiment, even when the recording apparatus changes the setting of the voltage of the recording head during the recording operation, a stable recording operation can be realized for the following reason.

  During the recording operation, digital noise generated by the image processing operation executed by the ASIC 603 and the MPU 601 of the recording apparatus and the exchange of various control signals performed by the control 600 increases. However, these noises are components whose levels are lower and higher in frequency than noise components associated with the switching operation of the DC / DC converter, and are sufficiently suppressed by the integration time constant circuit 110 having the above-described time constant.

  Furthermore, as described above, for the recording operation of the recording apparatus, the carriage transports the recording medium while reciprocating many times on the recording medium. Acts as a radiating antenna. However, since the harmonic component of the control signal of the D / A converter of the embodiment described above is suppressed by the time constant circuit 110, the noise component radiated by using the wiring of the FFC 20 as an antenna can be reduced. . Therefore, the recording apparatus has an advantage that it easily conforms to EMC noise standards.

1 is an external perspective view showing an outline of a configuration of an inkjet recording apparatus 1 that is a typical embodiment of the present invention. FIG. 2 is a block diagram illustrating a control configuration of the recording apparatus illustrated in FIG. 1. 3 is a block diagram showing a detailed configuration of a DC / DC converter 31. FIG. It is a circuit diagram showing a part of integration time constant circuit 110 incorporated in a DC / DC converter. It is a signal waveform diagram which shows operation | movement of an integration circuit. It is a signal waveform diagram which shows a simulation result. It is a block diagram which shows the structural example of the conventional DC / DC converter. It is a figure which shows the voltage waveform by the oscilloscope of the input terminal of the conventional D / A converter. It is the figure which showed the waveform when the DC / DC converter is exchanging the voltage setting signal from a D / A converter. It is the figure which showed the relationship between the output value of a D / A converter at the time of voltage setting, and the output value (Vo) of a DC / DC converter.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Inkjet recording device 3 Recording head 20 Flexible flat cable (FFC)
31 DC / DC converter 100 MOSFET
101 Power control IC
102 PWM controller 103 Error amplifier (comparator)
104 D / A converter 105 Inductor 106 Rectifier diode 107 Smoothing electrolytic capacitor 108, 109 Voltage dividing resistor 110 Time constant circuit 111 Decoupling capacitor 112 Regulator 201 Comparator 644 Carriage printed circuit board 650 Power supply unit

Claims (8)

A power supply device capable of changing a set output voltage based on a digital control signal input from the outside,
A time constant circuit for inputting the digital control signal;
A D / A converter for inputting a digital control signal distorted by the time constant circuit;
A comparator that compares the output voltage value with a voltage value output from the D / A converter as a threshold;
A controller that performs pulse width modulation according to a comparison result from the comparator;
A switching element that is turned on / off by a control signal pulse-width modulated by the controller, converts the input voltage into the set output voltage, and outputs the switching voltage;
The time constant circuit, the D / A converter, the comparator, the controller, and the switching element are mounted on the same substrate,
The time constant of the time constant circuit is determined in consideration of a cycle of the digital control signal and a frequency of switching noise related to a switching operation of the switching element.   The power supply apparatus according to claim 1, wherein the switching element is a MOS-FET. The digital control signal is serially transferred and includes a clock signal, a latch signal, and a digital data signal,
3. The power supply device according to claim 1, wherein the time constant of the time constant circuit is determined in consideration of a cycle of the clock signal.   4. The power supply device according to claim 1, wherein the time constant circuit is disposed in the vicinity of an input terminal of the digital control signal. 5. The upper limit of the time constant (τ) is
A frequency (f _CLK ) in which one cycle of the clock signal is a sine wave cycle is _defined as a cutoff frequency.
τ <1 / 2πf _CLK
The filling,
The lower limit of the time constant (τ) is
Τ> √ {(An / V _{TH )} , where An is the positive maximum value of the noise component generated by the switching operation, V _{TH (Logic)} is the threshold value of the comparator, and f _Noise is the noise frequency at this time. _(Logic) ) ² -1} / 2πf _Noise
The power supply device according to claim 2, wherein:   6. The power supply device according to claim 1, wherein the power supply device is a DC / DC converter. A recording apparatus using the power supply device according to claim 1 to supply power to a recording head,
A carriage that incorporates the power supply device and reciprocates with the recording head mounted thereon;
Generating means for generating the digital control signal;
A recording apparatus comprising: a signal line for connecting the generation unit and the carriage, and transferring the digital control signal and a recording signal for the recording head; and a built-in flexible flat cable. The recording apparatus according to claim 7, wherein the recording head is an ink jet recording head.

Images