JP2013102647A - Dc-dc converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively prevent degradation of characteristics due to a set output voltage in an output-voltage variable DC-DC converter.SOLUTION: An output-voltage variable DC-DC converter having a negative feedback loop for controlling an output voltage on the basis of a predetermined reference voltage comprises: reference signal generating means that generates the reference voltage on the basis of a voltage setting signal; phase compensation means that is disposed in the negative feedback loop; and phase compensation control means that changes the circuit constant of the phase compensation means on the basis of the voltage setting signal to obtain desired characteristics.

Description

  The present invention relates to a control technique for a DC-DC converter used for power supply of a portable device or the like.

  In portable devices, reduction of power consumption for extending battery duration is an important issue. In order to reduce power consumption, a portable device can select a high-speed operation and a low-speed operation, and may increase the voltage only when high-speed operation is necessary, and may decrease the voltage during normal operation.

  As a voltage supply source for supplying such different voltages, a highly efficient and variable output voltage variable DC-DC converter is often used (see, for example, Patent Documents 1 to 3).

  In the above-described variable output voltage type DC-DC converter, the phase margin (phase at 0 dB gain) and the gain margin (phase 0 °) of the phase characteristics of the negative feedback loop for controlling the output voltage based on a predetermined reference voltage. The operation is stable when a sufficient gain is obtained, but if the phase margin or gain margin is smaller than a predetermined value, the output voltage becomes unstable due to subharmonic oscillation. In circuits handling small amplitude AC signals, it is not necessary to consider changes in phase characteristics due to output voltage, but in circuits handling DC signals, the phase characteristics change greatly depending on the output voltage, and depending on the output voltage, the characteristics deteriorate and supply The required characteristics from the destination device may not be satisfied.

  Some DC-DC converters can be mounted by mounting external parts in order to prevent characteristic deterioration, but there is a problem that the number of parts increases and the cost increases.

  Japanese Patent Application Laid-Open No. H10-228707 discloses a technique for performing variable gain and variable phase compensation to prevent oscillation in a DC-DC converter that supports a wide range of input voltages. However, it is intended for fluctuations in the input voltage, not for the fluctuations in the output voltage described above, and does not solve the above problem.

  The present invention has been proposed in view of the above-described conventional problems, and the object of the present invention is to effectively reduce the characteristics of the output voltage variable type DC-DC converter due to the set output voltage. An object of the present invention is to provide a DC-DC converter that can be prevented.

  In order to solve the above-described problems, the present invention provides a variable output voltage type DC-DC converter having a negative feedback loop for controlling an output voltage based on a predetermined reference voltage. A reference voltage generating means for generating the reference voltage based on a signal; a phase compensating means disposed in the negative feedback loop; and a circuit constant of the phase compensating means is changed based on the voltage setting signal to obtain a desired value. Phase compensation control means for providing phase characteristics is provided.

  In the DC-DC converter of the present invention, it is possible to effectively prevent the characteristics from deteriorating due to the set output voltage.

It is a figure which shows the structural example of the DC-DC converter concerning one Embodiment of this invention. It is a figure which shows the structural example of a phase compensation part. It is a figure which shows the structural example of a phase compensation control circuit. It is a figure which shows the example of the Bode diagram in the whole system | strain. It is a figure which shows the example of the Bode diagram in a phase compensation part.

  Hereinafter, preferred embodiments of the present invention will be described.

<Circuit configuration>
FIG. 1 is a diagram illustrating a configuration example of a DC-DC converter 1 according to an embodiment of the present invention.

  The circuit shown is a current-mode controlled DC-DC converter, which includes a DA converter (DAC) 101, an error amplifier circuit (ERR AMP) 102, a voltage divider 103 (resistors R1, R2), a PWM comparator (PWM COMP) 104, Inductor current detection circuit (I / V) 105, oscillation circuit (OSC) 106, PWM control circuit 107, switching transistor (PchTr) 108, synchronous rectification transistor (NchTr) 109, inductor (Lo) 110, capacitor (Co) 111, a phase compensation unit 112, a ROM 113, a register 114, an interface unit 115, an operation input unit 116, and a phase compensation control circuit 117.

  The DA converter 101 is supplied with the output voltage setting code Voset from the register 114, converted into a voltage by DA conversion, and output. The output is input to the non-inverting input of the error amplifier circuit 102 as a reference voltage Vref. A voltage Vfbin obtained by dividing the output voltage Vfb applied to the load 2 by the resistors R1 and R2 of the voltage divider 103 is input to the inverting input of the error amplifier circuit 102.

  The output of the error amplification circuit 102 is input to the inverting input of the PWM comparator 104. The output of the inductor current detection circuit 105 is input to the non-inverting input of the PWM comparator 104. The inductor current detection circuit 105 performs slope compensation for preventing subharmonic oscillation on the feedback current of the inductor Lo, and then converts the feedback current into a voltage and outputs the voltage.

  The PWM control circuit 107 controls the ON / OFF duty of the switching transistor 108 based on the clock CLK from the oscillation circuit 106 and the output of the PWM comparator 104, and the synchronous rectification transistor 109 is complementary to the switching transistor 108. To control ON / OFF.

  The source of the switching transistor 108 is connected to the input voltage VIN, the drain is connected to the drain of the synchronous rectification transistor 109, and the source of the synchronous rectification transistor 109 is connected to the ground (GND). The drain of the switching transistor 108 is connected to GND via the inductor Lo and the capacitor Co, and the connection point between the inductor Lo and the capacitor Co is connected to the load 2.

  The input / output of the main path of the phase compensator 112 is connected between the input (Vfb) of the voltage divider 103 and the inverting input (Vfbin) of the error amplifier circuit 102. Note that the phase compensation unit 112 can be inserted not only in the illustrated position, but also between Vfbin and the output of the error amplification circuit 102, or between the output of the error amplification circuit 102 and GND. Further, a plurality of phase compensation units 112 may be provided.

  The output Phase_sft of the phase compensation control circuit 117 is input to the control input of the phase compensation unit 112.

  The phase compensation control circuit 117 includes an output voltage setting code Voset output from the register 114, a phase compensation setting code Extset1 output from the ROM 113, a phase compensation setting code Extset2 output from the register 114, and a phase compensation setting selection signal Swset_sel. Is entered.

  An interface unit 115 that accepts software operations from the host system 3 and an operation input unit 116 that accepts manual operations are connected to the register 114.

  FIG. 2 is a diagram illustrating a configuration example of the phase compensation unit 112.

  In FIG. 2, the phase compensation unit 112 includes switches Sw1 / Sw1 ′, Sw2 / Sw2 ′, Sw3 / Sw3 ′, and switches Sw1 / Sw1 ′, Sw2 whose ON / OFF is controlled by the output Phase_sft of the phase compensation control circuit 117. Capacitors Cph1, Cph2, and Cph3 connected between Vfb and Vfbin by turning on / Sw2 ′ and Sw3 / Sw3 ′. The switch Sw1 and the switch Sw1 ′ perform the same operation, the switch Sw2 and the switch Sw2 ′ perform the same operation, and the switch Sw3 and the switch Sw3 ′ perform the same operation. The combination of using the capacitors Cph1, Cph2, and Cph3 is selected by the combination of ON / OFF of the switches Sw1 / Sw1 ′, Sw2 / Sw2 ′, and Sw3 / Sw3 ′, and the phase compensation constant is changed. By changing the phase compensation constant, unstable operation due to output voltage change can be avoided. The illustrated phase compensator 112 includes a switch and a capacitor, and the capacitance is variable. However, a resistor may be added to the switch and the capacitor, and the resistor may be variable or both the capacitor and the resistor may be variable by the switch. Further, the capacitance and resistance values may be directly trimmed manually.

  FIG. 3 is a diagram illustrating a configuration example of the phase compensation control circuit 117.

  In FIG. 3, the phase compensation control circuit 117 decodes the decode circuit DEC1 that decodes the output voltage setting code Voset from the register 114, the output voltage setting code Voset from the register 114, and the phase compensation setting code Extset1 from the ROM 113. Decoding circuit DEC2, decoding circuit DEC3 for decoding output voltage setting code Voset from register 114 and phase compensation setting code Extset2 from register 114, decoding circuit DEC1, based on phase compensation setting selection signal Swset_sel from register 114, Select one of the outputs of DEC2 and DEC3 and output it as a selection signal Swon_sel, and select one from the preset combination of switches SW1, Sw2, and Sw3 based on the output of selector SEL1 And selector SEL2 for outputting as Phase_sft.

  The decode circuit DEC1 is a signal that selects one of the ON combinations of the switches Sw1, Sw2, and Sw3 that are input to the selector SEL2 with respect to the range of the value indicated by the output voltage setting code Voset expressed by a predetermined number of bits. (For example, when selecting seven combinations of signals shown in the figure, the selection contents are expressed by a combination of three bits, or selection is expressed by seven bits corresponding to each of the seven combinations). The output voltage setting code Voset is a digital output voltage value set in the register 114 from the host system 3 via the interface unit 115 or manually through the operation input unit 116. Correspondence between input and output in the decoding circuit DEC1 can be implemented by wired logic or programmable logic.

  The decoding circuit DEC2 selects one of the ON signals of the switches Sw1, Sw2, and Sw3 that are input to the selector SEL2 for the code obtained by combining the output voltage setting code Voset and the phase compensation setting code Extset1 by bit operation etc. Output a signal. Correspondence between input and output in the decoding circuit DEC2 can be implemented by wired logic or programmable logic. The advantage of determining the phase compensation constant by decoding from both the output voltage setting code Voset and the phase compensation setting code Extset1 is that the phase compensation setting code Extset1 is used when the characteristics cannot be satisfied with the preset settings only with the output voltage setting code Voset. Thus, the ON combination of the switches Sw1, Sw2, and Sw3 can be changed, and the characteristics can be corrected. At the stage before shipment to the user, the phase compensation setting code Extset1 can be set as a correction value in the ROM 113 to ensure the characteristics.

  The decode circuit DEC3 selects one of the ON combinations of the switches Sw1, Sw2, and Sw3 that are input to the selector SEL2 with respect to the code obtained by combining the output voltage setting code Voset and the phase compensation setting code Extset2 by bit operation etc. Output a signal. Correspondence between input and output in the decoding circuit DEC3 can be implemented by wired logic or programmable logic. The advantage of determining the phase compensation constant by decoding from both the output voltage setting code Voset and the phase compensation setting code Extset2 is that the phase compensation setting code Extset2 of the register 114 is used to determine the phase compensation setting code Extset1 in the ROM 113 described above. It is easy to confirm in advance. Since the phase compensation setting code Extset2 can be set in the register 114 by software, it is possible to change the ON combination of the switches Sw1, Sw2, and Sw3, and the characteristics can be easily confirmed by the change.

  The selector SEL1 selects one of the outputs of the decoding circuits DEC1, DEC2, and DEC3 based on the phase compensation setting selection signal Swset_sel and outputs it as the selection signal Swon_sel.

  Based on the selection signal Swon_sel that is the output of the selector SEL1, the selector SEL2 selects one of the preset combination signals of the switches Sw1, Sw2, and Sw3 and outputs it as Phase_sft. Phase_sft is supplied to the phase compensation unit 112.

  The input to the phase compensation control circuit 117 uses the ROM 113 or the register 114 set by software as described above. However, when there is no setting path from the software, the operation input unit 116 such as an external terminal or the like is used. Can be set manually.

  In general, when changing the filter constant, the analog amount of the input voltage or output voltage is monitored and changed based on the analog amount. In this embodiment, however, the digital value set in the register 114 or the ROM 113 is used. Since the reference voltage and the filter constant are controlled, the circuit configuration is easy. In a circuit that handles analog quantities, it is necessary to consider characteristic variations due to process parameter variations in the semiconductor manufacturing process, but in this circuit that handles digital values, these considerations are unnecessary.

<Method of phase compensation>
In the DC-DC converter 1 shown in FIG. 1, an error amplification circuit 102, a PWM comparator 104, a PWM control circuit 107, a switching transistor 108, a synchronous rectification transistor 109, an inductor 110, a capacitor 111, a voltage dividing unit 103, a phase The negative feedback loop formed by the compensation unit 112 and the inductor current detection circuit 105 is controlled so that the output voltage Vfb is constant.

  Here, consider a case where the phase characteristics of the negative feedback loop are given by, for example, the Bode diagram of FIG.

  In the DC-DC converter 1 of FIG. 1, in a situation where the phase margin or the gain margin cannot be sufficiently secured by the combination of the input voltage, the output setting voltage, the load current, the inductor Lo, and the capacitor Co, the sub-harmonic oscillation The output voltage may become unstable. In FIG. 4, the phase margin is defined as a phase (frequency fg0) at a gain of 0 dB, and the gain margin is defined as a gain (frequency fp0) at a phase of 0 °. In the DC-DC converter 1 of FIG. 1, it is necessary to prevent the subharmonic oscillation of the output voltage by performing phase compensation to sufficiently secure the phase margin and the gain margin.

  In the DC-DC converter 1 of FIG. 1, the reference voltage Vref is set by the output voltage setting code Voset, and the output voltage Vfb corresponding to each setting can be output. However, when the capacitance value of the phase compensation unit 112 is constant regardless of the output setting voltage, the phase margin or gain margin of the negative feedback loop cannot be sufficiently secured depending on the output setting voltage, and the output voltage May become unstable. In this regard, in this embodiment, it is possible to optimize the phase margin and gain margin of the negative feedback loop by making the constant of the phase compensation unit 112 shown in FIG. 2 variable according to the output setting voltage. .

  In order to explain this, a transfer function from the output voltage Vfb to the divided voltage Vfbin is calculated, and a Bode diagram is obtained from this transfer function.

  First, the voltage Vfbin in the Laplace transform format is given by the following equation using circuit constants R1, R2, and C. However, s = iω. i is an imaginary number, and ω is an angular frequency.

ここで、

here,

とおくと、式（１）は次式のように書き換えることができる。

Then, the equation (1) can be rewritten as the following equation.

この式から、伝達関数は次式で与えられる。

From this equation, the transfer function is given by:

したがって、伝達関数Vfbin／Vfb（ｓ）のボーデ線図は図５に示すようになり、周波数fz、fpの間に位相カーブの山ができる。ただし、図５の周波数fz、fpは、前記のωｚ＝２πｆｚ、ωｐ＝２πｆｐにより計算される。

Therefore, the Bode diagram of the transfer function Vfbin / Vfb (s) is as shown in FIG. 5, and a peak of the phase curve is formed between the frequencies fz and fp. However, the frequencies fz and fp in FIG. 5 are calculated by the above-described ωz = 2πfz and ωp = 2πfp.

  From equations (2), (3), and (5), it can be seen that the phase characteristic of the transfer function Vfbin / Vfb (s) is determined by the frequency fz, fp, that is, the circuit constants of R1, R2, and C.

  Therefore, by changing the value of the total capacitance C in the phase compensation unit 112, the peak frequency of the peak in the phase curve can be changed, so that the phase margin in the Bode diagram of the negative feedback loop shown in FIG. The peak frequency of the phase compensation unit 112 is overlapped in the vicinity of the frequencies fg0 and fp0 for determining the gain margin, and the total of the phase compensation unit 112 according to each output setting voltage so that the phase margin and the gain margin can be sufficiently secured. What is necessary is just to optimize the value of the capacity C.

  From the above, in the DC-DC converter 1, it is possible to optimize the phase characteristics of the negative feedback loop for keeping the output voltage constant by changing the capacity of the phase compensation unit 112 according to the output setting voltage. Become.

<Summary>
As described above, the present embodiment has the following advantages.

  (1) The phase compensation control circuit as the phase compensation control means changes the circuit constant of the phase compensation unit as the phase compensation means based on the voltage setting signal to obtain a desired phase characteristic. Degradation of the phase characteristics of the negative feedback loop can be prevented, and a stable voltage can be supplied.

  (2) By setting all of the voltage setting signal and the phase compensation with digital values, it is not necessary to consider characteristic variations due to process parameter variations in the semiconductor manufacturing process, and the circuit configuration is facilitated.

  (3) Since the correction setting signal can be given by manual operation, it is reliable even if it exceeds the characteristic fluctuation assumed in advance due to the application variation of the DC-DC converter, the connection environment, and the process variation in the semiconductor manufacturing process. Phase compensation can be performed. In addition, an external component for phase compensation is unnecessary, which can contribute to cost reduction.

  (4) By making changes by software, external terminals, etc., it is possible to facilitate analysis when an oscillation problem occurs by using only automatic change. In addition, since the setting can be changed according to the use state of the DC-DC converter, more reliable phase compensation is possible. By having a change means for ROM or trimming, there is no burden on the user side as in the case of automatic change.

  (5) In addition to automatic change, phase compensation can be performed more reliably by combining correction by software, further trimming and correction by ROM. In addition, it is possible to evaluate phase compensation with an engineer sample by setting from software, and to reflect the result in trimming and ROM settings.

  The present invention has been described above by the preferred embodiments of the present invention. While the invention has been described with reference to specific embodiments, various modifications and changes may be made to the embodiments without departing from the broad spirit and scope of the invention as defined in the claims. Obviously you can. In other words, the present invention should not be construed as being limited by the details of the specific examples and the accompanying drawings.

DESCRIPTION OF SYMBOLS 1 DC-DC converter 2 Load 101 DA converter 102 Error amplification circuit 103 Voltage dividing part 104 PWM comparator 105 Inductor current detection circuit 106 Oscillation circuit 107 PWM control circuit 108 Switching transistor 109 Synchronous rectification transistor 110 Inductor 111 Capacitor 112 Phase compensation part 113 ROM
114 Register 115 Interface Unit 116 Operation Input Unit 117 Phase Compensation Control Circuit 3 Host System

JP-A-11-187647 Japanese Unexamined Patent Publication No. 2009-261048 JP 2010-130856 A

Claims (7)

An output voltage variable type DC-DC converter including a negative feedback loop for controlling an output voltage based on a predetermined reference voltage,
A reference voltage generating means for generating the reference voltage based on a voltage setting signal;
Phase compensation means disposed in the negative feedback loop;
A DC-DC converter comprising phase compensation control means for changing a circuit constant of the phase compensation means based on the voltage setting signal to obtain a desired phase characteristic. The DC-DC converter according to claim 1, wherein
The voltage setting signal is a digital value,
The reference voltage generation means generates the reference voltage by DA converting the voltage setting signal based on a digital value,
The phase compensation control means changes a circuit constant of the phase compensation means based on the voltage setting signal based on a digital value. The DC-DC converter according to any one of claims 1 and 2,
Correction setting means for providing a correction setting signal to the phase compensation control means,
The DC-DC converter characterized in that the phase compensation control means changes a circuit constant of the phase compensation means based on the voltage setting signal and the correction setting signal. The DC-DC converter according to claim 3,
The correction setting means includes
Means for outputting the correction setting signal by software operation from an upper host system;
Means for outputting the correction setting signal by manual operation received by the operation input unit;
A DC-DC converter including any one of means for outputting the correction setting signal by a ROM. In the DC-DC converter as described in any one of Claim 3 or 4,
A DC-DC converter comprising: means for selecting one or a combination of the voltage setting signal and the correction setting signal which are input to the phase compensation control means. The DC-DC converter according to any one of claims 1 to 5,
A DC-DC converter comprising means for directly trimming the circuit constant of the phase compensation means. A method for controlling a variable output voltage type DC-DC converter having a negative feedback loop for controlling an output voltage based on a predetermined reference voltage,
A reference voltage generating means for generating the reference voltage based on a voltage setting signal;
The phase compensation control means includes a phase compensation control step of changing a circuit constant of the phase compensation means arranged in the negative feedback loop based on the voltage setting signal to obtain a desired phase characteristic. DC-DC converter compensation control method.

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