JP5645466B2 - Power supply control circuit and electronic device - Google Patents

Description

  The present application relates to a power supply control circuit that generates a desired output voltage from an input voltage, and an electronic apparatus.

  In an electronic device or the like, a switching power supply is used to supply power to a load, and for example, a DCDC converter that converts a DC voltage into another DC voltage is used. Conventionally, various control methods have been proposed for DCDC converters (see, for example, Patent Documents 1 to 3).

  FIG. 1 shows an example of a conventional DCDC converter. A feedback voltage Fb obtained by dividing the output voltage Vo by the resistors R1 and R2 is input to the inverting input terminal of the comparator ErrComp. A voltage obtained by adding a predetermined constant voltage V1 and a predetermined slope voltage Vs by an adder is input to the non-inverting input terminal of the comparator ErrComp. The output signal of the comparator ErrComp is input to the set terminal of the RS flip-flop 1.

  The PWM signal output from the RS flip-flop 1 is input to the on period generation circuit 3. The on period generation circuit 3 is a circuit that determines the on period Ton of the switch SW1 based on the input voltage Vin and the output voltage Vo. When the RS flip-flop 1 is set according to the output signal of the comparator ErrComp and the PWM signal becomes H level, the on-period generation circuit 3 causes the RS flip-flop 1 after the on-period Ton based on the input voltage Vin and the output voltage Vo elapses. To reset the PWM signal to L level. The on / off periods of the switches SW1 and SW2 are assigned within a predetermined period so that the output voltage Vo approaches the set voltage by the PWM signal.

  The PWM signal is input to an AST (Anti-Shoot-Through) circuit 2. The AST circuit 2 is a driver having a function of preventing the switches SW1 and SW2 from being turned on at the same time. The AST circuit 2 drives the switches SW1 and SW2 based on the PWM signal. The switch SW1 is, for example, a P channel MOSFET. The switch SW2 that performs the synchronous rectification operation is, for example, an N-channel MOSFET.

  With the above configuration, the switches SW1 and SW2 are alternately turned on, and a current flows through the coil L via the switches SW1 and SW2. The output capacitor Co smoothes the output voltage Vo together with the coil L. Thereby, the input voltage Vin is stepped down and the output voltage Vo is generated.

  In order to prevent oscillation in the DCDC converter of FIG. 1, the phase of the ripple of the output voltage Vo and the phase of the coil current IL flowing through the coil L are matched. On the other hand, a ceramic capacitor having a small ESR (equivalent series resistance) is increasingly used as the output capacitor Co for reasons such as low cost.

  When the ESR of the output capacitor Co is small, the ripple of the output voltage Vo is delayed by 90 ° from the coil current IL, and oscillation tends to occur. In the DCDC converter of FIG. 1, a slope voltage Vs having a fixed magnitude is added to the constant voltage V1, and the phases are matched in a pseudo manner.

WO2005 / 046036 JP 2006-141191 A US Pat. No. 6,828,766

  When suppressing the oscillation of the DCDC converter, the regulation (voltage fluctuation rate) of the output voltage is deteriorated due to the loss due to the load current, the influence of the input voltage, and the output voltage.

  An object of the present application is to provide a power supply control circuit and an electronic device that can improve regulation of output voltage.

  A power supply control circuit disclosed in the present application includes a switching control unit that controls on / off of a switch based on a difference between a feedback voltage corresponding to an output voltage of the power supply and a first reference voltage, a second reference voltage, and the feedback An amplifier that outputs a current corresponding to a difference from the voltage; a first resistor through which the output current of the amplifier flows; and a first capacitor that is charged by the output current of the amplifier; and the voltage of the first resistor; The first reference voltage is generated based on the voltage of the first capacitor.

  According to the disclosed power supply control circuit and electronic device, the regulation of the output voltage can be improved by feedback from the amplifier.

It is a circuit block diagram which shows a prior art example. It is a circuit block diagram of a 1st embodiment. It is a circuit block diagram of a 2nd embodiment. It is a circuit block diagram of a 3rd embodiment. It is a circuit block diagram of a 4th embodiment. It is a figure which shows the effect by AC coupling. It is FIG. (1) explaining the effect by comparator Comp1. It is FIG. (2) explaining the effect by comparator Comp1.

  FIG. 2 is a circuit block diagram of the first embodiment. 2, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. In the amplifier AMP, the feedback voltage Fb is input to the inverting input terminal, and the reference voltage VREF is input to the non-inverting input terminal. The output signal of the amplifier AMP is input to the gate of the transistor M3. The resistor RS is connected to the source of the transistor M3. The transistors M1 and M2 constitute a current mirror circuit, and a charging current having the same value or a predetermined multiple as the current flowing through the transistor M3 is supplied to the capacitor Cs via the resistor RD. The above configuration surrounded by a broken line in FIG. 2 functions as a gm amplifier (transconductance amplifier) that outputs a current corresponding to the difference between the reference voltage VREF and the feedback voltage Fb.

  The transistor M4 has a gate to which the PWM signal output from the RS flip-flop 1 is input, and switches charging / discharging of the capacitor Cs based on the PWM signal. Thereby, the capacitor Cs is discharged during the period when the PWM signal is at the H level, that is, during the ON period Ton of the switch SW1, and during the period when the PWM signal is at the L level, that is, during the OFF period Toff of the switch SW1. Charged. The voltage at one end of the resistor RD is input to the non-inverting input terminal of the comparator ErrComp as the internal reference voltage intref. That is, the voltage obtained by adding the offset voltage generated by the output current of the gm amplifier and the resistor RD and the slope voltage based on the charging voltage of the capacitor Cs is used as the internal reference voltage intref at the non-inverting input terminal of the comparator ErrComp. Entered.

As described above, in the first embodiment, voltages corresponding to the constant voltage V1 and the slope voltage Vs in the conventional example of FIG. 1 are simultaneously generated by the gm amplifier that receives the reference voltage VREF and the feedback voltage Fb. In the first embodiment of FIG. 2, the feedback voltage Fb is
Fb = ((RD / RS) + (Toff / RS · Cs)) (VREF−Fb)
Than,
Fb = (RD + Toff / Cs) VREF / (RS + RD + Toff / Cs)
It becomes. Here, RD is a resistance value of the resistor RD, RS is a resistance value of the resistor RS, Cs is a capacitance value of the capacitor Cs, and Toff is an OFF period of the switch SW1. Therefore, regulation is possible by the mutual conductance gm (in this case, 1 / RS) of the gm amplifier surrounded by a broken line, and the regulation of the output voltage Vo can be improved.

  FIG. 3 is a circuit block diagram of the second embodiment. In addition to the configuration of the first embodiment, the second embodiment includes a current mirror circuit including a transistor M5, a current source Ic1, and a current source Is. The current I1 flowing through the transistor M2 and the current from the current source Ic1 flow through the resistor RD, and an offset voltage is generated. Further, the current I2 flowing through the transistor M5 and the current of the current source Is flow through the capacitor Cs, and a slope voltage is generated. The offset voltage and the slope voltage are added by an adder to obtain an internal reference voltage intref. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

  In the second embodiment, the offset voltage and the slope voltage are added by an adder to obtain the internal reference voltage intref, so that flexibility with respect to the offset voltage and the slope voltage can be provided. For example, by changing the ratio of the current flowing through the resistor RD and the current flowing through the capacitor Cs, the range of combinations of element values of the resistor RD and the capacitor Cs is expanded. Thereby, for example, it is possible to prevent the capacitance value of the capacitor Cs from becoming too large or too small in order to obtain a slope voltage having a desired magnitude.

  In the second embodiment, the minimum value of the offset voltage can be set by flowing the current of the current source Ic1 through the resistor RD. Thereby, the delay due to the responsiveness of the gm amplifier can be reduced. For example, when it takes 10 μs for the internal reference voltage intref to change from 0V to 1V, the minimum value of the offset voltage is set to 0.5V. As a result, the time required for setting the internal reference voltage intref to 1V can be reduced to the time required for the internal reference voltage intref to change from 0.5V to 1V (for example, 5 μs).

  FIG. 4 is a circuit block diagram of the third embodiment. In the third embodiment of FIG. 4, the overall configuration of the DCDC converter is the same as that of the first and second embodiments, so illustration is omitted, and parts corresponding to those of the first and second embodiments are denoted by the same reference numerals. The description is omitted.

  In the third embodiment, the capacitor Cs is connected between one end of the resistor RD and the output terminal of the internal reference voltage intref. The current of the current source Ic1 flows from the resistor RP to the resistor RD. In addition to the current flowing through the transistor M2 and the current from the current source Ic1, the current from the current source Ic2 flows through the resistor RD. In addition to the current flowing through the transistor M5 and the current from the current source Is, the current from the current source Ic3 flows through the capacitor Cs. In the comparator Comp1, the voltage Vth at one end of the resistor RP is input to the inverting input terminal, and the internal reference voltage intref is input to the non-inverting input terminal. The switch SW3 that connects both ends of the capacitor Cs corresponds to the transistor M4 in the first and second embodiments, and is ON / OFF controlled by the PWM signal and the output signal of the comparator Comp1.

  Here, the current of the current source Ic1 is a constant current. The current of the current source Ic2 is a current that is inversely proportional to the AC component of the output voltage Vo. The current of the current source Is is a current for adjusting the slope voltage. The current of the current source Ic3 is a current that is inversely proportional to the AC component of the output voltage Vo. The resistor RP is a resistor for generating the voltage Vth that sets the maximum value of the slope voltage based on the charging voltage of the capacitor Cs. The comparator Comp1 is a comparator for turning on the switch SW3 and discharging the capacitor Cs when the slope voltage reaches the voltage Vth.

  The third embodiment includes current sources Ic2 and Ic3 that flow a current inversely proportional to the AC component of the output voltage Vo. Here, the feedback voltage Fb is generated by dividing the output voltage Vo by the resistors R1 and R2. However, when a sudden load change occurs, the fluctuation value of the output voltage Vo is also divided and transmitted to the feedback voltage Fb. Responsiveness deteriorates. With the configuration in which the current sources Ic2 and Ic3 add a current that is inversely proportional to the AC component of the output voltage Vo, the third embodiment behaves so that the internal reference voltage intref is inversely proportional to the output voltage Vo. Therefore, the output response from the feedback voltage Fb side is compensated by the internal reference voltage intref, so that the load response can be improved.

  In the third embodiment, the comparator Comp1 is provided that compares the voltage Vth at one end of the resistor RP inserted between the current source Ic1 and the resistor RD with the internal reference voltage intref. When the slope voltage of the internal reference voltage intref reaches the voltage Vth, the capacitor Cs is discharged by the comparator Comp1. Thereby, an increase in overshoot of the output voltage Vo due to overcompensation of the slope voltage can be suppressed.

  FIG. 5 is a circuit block of the fourth embodiment. The fourth embodiment is an embodiment in which the current sources Ic2 and Ic3 that flow a current inversely proportional to the AC component of the output voltage Vo in the third embodiment are specifically realized. The fourth embodiment includes a capacitor Cc to which the output voltage Vo is applied at one end and the other end is connected to the gates of the transistors M1, M2, and M5. Thus, by coupling the output voltage Vo with the capacitor Cc, the gates of the transistors M2 and M5 fluctuate in an AC manner, and a current that is inversely proportional to the output voltage Vo can flow. Other configurations are the same as those of the third embodiment, and thus the description thereof is omitted.

  FIG. 6 is a diagram showing the effect of AC coupling, where the input voltage Vin is 3.6 [V], the output voltage Vo is 1.2 [V], the inductance of the coil L is 1.5 [μH], and the output A simulation result when the capacitance value of the capacitor Co is set to 10 [μF] is shown. When the load current suddenly changes from 0 [mA] to 500 [mA], the undershoot of the output voltage Vo is 18.5 [mV] with AC coupling (solid line), and 21. 5 [mV], which is an improvement of 3 [mV]. The overshoot of the output voltage Vo when the load current suddenly changes from 500 [mA] to 0 [mA] is 29.5 [mV] with AC coupling (solid line), and 34. 7 [mV], which is an improvement of 5.2 [mV]. Also, convergence is better with AC coupling (solid line). Thus, the responsiveness at the time of sudden load change can be improved by the AC coupling in the fourth embodiment.

  7 and 8 are diagrams for explaining the effect of the comparator Comp1, in which the input voltage Vin is 3.6 [V], the output voltage Vo is 1.2 [V], and the inductance of the coil L is 1.5 [μH. ] Shows a simulation result when the capacitance value of the output capacitor Co is set to 10 [μF]. FIG. 7 shows a case where the comparator Comp1 is not provided, and FIG. 8 shows a case where the comparator Comp1 is provided. 7 and 8, the coil end voltage is a voltage at a connection point between the switch SW1 and the coil L.

  As shown in FIG. 7, in the absence of the comparator Comp1, the internal reference voltage intref changes between the feedback voltage Fb and the voltage ref at one end of the resistor RD. When the load current suddenly changes from 500 [mA] to 0 [mA] at time 110 [μs], the coil end voltage becomes H level from time 110 [μs] to 112 [μs], and there is a period during which the coil current is supplied. Exists. From this, it can be seen that when the load current is suddenly reduced without the comparator Comp1, the switch SW1 is turned on due to the overcompensation of the slope voltage, and an extra current is supplied.

  On the other hand, as shown in FIG. 8, when the comparator Comp1 is provided, the internal reference voltage intref is between the smaller one of the feedback voltage Fb and the voltage Vth at one end of the resistor RP and the voltage ref at one end of the resistor RD. It changes with. When the load current suddenly changes from 500 [mA] to 0 [mA] at time 110 [μs], there is a period in which the output signal of the comparator Comp1 becomes H level from time 110 [μs] to 111.5 [μs]. From this, it can be seen that when the load current decreases rapidly when the comparator Comp1 is present, the internal reference voltage intref reaches the voltage Vth at one end of the resistor RP, and the switch SW1 is not turned on.

  As a result, the overshoot of the output voltage Vo is 29.5 [mV] in the absence of the comparator Comp1 (FIG. 7), whereas it is 21.8 [mV in the presence of the comparator Comp1 (FIG. 8). ], Which is an improvement of about 8 [mV]. Thus, in the third and fourth embodiments, by including the comparator Comp1 that compares the voltage Vth at one end of the resistor RP inserted between the current source Ic1 and the resistor RD and the internal reference voltage intref, An increase in overshoot of the output voltage Vo due to the overcompensation of the slope voltage can be suppressed.

  As described above in detail, according to the first to fourth embodiments, feedback control is performed by the gm amplifier. This improves the regulation of the output voltage Vo, because the internal reference voltage intref is adjusted so that the feedback voltage Fb = the reference voltage VREF even if there is a loss due to the load current or a duty fluctuation due to the input voltage Vin and the output voltage Vo. be able to.

  Further, as is often done in the past, when the output voltage Vo is divided by a resistor to generate the feedback voltage Fb, if a sudden load change occurs, the fluctuation value of the output voltage Vo is also divided and transmitted to the feedback voltage Fb. There was a problem that load responsiveness deteriorated. In contrast, in the fourth embodiment, the output voltage Vo is coupled to the gates of the transistors M1, M2, and M5 by the capacitor Cc. Thereby, the internal reference voltage intref moves so as to be inversely proportional to the output voltage Vo, output fluctuation from the feedback voltage Fb side is compensated by the internal reference voltage intref, and load response can be improved.

  Needless to say, the present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the spirit of the present invention.

For example, the configuration of the DCDC converter is not limited to the above embodiment.
The on-period generating circuit 3 is a circuit that determines the on-period Ton of the switch SW1 based on the input voltage Vin and the output voltage Vo. However, a fixed on-period Ton may be generated. The RS flip-flop 1 may be set or reset at a fixed frequency based on the clock signal instead of the on period generation circuit 3.

  An error amplifier may be provided in front of the gm amplifier, and the feedback voltage Fb may be input to the gm amplifier via the error amplifier. Thereby, accuracy can be further improved and regulation can be further improved.

  In addition, it goes without saying that the embodiments may be appropriately combined and used.

  Moreover, you may comprise an electronic device provided with the DCDC converter mentioned above, the battery which supplies the input voltage Vin, and the system which is supplied with the output voltage Vo and operate | moves.

  Note that the comparator ErrComp is an example of a first comparator, the flip-flop 1, the AST circuit 2, the on-period generation circuit 3 is an example of a switching control unit, the resistor RD is an example of a first resistor, the capacitor Cs is an example of a first capacitor, The source Ic2 is an example of a first current source, the current source Ic3 is an example of a second current source, the amplifier AMP is an example of an amplifier, the transistor M3 is an example of a first transistor, the resistor RS is an example of a second resistor, and the transistors M1, M2 , M5 is an example of a current mirror circuit, the capacitor Cc is an example of a second capacitor, and the comparator Comp1 is an example of a second comparator.

  The feedback voltage Fb is an example of a feedback voltage, the internal reference voltage intref is an example of a first reference voltage, the reference voltage VREF is an example of a second reference voltage, and the voltage Vth is an example of a threshold voltage.

DESCRIPTION OF SYMBOLS 1 RS flip-flop 2 AST circuit 3 ON period generation circuit AMP amplifier Cc, Cs capacitor Co Output capacitor Comp1, ErrComp Comparator L Coil M1-M5 Transistors R1, R2, RS, RD, RP Resistor SW1, SW2, SW3 Switch

Claims (6)

A power supply control circuit,
A switching control unit that controls on / off of the switch based on a difference between a feedback voltage corresponding to an output voltage of the power source and a first reference voltage;
An amplifier that outputs a current according to a difference between the second reference voltage and the feedback voltage;
A first resistor through which an output current of the amplifier flows;
A first capacitor charged by the output current of the amplifier;
With
The control circuit, wherein the first reference voltage is generated based on a voltage of the first resistor and a voltage of the first capacitor. A first current source for causing a current that is inversely proportional to the AC component of the output voltage of the power source to flow through the first resistor;
A second current source for causing a current that is inversely proportional to the AC component of the output voltage of the power source to flow through the first capacitor;
The control circuit according to claim 1, further comprising: The amplifier is
An amplifier in which the second reference voltage is input to a non-inverting input terminal and the feedback voltage is input to an inverting input terminal;
A first transistor whose gate voltage is controlled by the output of the amplifier;
A second resistor connected to the source of the first transistor;
A current mirror circuit for causing a mirror current of a current flowing through the first transistor to flow through the first resistor and the first capacitor;
Including
The first current source and the second current source are:
The control circuit according to claim 2, wherein an output voltage of the power source is applied to one end, and the other end is realized by a second capacitor connected to a gate of a transistor constituting the current mirror circuit. The switching controller is
A flip-flop set by an output signal of a first comparator for comparing the feedback voltage with the first reference voltage;
An on-period generation circuit that resets the flip-flop after a predetermined on-period has elapsed since the output pulse of the flip-flop rises;
A drive circuit for driving the switch based on an output pulse of the flip-flop;
With
Wherein the first capacitor, the control circuit according to any one of claims 1 to 3, characterized in that switches charging and discharging in accordance with the output pulse of the flip-flop. A second comparator for comparing the first reference voltage and a threshold voltage;
The control circuit according to claim 4, wherein charging and discharging of the first capacitor is switched according to an output pulse of the flip-flop and an output signal of the second comparator. An electronic device including a power supply, a system to which an output voltage of the power supply is supplied, and a control circuit for the power supply,
The control circuit includes:
A switching control unit that controls on / off of the switch based on a difference between a feedback voltage corresponding to an output voltage of the power source and a first reference voltage;
An amplifier that outputs a current according to a difference between the second reference voltage and the feedback voltage;
A first resistor through which an output current of the amplifier flows;
A first capacitor charged by the output current of the amplifier;
With
The electronic device, wherein the first reference voltage is generated based on a voltage of the first resistor and a voltage of the first capacitor.

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