JP2007158007A - Monocrystal silicon electrode plate for plasma etching with little in-plane variation of specific resistance value - Google Patents

Monocrystal silicon electrode plate for plasma etching with little in-plane variation of specific resistance value Download PDF

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JP2007158007A
JP2007158007A JP2005350927A JP2005350927A JP2007158007A JP 2007158007 A JP2007158007 A JP 2007158007A JP 2005350927 A JP2005350927 A JP 2005350927A JP 2005350927 A JP2005350927 A JP 2005350927A JP 2007158007 A JP2007158007 A JP 2007158007A
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crystal silicon
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JP4535283B2 (en
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Takashi Yonehisa
孝志 米久
Takafumi Iwamoto
尚文 岩元
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Mitsubishi Materials Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a monocrystal silicon electrode plate for plasma etching with little in-plane variation of a specific resistance value, wherein a wafer surface is uniformly etched without variations thereby. <P>SOLUTION: In the monocrystal silicon electrode plate for plasma etching, the in-plane variations of the specific resistance value is within 5%. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は、比抵抗値の面内バラツキが少ないプラズマエッチング用単結晶シリコン電極板に関するものであり、この比抵抗値の面内バラツキが少ない単結晶シリコン電極板を使用すると、ウエハ表面をバラツキなく均一にエッチングすることができる。   The present invention relates to a single-crystal silicon electrode plate for plasma etching that has a small in-plane variation in specific resistance value, and when a single-crystal silicon electrode plate with a small in-plane variation in specific resistance value is used, the wafer surface does not vary. It can etch uniformly.

一般に、半導体集積回路を製造する工程において使用するウエハをエッチングするためのプラズマエッチング装置は、図１に示されるように、真空容器１内にシリコン電極板２および架台３が間隔をおいて設けられており、架台３の上にウエハ４を載置し、エッチングガス７をシリコン電極板２に設けられた貫通細孔５を通してウエハ４に向って流しながら高周波電源６により電極板２と架台３の間に高周波電圧を印加し、高周波電圧の印加によりシリコン電極板２と架台３の間の空間にプラズマ１０を発生させ、このプラズマ１０による物理反応と、シリコン−エッチングガス７による化学反応により、ウエハ４の表面をエッチングする装置であることは知られている。   In general, in a plasma etching apparatus for etching a wafer used in a process of manufacturing a semiconductor integrated circuit, as shown in FIG. 1, a silicon electrode plate 2 and a pedestal 3 are provided in a vacuum container 1 at intervals. The wafer 4 is placed on the gantry 3, and the etching gas 7 flows through the through-hole 5 provided in the silicon electrode plate 2 toward the wafer 4 while the electrode plate 2 and the gantry 3 are A high frequency voltage is applied between them, plasma 10 is generated in the space between the silicon electrode plate 2 and the gantry 3 by the application of the high frequency voltage, and the wafer undergoes a physical reaction by the plasma 10 and a chemical reaction by the silicon-etching gas 7. It is known that this is an apparatus for etching the surface of 4.

シリコン電極板２としては、単結晶シリコン電極板、多結晶シリコン電極板、柱状晶シリコン電極板などが知られているが、現在ではＣＺ法により引き上げられた単結晶シリコンインゴットを輪切り状に切断したのち表面研磨して作製した単結晶シリコン電極板が主に使用されている。（特許文献１参照）。
特開２００３−５１４８５号公報 As the silicon electrode plate 2, a single crystal silicon electrode plate, a polycrystalline silicon electrode plate, a columnar crystal silicon electrode plate, and the like are known, but at present, a single crystal silicon ingot pulled up by the CZ method is cut into a ring shape. After that, single crystal silicon electrode plates produced by surface polishing are mainly used. (See Patent Document 1).
JP 2003-51485 A

従来の単結晶シリコン電極板を使用してウエハのプラズマエッチングを行うと
被エッチング物であるウエハの中心部と周辺部とでエッチングレートにバラツキが生じるなどウエハ表面の位置によってエッチングレートにバラツキが生じ、ウエハの均一なプラズマエッチングができないことがあった。特に、近年、高純度で比抵抗の高い比抵抗値が：１０〜１００×１０−２Ω・ｍを有する単結晶シリコン電極板を使用されるようになり、この比抵抗の高い単結晶シリコン電極板ではウエハの表面位置によるエッチングレートのバラツキが大きくなるなどの問題点があった。 When plasma etching of a wafer is performed using a conventional single crystal silicon electrode plate, the etching rate varies depending on the position of the wafer surface, for example, the etching rate varies between the central portion and the peripheral portion of the wafer to be etched. In some cases, uniform plasma etching of the wafer could not be performed. In particular, in recent years, a single crystal silicon electrode plate having a high purity and high specific resistance value of 10 to 100 × 10 −2 Ω · m has come to be used. There is a problem that the plate has a large variation in etching rate depending on the surface position of the wafer.

そこで、本発明者等は、プラズマエッチングに際してウエハ表面のエッチングレートのバラツキが少ない単結晶シリコン電極板を得るべく研究を行った。その結果、
（イ）プラズマエッチングに際して使用する単結晶シリコン電極板の比抵抗値の面内バラツキが被エッチング物であるウエハ表面のエッチングレートのバラツキに大きく影響を及ぼし、単結晶シリコン電極板の比抵抗値の面内バラツキが少ないほどウエハ表面のエッチングレートのバラツキが少なくなる、
（ロ）従来の単結晶シリコン電極板における比抵抗値の面内バラツキは１０％程度であったが、比抵抗値の面内バラツキを５％以下にすると、ウエハ表面のエッチングレートのバラツキが格段に少なくなる、
（ハ）ウエハ表面のエッチングレートのバラツキに及ぼす影響は比抵抗値が高い単結晶シリコン電極板で大きくなり、特に比抵抗値が１０〜１００×１０−２Ω・ｍの比抵抗値が高い単結晶シリコン電極板に対して大きく影響を及ぼす、などの研究結果が得られたのである。 Therefore, the present inventors conducted research to obtain a single crystal silicon electrode plate with less variation in the etching rate of the wafer surface during plasma etching. as a result,
(A) In-plane variation of the specific resistance value of the single crystal silicon electrode plate used for plasma etching greatly affects the variation of the etching rate of the wafer surface to be etched, and the specific resistance value of the single crystal silicon electrode plate The smaller the in-plane variation, the less the variation in the etching rate on the wafer surface.
(B) The in-plane variation of the specific resistance value in the conventional single crystal silicon electrode plate was about 10%. However, when the in-plane variation of the specific resistance value is 5% or less, the variation in the etching rate on the wafer surface is marked. To be less,
(C) The influence on the variation in the etching rate on the wafer surface is greater with a single crystal silicon electrode plate having a high specific resistance value. In particular, the single resistance value with a high specific resistance value of 10 to 100 × 10 −2 Ω · m is high. Research results, such as having a great influence on the crystalline silicon electrode plate, were obtained.

この発明は、かかる研究結果に基づいてなされたものであって、
（１）比抵抗値の面内バラツキが５％以内であるプラズマエッチング用単結晶シリコン電極板、
（２）前記単結晶シリコン電極板は比抵抗値が１０〜１００×１０−２Ω・ｍの高抵抗を有する前記（１）記載のプラズマエッチング用単結晶シリコン電極板、に特長を有するものである。 The present invention has been made based on the results of such research,
(1) A single-crystal silicon electrode plate for plasma etching whose in-plane variation of specific resistance value is within 5%,
(2) The single crystal silicon electrode plate is characterized by the single crystal silicon electrode plate for plasma etching according to the above (1), which has a high resistivity of 10 to 100 × 10 −2 Ω · m. is there.

この発明の比抵抗値の面内バラツキが５％以内であるプラズマエッチング用単結晶シリコン電極板を製造するには、先ず、所望の径よりも大きな単結晶シリコンインゴットを通常のＣＺ法により作製し、この所望の径よりも大きな単結晶シリコンインゴットを輪切りに切断して単結晶シリコン基板を作製し、得られた単結晶シリコン基板の外周を通常よりも厚く研削することにより作製することができる。   In order to manufacture a single-crystal silicon electrode plate for plasma etching having an in-plane variation of the specific resistance value within 5% according to the present invention, first, a single-crystal silicon ingot larger than a desired diameter is manufactured by a normal CZ method. The single crystal silicon ingot larger than the desired diameter can be cut into round pieces to produce a single crystal silicon substrate, and the resulting single crystal silicon substrate can be produced by grinding the outer periphery thicker than usual.

この輪切りにした単結晶シリコン基板の外周を通常よりも厚く研削する理由は、一般に、ＣＺ法により引き上げられた単結晶シリコンインゴットは外周部ほど純度が高く、中心部に近いほど純度が低くなっているところから、中心部と外周部との比抵抗値の差が大きくなっているが、単結晶シリコン基板の外周を通常よりも厚く研削することにより中心部と外周部との純度を均等にし、中心部と外周部との比抵抗値の差を小さくして面内バラツキを小さくするという理由によるものである。   The reason for grinding the outer periphery of the single crystal silicon substrate cut into a thicker thickness than usual is that the single crystal silicon ingot pulled up by the CZ method is generally higher in purity at the outer periphery and lower in purity as it is closer to the center. From there, the difference in specific resistance value between the central portion and the outer peripheral portion is large, but by grinding the outer periphery of the single crystal silicon substrate thicker than usual, the purity of the central portion and the outer peripheral portion is made uniform, This is because the in-plane variation is reduced by reducing the difference in specific resistance value between the central portion and the outer peripheral portion.

従来の単結晶シリコン電極板は、単結晶シリコンインゴットを輪切りに切断して得られた単結晶シリコン基板の外周を薄く研削して作製しているために比抵抗値の面内バラツキは１０％程度になっていたが、前述のように径の大きな単結晶シリコンインゴットを輪切りに切断した単結晶シリコン基板の外周を通常より厚く研削することにより比抵抗値の面内バラツキが５％以内であるこの発明のプラズマエッチング用単結晶シリコン電極板を製造することができる。   Since the conventional single crystal silicon electrode plate is manufactured by thinly grinding the outer periphery of a single crystal silicon substrate obtained by cutting a single crystal silicon ingot into round pieces, the in-plane variation of the specific resistance value is about 10%. However, as described above, the in-plane variation of the specific resistance value is within 5% by grinding the outer periphery of the single crystal silicon substrate obtained by cutting the single crystal silicon ingot having a large diameter into round pieces as described above. The single crystal silicon electrode plate for plasma etching of the invention can be manufactured.

なお、比抵抗値の面内バラツキが５％以内であるプラズマエッチング用単結晶シリコン電極板を製造する方法として、ＣＺ法による引き上げ速度や回転数を制御して中心部と外周部の不純物の含有量が均等に含まれる単結晶シリコンインゴットを作製し、この単結晶シリコンインゴットを輪切りにして作製することもできる。   In addition, as a method for producing a single-crystal silicon electrode plate for plasma etching whose in-plane variation of specific resistance value is within 5%, inclusion of impurities in the central portion and the outer peripheral portion by controlling the pulling speed and the rotational speed by the CZ method It is also possible to produce a single crystal silicon ingot containing the same amount, and to produce the single crystal silicon ingot by slicing it.

この発明のプラズマエッチング用単結晶シリコン電極板は、ウエハのプラズマエッチングレートを均一化し、不良品が発生することなく半導体集積回路を効率良く生産することができ、半導体装置産業の発展に大いに貢献しうるものである。   The single-crystal silicon electrode plate for plasma etching according to the present invention makes the plasma etching rate of the wafer uniform and enables efficient production of semiconductor integrated circuits without causing defective products, greatly contributing to the development of the semiconductor device industry. It can be.

この発明のプラズマエッチング用単結晶シリコン電極板を実施例に基づいて具体的に説明する。
実施例１
ＣＺ法により引き上げることにより直径：４５０ｍｍの単結晶シリコンインゴットを作製し、この単結晶シリコンインゴットをダイヤモンドバンドソーにより厚さ：５ｍｍに輪切り切断し、外周を厚さ：７５ｍｍに渡って研削することにより直径：３００ｍｍを有する単結晶シリコン基板を作製した。この単結晶シリコン基板の中心における比抵抗値Ｘを測定してその結果を表１に示し、さらに単結晶シリコン基板の外周から半径方向に１０ｍｍの任意の地点における比抵抗値を複数個所測定し、その内の最大比抵抗値Ｙを表１に示し、前記ＸおよびＹの値から（Ｙ−Ｘ）／Ｙ×１００（％）の式にしたがって比抵抗値の面内バラツキを求めたところ、比抵抗値の面内バラツキは２％であった。 The single-crystal silicon electrode plate for plasma etching according to the present invention will be specifically described based on examples.
Example 1
A single crystal silicon ingot having a diameter of 450 mm is produced by pulling up by the CZ method, this single crystal silicon ingot is cut into a ring of 5 mm in thickness with a diamond band saw, and the outer periphery is ground to a thickness of 75 mm. A single crystal silicon substrate having a thickness of 300 mm was prepared. The specific resistance value X at the center of the single crystal silicon substrate was measured and the results are shown in Table 1. Further, the specific resistance values at arbitrary points 10 mm in the radial direction from the outer periphery of the single crystal silicon substrate were measured at a plurality of locations. The maximum specific resistance value Y among them is shown in Table 1, and when the in-plane variation of the specific resistance value is obtained from the X and Y values according to the formula of (Y−X) / Y × 100 (%), The in-plane variation of the resistance value was 2%.

得られた単結晶シリコン基板に内径０．５ｍｍの貫通細孔をダイヤモンドドリルを用いて孔間ピッチ８ｍｍで直径：２００ｍｍの範囲内に形成し、本発明プラズマエッチング用単結晶シリコン電極板（以下、本発明電極板という）１を作製した。   Through-holes having an inner diameter of 0.5 mm were formed in the obtained single crystal silicon substrate within a range of diameter: 200 mm with a pitch between holes of 8 mm using a diamond drill. 1) was prepared.

このようにして作製した本発明電極板を１をエッチング装置にセットし、予めＣＶＤによりＳｉＯ2 層を形成したウエハをエッチング装置にセットし、
チャンバー内圧力：１０-1Ｔｏｒｒ、
エッチングガス組成：９０sccmＣＨＦ3 ＋４sccmＯ2 ＋１５０sccmＨｅ、
高周波電力：２ｋＷ、
周波数：２０ｋＨｚ、
の条件で、ウエハ表面のＳｉＯ2 層のプラズマエッチングを行ない、エッチング開始から１０分間経過した時点および４００時間経過した時点でのウエハ表面のＳｉＯ2 層の中心部のエッチングの深ｘさおよび周辺部のエッチングの深さｙをそれぞれ測定し、その測定値から（ｙ−ｘ）／ｙ×１００（％）の値を求め、その結果を表１に示してウエハ表面のエッチング均一性を評価した。
実施例２
ＣＺ法により引き上げることにより直径：４２０ｍｍの単結晶シリコンインゴットを作製し、この単結晶シリコンインゴットをダイヤモンドバンドソーにより厚さ：５ｍｍに輪切り切断し、外周を厚さ：６０ｍｍに渡って研削することにより直径：３００ｍｍを有する単結晶シリコン基板を作製した。この単結晶シリコン基板の中心における比抵抗値Ｘを測定してその結果を表１に示し、さらに単結晶シリコン基板の外周から半径方向に１０ｍｍの任意の地点における比抵抗値を複数個所測定し、その内の最大比抵抗値Ｙを表１に示し、前記ＸおよびＹの値から（Ｙ−Ｘ）／Ｙ×１００（％）の式にしたがって比抵抗値の面内バラツキを求めたところ、比抵抗値の面内バラツキは３％であった。 The electrode plate 1 of the present invention thus produced was set in an etching apparatus, a wafer on which a SiO 2 layer was previously formed by CVD was set in an etching apparatus,
Chamber internal pressure: 10 −1 Torr,
Etching gas composition: 90 sccm CHF 3 +4 sccm O 2 +150 sccm He,
High frequency power: 2kW
Frequency: 20kHz,
Under these conditions, plasma etching of the SiO 2 layer on the wafer surface is performed, and the etching depth x depth at the central portion of the SiO 2 layer on the wafer surface and the peripheral portion at the time when 10 minutes have elapsed and 400 hours have elapsed since the start of etching. Each etching depth y was measured, and a value of (y−x) / y × 100 (%) was obtained from the measured value. The results are shown in Table 1, and the etching uniformity on the wafer surface was evaluated.
Example 2
A single crystal silicon ingot having a diameter of 420 mm is produced by pulling up by the CZ method, the single crystal silicon ingot is cut into a ring of 5 mm in thickness with a diamond band saw, and the outer periphery is ground to a thickness of 60 mm. A single crystal silicon substrate having a thickness of 300 mm was prepared. The specific resistance value X at the center of the single crystal silicon substrate was measured and the results are shown in Table 1. Further, the specific resistance values at arbitrary points 10 mm in the radial direction from the outer periphery of the single crystal silicon substrate were measured at a plurality of locations. The maximum specific resistance value Y among them is shown in Table 1, and when the in-plane variation of the specific resistance value is obtained from the X and Y values according to the formula of (Y−X) / Y × 100 (%), The in-plane variation of the resistance value was 3%.

得られた単結晶シリコン基板に内径０．５ｍｍの貫通細孔をダイヤモンドドリルを用いて孔間ピッチ８ｍｍで直径：２００ｍｍの範囲内に形成し、本発明電極板２を作製した。   Through-holes having an inner diameter of 0.5 mm were formed in the obtained single crystal silicon substrate within a range of diameter: 200 mm with a pitch between holes of 8 mm using a diamond drill, thereby producing the electrode plate 2 of the present invention.

このようにして作製した本発明電極板２をエッチング装置にセットし、さらに予めＣＶＤによりＳｉＯ2 層を形成したウエハをエッチング装置にセットし、実施例１と同じ条件でウエハ表面のＳｉＯ2 層のプラズマエッチングを行ない、エッチング開始から１０分間経過した時点および４００時間経過した時点でのウエハ表面のＳｉＯ2 層の中心部のエッチングの深ｘさおよび周辺部のエッチングの深さｙをそれぞれ測定し、その測定値から（ｙ−ｘ）／ｙ×１００（％）の値を求め、その結果を表１に示してウエハ表面のエッチング均一性を評価した。
実施例３
ＣＺ法により引き上げることにより直径：４００ｍｍの単結晶シリコンインゴットを作製し、この単結晶シリコンインゴットをダイヤモンドバンドソーにより厚さ：５ｍｍに輪切り切断し、外周を厚さ：５０ｍｍに渡って研削することにより直径：３００ｍｍを有する単結晶シリコン基板を作製した。この単結晶シリコン基板の中心における比抵抗値Ｘを測定してその結果を表１に示し、さらに単結晶シリコン基板の外周から半径方向に１０ｍｍの任意の地点における比抵抗値を複数個所測定し、その内の最大比抵抗値Ｙを表１に示し、前記ＸおよびＹの値から（Ｙ−Ｘ）／Ｙ×１００（％）の式にしたがって比抵抗値の面内バラツキを求めたところ、比抵抗値の面内バラツキは４％であった。 Thus the present invention the electrode plate 2 was prepared in the set in an etching apparatus, further in advance by CVD sets the wafer to form a SiO 2 layer to the etching apparatus, the SiO 2 layer on the wafer surface under the same conditions as in Example 1 Perform plasma etching and measure the etching depth x of the central portion of the SiO 2 layer on the wafer surface and the etching depth y of the peripheral portion at the time when 10 minutes have passed and 400 hours have passed since the start of etching, A value of (y−x) / y × 100 (%) was obtained from the measured value, and the result is shown in Table 1 to evaluate the etching uniformity of the wafer surface.
Example 3
A single crystal silicon ingot having a diameter of 400 mm is produced by pulling up by the CZ method, and this single crystal silicon ingot is cut into a ring with a diamond band saw to a thickness of 5 mm and the outer periphery is ground to a thickness of 50 mm to obtain a diameter. A single crystal silicon substrate having a thickness of 300 mm was prepared. The specific resistance value X at the center of the single crystal silicon substrate was measured and the results are shown in Table 1. Further, the specific resistance values at arbitrary points 10 mm in the radial direction from the outer periphery of the single crystal silicon substrate were measured at a plurality of locations. The maximum specific resistance value Y among them is shown in Table 1, and when the in-plane variation of the specific resistance value is obtained from the X and Y values according to the formula of (Y−X) / Y × 100 (%), The in-plane variation of the resistance value was 4%.

得られた単結晶シリコン基板に内径０．５ｍｍの貫通細孔をダイヤモンドドリルを用いて孔間ピッチ８ｍｍで直径：２００ｍｍの範囲内に形成し、本発明電極板３を作製した。   Through-holes having an inner diameter of 0.5 mm were formed in the obtained single crystal silicon substrate within a range of diameter: 200 mm with a pitch between holes of 8 mm using a diamond drill, and the electrode plate 3 of the present invention was produced.

このようにして作製した本発明電極板３をエッチング装置にセットし、さらに予めＣＶＤによりＳｉＯ2 層を形成したウエハをエッチング装置にセットし、実施例１と同じ条件でウエハ表面のＳｉＯ2 層のプラズマエッチングを行ない、エッチング開始から１０分間経過した時点および４００時間経過した時点でのウエハ表面のＳｉＯ2 層の中心部のエッチングの深ｘさおよび周辺部のエッチングの深さｙをそれぞれ測定し、その測定値から（ｙ−ｘ）／ｙ×１００（％）の値を求め、その結果を表１に示してウエハ表面のエッチング均一性を評価した。
実施例４
ＣＺ法により引き上げることにより直径：３８０ｍｍの単結晶シリコンインゴットを作製し、この単結晶シリコンインゴットをダイヤモンドバンドソーにより厚さ：５ｍｍに輪切り切断し、外周を厚さ：４０ｍｍに渡って研削することにより直径：３００ｍｍを有する単結晶シリコン基板を作製した。この単結晶シリコン基板の中心における比抵抗値Ｘを測定してその結果を表１に示し、さらに単結晶シリコン基板の外周から半径方向に１０ｍｍの任意の地点における比抵抗値を複数個所測定し、その内の最大比抵抗値Ｙを表１に示し、前記ＸおよびＹの値から（Ｙ−Ｘ）／Ｙ×１００（％）の式にしたがって比抵抗値の面内バラツキを求めたところ、比抵抗値の面内バラツキは５％であった。 得られた単結晶シリコン基板に内径０．５ｍｍの貫通細孔をダイヤモンドドリルを用いて孔間ピッチ８ｍｍで直径：２００ｍｍの範囲内に形成し、本発明電極板４を作製した。 Thus the present invention the electrode plate 3 prepared in the set in an etching apparatus, further in advance by CVD sets the wafer to form a SiO 2 layer to the etching apparatus, the SiO 2 layer on the wafer surface under the same conditions as in Example 1 Perform plasma etching and measure the etching depth x of the central portion of the SiO 2 layer on the wafer surface and the etching depth y of the peripheral portion at the time when 10 minutes have passed and 400 hours have passed since the start of etching, A value of (y−x) / y × 100 (%) was obtained from the measured value, and the result is shown in Table 1 to evaluate the etching uniformity of the wafer surface.
Example 4
A single crystal silicon ingot having a diameter of 380 mm is produced by pulling it up by the CZ method, and this single crystal silicon ingot is cut by a diamond band saw into a thickness of 5 mm and the outer periphery is ground to a thickness of 40 mm. A single crystal silicon substrate having a thickness of 300 mm was prepared. The specific resistance value X at the center of the single crystal silicon substrate was measured and the results are shown in Table 1. Further, the specific resistance values at arbitrary points 10 mm in the radial direction from the outer periphery of the single crystal silicon substrate were measured at a plurality of locations. The maximum specific resistance value Y among them is shown in Table 1, and when the in-plane variation of the specific resistance value is obtained from the X and Y values according to the formula of (Y−X) / Y × 100 (%), The in-plane variation of the resistance value was 5%. Through-holes having an inner diameter of 0.5 mm were formed in the obtained single crystal silicon substrate within a range of diameter: 200 mm with a pitch between holes of 8 mm using a diamond drill, and the electrode plate 4 of the present invention was produced.

このようにして作製した本発明電極板４をエッチング装置にセットし、さらに予めＣＶＤによりＳｉＯ2 層を形成したウエハをエッチング装置にセットし、実施例１と同じ条件でウエハ表面のＳｉＯ2 層のプラズマエッチングを行ない、エッチング開始から１０分間経過した時点および４００時間経過した時点でのウエハ表面のＳｉＯ2 層の中心部のエッチングの深ｘさおよび周辺部のエッチングの深さｙをそれぞれ測定し、その測定値から（ｙ−ｘ）／ｙ×１００（％）の値を求め、その結果を表１に示してウエハ表面のエッチング均一性を評価した。
比較例
ＣＺ法により引き上げることにより直径：３４０ｍｍの単結晶シリコンインゴットを作製し、この単結晶シリコンインゴットをダイヤモンドバンドソーにより厚さ：５ｍｍに輪切り切断し、外周を厚さ：２０ｍｍに渡って研削することにより直径：３００ｍｍを有する単結晶シリコン基板を作製した。この単結晶シリコン基板の中心における比抵抗値Ｘを測定してその結果を表１に示し、さらに単結晶シリコン基板の外周から半径方向に１０ｍｍの任意の地点における比抵抗値を複数個所測定し、その内の最大比抵抗値Ｙを表１に示し、前記ＸおよびＹの値から（Ｙ−Ｘ）／Ｙ×１００（％）の式にしたがって比抵抗値の面内バラツキを求めたところ、比抵抗値の面内バラツキは７％であった。 Thus the present invention electrode plate 4 was prepared in the set in an etching apparatus, further in advance by CVD sets the wafer to form a SiO 2 layer to the etching apparatus, the SiO 2 layer on the wafer surface under the same conditions as in Example 1 Perform plasma etching and measure the etching depth x of the central portion of the SiO 2 layer on the wafer surface and the etching depth y of the peripheral portion at the time when 10 minutes have passed and 400 hours have passed since the start of etching, A value of (y−x) / y × 100 (%) was obtained from the measured value, and the result is shown in Table 1 to evaluate the etching uniformity of the wafer surface.
Comparative Example A single crystal silicon ingot having a diameter of 340 mm is produced by pulling up by the CZ method, this single crystal silicon ingot is cut into a ring of 5 mm in thickness with a diamond band saw, and the outer periphery is ground over a thickness of 20 mm. Thus, a single crystal silicon substrate having a diameter of 300 mm was manufactured. The specific resistance value X at the center of the single crystal silicon substrate was measured and the results are shown in Table 1. Further, the specific resistance values at arbitrary points 10 mm in the radial direction from the outer periphery of the single crystal silicon substrate were measured at a plurality of locations. The maximum specific resistance value Y among them is shown in Table 1, and when the in-plane variation of the specific resistance value is obtained from the X and Y values according to the formula of (Y−X) / Y × 100 (%), The in-plane variation of the resistance value was 7%.

得られた単結晶シリコン基板に内径０．５ｍｍの貫通細孔をダイヤモンドドリルを用いて孔間ピッチ８ｍｍで直径：２００ｍｍの範囲内に形成し、比較電極板を作製した。   Through-holes having an inner diameter of 0.5 mm were formed in the obtained single crystal silicon substrate within a range of diameter: 200 mm with a pitch between holes of 8 mm using a diamond drill, to prepare a comparative electrode plate.

このようにして作製した比較電極板をエッチング装置にセットし、さらに予めＣＶＤによりＳｉＯ2 層を形成したウエハをエッチング装置にセットし、実施例１と同じ条件でウエハ表面のＳｉＯ2 層のプラズマエッチングを行ない、エッチング開始から１０分間経過した時点および４００時間経過した時点でのウエハ表面のＳｉＯ2 層の中心部のエッチングの深ｘさおよび周辺部のエッチングの深さｙをそれぞれ測定し、その測定値から（ｙ−ｘ）／ｙ×１００（％）の値を求め、その結果を表１に示してウエハ表面のエッチング均一性を評価した。
従来例
ＣＺ法により引き上げることにより直径：３１０ｍｍの単結晶シリコンインゴットを作製し、この単結晶シリコンインゴットをダイヤモンドバンドソーにより厚さ：５ｍｍに輪切り切断し、外周を厚さ：５ｍｍに渡って研削することにより直径：３００ｍｍを有する単結晶シリコン基板を作製した。この単結晶シリコン基板の中心における比抵抗値Ｘを測定してその結果を表１に示し、さらに単結晶シリコン基板の外周から半径方向に１０ｍｍの任意の地点における比抵抗値を複数個所測定し、その内の最大比抵抗値Ｙを表１に示し、前記ＸおよびＹの値から（Ｙ−Ｘ）／Ｙ×１００（％）の式にしたがって比抵抗値の面内バラツキを求めたところ、比抵抗値の面内バラツキは１０％であった。 The thus prepared comparative electrode plate was set in an etching apparatus, and a wafer on which a SiO 2 layer was previously formed by CVD was set in an etching apparatus, and plasma etching of the SiO 2 layer on the wafer surface was performed under the same conditions as in Example 1. And the etching depth x of the central portion of the SiO 2 layer on the wafer surface and the etching depth y of the peripheral portion at the time when 10 minutes have passed and 400 hours have elapsed from the start of etching, respectively. A value of (y−x) / y × 100 (%) was obtained from the value, and the result is shown in Table 1 to evaluate the etching uniformity of the wafer surface.
Conventional Example A single crystal silicon ingot having a diameter of 310 mm is produced by pulling up by the CZ method, and this single crystal silicon ingot is cut into a circle with a diamond band saw to a thickness of 5 mm and the outer periphery is ground over a thickness of 5 mm. Thus, a single crystal silicon substrate having a diameter of 300 mm was manufactured. The specific resistance value X at the center of the single crystal silicon substrate was measured and the results are shown in Table 1. Further, the specific resistance values at arbitrary points 10 mm in the radial direction from the outer periphery of the single crystal silicon substrate were measured at a plurality of locations. The maximum specific resistance value Y among them is shown in Table 1, and when the in-plane variation of the specific resistance value is obtained from the X and Y values according to the formula of (Y−X) / Y × 100 (%), The in-plane variation of the resistance value was 10%.

得られた単結晶シリコン基板に内径０．５ｍｍの貫通細孔をダイヤモンドドリルを用いて孔間ピッチ８ｍｍで直径：２００ｍｍの範囲内に形成し、従来電極板を作製した。   A through-hole having an inner diameter of 0.5 mm was formed in the obtained single crystal silicon substrate using a diamond drill in a range of a hole diameter of 8 mm and a diameter of 200 mm to produce a conventional electrode plate.

このようにして作製した従来電極板をエッチング装置にセットし、さらに予めＣＶＤによりＳｉＯ2 層を形成したウエハをエッチング装置にセットし、実施例１と同じ条件でウエハ表面のＳｉＯ2 層のプラズマエッチングを行ない、エッチング開始から１０分間経過した時点および４００時間経過した時点でのウエハ表面のＳｉＯ2 層の中心部のエッチングの深ｘさおよび周辺部のエッチングの深さｙをそれぞれ測定し、その測定値から（ｙ−ｘ）／ｙ×１００（％）の値を求め、その結果を表１に示してウエハ表面のエッチング均一性を評価した。 The conventional electrode plate thus prepared is set in an etching apparatus, and a wafer on which a SiO 2 layer is formed in advance by CVD is set in an etching apparatus, and plasma etching of the SiO 2 layer on the wafer surface is performed under the same conditions as in Example 1. And the etching depth x of the central portion of the SiO 2 layer on the wafer surface and the etching depth y of the peripheral portion at the time when 10 minutes have passed and 400 hours have elapsed from the start of etching, respectively. A value of (y−x) / y × 100 (%) was obtained from the value, and the result is shown in Table 1 to evaluate the etching uniformity of the wafer surface.

Figure 2007158007
Figure 2007158007

表１に示される結果から、面内バラツキが５％以下の本発明電極板１〜４は、面内バラツキが５％を超える比較電極板および従来電極板に比べて（ｙ−ｘ）／ｙ×１００（％）の値が格段に小さいところからＳｉＯ2 層を均一にプラズマエッチングできることがわかる。 From the results shown in Table 1, the electrode plates 1 to 4 of the present invention having an in-plane variation of 5% or less are (yx) / y compared to the comparative electrode plate and the conventional electrode plate having an in-plane variation of more than 5%. From the fact that the value of × 100 (%) is remarkably small, it can be seen that the SiO 2 layer can be uniformly plasma etched.

従来のプラズマエッチング装置の断面説明図である。It is sectional explanatory drawing of the conventional plasma etching apparatus.

符号の説明Explanation of symbols

１：真空容器、２：電極板、３：架台、４：Ｓｉウエハ、５：貫通細孔、６：高周波電源、７：プラズマエッチングガス、８：下面、９：上面、１０：ブラズマ、
1: vacuum vessel, 2: electrode plate, 3: mount, 4: Si wafer, 5: through-hole, 6: high frequency power supply, 7: plasma etching gas, 8: lower surface, 9: upper surface, 10: plasma,

Claims (2)

比抵抗値の面内バラツキが５％以内であることを特徴とするプラズマエッチング用単結晶シリコン電極板。 A single crystal silicon electrode plate for plasma etching, wherein the in-plane variation in specific resistance value is within 5%. 前記単結晶シリコン電極板は比抵抗値が１０〜１００×１０−２Ω・ｍの高抵抗を有することを特徴とする請求項１記載のプラズマエッチング用単結晶シリコン電極板。

2. The single-crystal silicon electrode plate for plasma etching according to claim 1, wherein the single-crystal silicon electrode plate has a high resistance of 10 to 100 * 10 <-2 > [Omega] .m.

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008159773A (en) * 2006-12-22 2008-07-10 Mitsubishi Materials Corp Composite silicon electrode having small resistivity in in-plane variations and its manufacturing method
DE102013107189A1 (en) 2013-03-22 2014-09-25 Schott Ag Blank of silicon, process for its preparation and use thereof
WO2014147262A1 (en) 2013-03-22 2014-09-25 Schott Ag Blank made of silicon, method for the production thereof and use thereof
DE102013107193A1 (en) 2013-04-08 2014-10-09 Schott Ag Blank of silicon, process for its preparation and use thereof
JP2022016604A (en) * 2014-12-26 2022-01-21 エーサット株式会社 Electrode for plasma etching device

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JPH1017393A (en) * 1996-06-28 1998-01-20 Nisshinbo Ind Inc Plasma etching electrode and its manufacture
JP2004315289A (en) * 2003-04-16 2004-11-11 Shin Etsu Handotai Co Ltd Method for manufacturing single crystal

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1017393A (en) * 1996-06-28 1998-01-20 Nisshinbo Ind Inc Plasma etching electrode and its manufacture
JP2004315289A (en) * 2003-04-16 2004-11-11 Shin Etsu Handotai Co Ltd Method for manufacturing single crystal

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008159773A (en) * 2006-12-22 2008-07-10 Mitsubishi Materials Corp Composite silicon electrode having small resistivity in in-plane variations and its manufacturing method
DE102013107189A1 (en) 2013-03-22 2014-09-25 Schott Ag Blank of silicon, process for its preparation and use thereof
WO2014147262A1 (en) 2013-03-22 2014-09-25 Schott Ag Blank made of silicon, method for the production thereof and use thereof
DE102013107193A1 (en) 2013-04-08 2014-10-09 Schott Ag Blank of silicon, process for its preparation and use thereof
JP2022016604A (en) * 2014-12-26 2022-01-21 エーサット株式会社 Electrode for plasma etching device

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