JP2007157267A - Wobble signal demodulation circuit, recording and reproducing apparatus, and wobble signal demodulation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wobble signal demodulation circuit to provide constant appropriate integration output amplitude. <P>SOLUTION: In a demodulation circuit demodulating a wobble signal obtained from a disk having a meandering track and including a carrier part having the carrier of the prescribed period and a phase modulation wave part in which information is added to the carrier, integrators 71a, 72a integrate the wobble signal synchronizing with a clock generated from the carrier and dividing it to a first half and a second half, an A/D converter 52 generates digital signals from two digital values corresponding to respective integration output of the first-half/second-half, a multiplier 53 performs phase demodulation of the phase modulation wave part from the digital signal and the clock, while a CPU sets a value in accordance with the integration output of the integrator 71a detected by the A/D converter 76 to a speed register 78 and sets a value in accordance with the integration output of the integrator 72a detected by the A/D converter 77 to a speed register 79, and the integrators 71a, 72a perform integration with integration speed of the set value. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a phase demodulation technique for demodulating a phase-modulated wobble signal read from a recording medium such as an optical disk on which meandering tracks are formed.

In general, disc-shaped recording media such as optical discs adopt a format in which tracks wobble (wobbling) so that the frequency of the carrier signal to be recorded and reproduced becomes constant when CLV (constant linear velocity) rotation control is performed. ing. For this reason, the recording / reproducing apparatus detects a wobble signal which is a kind of carrier wave signal, controls the rotation of the recording medium, and generates a recording clock. Also, address information is necessary so that the recording position can be specified in the unrecorded area. For example, in CD-R (Compact Disk-Recordable), the address data is superimposed by performing frequency modulation or phase modulation on the wobble signal described above. is doing. For demodulation, for example, a carrier wave signal is extracted from the phase modulation signal, and the demodulation is performed by comparing the phases of the phase modulation signal and the carrier wave signal.
Specifically, in a typical conventional phase demodulation technique using meandering tracks, a carrier wave is extracted (generated) from a wobble signal obtained from a recording medium, the carrier wave and the wobble signal are multiplied, and the multiplication result is obtained. Integration is performed, and a phase demodulated signal is obtained based on the integration result. However, in the case of this prior art, when noise is superimposed on the wobble signal, the performance of phase demodulation is reduced, and erroneous detection frequently occurs.
From such a background, there is provided a phase demodulation technique disclosed in Patent Document 1 that can reduce erroneous detection even when noise is superimposed on a wobble signal. Hereinafter, the phase demodulation technique disclosed in Patent Document 1 will be described.

FIG. 14 is a block diagram showing the configuration of the wobble signal demodulation circuit disclosed in Patent Document 1. In FIG. A feature is that an integrator 54 and the like are provided in order to eliminate the influence of noise. The wobble signal demodulating circuit is a circuit after the carrier wave is separated. FIG. 15 shows signals of respective parts of the wobble signal demodulation circuit.
As shown in FIG. 14, this wobble signal demodulating circuit obtains ADIP (Address In Pre-groove) information S10 from the input analog wobble signal (signal from which the carrier wave is removed) S2 and digital wobble signal (carrier wave signal) S4. Generate. The analog wobble signal S2 is A / D converted by the A / D converter 52. This A / D conversion is sampled n times per cycle of the wobble signal (n is about 8 to 16 samples, depending on the state of the analog wobble signal, 16 samples in FIG. 15). Here, the timing pulse for sampling is generated from the digital wobble signal S4. That is, the digital wobble signal S4 is supplied to the A / D converter 52 as a timing pulse via the PLL 49 and the timing circuit 55.
Thus, the A / D converter 52 outputs a signal having a waveform like S16 (see FIG. 15), and this S16 is multiplied by the sine wave S6 generated by the sine wave generator 51. The resolution of the sine wave is n times per wobble period. The multiplication result has a waveform like S7 (see FIG. 15). S7 is integrated by the integrator 54 every period of the wobble signal, and an integration result as shown as S8 is obtained. The integration result signal S8 is sampled and held by the S / H circuit, and a signal having a waveform as shown at S9 is input to the ADIP information detector 57. The ADIP information detector 57 detects the ADIP information S10 based on S9. This ADIP information includes address information and a synchronization signal, and is used, for example, for read / write of an optical disc apparatus.
JP 2002-74660 A

However, in the prior art disclosed in Patent Document 1, the sampling rate of the A / D converter 52 becomes a problem. When an optical disk device or the like is performing high-speed read / write, it is quite difficult to achieve a sampling rate equivalent to that at low speed. For example, when the optical disk apparatus is operating at 1 × speed, the time of one wobble signal period is 1.22 us. At this time, if sampling is performed 16 times per wobble signal period, it is sampled once every 75 ns. On the other hand, since the time of one wobble signal period is 76.5 ns during 16 × speed operation, if sampling is performed 16 times per wobble signal period, it must be sampled once every 4.78 ns. Even if sampling is performed 8 times, it must be sampled once every 9.56 ns.
The severity of the sampling period is specifically the severity of the integration timing of the analog wobble signal. This is because the center of the integration timing pulse must be set to be the center of the half cycle of the analog wobble (WBL) signal (that is, the position of the quarter cycle) (see FIG. 9). Due to variations in the disk drive mechanism and the optical disk medium, even if the center of the integration timing pulse is at the center of the half period of the analog wobble signal in a certain optical disk apparatus, this may not be the case in a different optical disk apparatus. If this position shifts, the amplitude of the integrator output also decreases, and as a result, the reliability of the ADIP information (S10) decreases.
As a countermeasure against this, the configuration shown in FIG. 7 can be considered. In this configuration, an analog integration unit 58 is added to the configuration shown in FIG. 6 (described later), and a digital signal processing unit 59 (in FIG. 6, PLL circuit 49 to sine wave generation circuit 51, multiplier 53 to ADIP information detector 57). ), The integrator 54 and the S / H circuit 56 are deleted.

As shown in FIG. 7, the analog wobble signal S2 enters the analog integrator 58, and the first integrator (INTEG1) 71 integrates the wobble signal for the period of the first half cycle of the wobble signal, and the rest. It is reset during 1/2 period. INT1 and INT2 shown in FIG. 8 are waveforms indicating integration timing, and CLR1 and CLR2 are waveforms indicating integration output reset (integration / reset when the signal is at a high level).
In the second integrator (INTEG2) 72, the same operation as that of the first integrator (INTEG1) 71 is performed with a ½ cycle shift. The output waveforms of the integrators 71 and 72 are the INTEG1 output S17 and the INTEG2 output S18 shown in FIG.
Thereafter, S17 and S18 are input to the multiplexer (MUX) 73, and the INTEG1 output S17 and the INTEG2 output S18 are alternately selected at the timing of SEL1 shown in FIG. And select the INTEG2 output when the SEL1 waveform is Low). The resulting WBLO waveform S19 is input to the digital signal processing unit 59 and A / D converted by the A / D converter 52. The second timing circuit 74 generates timing pulses to be output to the first integrator 71, the second integrator 72, and the multiplexer 73.

As shown in FIG. 9, A / D conversion is performed between the integration timing pulse (INT1 / 2) and the reset timing pulse (CLR1 / 2). A / D conversion sampling may be performed twice in one wobble period (sampling once for the INTEG1 integration result and once for the INTEG2 integration result). Thereafter, the A / D converter output S <b> 20 has a signal waveform as shown in FIG. 8, and the sine wave S <b> 23 is multiplied by the multiplier 53. As a result of this multiplication, S21 is as shown in FIG. 8, from which ADIP information S22 is obtained.
When the load of the A / D converter 52 is compared between 16 samples and 2 samples, it is as follows. When the optical disc apparatus 10 operates at 16 times speed, the time of one wobble period is 76.5 ns. Therefore, at this time, if sampling is performed 16 times per wobble period, it must be sampled once every 4.78 ns. However, if sampling is performed twice per wobble period, it is only necessary to sample once at 38.25 ns, so that the load on the A / D converter 52 can be reduced.
However, in the methods shown in FIGS. 7 and 8, the integrated output amplitude is smaller than necessary (that is, the problem of Patent Document 1 is not sufficiently solved) due to variations in the disk drive mechanism and the optical disk medium. Or If the integrated output amplitude is too small, an error occurs in the wobble demodulation result. If the integrated output amplitude is too large, the dynamic range is exceeded.
The present invention is intended to solve the problems of the prior art as described above. Specifically, it is intended to provide a wobble signal demodulating circuit and the like that can always set the integral output amplitude to an appropriate magnitude. Objective.

In order to solve the above-described problem, a wobble signal demodulating circuit according to claim 1 includes a carrier wave unit having a carrier wave having a predetermined basic period, obtained from a recording surface of a disk-shaped recording medium on which a meandering track is formed. A wobble signal demodulating circuit for demodulating a wobble signal including a phase modulation wave portion having predetermined information added to the carrier wave, the wobble signal being synchronized with a clock signal generated from the carrier wave An integration means for integrating each of the first half part and the second half part, and at least one digital value corresponding to the integration output of the first half part and at least one digital value corresponding to the integration output of the second half part. A digital means for generating a signal, and a phase demodulation of the phase modulation wave unit based on the digital signal and the clock signal And a wobble signal demodulating circuit including an adjusting means, comprising an integration speed setting means for setting the integration speed of the integration means to any one of a plurality of values, wherein the integration means has an integration speed set by the integration speed setting means. The integration is performed accordingly.
3. The wobble signal demodulating circuit according to claim 2, wherein the integral speed setting means sets the integral speed based on a digital value generated corresponding to each integral output. To.
The wobble signal demodulating circuit according to claim 3 is a carrier wave part having a carrier wave of a predetermined basic period, obtained from a recording surface of a disk-shaped recording medium on which a meandering track is formed, and predetermined information is added to the carrier wave. A wobble signal demodulating circuit for demodulating a wobble signal including a phase modulation wave section, wherein the wobble signal is divided into a first half part and a second half part of the basic period in synchronization with a clock signal generated from the carrier wave. Integration means for integrating, sample hold means for sample-holding the integration output of the integration means, one digital value corresponding to the sample hold output of the first half part, and one corresponding to the sample hold output of the second half part Digitizing means for generating a digital signal based on a digital value, the digital signal and the clock signal; A wobble signal demodulating circuit including a demodulating means for performing phase demodulation of the phase-modulated wave unit, and comprising an integrating speed setting means for setting an integrating speed of the integrating means to any one of a plurality of values, Is configured to perform integration according to the integration speed set by the integration speed setting means.

The wobble signal demodulating circuit according to claim 4 is the wobble signal demodulating circuit according to claim 3, wherein the integral speed setting means sets the integral speed based on a digital value generated corresponding to each sample hold output. Make the configuration.
A wobble signal demodulating circuit according to a fifth aspect of the present invention is the wobble signal demodulating circuit according to the second or fourth aspect, wherein the integral speed setting means sets the integral speed for each disk position or for each predetermined time interval.
A recording / reproducing apparatus according to claim 6 is a recording / reproducing apparatus comprising a wobble signal demodulating circuit for demodulating a wobble signal acquired from a recording surface of a disc-shaped recording medium on which meandering tracks are formed. A wobble signal demodulation circuit is provided.
A recording / reproducing apparatus according to a seventh aspect is the recording / reproducing apparatus according to the sixth aspect, comprising the wobble signal demodulation circuit according to the second aspect.
The recording / reproducing apparatus according to claim 8 is a recording / reproducing apparatus comprising a wobble signal demodulating circuit for demodulating a wobble signal acquired from a recording surface of a disc-shaped recording medium on which meandering tracks are formed. A wobble signal demodulation circuit is provided.
A recording / reproducing apparatus according to a ninth aspect is the recording / reproducing apparatus according to the eighth aspect, comprising the wobble signal demodulation circuit according to the fourth aspect.
11. The method according to claim 10, comprising: a carrier wave part having a carrier wave having a predetermined basic period, obtained from a recording surface of a recording medium on which a meandering track is formed; and a phase modulation wave part having predetermined information added to the carrier wave In the wobble signal demodulating method for demodulating a wobble signal including: each integration speed is set to any one of a plurality of values, and each is set in synchronization with the clock signal generated from the carrier wave unit. The wobble signal is divided into a first half part and a second half part of the basic period at an integration speed, and integration is performed. At least one first digital value corresponding to the integration output of the first half part and the integration output of the second half part are obtained. Generating a digital signal based on the corresponding at least one second digital value and determining the phase based on the digital signal and the clock signal. To configure for phase demodulating the harmonic portion.

According to a eleventh aspect of the present invention, in the wobble signal demodulation method according to the tenth aspect, each integration speed is set based on a digital value corresponding to each integration output.
13. The method according to claim 12, comprising: a carrier wave part having a carrier wave having a predetermined basic period, obtained from a recording surface of a recording medium on which a meandering track is formed; and a phase modulation wave part having predetermined information added to the carrier wave In the wobble signal demodulating method for demodulating a wobble signal including: each integration speed is set to any one of a plurality of values, and each is set in synchronization with the clock signal generated from the carrier wave unit. The wobble signal is divided into the first half part and the second half part of the basic period at the integration speed, integration is performed, sample holding of each integration output is performed, and a first digital value corresponding to the sample hold output of the first half part is obtained. And a second digital value corresponding to the sample-and-hold output of the latter half portion, and generating a digital signal, To configure for phase demodulation of the phase modulated wave part on the basis of the serial clock signal.
According to a thirteenth aspect of the present invention, in the wobble signal demodulation method according to the twelfth aspect of the present invention, each integration speed is set based on a digital value corresponding to each sample and hold output.

  According to the present invention, when demodulating a wobble signal, the integration speed of the integration unit for removing noise can be set to any one of a plurality of values, integration is performed at the set integration speed, and the integration output amplitude is obtained. Since a digital signal can be generated based on the corresponding digital value and phase demodulation can be performed based on the digital signal and the clock signal, if the integrated output amplitude is too small, the integration speed is increased and the integrated output amplitude is If it is too large, the integral output amplitude can always be set appropriately by slowing down the integration speed. Therefore, if the integral output amplitude is too small, an error occurs in the wobble demodulation result, or the integral output amplitude It is possible to prevent such a situation that is too large and exceeds the dynamic range.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the components, types, combinations, shapes, relative positions, and the like described in this embodiment are not merely intended to limit the scope of this description unless otherwise specified, but are merely illustrative examples. .
FIG. 1 shows a main part of an optical disc 1 such as a DVD or a CD-RW used in an optical disc apparatus showing an embodiment of the present invention. As shown in FIG. 1A, the optical disc 1 includes information tracks 2 that are periodically wobbled (wobbled), and the tracks 2 are on the substrate of the optical disc 1 as shown in FIG. A mark formed in a spiral shape and modulated by a phase modulation method (PSK method = Phase Shift Keying) is recorded in advance on the track 2. In FIG. 1A, the black portion is an example of the recording mark 3.
FIG. 2 is a block diagram showing the configuration of the main part of the optical disc apparatus according to an embodiment of the present invention. As shown in the figure, this optical disk device 10 includes a spindle motor 11 that rotates the optical disk 1, an optical pickup device 12, a laser control circuit 13, an encoder 14, a motor driver (motor drive circuit) 15, an analog signal processing circuit 16, and a decoder. 17, a servo controller 18, a buffer RAM 19, a D / A converter 20, a buffer manager 21, an interface 22, a ROM 23, a CPU 24, a RAM 25, and the like. The arrows shown in FIG. 2 indicate a typical signal or information flow as the connection relationship of each block, but do not represent the entire connection relationship of each block.
The optical pickup device 12 guides a light beam emitted from the semiconductor laser as a light source and a laser control circuit 13 to the recording surface of the optical disc 1 according to the control of the laser control circuit 13, and sends a return light beam reflected by the recording surface to a predetermined amount. An optical system that leads to the light receiving position, a light receiver that is arranged at the light receiving position and receives the return light beam, and a drive system (such as a focusing actuator, a tracking actuator, and a seek motor) (all not shown) are incorporated.

The light receiver in the optical pickup device 12 includes, for example, a four-divided light receiving element 30 (first to fourth light receiving elements 30a to 30d) as shown in FIG. In FIG. 3A, for the sake of convenience, the vertical direction of the paper is the X axis direction, the horizontal direction of the paper is the Y axis direction, and the vertical direction of the paper is the Z axis direction. Each of the first and second light receiving elements 30a and 30b has the same rectangular shape with the long side in the horizontal direction (Y-axis direction) in FIG. 3A, and the vertical direction (X-axis direction). ). The third and fourth light receiving elements 30c and 30d have the same rectangular shape with the long side in the vertical direction (X-axis direction) in FIG. 3A and the horizontal direction (Y (Axial direction) adjacent to each other.
Then, as shown in FIG. 3B, the reflected light RB from the recording surface of the optical disc 1 (in the example shown, the optical axis is in the Z direction) is 2 by the prism 31 constituting the optical system of the optical pickup device 12. One reflected light RB1 branched in the direction and transmitted through the prism 31 is applied to the first and second light receiving elements 30a and 30b. Further, the other reflected light RB2 branched in the negative direction of the X axis by the prism 31 is bent in the + Z direction by the reflecting mirror 32 and irradiated to the third and fourth light receiving elements 30c and 30d.

As shown in FIG. 4A, in the above, among the reflected light RB, the reflected light RBa in the upper half of the paper surface in FIG. 4A is irradiated to the first light receiving element 30a and reflected in the lower half of the paper surface. The light RBb is applied to the second light receiving element 30b. Also, as shown in FIG. 4B, the reflected light RBc in the right half of the paper surface in FIG. 4B among the reflected light RB is irradiated to the third light receiving element 30c, and the reflected light RBd in the left half of the paper surface. Is irradiated to the fourth light receiving element 30d. Each of the first to fourth light receiving elements 30a to 30d performs photoelectric conversion, and outputs a current (current signal) corresponding to the amount of received light to the analog signal processing circuit 16 as a photoelectric conversion signal.
Note that the light receiver is not limited to the four-divided light receiving element 30; for example, a two-divided light receiving element configuration including the first and second light receiving elements 30a and 30b, the third and fourth light receiving elements 30c, A two-divided light receiving element configuration including 30d may be used, or a configuration in which the first to fourth light receiving elements 30a to 30d are arranged in a line may be used, and the shape and arrangement are arbitrary.

  As shown in FIG. 2, the analog signal processing circuit 16 is an I / V amplifier (current-voltage conversion amplifier) that converts a current signal that is an output signal of the light receiving elements 30 a to 30 d in the optical pickup device 12 into a voltage signal. 26, a wobble signal demodulation circuit 27 for detecting a wobble signal, an RF signal detection circuit 28 for detecting an RF signal including reproduction information (reproduction information is added to a carrier wave by phase modulation), and a focus error signal and a track error signal And an error signal detection circuit 29 for detecting the error. The wobble signal includes a carrier part having only a carrier wave having a predetermined basic period and a phase modulation wave part in which address information or the like is added to the carrier wave.

As shown in FIG. 5, the I / V amplifier 26 includes I / V amplifiers 26 a to 26 d that convert current signals from the first to fourth light receiving elements 30 a to 30 d into voltage signals (signals Sa to Sd). I have. Further, the RF signal detection circuit 28 adds all these voltage signals Sa to Sd, further binarizes the addition result, and detects it as an RF signal.
The error signal detection circuit 29 obtains a difference between the voltage signal Ra and the voltage signal Rb, binarizes the result, detects it as a focus error signal, obtains a difference between the voltage signal Rc and the voltage signal Rd, and obtains the result. Is binarized and detected as a track error signal. The detected focus error signal and track error signal are respectively output from the error signal detection circuit 29 to the servo controller 18.
The wobble signal demodulation circuit 27 detects a wobble signal based on the voltage signals Sc and Sd and outputs it to the decoder 17. The configuration of the wobble signal demodulation circuit 27 will be described later.
The decoder 17 extracts address information, a synchronization signal, and the like from ADIP information included in the wobble signal detected by the wobble signal demodulation circuit 27. Then, the extracted address information is output to the CPU 24 and a synchronization signal is output to the encoder 14. The decoder 17 performs reproduction processing such as demodulation and error correction processing on the RF signal detected by the RF signal detection circuit 28. Further, when the reproduction data is other than music data (for example, image data, document data, etc.), the decoder 17 performs error check and error correction processing based on a check code added to the data, via the buffer manager 21. The reproduction data is stored in the buffer RAM 19.

The servo controller 18 creates a control signal for controlling the focusing actuator of the optical pickup device 12 based on the focus error signal detected by the error signal detection circuit 29 and outputs the control signal to the motor driver 15. Further, the servo controller 18 creates a control signal for controlling the tracking actuator of the optical pickup device 12 based on the track error signal detected by the error signal detection circuit 29 and outputs the control signal to the motor driver 15.
When the data recorded on the optical disc 1 is music data, the D / A converter 20 converts the output signal of the decoder 17 into analog data and outputs it as an audio signal to an audio device or the like.
The buffer manager 21 manages data accumulation in the buffer RAM 19, and notifies the CPU 24 when the accumulated data amount reaches a predetermined value.
The motor driver 15 drives the focusing actuator and tracking actuator of the optical pickup device 12 based on a control signal from the servo controller 18. Further, the motor driver 15 controls the spindle motor 11 based on an instruction from the CPU 24 so that the optical disc 1 has a constant linear velocity (CLV method) or a constant rotation speed (CAV method). Further, the motor driver 15 drives a seek motor based on an instruction from the CPU 24 to control the position of the optical pickup device 12 in the sledge direction (radial direction of the optical disc 1).

The encoder 14 adds data such as an error correction code to the data stored in the buffer RAM 19 to create data to be written on the optical disc 1. Based on the instruction from the CPU 24, the write data is output to the laser control circuit 13 in synchronization with the synchronization signal from the decoder 17.
The laser control circuit 13 controls the output of the semiconductor laser in the optical pickup device 12 based on the write data from the encoder 14. Then, the laser control circuit 13 outputs a timing signal synchronized with the mark recording period and the space recording period to the wobble signal demodulation circuit 27 during recording.
The interface 22 is a bidirectional communication interface with a host device (for example, a personal computer), and conforms to a standard interface such as ATAPI (At Attachment Packet Interface), SCSI (Small Computer System Interface).
The CPU 24 controls the operation of each unit as described above in accordance with a program stored in the ROM 23 and temporarily stores data necessary for control in the RAM 25.

FIG. 6 is a configuration block diagram showing the embodiment of the wobble signal demodulating circuit 27 and its output side in a configuration before the present invention is implemented (that is, a conventional configuration). Hereinafter, the wobble signal demodulation circuit 27 and the like shown in FIG. 6 will be described.
As shown in the figure, sample hold circuits (S / H) 41a and 41b to which voltage signals Sc and Sd from the I / V amplifiers 26c and 26d are input are provided, and sample hold is provided on the output side of the S / H 41a and 41b. A balance AGC 42 for balancing the amplitudes of the subsequent voltage signals Sc and Sd is provided. On the output side of the balance AGC 42, a subtractor 43 for calculating a difference “Sc−Sd” between the voltage signal Sc after the sample hold and the voltage signal Sd is provided. A filter circuit 44 is provided on the output side of the subtractor 43. The filter circuit 44 has a BPF path for a digital wobble signal through which a carrier frequency component is passed by a BPF (band pass filter) 45, and an HPF (high pass filter). ) 46 and LPF (low-pass filter) 47, and an “HPF + LPF” path for an analog wobble signal that passes information components (modulation components) other than the carrier frequency component. On the output side of the BPF 45, for example, a binarizer 48 using a comparator is provided.
For the digital wobble signal S4 obtained from the binarizer 48, a PLL circuit 49 for stabilizing the digital wobble signal S4 and a delay circuit 50 for timing adjustment are provided in order, and the digital wobble signal S4 is in phase with the digital wobble signal. A sine wave generation circuit 51 that generates a sine wave (sin wave) is provided. Since the digital wobble signal S4 input to the PLL circuit 49 is a carrier wave portion signal according to claim 1 having a carrier frequency component of a predetermined fraction by the BPF 45, the PLL circuit 49 is used for the phase modulated wave portion according to claim 1. It supplements with.

On the other hand, an A / D converter (corresponding to the digitizing means described in claim 1) 52 for converting the analog wobble signal S2 obtained from the LPF 47 into digital data is provided at the next stage of the LPF 47. A multiplier (corresponding to the demodulating means described in claim 1) 53 is converted into a wobble signal (corresponding to the digital signal described in claim 1) converted into a digital value by the A / D converter 52 and a sine wave. The digital wobble signal (corresponding to the clock signal according to claim 1) is multiplied. On the output side of the multiplier 53, an integrator 54 for integrating the multiplication result is provided. The wobble signal is reset in units of one wobble period by a reset signal from a timing circuit 55 that generates and outputs a timing signal synchronized with the output of the integrator 54.
An ADIP information detector 57 is provided on the output side of the integrator 54 via a sample and hold circuit (S / H) 56, and outputs ADIP information S10. A decoder 17 is connected to the ADIP information detector 57. The decoder 17 includes a synchronization detector 61 that detects a synchronization signal ADIPsync based on ADIP information, an error correction unit 62 that performs error correction processing, an address information extraction unit 63 that extracts address information based on ADIP information after error correction, and a delay A circuit 64 is provided.
The synchronization signal ADIPsync detected by the synchronization detector 61 is input to the encoder 14 via the delay circuit 64, and used for generating a write timing signal (recording start timing signal). A write command (or read command) is also input to the encoder 14 from the CPU 24 at a predetermined timing, and the laser control circuit 13 starts a recording operation when a write timing signal is generated in the presence of the write command.

7 adds an analog integration unit 58 to the configuration shown in FIG. 6, and integrates from the digital signal processing unit 59 (in FIG. 6, PLL circuit 49 to sine wave generation circuit 51, multiplier 53 to ADIP information detector 57). The device 54 and the S / H circuit 56 are omitted.
As shown in FIG. 7, the analog wobble signal S2 enters the analog integrator 58, and the first integrator (INTEG1) 71 integrates the wobble signal for the period of the first half cycle of the wobble signal, and the rest. It is reset during 1/2 period. INT1 and INT2 shown in FIG. 8 are waveforms indicating integration timing, and CLR1 and CLR2 are waveforms indicating integration output reset (integration / reset when the signal is at a high level). However, as shown in FIG. 9, the center of the integration timing pulse (INT1 in FIG. 9) should be set to the center of the half cycle of the analog wobble (WBL) signal (that is, the position of the quarter cycle). . Also, it is better to open the integration timing and reset interval as much as possible.
In the second integrator (INTEG2) 72, the same operation as that of the first integrator (INTEG1) 71 is performed with a ½ cycle shift. The output waveforms of the integrators 71 and 72 are the INTEG1 output S17 and the INTEG2 output S18 shown in FIG. The integrators 71 and 72 realize the integration means described in the claims.
Thereafter, S17 and S18 are input to the multiplexer (MUX) 73, and the INTEG1 output S17 and the INTEG2 output S18 are alternately selected at the timing of SEL1 shown in FIG. Select and select INTEG2 output when SEL1 waveform is Low). The result is a WBLO waveform S 19, which is input to the digital signal processing unit 59 and A / D converted by the A / D converter 52. The second timing circuit 74 generates timing pulses to be output to the first integrator 71, the second integrator 72, and the multiplexer 73.

As shown in FIG. 9, A / D conversion is performed between the integration timing pulse (INT1 / 2) and the reset timing pulse (CLR1 / 2). The A / D conversion may be sampled twice in one wobble period (sampling once for the INTEG1 integration result and once for the INTEG2 integration result). Thereafter, the A / D converter output S20 (corresponding to the digital signal described in claim 1) has a signal waveform as shown in FIG. 8, and a sine wave S23 (corresponding to the clock signal described in claim 1, Since the resolution may be twice in one wobble period, the multiplier 53 multiplies the wave by a rectangular wave rather than a sine wave. As a result of this multiplication, S21 is as shown in FIG. 8, from which ADIP information S22 is obtained.
When the load of the A / D converter 52 is compared between 16 samples and 2 samples, it is as follows. When the optical disc apparatus 10 operates at 16 times speed, the time of one wobble period is 76.5 ns. Therefore, at this time, if sampling is performed 16 times per wobble period, it must be sampled once every 4.78 ns. However, when sampling is performed twice per wobble period, it is only necessary to sample once at 38.25 ns, so that the load on the A / D converter 52 can be reduced.
However, in the methods shown in FIGS. 7 and 8, the integrated output amplitude is smaller than necessary (that is, the problem of Patent Document 1 is not sufficiently solved) due to variations in the disk drive mechanism and the optical disk medium. Or If the integrated output amplitude is too small, an error occurs in the wobble demodulation result. If the integrated output amplitude is too large, the dynamic range is exceeded.

Examples of the present invention will be described below.
[Example 1]
FIG. 10 is a block diagram showing the configuration of the main part of the wobble signal demodulation circuit of this embodiment. As shown in the figure, in addition to the configuration shown in FIG. 7, A / D converters 76 and 77 are provided in the digital signal processing unit 59a, and further, a first integrator (INTEG1) 71a and a second integrator are provided. In (INTEG2) 72a, a plurality of resistors R (not shown) constituting the integrating circuit are provided so as to be switchable, and speed registers 78 and 79 for switching the resistor R are provided. The reason why the A / D converters 76 and 77 are provided is to detect the level of the integrated output amplitude. In this embodiment, the integration speed setting means described in the claims is realized by the CPU 24, A / D converters 76 and 77, speed registers 78 and 79, and the like.
In this embodiment, the integration time constant is realized by the capacitor C and the resistor R. By increasing the value of the time constant C × R, the integration speed is lowered, and by decreasing the value of the time constant C × R. Increase the integration speed. As shown in the figure, the data bus line B is connected to the speed registers 78 and 79, and the CPU 24 (see FIG. 6) uses the bus line B to select a value for selecting the resistor R in the speed registers 78 and 79. The speed is switched to multiple levels by writing.

As shown in FIG. 11, in the A / D converter 76 (ADC2), the integrator 71a (INTEG1) is sampled between the digital pulse INT1 and the digital pulse CLR1. In the A / D converter 77 (ADC3), the integrator 72a (INTEG2) is sampled between the digital pulse INT2 and the digital pulse CLR2. Then, the CPU 24 acquires the output values (amplitude information 1 and amplitude information 2 shown in FIG. 10) of the A / D converters 76 and 77 (ADCs 2 and 3), and integrators 71a and 72a (INTEG1, It is determined whether or not the output amplitude of 2) is at an appropriate level, and the value of the resistor R is written in the speed registers 78 and 79 according to the determination result. That is, when the high levels of the integrators 71a and 72a are lower than a predetermined value, the value of the resistor R is decreased to reduce the time constant and increase the integration speed, so that the high levels of the integrators 71a and 72a are predetermined. If the value is higher than this value, the value of the resistor R is increased to increase the time constant and thereby reduce the integration speed.
Note that writing to the speed registers 78 and 79 using the output values of the A / D converters 76 and 77 is performed when, for example, the user instructs switching of the integral speed using an operation unit (not shown), at the start of operation, and on the optical disk medium. Or when a drive system component or the like is replaced, or every disk position, every predetermined time interval. Specifically, for each disk position, the reading area is divided into a plurality of areas depending on whether the reading disk position is the inner circumference or the outer circumference, and the CPU 24 stores the reading area at the time of the latest reading. It is determined whether or not the reading area is different from the stored reading area, and if it is different, the integral speed switching is executed. Since the period of the clock signal generated from the carrier wave may be different between the inner periphery and the outer periphery, such integration speed switching is particularly effective.
Thus, according to this embodiment, the integral output amplitude can always be set to an appropriate magnitude. Therefore, the integral output amplitude is too small and an error occurs in the wobble demodulation result, or the integral output amplitude is too large. Problems such as exceeding the dynamic range can be avoided.

[Example 2]
FIG. 12 is a block diagram showing the configuration of the main part of the wobble signal demodulation circuit of this embodiment. As shown in the figure, in addition to the configuration shown in FIG. 10, sample hold circuits 80 and 81 for performing sample hold of the outputs of the integrators 71a and 72a are provided. The sample hold circuits 80 and 81 are provided to increase the timing margin. In the A / D conversion, one point of the analog signal is sampled into a digital signal, whereas in the sample and hold circuit, the integrator 71a and 72a charge the analog signal and hold the charged signal. This is not a problem as in the case of A / D conversion. In this embodiment, the integral speed setting means described in the claims is realized by the CPU 24, the A / D converters 76 and 77, the speed registers 78 and 79, etc., as in the first embodiment, and the sample hold means is the sample hold. This is realized by the circuits 80 and 81.
With this configuration, in this embodiment, the outputs of the sample and hold circuits 80 and 81 are input to the multiplexer (MUX) 73.

As shown in FIG. 13, the A / D converter 76 (ADC2) samples the output of the sample hold circuit 80 (S / H1) when the digital pulse SH1 is at the low level. The A / D converter 77 (ADC3) samples the output of the sample hold circuit 81 (S / H2) when the digital pulse SH2 is at a low level. Then, the CPU 24 determines whether or not the output amplitude of the integrators 71 and 72 is an appropriate level based on the output levels of the A / D converters 77 and 78.
Specifically, if the digital value of the A / D converter 76 indicating the output amplitude of the sample hold circuit 80 is lower than a predetermined amplitude level, the value of the resistor R set in the speed register 78 is reduced to reduce the integration speed. Raise. If the digital value of the A / D converter 76 is above a predetermined amplitude level, the value of the resistor R set in the speed register 78 is increased to lower the integration speed. Further, if the digital value of the A / D converter 77 indicating the output amplitude of the sample hold circuit 81 is lower than a predetermined amplitude level, the integration speed is similarly increased by the speed register 79. If the digital value of the A / D converter 77 is higher than a predetermined amplitude level, the integration speed is similarly lowered by the speed register 79.
Note that the writing to the speed registers 78 and 79 using the output values of the A / D converters 76 and 77 is performed in the same manner as in the first embodiment, for example, by the user instructing the integral speed switching by the operation unit (not shown). At the start of operation, when the optical disk medium, drive system components, etc. are replaced, or at each disk position, at predetermined time intervals.
Thus, according to this embodiment, not only the same effects as those of the first embodiment can be obtained, but also the timing margin can be increased by performing the sample hold of the integrated output.

  As described above, the disk-shaped recording medium described in the claims is an optical disk and the recording / reproducing apparatus is an optical disk apparatus. However, the disk-shaped recording medium in which the present invention can be implemented is not limited to an optical disk, for example, a magnetic disk. Alternatively, the recording / reproducing device may be a magnetic disk device, for example.

It is explanatory drawing of the principal part of the optical disk which shows one Embodiment of this invention. It is a block diagram of the principal part of the optical disk apparatus which shows one Embodiment of this invention. It is explanatory drawing of the principal part of the optical disk apparatus which shows one Embodiment of this invention. It is another explanatory drawing of the principal part of the optical disk apparatus which shows one Embodiment of this invention. It is another explanatory drawing of the principal part of the optical disk apparatus which shows one Embodiment of this invention. It is a block diagram of a wobble signal demodulation circuit showing an embodiment of the present invention. It is a block diagram of the principal part of the wobble signal demodulation circuit which shows one Embodiment of this invention. FIG. 4 is a timing / waveform diagram of a main part of a wobble signal demodulation circuit showing an embodiment of the present invention. FIG. 6 is another timing / waveform diagram of the main part of the wobble signal demodulation circuit showing an embodiment of the present invention. It is a block diagram of the principal part of a wobble signal demodulation circuit showing a first embodiment of the present invention. FIG. 3 is a timing / waveform diagram of the main part of the wobble signal demodulation circuit showing the first embodiment of the present invention. It is a block diagram of the principal part of the wobble signal demodulation circuit which shows the 2nd Example of this invention. It is a timing / waveform diagram of the main part of the wobble signal demodulation circuit showing the second embodiment of the present invention. It is a block diagram of the principal part of the wobble signal demodulation circuit which shows an example of a prior art. FIG. 10 is a timing / waveform diagram of a main part of a wobble signal demodulating circuit showing an example of the prior art.

Explanation of symbols

  1 optical disc, 10 optical disc device, 16 analog signal processing circuit, 24 CPU, 27 wobble signal demodulation circuit, 51 sine wave generation circuit, 52 A / D converter, 53 multiplier, 54 integrator, 55 timing circuit, 57 ADIP information Detector, 58 Analog integrator, 59 Digital signal processor, 71 First integrator, 72 Second integrator, 76, 77 A / D converter, 78, 79 Speed register, 80, 81 Sample hold circuit

Claims (13)

  Demodulate a wobble signal including a carrier wave part having a carrier wave of a predetermined basic period acquired from a recording surface of a disk-shaped recording medium on which a meandering track is formed, and a phase modulation wave part having a predetermined information added to the carrier wave. A wobble signal demodulating circuit that integrates the wobble signal divided into a first half part and a second half part of the fundamental period in synchronization with a clock signal generated from the carrier wave; and integration of the first half part Digitizing means for generating a digital signal based on at least one digital value corresponding to the output and at least one digital value corresponding to the integrated output of the latter half, and based on the digital signal and the clock signal And a wobble signal demodulating circuit including a demodulating means for performing phase demodulation of the phase modulation wave section. Equipped with an integrating speed setting means for setting either during the number of values, the integrating means is a wobble signal demodulation circuit, characterized in that the integration is performed according to the integral speed set in the integrating speed setting means.   2. A wobble signal demodulation circuit according to claim 1, wherein said integration speed setting means sets an integration speed based on a digital value generated corresponding to each integration output.   Demodulate a wobble signal including a carrier wave part having a carrier wave of a predetermined basic period acquired from a recording surface of a disk-shaped recording medium on which a meandering track is formed, and a phase modulation wave part having a predetermined information added to the carrier wave. A wobble signal demodulating circuit that integrates the wobble signal divided into a first half and a second half of the fundamental period in synchronization with a clock signal generated from the carrier, and integration of the integration means Sample hold means for performing sample hold of the output, and digital for generating a digital signal based on one digital value corresponding to the sample hold output of the first half and one digital value corresponding to the sample hold output of the second half And phase demodulating the phase-modulated wave unit based on the digital signal and the clock signal. A wobble signal demodulating circuit including a demodulating means, comprising: an integral speed setting means for setting the integral speed of the integral means to any one of a plurality of values, wherein the integral means has an integral speed set by the integral speed setting means. A wobble signal demodulating circuit that performs integration in response.   4. A wobble signal demodulation circuit according to claim 3, wherein said integration speed setting means sets an integration speed based on a digital value generated corresponding to each sample and hold output.   5. The wobble signal demodulation circuit according to claim 2, wherein the integration speed setting means sets the integration speed for each disk position or for each predetermined time interval.   2. A recording / reproducing apparatus comprising a wobble signal demodulating circuit for demodulating a wobble signal acquired from a recording surface of a disk-shaped recording medium on which a meandering track is formed, comprising the wobble signal demodulating circuit according to claim 1. A recording / reproducing apparatus.   7. The recording / reproducing apparatus according to claim 6, comprising the wobble signal demodulating circuit according to claim 2.   3. A recording / reproducing apparatus comprising a wobble signal demodulating circuit for demodulating a wobble signal acquired from a recording surface of a disk-shaped recording medium on which a meandering track is formed, comprising the wobble signal demodulating circuit according to claim 2. A recording / reproducing apparatus.   9. The recording / reproducing apparatus according to claim 8, comprising the wobble signal demodulating circuit according to claim 4.   Demodulate a wobble signal obtained from a recording surface of a recording medium on which a meandering track is formed, including a carrier wave part having a carrier wave having a predetermined basic period and a phase modulation wave part having predetermined information added to the carrier wave. In the wobble signal demodulation method, each integration speed is set to any one of a plurality of values, and the wobble signal is set at the set integration speed in synchronization with the clock signal generated from the carrier wave unit. The integration is performed separately for the first half and the second half of the basic period, and at least one first digital value corresponding to the integration output of the first half and at least one second corresponding to the integration output of the second half. A digital signal is generated based on the digital value, and phase demodulation of the phase modulation wave unit is performed based on the digital signal and the clock signal. Wobble signal demodulating method comprising and.   11. The wobble signal demodulation method according to claim 10, wherein each integration speed is set based on a digital value corresponding to each integration output.   Demodulate a wobble signal obtained from a recording surface of a recording medium on which a meandering track is formed, including a carrier wave part having a carrier wave having a predetermined basic period and a phase modulation wave part having predetermined information added to the carrier wave. In the wobble signal demodulation method, each integration speed is set to any one of a plurality of values, and the wobble signal is set at the set integration speed in synchronization with the clock signal generated from the carrier wave unit. Integration is performed separately for the first half and the second half of the basic period, sample integration of each integration output is performed, and the first digital value corresponding to the sample hold output of the first half and the sample hold output of the second half A digital signal is generated based on the second digital value corresponding to, and based on the digital signal and the clock signal. Wobble signal demodulating method and performing a phase demodulation of the phase modulated wave part Te.   13. The wobble signal demodulation method according to claim 12, wherein each integration speed is set based on a digital value corresponding to each sample hold output.

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