JP2004192807A - Wobble signal detecting circuit and optical disk device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wobble signal detecting circuit which is used for a plurality of kinds of optical recording media and which precisely and stably detects wobble signals at least during recording. <P>SOLUTION: The circuit is provided with a first amplitude adjusting circuit 57a' which is used to adjust the amplitudes of first voltage signals corresponding to the opto-electric conversion signals from a first light receiving region of a light receiving element. The amplitudes are matched with a target amplitude, a second amplitude adjusting circuit which is used to adjust the amplitudes of second voltage signals corresponding to the opto-electric conversion signals from a second light receiving region of the light receiving element. The amplitudes are matched with the target amplitude, a target amplitude setting circuit which is used to individually set the target amplitudes for the circuits 57a' and the second amplitude adjusting circuit and a subtracting circuit which outputs the difference in the output signals of the circuit 57a' and the second amplitude adjusting circuit as wobble signals. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a wobble signal detection circuit and an optical disc device, and more particularly, to a recordable optical recording medium such as a CD (compact disc) and a DVD (digital versatile disc), particularly a DVD + R (DVD + recordable) and a DVD + RW (DVD + rewritable). The present invention relates to a wobble signal detection circuit for detecting a wobble signal recorded in a wobble signal, and an optical disc device provided with the wobble signal detection circuit.

  An information recording / reproducing apparatus (for example, an optical disc) that records information on an optical disc as an optical recording medium having a spiral recording area and reproduces information recorded on the optical disc by using a laser beam output from an optical pickup. Device) has been put to practical use.

  2. Description of the Related Art In recent years, personal computers have been able to handle AV (Audio-Visual) information such as music and video as their functions have improved. Since the amount of information of these AV information is very large, an optical disk has been attracting attention as an information recording medium, and at a low price, an optical disk device has become popular as one of peripheral devices of a personal computer. Was.

  Generally, a groove called a track (pre-groove) is provided in advance in a recording area of a write-once optical disc such as a DVD + R or a rewritable optical disc such as a DVD + RW. The track is meandered (wobbled) to record various accompanying information as a wobble signal.

  Particularly important as additional information is ADIP (ADdress In Pregroove) information. The ADIP information includes address information indicating a position on the optical disc. This address information is information necessary for accurately controlling the position of the optical pickup during recording and reproduction. Further, the ADIP information includes a signal synchronized with the rotation speed of the optical disk, and is used for accurately recording information at a predetermined position.

  Therefore, if the ADIP information cannot be correctly detected, the synchronization with the rotation of the optical disc cannot be obtained, and a recording error may occur. In particular, in a write-once DVD + R, if a recording error occurs, the optical disk cannot be reused. Therefore, accurate detection of ADIP information, that is, detection of a wobble signal is very important.

  The wobble signal is included in the reflected light from the track, but due to fluctuations in the recording data recorded on the optical disk and the output of the laser light, the reflected light includes a complex component that becomes noise with respect to the wobble signal. Have been. Therefore, conventionally, for example, light reflected from a track is received by a light receiving element divided into two in the tangential direction of the track (a two-divided light receiving element), and a difference between output signals (photoelectric conversion signals) of the respective light receiving elements is obtained. The noise component was removed, and the wobble signal was extracted.

  The mounting position of the two-piece light receiving element is adjusted before shipment so that the reflected light from the track is located at the center of the light receiving surface of the two-piece light receiving element. Due to a change over time (aging) due to the above, the light receiving position of the reflected light may be shifted from the center of the light receiving surface. In this case, since the noise components included in the output signals of the respective light receiving elements are different, the noise components remain even if the difference between the output signals of the respective light receiving elements is obtained. Therefore, the S / N ratio of the wobble signal is reduced, and it is difficult to accurately detect the wobble signal.

  In order to improve such inconvenience, for example, in Japanese Patent Application Laid-Open No. 8-194969, a signal amplitude is normalized with respect to each of output signals from a light receiving element divided in a tangential direction of a track, that is, a so-called so-called. An optical disk device that detects a wobble signal from a difference between these signals after performing gain adjustment by a constant amplitude AGC (auto gain control) circuit is disclosed.

  In an optical disc, information is recorded by associating data "1" and "0" with two areas having different reflectivities called a mark (pit) area and a space area. The method for forming the mark area and the space area may differ depending on the type of the optical disc.

  For example, in an optical disk such as a DVD + RW (hereinafter referred to as “phase-change medium” for convenience) having a recording layer containing a special alloy, a laser beam is used to form a special alloy when forming a mark area (hereinafter referred to as “marking time”). Is heated to the first temperature, the laser light output is reduced, the special alloy is rapidly cooled, and the special alloy is in an amorphous state. When forming the space region (hereinafter, referred to as “space time”), the special alloy is heated to a second temperature (<first temperature) by a laser beam, and then the special alloy is gradually cooled, and the special alloy is cooled. It is in a crystalline state. Thereby, the reflectance is lower in the mark area than in the space area. As shown in FIG. 13, in the phase change type medium, the average output of the laser light at the time of the mark (M) is substantially equal to the output of the laser light at the time of the space (S).

  In an optical disk such as a DVD + R or the like containing an organic dye in a recording layer (hereinafter referred to as “dye-type medium” for convenience), at the time of marking, the laser light output is increased to heat and melt the dye, In a space, the laser light output is reduced to the same extent as during reproduction so that the substrate does not deteriorate or deform. Thereby, the reflectance is lower in the mark area than in the space area. As shown in FIG. 13, in the dye-type medium, the laser light output in the space (S) is much lower than the laser light output in the mark (M). Specifically, as an example, the laser light output at the time of marking is about 30 mW, while the laser light output at the time of space is about 1.5 mW.

  In the above-mentioned Japanese Patent Application Laid-Open No. 8-194969, at the time of reproduction, a wobble signal can be detected with high accuracy for both a dye-type medium and a phase-change medium. This is because the laser beam output during reproduction is almost constant, and only a change in the reflectance of the optical disc results in a change in the output signal from the light receiving element. That is, since the amplitude of the output signal from the light receiving element is small, the signal level of the wobble signal component is also amplified by the gain adjustment in the constant amplitude AGC circuit.

  However, especially when recording information on a dye-type medium, there is a large difference between the laser light output at the time of marking and the laser light output at the time of space, so that the signal level of the output signal from the light receiving element at the time of marking is low. The signal level of the output signal from the light receiving element in the space may be 20 times or more. That is, since the amplitude of the output signal from the light receiving element is large, the gain is adjusted in the constant amplitude AGC circuit so that the signal level at the time of marking falls within the allowable voltage range (dynamic range) of the circuit. Therefore, the gain is smaller than that at the time of reproduction, and the wobble signal component at the time of space is buried in the noise component. Further, at the time of marking, the length of the mark area (hereinafter, referred to as “mark length”) tends to increase due to heat accumulation in the recording film. Therefore, as shown in FIG. It goes to a low level before switching to the space area from. For example, when the ratio between the mark area and the space area in the recording data is 1: 1, the laser light output time at a high level (hereinafter, referred to as “high level time”) and the laser light output time at a low level (Hereinafter referred to as “low-level time”) is about 0.7: 1.3. That is, in the output signal from the light receiving element, the portion corresponding to the high-level time (including the wobble signal component) is compared with the portion corresponding to the low-level time (the wobble signal component is buried in the noise component). And very little. Therefore, in the gain adjustment in the constant-amplitude AGC circuit, only a part of the wobble signal component is obtained in a fragmentary manner, and there is a disadvantage that the wobble signal cannot be detected with high accuracy.

  Even during recording on the optical disc, it is necessary to rewrite the management information recorded at a predetermined position in the recording area at a predetermined timing. In this case, the recording is temporarily stopped, the management information is read out, the content is changed, and the information is recorded at a predetermined position in the recording area. That is, even during recording, reproduction is actually performed at a predetermined timing. However, the response speed of the constant-amplitude AGC circuit requires a certain amount of time until a predetermined gain is obtained at the time of switching between recording and reproduction, and there is a disadvantage that a correct wobble signal cannot be obtained during that time.

  The present invention has been made under such circumstances, and a first object of the present invention is to provide a wobble signal capable of coping with a plurality of types of optical recording media and capable of accurately and stably detecting a wobble signal at least during recording. A detection circuit is provided.

  A second object of the present invention is to provide an optical disk device which can handle a plurality of types of optical recording media and can stably perform highly reliable and good recording.

  The invention according to claim 1 is a tangential direction of the recording area, which receives reflected light from the recording surface of spot light applied to an optical recording medium having a recording area formed spirally or concentrically on the recording surface. A wobble signal detection circuit for detecting a wobble signal based on the meandering of the recording area on the basis of a signal from a light receiving element whose light receiving area is divided into two. A first amplitude adjustment circuit that adjusts the amplitude of the first voltage signal according to the converted signal so as to match the target amplitude; and a second amplitude signal corresponding to the photoelectric conversion signal from the second light receiving region of the light receiving element. A second amplitude adjustment circuit for adjusting the amplitude so as to match the target amplitude; and a target amplitude setting for individually setting the target amplitudes of the first amplitude adjustment circuit and the second amplitude adjustment circuit in accordance with a control signal. Circuit and; a wobble signal detecting circuit comprising: a difference between the output signal of the output signal and the second amplitude adjusting circuit of the first amplitude adjustment circuit, and a subtracting circuit for outputting as the wobble signal.

  In this specification, the optical recording medium includes not only optical disks such as CDs and DVDs but also all recording media on which incidental information and the like are recorded as wobble signals.

  According to this, in the target amplitude setting circuit, the target amplitudes of the first amplitude adjustment circuit and the second amplitude adjustment circuit are individually set. Here, in the target amplitude setting circuit, for example, by setting the target amplitude at the time of recording such that the signal level of the wobble signal detected at the time of recording substantially matches the signal level of the wobble signal detected at the time of reproduction, It is possible to prevent erroneous detection of a wobble signal immediately after switching between recording and reproduction. That is, the wobble signal can be accurately and stably detected.

  According to a second aspect of the present invention, there is provided an optical disk apparatus for recording at least information by irradiating a spot light on an optical recording medium having a recording area formed spirally or concentrically on a recording surface. An optical disc apparatus comprising: a wobble signal detection circuit according to any one of (1) to (3);

  According to this, the wobble signal detection circuit according to claim 1 is compatible with a plurality of types of optical recording media and can detect a wobble signal accurately and stably at the time of recording. And other incidental information can be accurately obtained. Therefore, as a result, it is possible to cope with a plurality of types of optical recording media, and it is possible to stably perform high-reliability and good recording. Of course, when the optical disc apparatus reproduces information, highly reliable reproduction can be stably performed.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 shows a schematic configuration of an optical disc device 20 according to an embodiment including a wobble signal detection circuit according to the present invention.

  An optical disk device 20 shown in FIG. 1 includes a spindle motor 22, an optical pickup device 23, a laser control circuit 24, an encoder 25, a motor driver 27, and an analog signal processing circuit 28 for rotationally driving an optical disk 15 as an optical recording medium. , A decoder 31, a servo controller 33, a buffer RAM 34, a D / A converter 36, a buffer manager 37, an interface 38, a ROM 39, a CPU 40, a RAM 41, and the like. Note that the arrows in FIG. 1 indicate typical flows of signals and information, and do not indicate all of the connection relationships of the respective blocks. In the present embodiment, a DVD is used as the optical disk 15 as an example.

  The optical pickup device 23 includes a semiconductor laser as a light source, an optical system that guides a light beam emitted from the semiconductor laser to a recording surface of the optical disk 15 and guides a return light beam reflected by the recording surface to a predetermined light receiving position. A light receiving device arranged at the light receiving position for receiving the return light beam, a driving system (a focusing actuator, a tracking actuator, a seek motor, etc.) (all not shown), and the like are built therein.

  As an example, as shown in FIG. 2A, the light receiving device includes a four-divided light receiving element 80 (a first light receiving element 80a, a second light receiving element 80b, a third light receiving element 80c, and a fourth light receiving element). 80d). In FIG. 2A, for convenience, the vertical direction of the paper is defined as the X-axis direction, the horizontal direction of the paper is defined as the Y-axis direction, and the vertical direction of the paper is defined as the Z-axis direction. Each of the first light receiving element 80a and the second light receiving element 80b has the same rectangular shape whose long side is in the left-right direction (Y-axis direction) in FIG. 2A. Each of the third light receiving element 80c and the fourth light receiving element 80d has the same rectangular shape whose long side is the vertical direction (X-axis direction) in FIG. 2A. Then, a second light receiving element 80b is disposed in contact with the first light receiving element 80a on the lower side (-X side) of the first light receiving element 80a in FIG. A fourth light receiving element 80d is disposed in contact with the third light receiving element 80c on the left side (−Y side) of the third light receiving element 80c in FIG.

  As shown in FIG. 2B, the reflected light RB from the recording surface of the optical disc 15 is split in two directions by a prism 85 constituting the optical system of the optical pickup device 23, and one of the reflected lights transmitted through the prism 85. The light RB1 is applied to the first light receiving element 80a and the second light receiving element 80b. The other reflected light RB2 branched in the -X direction by the prism 85 is further bent in the + Z direction by the reflecting mirror 86, and is irradiated to the third light receiving element 80c and the fourth light receiving element 80d.

  Here, as shown in FIG. 3A, among the reflected lights RB, the reflected light RBa on the upper side of the paper surface in FIG. 3A is irradiated on the first light receiving element 80a, and The lower reflected light RBb is applied to the second light receiving element 80b. Further, as shown in FIG. 3B, of the reflected light RB, the reflected light RBc on the right side of the drawing in FIG. 3B is irradiated on the third light receiving element 80c, and the left side of the drawing in FIG. Is irradiated on the fourth light receiving element 80d. Each of the light receiving elements 80a to 80d performs photoelectric conversion, and outputs a current (current signal) corresponding to the amount of received light to the analog signal processing circuit 28 as a photoelectric conversion signal.

  The light receiver is not limited to the four-segment light receiving element 80. For example, a two-segment light receiving element including a first light receiving element 80a and a second light receiving element 80b, and a third light receiving element 80c And a two-divided light receiving element including the fourth light receiving element 80d. Further, four light receiving elements may be provided in parallel. Furthermore, the shape and arrangement of each light receiving element are not limited to the present embodiment.

  Referring back to FIG. 1, the analog signal processing circuit 28 includes an I / V amplifier (current-voltage conversion amplifier) unit 81 that converts a current signal, which is an output signal of the light receiving element 80a to 80d of the optical pickup device 23, into a voltage signal. A wobble signal detection circuit 30 for detecting a wobble signal, an RF signal detection circuit 82 for detecting an RF signal including reproduction information, and an error signal detection circuit 83 for detecting an error signal such as a focus error signal and a track error signal are provided. ing.

  As shown in FIG. 4, the I / V amplifier unit 81 includes a first I / V amplifier 81a that converts a current signal from the first light receiving element 80a into a voltage signal (signal Sa), and a second light receiving unit. A second I / V amplifier 81b that converts a current signal from the element 80b into a voltage signal (signal Sb), and a third I / V amplifier that converts a current signal from the third light receiving element 80c into a voltage signal (signal Sc). / V amplifier 81c and a fourth I / V amplifier 81d that converts a current signal from the fourth light receiving element 80d into a voltage signal (signal Sd).

  The RF signal detection circuit 82 adds the signal Sa, the signal Sb, the signal Sc, and the signal Sd, respectively, further binarizes the addition result, and detects the result as an RF signal.

  The error signal detection circuit 83 calculates the difference between the signal Sa and the signal Sb, binarizes the result, and detects the result as a focus error signal. Further, a difference between the signal Sc and the signal Sd is obtained, and the result is further binarized and detected as a track error signal. The focus error signal and the track error signal detected here are output from the error signal detection circuit 83 to the servo controller 33, respectively.

  The wobble signal detection circuit 30 detects a wobble signal from the signals Sc and Sd, and outputs it to the decoder 31. The configuration and the like of the wobble signal detection circuit 30 will be described later in detail.

  The decoder 31 extracts address information, a synchronization signal, and the like from ADIP information included in the wobble signal detected by the wobble signal detection circuit 30. The extracted address information is output to the CPU 40, and the synchronization signal is output from the decoder 31 to the encoder 25.

  Then, the decoder 31 performs reproduction processing such as demodulation and error correction processing on the RF signal detected by the RF signal detection circuit 82. Further, when the reproduction data is other than music data (for example, image data or document data), the decoder 31 performs an error check and an error correction process based on the check code added to the data. Stored in the buffer RAM 34.

  The servo controller 33 creates a control signal for controlling the focusing actuator of the optical pickup device 23 based on the focus error signal detected by the error signal detection circuit 83, and outputs the control signal to the motor driver 27. Further, the servo controller 33 creates a control signal for controlling the tracking actuator of the optical pickup device 23 based on the track error signal detected by the error signal detection circuit 83, and outputs the control signal to the motor driver 27.

  When the data recorded on the optical disk 15 is music data, the D / A converter 36 converts an output signal of the decoder 31 into analog data and outputs the analog signal to an audio device or the like as an audio signal.

  The buffer manager 37 manages the accumulation of data in the buffer RAM 34, and notifies the CPU 40 when the accumulated data amount reaches a predetermined value.

  The motor driver 27 drives the focusing actuator and the tracking actuator of the optical pickup device 23 based on a control signal from the servo controller 33. Further, the motor driver 27 controls the spindle motor 22 based on an instruction from the CPU 40 so that the linear velocity of the optical disk 15 is constant (CLV: Constant Linear Velocity) or the rotation speed is constant (CAV: Constant Angular Velocity). . Further, the motor driver 27 drives the seek motor of the optical pickup device 23 based on an instruction from the CPU 40, and controls the position of the optical pickup device 23 in the sledge direction (radial direction of the optical disk 15).

  The encoder 25 adds an error correction code to the data stored in the buffer RAM 34 and creates data to be written on the optical disk 15. Then, based on an instruction from the CPU 40, the write data is output to the laser control circuit 24 in synchronization with a synchronization signal from the decoder 31.

  The laser control circuit 24 controls the output of the semiconductor laser of the optical pickup device 23 based on the write data from the encoder 25. Then, the laser control circuit 24 outputs a timing signal synchronized with the mark recording period and the space recording period to the wobble signal detection circuit 30 during recording.

  The interface 38 is a bidirectional communication interface with a host (for example, a personal computer) and conforms to a standard interface such as an ATAPI (AT Attachment Packet Interface) and a SCSI (Small Computer System Interface).

  The CPU 40 controls the operation of each unit according to a program stored in the ROM 39, and temporarily stores data and the like necessary for the control in the RAM 41.

  Next, the configuration and the like of the wobble signal detection circuit 30 will be described with reference to FIGS.

  As shown in FIG. 5, the wobble signal detection circuit 30 includes a first signal extraction circuit 30a, a second signal extraction circuit 30b, a circuit selector 61, a band limiting circuit 62, a binarization circuit 63, and the like. I have.

  The first signal extraction circuit 30a includes a first space sample circuit 51a, a first sample signal adjustment circuit 52a, a first AC coupling circuit 53a, a second space sample circuit 51b, and a second sample signal adjustment circuit 52b. , A second AC coupling circuit 53b, an arithmetic processing circuit 90, and the like.

  The second signal extraction circuit 30b includes a first constant amplitude AGC 59a, a second constant amplitude AGC 59b, a first subtractor 60, and the like.

  As shown in FIG. 6, the arithmetic processing circuit 90 includes a first constant voltage AGC 57a, a first adder 54a, a first signal selection circuit 56a, a second constant voltage AGC 57b, a second adder 54b, a second signal selection circuit 56b, a second subtractor 58a, a third subtractor 58b, a fourth subtractor 58c, a third adder 54c, a switch 55a, a signal selector 55b, and the like. I have.

  Returning to FIG. 5, in the first space sampling circuit 51a, during recording, a signal component at the time of space is sampled with respect to the signal Sc in synchronization with the timing signal from the laser control circuit 24, and is output as the signal S1a. . Note that the signal level corresponding to the mark is a reference potential (reference level). The first space sampling circuit 51a does not perform sampling on the signal Sc during reproduction, and outputs the signal Sc as it is as the signal S1a.

  As shown in FIG. 7A, the first sample signal adjustment circuit 52a includes an amplitude adjustment circuit 64a, an amplifier 65a, a DC component removal circuit 66a, an output signal switch 67a, and the like.

  In the amplitude adjusting circuit 64a, the amplitude of the output signal S1a of the first space sampling circuit 51a is adjusted so as to be an appropriate signal level (not small enough to be buried in noise and not large enough to saturate). Here, at least two types of gains as adjustment gains are set in advance, and one of the gains is selected by an instruction from the CPU 40. In the present embodiment, as an example, of the two types of gains G1 and G2, G1 during reproduction and G2 during recording are selected by an instruction from the CPU 40.

  The amplifier 65a amplifies the output signal S1a of the first space sampling circuit 51a. Here, the amplification factor is set such that the signal level of the wobble signal component included in the signal S1a substantially matches the signal level of the wobble signal component included in the signal at the time of the mark in the signal Sc.

  The DC component removal circuit 66a removes a DC component included in the output signal of the amplifier 65a.

  The output signal changeover switch 67a is controlled by the CPU 40, thereby selecting either the output signal of the amplitude adjustment circuit 64a or the output signal of the DC component removal circuit 66a, and the output signal of the first sample signal adjustment circuit 52a. Output as S2a.

  Returning to FIG. 5, the first AC coupling circuit 53a removes a DC component included in the signal Sc and outputs the signal as a signal S3a.

  In the second space sampling circuit 51b, during recording, a signal component at the time of space is sampled with respect to the signal Sd in synchronization with a timing signal from the laser control circuit 24, and is output as a signal S1b. Note that the signal level corresponding to the mark is a reference potential (reference level). The second space sampling circuit 51b does not perform sampling on the signal Sd during reproduction, and outputs the signal Sd as it is as the signal S1b.

  Like the first sample signal adjustment circuit 52a, the second sample signal adjustment circuit 52b includes an amplitude adjustment circuit 64b, an amplifier 65b, a DC component removal circuit 66b, and an output signal switch 67b (all not shown). , And performs the same signal adjustment as the first sample signal adjustment circuit 52a on the output signal S1b of the second space sample circuit 51b, and outputs the signal as a signal S2b.

  The second AC coupling circuit 53b removes a DC component included in the signal Sd and outputs the signal as a signal S3b.

  In the arithmetic processing circuit 90, the output signal S2a of the first sample signal adjustment circuit 52a, the output signal S3a of the first AC coupling circuit 53a, the output signal S1b of the second space sampling circuit 51b, and the second AC coupling circuit 53b The output signal S3b is input and predetermined arithmetic processing is performed. The arithmetic processing circuit 90 will be described later in detail.

  As shown in FIG. 8A, the first constant amplitude AGC 59a includes a VCA circuit 75a, a filter circuit 76a, an amplitude detection circuit 77a, a gain setting circuit 78a, and the like, like the conventional constant amplitude AGC. I have. The filter circuit 76a removes high frequency components included in the output signal of the VCA circuit 75a. The amplitude detection circuit 77a detects the amplitude of the output signal of the filter circuit 76a. The gain setting circuit 78a sets the gain of the VCA circuit 75a based on the amplitude detected by the amplitude detection circuit 77a. The VCA circuit 75a adjusts the amplitude of the signal Sc based on the gain set by the gain setting circuit 78a.

  The second constant amplitude AGC 59b is configured similarly to the first constant amplitude AGC 59a, and adjusts the amplitude of the signal Sd. The output signal S1c of the first constant amplitude AGC 59a and the output signal S1d of the second constant amplitude AGC 59b are set to have the same amplitude.

  Returning to FIG. 5, the first subtractor 60 outputs the difference between the output signal S1c of the first constant amplitude AGC 59a and the output signal S1d of the second constant amplitude AGC 59b as a signal S9b.

  The circuit selector 61 is controlled by the CPU 40, thereby selecting either the output signal S9a of the arithmetic processing circuit 90 or the output signal S9b of the first subtractor 60, and outputs the signal S10. That is, the circuit selector 61 selects one of the first signal extraction circuit 30a and the second signal extraction circuit 30b.

  The band limiting circuit 62 has a BPF (Band Pass Filter) or the like, and extracts a wobble signal component from the output signal S10 of the circuit selector 61. Note that the band limiting circuit 62 may include an LPF (low-pass filter) instead of the BPF.

  The binarization circuit 63 is configured by a comparator or the like, binarizes the output signal of the band limiting circuit 62, and outputs it as a wobble signal.

  Here, the arithmetic processing circuit 90 will be described in detail.

  The first adder 54a adds the output signal S2a of the first sample signal adjustment circuit 52a and the output signal S3a of the first AC coupling circuit 57a and outputs the result as a signal S4a.

  As shown in FIG. 7B, the first constant voltage AGC 57a includes a VCA (voltage control amplifier) circuit 68a, a filter circuit 69a, a DC detection circuit 70a, a gain setting circuit 71a, a target voltage setting circuit 72a, And a speed setting circuit 73a.

  The target voltage setting circuit 72a is controlled by the CPU 40, and thereby sets a target voltage. In the present embodiment, the target voltage during reproduction is set to Vs, and the target voltage during recording is set to Vk. The speed setting circuit 73a is controlled by the CPU 40, thereby setting a response speed to an input signal. In the present embodiment, the response speed VRf is set immediately after switching from reproduction to recording or from recording to reproduction, and otherwise, the response speed VRs (<VRf) is set. The filter circuit 69a removes high frequency components included in the output signal of the VCA circuit 68a. The DC detection circuit 70a detects the average DC voltage level of the output signal of the filter circuit 69a. The gain setting circuit 71a sets the gain of the VCA circuit 68a so that the average DC voltage level detected by the DC detection circuit 70a matches the target voltage set by the target voltage setting circuit 72a. The VCA circuit 68a adjusts the output signal S6a of the first signal selection circuit 56a at the response speed set by the speed setting circuit 73a based on the gain set by the gain setting circuit 71a.

  The first signal selection circuit 56a is controlled by the CPU 40, thereby selecting any one of the output signal S6a of the first constant voltage AGC 57a and the output signal S4a of the first adder 54a, and sets the selected signal as the signal S7a. Output.

  The second adder 54b adds the output signal S2b of the second sample signal adjustment circuit 52b and the output signal S3b of the second AC coupling circuit 53b and outputs the result as a signal S4b.

  The second constant voltage AGC 57b is, like the first constant voltage AGC 57a, a VCA circuit 68b, a filter circuit 69b, a DC detection circuit 70b, a gain setting circuit 71b, a target voltage setting circuit 72b, and a speed setting circuit 73b. The signal level is adjusted so that the average DC voltage level of the output signal S6b of the second signal selection circuit 56b matches the target voltage, and is output as a signal S7b. Note that the target voltage and response speed at the second constant voltage AGC 57b are set to the same values as the target voltage and response speed at the first constant voltage AGC 57a, respectively.

  The second signal selection circuit 56b is controlled by the CPU 40, thereby selecting either the output signal S6b of the second constant voltage AGC 57b or the output signal S4b of the second adder 54b, and outputs the selected signal as the signal S7b. I do.

  The second subtractor 58a outputs a difference between the output signal S7a of the first signal selection circuit 56a and the output signal S7b of the second signal selection circuit 56b as a signal S8a. Here, since the wobble signal component included in the output signal S7a of the first signal selection circuit 56a and the wobble signal component included in the output signal S7b of the second signal selection circuit 56b are in opposite phases, substantially. The wobble signal component will be amplified.

  The third subtractor 58b outputs the difference between the signal S3a and the signal S3b.

  The fourth subtractor 58c outputs the difference between the signal S2a and the signal S2b.

  The third adder 54c adds the output signal of the third subtractor 58b and the output signal of the fourth subtractor 58c and outputs the result as a signal S8b.

  The switch 55a selects the output signal of the third subtractor 58b at the time of the mark and the output signal of the fourth subtractor 58c at the time of the space in synchronization with the timing signal from the laser control circuit 24, and outputs the signal S8c Is output as

  The signal selector 55b is controlled by the CPU 40, and thereby outputs any one of the output signal S8a of the second subtractor 58a, the output signal S8b of the third adder 54c, and the output signal S8c of the switch 55a. And outputs it as a signal S9a.

  Instead of the first constant voltage AGC 57a, as shown in FIG. 8B, a VCA circuit 68a ', a filter circuit 69a', an amplitude detection circuit 70a ', a gain setting circuit 71a', and a target amplitude setting circuit 72a. And a third constant amplitude AGC 57a 'including a speed setting circuit 73a' and the like.

  The target amplitude setting circuit 72a 'is controlled by the CPU 40, and thereby sets a target amplitude. Here, the target amplitude during reproduction and the target amplitude during recording are individually set. The speed setting circuit 73a 'is controlled by the CPU 40, thereby setting the response speed to the input signal. Here, similarly to the case of the first constant voltage AGC 57a, the response speed immediately after switching from reproduction to recording or from recording to reproduction is set to be higher than the response speed in other cases. The filter circuit 69a 'removes high frequency components included in the output signal of the VCA circuit 68a'. The amplitude detection circuit 70a 'detects the amplitude of the output signal of the filter circuit 69a'. The gain setting circuit 71a 'sets the gain of the VCA circuit 68a' so that the amplitude detected by the amplitude detection circuit 70a 'matches the target amplitude set by the target amplitude setting circuit 72a'. The VCA circuit 68a 'adjusts the output signal S6a of the first signal selection circuit 56a at the response speed set by the speed setting circuit 73a' based on the gain set by the gain setting circuit 71a '. That is, by adjusting the target amplitude, the output signal S6a 'of the third constant amplitude AGC 57a' can be a signal having the same waveform as the output signal S6a in the case of the first constant voltage AGC 57a. Similarly, instead of the second constant voltage AGC 57b, a VCA circuit 68b ', a filter circuit 69b', an amplitude detection circuit 70b ', a gain setting circuit 71b', a target amplitude setting circuit 72b ', and a speed setting circuit 73b' (all shown) A fourth constant-amplitude AGC 57b 'having an abbreviation) may be used.

  Next, a description will be given of a wobble signal detection processing operation in the wobble signal detection circuit 30 configured as described above.

  First, various settings are made by the CPU 40 in the wobble signal detection circuit 30 prior to detection of a wobble signal. Here, the setting process of the wobble signal detection circuit 30 will be described with reference to the flowchart of FIG. The flowchart of FIG. 9 corresponds to a series of processing algorithms executed by the CPU 40.

  In step 401, it is determined whether or not the optical disk 15 is a dye-type medium. If not, the determination is negative and the process proceeds to step 403. The dye-based media and the phase-change media can be distinguished from each other based on the intensity of light reflected from the recording surface of the optical disc 15. For example, the reflectivity of a dye-type medium such as DVD + R is about 80%, while the reflectivity of a phase-change medium such as DVD + RW is about 30%.

  In step 403, the circuit selector 61 is instructed to select the output signal S9b of the first subtractor 60. Then, the setting process ends.

  On the other hand, if it is determined in step 401 that the optical disk 15 is a dye-type medium, the determination in step 401 is affirmative, and the process proceeds to step 405.

  In step 405, the circuit selector 61 is instructed to select the output signal S9a of the arithmetic processing circuit 90.

  In step 407, it is determined whether or not the purpose of accessing the optical disk 15 is information recording. If not, the determination is negative and the process proceeds to step 409.

  At step 409, the amplitude adjustment circuits 64a and 64b are instructed to set the gain to G1.

  In step 411, the target voltage setting circuits 72a and 72b are instructed to set the target voltage to Vs.

  In step 413, the output signal changeover switch 67a is instructed so that the output signal of the amplitude adjustment circuit 64a becomes the output signal S2a of the first sample signal adjustment circuit 52a. Further, it instructs the output signal changeover switch 67b so that the output signal of the amplitude adjustment circuit 64b becomes the output signal S2b of the second sample signal adjustment circuit 52b.

  In step 415, the first signal selection circuit 56a is instructed to select the output signal S6a of the first constant voltage AGC 57a. Then, it instructs the second signal selection circuit 56b to select the output signal S6b of the second constant voltage AGC 57b.

  In step 419, the signal selector 55b is instructed to select the output signal S8a of the second subtractor 58a. Then, the setting process ends.

  On the other hand, if the purpose of accessing the optical disc 15 is to record information in step 407, the determination in step 407 is affirmative, and the process proceeds to step 421.

  In step 421, the control unit instructs the amplitude adjustment circuits 64a and 64b to set the gain to G2.

  In step 423, the target voltage setting circuits 72a and 72b are instructed to set the target voltage to Vk.

  In step 425, it is determined whether or not a wobble signal is to be detected based only on the space signal. When the wobble signal is detected based on only the signal at the time of the space according to the instruction from the host, the determination here is affirmed, and the process proceeds to step 427.

  In step 427, the output signal changeover switch 67a is instructed so that the output signal of the amplitude adjustment circuit 64a becomes the output signal S2a of the first sample signal adjustment circuit 52a. Then, it instructs the output signal changeover switch 67b so that the output signal of the amplitude adjustment circuit 64b becomes the output signal S2b of the second sample signal adjustment circuit 52b.

  In step 429, the first signal selection circuit 56a is instructed to select the output signal S6a of the first constant voltage AGC 57a. Then, it instructs the second signal selection circuit 56b to select the output signal S6b of the second constant voltage AGC 57b.

  In step 433, the signal selector 55b is instructed to select the output signal S8a of the second subtractor 58a. Then, the setting process ends.

  On the other hand, when the wobble signal is detected based on both the signal at the time of the space and the signal at the time of the mark according to the instruction from the host in the step 425, the determination in the step 425 is affirmed, and the process proceeds to the step 435.

  In step 435, the output signal changeover switch 67a is instructed so that the output signal of the DC component removal circuit 66a becomes the output signal S2a of the first sample signal adjustment circuit 52a. Further, it instructs the output signal changeover switch 67b so that the output signal of the DC component removal circuit 66b becomes the output signal S2b of the second sample signal adjustment circuit 52b.

  In step 437, it is determined whether to switch between the signal at the time of space and the signal at the time of mark. In the case where the signal at the time of space and the signal at the time of mark are switched according to an instruction from the host, the determination here is affirmative, and the process proceeds to step 439.

  In step 439, the signal selector 55b is instructed to select the output signal S8c of the switch 55a. Then, the setting process ends.

  On the other hand, in step 437, when the signals at the time of the mark and the signal at the time of the mark are added without being switched according to the instruction from the host, the determination in step 437 is affirmative, and the process proceeds to step 441.

  In step 441, it is determined whether or not the output signal S8a of the second subtractor 58a is selected for the signal selector 55b. If the output signal S8a of the second subtractor 58a is not selected according to an instruction from the host, the determination here is negative and the process proceeds to step 443.

  In step 443, the signal selector 55b is instructed to select the output signal S8b of the third adder 54c. Then, the setting process ends.

  On the other hand, in step 441, when the output signal S8a of the second subtractor 58a is selected according to an instruction from the host, the determination in step 441 is affirmative, and the second subtractor 58a is supplied to the signal selector 55b. And then proceeds to step 445.

  In step 445, the first signal selection circuit 56a is instructed to select the output signal S4a of the first adder 54a. Then, it instructs the second signal selection circuit 56b to select the output signal S4b of the second adder 54b. Then, the setting process ends.

  The CPU 40 instructs the speed setting circuits 73a and 73b to set the speed during recording.

  Next, the processing operation in the wobble signal detection circuit 30 will be described. As shown in FIG. 9, a wobble signal detected when there is no influence from a change in laser light output is an ideal wobble signal.

  [Wobble signal detection processing when recording information on dye-type media]

  (A). A case where a wobble signal is detected based on only a signal in a space according to an instruction from the host will be described. It is assumed that the setting of the wobble signal detection circuit 30 corresponding thereto has already been made by the CPU 40. The laser light output actually has a complicated shape, but here, for convenience, it is assumed that the laser light output has a rectangular pulse shape corresponding to the recording data, as shown in FIG.

  The first space sampling circuit 51a samples a space-time signal component of the signal Sc in synchronization with the timing signal from the laser control circuit 24, and outputs it to the first sample signal adjustment circuit 52a. The second space sampling circuit 51b samples a space-time signal component of the signal Sd in synchronization with the timing signal from the laser control circuit 24, and outputs the signal to the second sample signal adjustment circuit 52b.

  In the first sample signal adjustment circuit 52a, the amplitude adjustment circuit 64a performs amplitude adjustment on the output signal (signal S1a) of the first space sample circuit 51a with the gain G2, and as an example, the waveform shown in FIG. (Signal S2a) is output via the output signal changeover switch 67a. Similarly, in the second sample signal adjustment circuit 52b, the amplitude adjustment circuit 64b performs amplitude adjustment on the output signal (signal S1b) of the second space sample circuit 51b with the gain G2. The signal having the waveform shown (signal S2b) is output via the output signal switch 67b.

  In the first constant voltage AGC 57a, the signal S2a is adjusted so that the average DC voltage level matches the target voltage Vk. For example, a signal (signal S6a) having a waveform shown in FIG. 10 is converted to a first signal selection circuit 56a. Output to The second constant voltage AGC 57b adjusts the signal S2b so that the average DC voltage level matches the target voltage Vk. For example, a signal (signal S6b) having a waveform shown in FIG. 10 is converted to a second signal selection circuit 56b. Output to

  The first signal selection circuit 56a selects the output signal S6a of the first constant voltage AGC 57a and outputs it to the second subtractor 58a. The second signal selection circuit 56b selects the output signal S6b of the second constant voltage AGC 57b and outputs it to the second subtractor 58a.

  The second subtractor 58a subtracts the output signal S7b (same as S6b) of the second signal selection circuit 56b from the output signal S7a (same as S6a) of the first signal selection circuit 56a. The signal having the waveform shown (signal S8a) is output to the signal selector 55b.

  The signal selector 55b selects the output signal S8a of the second subtractor 58a and outputs it as a signal S9a. The circuit selector 61 selects the output signal S9a of the signal selector 55b and outputs it as a signal S10. The band limiting circuit 62 extracts a wobble signal component from the signal S10. The wobble signal component is binarized by the binarization circuit 72 and output to the decoder 31 as a wobble signal.

  (B). A case where a wobble signal is detected based on both a signal at the time of a space and a signal at the time of a mark according to an instruction from the host will be described. In addition, it is assumed that the signal switching between the space signal and the mark signal is not performed by the instruction from the host, and the signal selector 55b does not select the signal S8b. It is also assumed that the setting of the wobble signal detection circuit 30 corresponding thereto has already been made by the CPU 40.

  The first space sampling circuit 51a samples a space-time signal component of the signal Sc in synchronization with the timing signal from the laser control circuit 24, and outputs it to the first sample signal adjustment circuit 52a. The second space sampling circuit 51b samples a space-time signal component of the signal Sd in synchronization with the timing signal from the laser control circuit 24, and outputs the signal to the second sample signal adjustment circuit 52b.

  In the first sample signal adjustment circuit 52a, the output signal (signal S1a) of the first space sample circuit 51a is amplified by the AMP 65a, and the DC component is removed by the DC component removal circuit 66a. Is output via the output signal changeover switch 67a. Similarly, in the second sample signal adjusting circuit 52b, the signal S1b is amplified by the AMP 65b, the DC component is removed by the DC component removing circuit 66b, and a signal (signal S2b) having a waveform shown in FIG. 11 is output as an example. The signal is output via the signal switch 67b.

  The first AC coupling circuit 53a removes a DC component included in the signal Sc and outputs a signal (signal S3a) having a waveform shown in FIG. 11 as an example. Further, the second AC coupling circuit 53b removes a DC component included in the signal Sd, and outputs a signal (signal S3b) having a waveform shown in FIG. 11 as an example.

  The third subtractor 58b outputs the difference between the signal S3a and the signal S3b. The fourth subtractor 58c outputs the difference between the signal S2a and the signal S2b.

  The third adder 54c adds the output signal of the third subtractor 58b and the output signal of the fourth subtractor 58c and outputs the result as a signal S8b.

  The signal selector 55b selects the output signal S8b of the third adder 54c and outputs it as a signal S9a. The circuit selector 61 selects the output signal S9a of the signal selector 55b and outputs it as a signal S10. The band limiting circuit 62 extracts a wobble signal component from the signal S10. The wobble signal component is binarized by the binarization circuit 72 and output to the decoder 31 as a wobble signal.

  (C). A case where a wobble signal is detected based on both a signal at the time of a space and a signal at the time of a mark according to an instruction from the host will be described. Further, it is assumed that the signal switching between the signal at the time of the space and the signal at the time of the mark is not performed by the instruction from the host, and the signal selector 55b selects the signal S8b. It is assumed that the setting of the wobble signal detection circuit 30 corresponding to the setting has already been made by the CPU 40.

  Note that the processing other than the processing in the arithmetic processing circuit 90 is the same as that in the case of (B) described above, and therefore, only the processing in the arithmetic processing circuit 90 will be described here.

  The first adder 54a adds the signal S2a and the signal S3a, and outputs the result as a signal S4a to the first signal selection circuit 56a. The second adder 54b adds the signal S2b and the signal S3b and outputs the result as a signal S4b to the second signal selection circuit 56b.

  The first signal selection circuit 56a selects the output signal S4a of the first adder 54a and outputs it as a signal S7a to the second subtractor 58a. Further, the second signal selection circuit 56b selects the output signal S4b of the second adder 54b and outputs it as a signal S7b to the second subtractor 58a.

  The second subtractor 58a outputs the difference between the output signal S7a and the output signal S7b to the circuit selector 61 as a signal S8a. The circuit selector 61 selects the output signal S8a of the second subtractor 58a and outputs it as a signal S9a.

  (D). A case where a wobble signal is detected based on a signal at the time of a space and a signal at the time of a mark according to an instruction from the host will be described. Further, it is assumed that the signal switching between the signal at the time of the space and the signal at the time of the mark is performed according to an instruction from the host. It is assumed that the setting of the wobble signal detection circuit 30 corresponding thereto has already been made by the CPU 40.

  Note that the processing other than the processing in the arithmetic processing circuit 90 is the same as that in the case of (B) described above, and therefore, only the processing in the arithmetic processing circuit 90 will be described here.

  The third subtractor 58b outputs the difference between the signal S3a and the signal S3b. The fourth subtractor 58c outputs the difference between the signal S2a and the signal S2b.

  The switch 55a selects the output signal of the third subtractor 58b at the time of a mark, and selects the output signal of the fourth subtractor 58c at the time of a space, in synchronization with the timing signal from the laser control circuit 24. To the signal selector 55b.

  The signal selector 55b selects the output signal S8c of the switch 55a and sets it as the signal S9a.

  [Wobble signal detection processing when recording on phase change media]

  Here, it is assumed that the setting of the wobble signal detection circuit 30 has already been performed by the CPU 40. That is, the second signal extraction circuit 30b is selected.

  The first constant amplitude AGC 59a adjusts the amplitude of the signal Sc so that the amplitude becomes a predetermined level, and then outputs the signal Sc to the second subtractor 60. The second constant amplitude AGC 59b adjusts the amplitude of the signal Sd so that the amplitude of the signal Sd becomes a predetermined level, and outputs the signal to the second subtractor 60.

  The second subtracter 60 subtracts the output signal S1d of the second constant amplitude AGC 59b from the output signal S1c of the first constant amplitude AGC 59a and outputs the result to the circuit selector 61. The circuit selector 61 outputs the output signal S8b of the second subtractor 60 to the band limiting circuit 62. The band limiting circuit 62 extracts a wobble signal component from the signal S8b. The wobble signal component is binarized by the binarization circuit 72 and output to the decoder 31 as a wobble signal.

  [Wobble signal detection processing when reproducing information from dye-type media]

  Here, it is assumed that the setting of the wobble signal detection circuit 30 has already been performed by the CPU 40.

  The first space sampling circuit 51a outputs the signal Sc as it is to the first sample signal adjustment circuit 52a. Further, the second space sampling circuit 51b outputs the signal Sd as it is to the second sample signal adjustment circuit 52b.

  In the first sample signal adjustment circuit 52a, the amplitude adjustment circuit 64a performs amplitude adjustment on the output signal S1a (same as Sc) of the first space sample circuit 51a with the gain G1, and switches the output signal as the signal S2a. Output via switch 67a. Similarly, in the second sample signal adjustment circuit 52b, the amplitude adjustment circuit 64b performs amplitude adjustment on the output signal S1b (same as Sd) of the second space sample circuit 51b with the gain G1 to obtain a signal S2b. The signal is output via the output signal changeover switch 67b.

  In the first constant voltage AGC 57a, the output signal S2a of the first sample signal adjustment circuit 52a is adjusted so that the average DC voltage level matches the target voltage Vs, and the signal (signal S6a) having the waveform shown in FIG. ) Is output to the first signal selection circuit 56a. In the second constant voltage AGC 57b, the output signal S2b of the second sample signal adjustment circuit 52b is adjusted so that the average DC voltage level matches the target voltage Vs, and a signal having a waveform shown in FIG. ) Is output to the second signal selection circuit 56b.

  The first signal selection circuit 56a selects the output signal S6a of the first constant voltage AGC 57a and outputs it to the second subtractor 58a. The second signal selection circuit 56b selects the output signal S6b of the second constant voltage AGC 57b and outputs it to the second subtractor 58a.

  The second subtractor 58a subtracts the output signal S7b of the second constant voltage AGC 57b from the output signal S7a of the first constant voltage AGC 57a, and outputs a signal (signal S8a) having a waveform shown in FIG. 12 to the signal selector 55b. Output.

  The signal selector 55b selects the output signal S8a of the second subtractor 58a and outputs it as a signal S9a. The circuit selector 61 selects the output signal S9a of the signal selector 55b and outputs it as a signal S10. The band limiting circuit 62 extracts a wobble signal component from the signal S10. The wobble signal component is binarized by the binarization circuit 72 and output to the decoder 31 as a wobble signal.

  Next, a processing operation when data is recorded on the optical disk 15 using the above-described optical disk device 20 will be described.

  When receiving a recording request from the host via the interface 38, the CPU 40 outputs a control signal for controlling the rotation of the spindle motor 22 to the motor driver 27 based on the recording speed specified by the host.

  The wobble signal detection circuit 30 detects the wobble signal based on the output signals Sc and Sd from the optical pickup device 23 as described above, and outputs the same to the decoder 31. The decoder 31 extracts ADIP information from the wobble signal and notifies the CPU 40 of the extracted ADIP information. Here, when it is determined that an error is included in the ADIP information based on, for example, an error detection code added to the ADIP information, the decoder 31 notifies the CPU 40 of the detection error of the ADIP information. The CPU 40 measures the detection error rate of the ADIP information, and when the error rate exceeds a predetermined value, stops the data recording operation and notifies the host to that effect.

  The error signal detection circuit 83 detects a focus error signal and a track error signal based on an output signal from the optical pickup device 23, and outputs the signals to the servo controller 33. The servo controller 33 drives the focusing actuator and the tracking actuator of the optical pickup device 23 via the motor driver 27 based on the focus error signal and the track error signal from the error signal detection circuit 83, and corrects the focus shift and the track shift. I do.

  When receiving data from the host, the CPU 40 accumulates the data in the buffer RAM 34 via the buffer manager 37. When the amount of data stored in the buffer RAM 34 exceeds a predetermined value, the buffer manager 37 notifies the CPU 40.

  Upon receiving the notification from the buffer manager 37, the CPU 40 instructs the encoder 25 to create write data. The encoder 25 takes out the data from the buffer RAM 34, adds an error correction code and the like, and creates write data.

  Then, based on the ADIP information from the decoder 31, the CPU 40 outputs to the motor driver 27 a signal instructing a seek operation of the optical pickup 23 so that the optical pickup 23 is located at a predetermined write start point.

  When the CPU 40 determines that the position of the optical pickup 23 is the writing start point based on the ADIP information, the CPU 40 notifies the encoder 25. Then, the encoder 25 records the write data on the optical disk 15 via the laser control circuit 24 and the optical pickup 23. In the encoder 25, the rotation speed of the spindle motor 22 is synchronized with the synchronization signal from the decoder 31. Thereby, writing at an accurate position is performed.

  Further, when switching between recording and reproduction, the CPU 40 instructs the speed setting circuits 73a and 73b so that the response speed of the constant voltages AGC 57a and 57b becomes VRf. As a result, the response speed at the constant voltage AGC 57a, 57b increases. During recording and reproduction, the CPU 40 instructs the speed setting circuits 73a and 73b so that the response speed of the constant voltages AGC 57a and 57b becomes VRs. As a result, the response speed at the constant voltages AGC 57a and 57b decreases. The instructions to the speed setting circuits 73a and 73b may be issued from the encoder 25 instead of the CPU 40.

  A processing operation for reproducing data recorded on the optical disk 15 using the optical disk device 20 will be described.

  When receiving the reproduction request from the host, the CPU 40 outputs a control signal for controlling the rotation of the spindle motor 22 to the motor driver 27 based on the reproduction speed.

  The wobble signal detection circuit 30 detects the wobble signal based on the output signals Sc and Sd from the optical pickup device 23 as described above, and outputs the same to the decoder 31. The decoder 31 extracts ADIP information from the wobble signal and notifies the CPU 40 of the extracted ADIP information. When the decoder 31 determines that the ADIP information contains an error based on, for example, an error detection code added to the ADIP information, the decoder 31 notifies the CPU 40 of the detection error of the ADIP information. The CPU 40 measures the detection error rate of the ADIP information, and when the error rate exceeds a predetermined value, stops the data reproducing operation and notifies the host to that effect.

  The error signal detection circuit 83 detects a focus error signal and a track error signal based on an output signal from the optical pickup device 23, and outputs the signals to the servo controller 33. The servo controller 33 drives the focusing actuator and the tracking actuator of the optical pickup device 23 via the motor driver 27 based on the focus error signal and the track error signal from the error signal detection circuit 83, and corrects the focus shift and the track shift. I do.

  The CPU 40 outputs a signal for instructing a seek operation to the motor driver 27 so that the optical pickup device 23 is located at a predetermined reading start point based on the ADIP information.

  The CPU 40 checks whether or not the read start point is based on the ADIP information, and notifies the RF signal detection circuit 82 when it determines that the position of the optical pickup device 23 is the read start point. Then, the RF signal detection circuit 82 detects the RF signal based on the output signal of the optical pickup device 23 and outputs the RF signal to the decoder 31. The decoder 31 performs error correction processing and the like on the RF signal.

  If the data recorded on the optical disk 15 is music data, the output signal of the decoder 31 is converted into analog data by the D / A converter 36 and output to audio equipment or the like.

  On the other hand, when the data recorded on the optical disk 15 is other than music data, the decoder 31 further performs an error check and an error correction process and the like, and stores the data in the buffer RAM 34.

  The buffer manager 37 transfers the data stored in the buffer RAM 34 to the host via the interface 38 when the data is prepared as sector data.

  As is clear from the above description, in the wobble signal detection circuit according to the present embodiment, the second subtractor 58a forms a subtraction circuit, and the third constant amplitude AGC 57a 'forms a first amplitude adjustment circuit. The fourth constant amplitude AGC 57b 'forms a second amplitude adjustment circuit.

  In the optical disk device according to the present embodiment, a processing device is configured by the CPU 40, the encoder 25, and the laser control circuit 24.

  As described above, according to the wobble signal detection circuit according to the present embodiment, when information is recorded on the optical disc 15, the first space sample circuit 51a synchronizes with the timing signal from the laser control circuit to generate the third signal. By sampling the voltage signal Sc corresponding to the photoelectric conversion signal from the light receiving element 80c, a signal in the space recording period is extracted from the voltage signal Sc. Similarly, the second space sampling circuit 51b samples the voltage signal Sd corresponding to the photoelectric conversion signal from the fourth light receiving element 80d in synchronization with the timing signal, so that the signal in the space recording period is converted from the voltage signal Sd. Is extracted. That is, a signal when the laser light output is small and stable is extracted. In the first constant voltage AGC 57a, the signal level is adjusted so that the average voltage level of the output signal of the first space sampling circuit 51a matches the target voltage. Similarly, at the second constant voltage AGC 57b, the signal level is adjusted so that the average voltage level of the output signal of the second space sampling circuit 51b matches the target voltage. Since the average voltage level of the sampled signal is much smaller than the target voltage, the level is adjusted with a large gain. That is, the wobble signal component is greatly amplified. As a result, for example, it is possible to accurately extract a wobble signal component in a space recording period that has been buried in a noise component in signal adjustment by a conventional constant-amplitude AGC circuit. The second subtractor 58a outputs a difference between the output signal of the first constant voltage AGC 57a and the output signal of the second constant voltage AGC 57b as a wobble signal. Since the wobble signal component is amplified, the wobble signal can be accurately detected even when only the signal in the space is used. Further, since the wobble signal is detected by extracting the wobble signal component in the space recording period, the laser light output at the time of the mark is smaller than the laser light output at the time of the space, for example, when information is recorded on a DVD + R. Is not affected by the laser light output. Of course, it is possible to obtain a high-quality wobble signal even on a rewritable optical disk in which the difference between the laser light output at the time of marking and the laser light output at the time of space is not so large. That is, it is possible to accurately detect a wobble signal for a plurality of types of optical recording media. Further, in the first constant voltage AGC 57a and the second constant voltage AGC 57b, since the same target voltage is set, the reflected light from the recording surface of the optical disk 15 is shifted from the center of the light receiving surface of the light receiving element. The wobble signal can be detected with high accuracy even if the wobble signal is received.

  In this embodiment, the amplitude of the output signal of the space sample circuit is adjusted with different gains during reproduction and during recording. Since the laser light output during reproduction and the laser light output during recording are significantly different, the amplitude of the output signal of the space sample circuit during reproduction and the amplitude of the output signal of the space sample circuit during recording are large. Is different. Therefore, the dynamics of the first constant voltage AGC 57a and the second constant voltage AGC 57b are set by setting the respective gains so that the amplitude of the output signal of the space sample circuit becomes a predetermined level at both the time of reproduction and the time of recording. The range can be effectively used, and the wobble signal can be detected with high accuracy both during reproduction and during recording. Note that the amplitude adjustment circuits 64a and 64b may be arranged in front of the space sampling circuits 51a and 51b, respectively.

  Furthermore, in the present embodiment, the CPU 40 instructs the target voltage setting circuit for the constant voltage AGC to set different target voltages for recording and reproduction. Usually, the amplitude of the output signal from the optical pickup device 23 during reproduction (hereinafter, referred to as “output signal during reproduction”) is the output signal from the optical pickup device 23 during recording (hereinafter, “output signal during recording”). For example, if the same target voltage is set at the time of recording and at the time of reproduction, the output signal at the time of recording at the constant voltage AGC is larger than the output signal at the time of reproduction. Amplified more than That is, the amplitude of the wobble signal component is larger during recording than during reproduction. It is not sufficient that the amplitude of the wobble signal component is large, and it must be detected at a predetermined amplitude in order to extract additional information such as ADIP information with high accuracy. Therefore, in the present embodiment, different target voltages are set for recording and reproduction so that the amplitude of the wobble signal component is substantially equal between recording and reproduction. Therefore, the wobble signal can be accurately detected during recording and reproduction. Also, since the target voltage at the time of recording is set so that the signal level of the wobble signal detected at the time of recording substantially matches the signal level of the wobble signal detected at the time of reproduction, Erroneous detection of the wobble signal can be prevented. That is, the wobble signal can be accurately and stably detected.

  In the present embodiment, the CPU 40 sets the target speed VRf in the target speed setting circuit for the constant voltage AGC immediately after the switching between the recording and the reproduction, and sets the target speed VRs when the recording and the reproduction are started. (<VRf). Thereby, even if the signal level of the wobble signal detected at the time of recording is different from the signal level of the wobble signal detected at the time of reproduction, the wobble signal can be stably detected immediately after switching between recording and reproduction. In addition, since a slow response speed is set during recording, it is possible to prevent the optical disk 15 from following a change in signal amplitude due to a scratch or the like that should not originally be followed. Therefore, the wobble signal can be accurately and stably detected.

  In addition, in the present embodiment, when information is recorded on the optical disc 15, the signal level of the wobble signal included in the output signals of the space sampling circuits 51a and 51b is the same as the signal level of the wobble signal at the time of marking. The amplitudes of the output signals of the space sampling circuits 51a and 51b are amplified by AMPs 65a and 65b, respectively. Then, the signal amplified by the AMP 65a and the voltage signal Sc from the third light receiving element 80c are added by the first adder 54a, and the signal amplified by the AMP 65b and the voltage signal from the fourth light receiving element 80d are added. Sd is added by the second adder 54b. Thus, the wobble signal component in the space recording period and the wobble signal component in the mark recording period are added at almost the same signal level. Then, the difference between the output signal of the first adder 54a and the output signal of the second adder 54b is output by the second subtractor 58a. Therefore, a highly accurate wobble signal is stably output from the second subtractor 58a.

  Further, in the present embodiment, when information is recorded on the optical disc 15, the difference between the signal amplified by the AMP 65a and the signal amplified by the AMP 65b is output by the third subtractor 58b. As a result, a wobble signal is output during the space recording period. The fourth subtractor 58c outputs the difference between the voltage signal Sc from the third light receiving element 80c and the voltage signal Sd from the fourth light receiving element 80d. As a result, a wobble signal is output during the mark recording period. Then, in the third adder 54c, the output signal of the third subtractor 58b and the output signal of the fourth subtractor 58c are added. That is, the wobble signal in the space recording period and the wobble signal in the mark recording period are added. Accordingly, a high-accuracy wobble signal is stably output from the third adder 54c.

  Further, in the present embodiment, when recording information on the optical disk 15, the switch 55a selects the output signal of the third subtractor 58b during the space recording period in synchronization with the timing signal from the laser control circuit. During the mark recording period, the output signal of the fourth subtractor 58c is selected and output. That is, the wobble signal in the space recording period and the wobble signal in the mark recording period are combined. As a result, it is possible to prevent the occurrence of noise due to circuit delay, rounded waveforms, and the like at the transition between the mark and the space. Therefore, a high-precision wobble signal is stably output from the switch 55a.

  Further, in the present embodiment, when the average voltage of the signal input to the arithmetic processing circuit 90 is greatly deviated from the reference voltage, the arithmetic processing circuit 90 needs a very wide dynamic range. If the signal levels of the output signals Sc and Sd from the optical pickup device 23 are significantly different, an offset occurs in the detected wobble signal. However, in this embodiment, the AC coupling circuits 53a and 53b and the DC component removing circuits 66a and 66b are arranged at the preceding stage of the arithmetic processing circuit 90 to remove the DC component included in the signal. There is no need to particularly widen the dynamic range at. Further, even when the signal levels of the output signals Sc and Sd from the optical pickup device 23 are significantly different, no offset occurs in the detected wobble signal. Therefore, the arithmetic processing circuit 90 can be inexpensively constructed using electronic parts and the like which are mass-produced and generally commercially available.

  In the present embodiment, the circuit selector 61 selects the first signal extraction circuit 30a when the optical disk 15 is a dye-type medium, and selects the second signal extraction circuit 30a when the optical disk 15 is not a dye-type medium. 30b is selected. As a result, an optimal circuit configuration is selected according to the type of the optical disk 15, and therefore, a wobble signal can be detected with high accuracy in correspondence with a plurality of types of optical disks.

  In the present embodiment, a third constant amplitude AGC 57a 'can be used instead of the first constant voltage AGC 57a, and a fourth constant amplitude AGC 57b' can be used instead of the second constant voltage AGC 57b. The target amplitude setting circuits 72a 'and 72b' individually set the target amplitudes of the constant amplitude AGCs 57a 'and 57b'. For example, by setting the target amplitude at the time of recording so that the signal level of the wobble signal detected at the time of recording substantially matches the signal level of the wobble signal detected at the time of reproduction, the wobble signal immediately after switching between recording and reproduction is set. Erroneous detection can be prevented. That is, the wobble signal can be accurately and stably detected. In the speed setting circuits 73a 'and 73b', the response speed to the input signal is individually set according to the control signal so that the response speed immediately after switching between recording and reproduction is higher than the response speed during recording. Therefore, even if the signal level of the wobble signal detected at the time of recording is different from the signal level of the wobble signal detected at the time of reproduction, it is possible to stably detect the wobble signal immediately after switching between recording and reproduction. In addition, since a slow response speed is set during recording, it does not follow a signal change due to a scratch on the optical disk 15 or the like. Therefore, the wobble signal can be accurately and stably detected.

  According to the optical disc device of the present embodiment, when information is recorded on the optical disc 15, the wobble signal detection circuit 30 can accurately detect a wobble signal on a plurality of types of optical discs. Thus, it is possible to stably perform highly reliable and good recording on a plurality of types of optical discs.

  In the above embodiment, the output signals of the space sampling circuits 51a and 51b are adjusted by the amplitude adjustment circuits 64a and 64b, respectively. However, if the output signals of the space sampling circuits 51a and 51b are at a predetermined level, the amplitude adjustment is performed. The circuits 64a and 64b are not always necessary.

  In the above-described embodiment, the DC components are removed by the AC coupling circuits 53a and 53b and the DC component removal circuits 66a and 66b. However, the average voltage of the signal input to the arithmetic processing circuit 90 is slightly different from the reference voltage. When there is no shift, the AC coupling circuits 53a and 53b and the DC component removal circuits 66a and 66b are not necessarily required.

  Further, in the above-described embodiment, different target voltages are set for the constant voltages AGC 55a and 55b at the time of recording and at the time of reproduction by the target voltage setting circuits 72a and 72b, respectively. The target voltage setting circuits 72a and 72b are not necessarily required when a signal of a predetermined level is obtained even if the target voltage at the time is the same.

  In the above-described embodiment, the case where the constant voltages AGC 55a and 55b include both the target voltage setting circuits 72a and 72b and the speed setting circuits 73a and 73b is described. However, the present invention is not limited to this. You may have. Similarly, a case has been described where the constant amplitude AGCs 55a 'and 55b' include both the target amplitude setting circuits 72a 'and 72b' and the speed setting circuits 73a 'and 73b'. However, the present invention is not limited to this. Only may be provided.

  Further, in the above embodiment, either the first signal extraction circuit 30a or the second signal extraction circuit 30b is selected according to the type of the optical disc 15, but the present invention is not limited to this, and three or more types of signal extraction circuits are used. And one circuit may be selected from them. Further, only the first signal extraction circuit 30a may be used. In this case, the circuit selector 61 is unnecessary, and the wobble signal is detected by the first signal extraction circuit 30a regardless of the type of the optical disk 15.

  Furthermore, the above embodiment includes a circuit for detecting a wobble signal from a signal only at the time of space and a circuit for detecting a wobble signal from both signals at the time of space and at the time of marking. May be included. For example, when a wobble signal is always detected from a signal only at the time of space, the first signal extraction circuit 30a includes the space sampling circuits 51a and 51b, the amplitude adjustment circuits 64a and 64b, the constant voltages AGC 57a and 57b, and the second signal extraction circuit 30a. It is sufficient that the subtractor 58a of the second embodiment is included. In addition, when the wobble signal is detected from both the signal at the time of the space and the signal at the time of the mark, and the switching is always performed between the time of the mark and the time of the space, the third adder 54c is unnecessary. In addition, when the switching between the mark and the space is not always performed, the switch 55a is unnecessary.

  In the above embodiment, when a wobble signal is detected from both the space signal and the mark signal, an added signal obtained by adding the signal S2a and the signal S3a and an added signal obtained by adding the signal S2b and the signal S3b are used. And a circuit for detecting a wobble signal from an addition signal obtained by adding a subtraction signal obtained by subtracting the signal S2b from the signal S2a and a subtraction signal obtained by subtracting the signal S3b from the signal S3a. However, only one of the circuits may be provided.

  In the above embodiment, the space sampling circuits 51a and 51b extract the signal components at the time of space from the output signals Sc and Sd from the optical pickup device 23, but instead of the space sampling circuits 51a and 51b. Alternatively, a signal component at the time of space may be extracted using a sample hold circuit.

  In the above embodiment, the case where the optical disk 15 is a DVD has been described. However, the present invention is not limited to this, and any optical recording medium on which a wobble signal is recorded may be used.

  In the above embodiment, the case where ADIP information is extracted from a wobble signal has been described. However, the present invention is not limited to this. For example, in the case of a CD, ATIP (Absolute Time In Pregroove) information is extracted from the wobble signal. May be extracted.

  In the above-described embodiment, the case where one of the two types of gains is selected by the instruction of the CPU 40 in the amplitude adjustment circuits 64a and 64b has been described. However, the present invention is not limited to this. One of the gains may be selected. Instead of selecting from preset gains, the CPU 40 may set an arbitrary value of gain.

  The optical disk device 20 according to the embodiment may be a so-called built-in type, which is disposed in the same housing as the host, or a so-called external type, which is disposed in a housing different from the host. There may be.

  As described above, the wobble signal detection circuit of the present invention is suitable for detecting a wobble signal at the time of recording information on each of a plurality of types of optical recording media. Further, the optical disk device of the present invention can support a plurality of types of optical recording media, and is suitable for recording information on each of the information recording media.

FIG. 1 is a block diagram illustrating a configuration of an optical disc device according to an embodiment of the present invention. FIGS. 2A and 2B are diagrams illustrating an example of a configuration of a light receiving element included in a light receiver. FIGS. 3A and 3B are diagrams for explaining a portion of the reflected light irradiated to the light receiving element. FIG. 2 is a block diagram for explaining a configuration of an I / V amplifier unit in FIG. 1. FIG. 2 is a block diagram illustrating a configuration of a wobble signal detection circuit in FIG. 1. FIG. 2 is a block diagram illustrating a configuration of an arithmetic processing circuit in FIG. 1. FIG. 7A is a block diagram for explaining the configuration of the first sample signal adjustment circuit of FIG. 1, and FIG. 7B is a diagram for explaining the configuration of the first constant voltage AGC of FIG. FIG. FIG. 8A is a block diagram for explaining the configuration of the first constant amplitude AGC of FIG. 1, and FIG. 8B is a third constant amplitude AGC used in place of the first constant voltage AGC. FIG. 3 is a block diagram for describing a configuration of an amplitude AGC. 9 is a flowchart for explaining setting of a wobble signal detection circuit by a CPU. FIG. 4 is a diagram for explaining a part of a signal waveform in a wobble signal detection circuit when detecting a wobble signal only with a signal in a space when recording information on a dye-type medium. FIG. 4 is a diagram for explaining a part of a signal waveform in a wobble signal detection circuit when detecting a wobble signal from a space signal and a mark signal when information is recorded on a dye-type medium. FIG. 4 is a diagram for explaining a part of a signal waveform in a wobble signal detection circuit when reproducing information of a dye-type medium. FIG. 4 is a diagram for explaining a light emission pattern of laser light in a dye type medium and a phase change type medium.

Explanation of reference numerals

15 optical disk (optical recording medium), 20 optical disk device, 30 wobble signal detection circuit (wobble signal detection device), 40 CPU, 57a '... third constant amplitude AGC (first amplitude adjustment circuit), 57b' ... Fourth constant amplitude AGC (second amplitude adjustment circuit), 58a... Second subtractor (subtraction circuit).

Claims (2)

The light receiving area is divided into two parts with respect to the tangential direction of the recording area which receives the reflected light from the recording surface of the spot light applied to the optical recording medium in which the recording area is formed spirally or concentrically on the recording surface. A wobble signal detection circuit that detects a wobble signal based on meandering of the recording area based on a signal from a light receiving element,
A first amplitude adjustment circuit that adjusts the amplitude of the first voltage signal according to the photoelectric conversion signal from the first light receiving region of the light receiving element so as to match the target amplitude;
A second amplitude adjustment circuit that adjusts an amplitude of a second voltage signal according to a photoelectric conversion signal from a second light receiving region of the light receiving element so as to match the target amplitude;
A target amplitude setting circuit for individually setting the target amplitudes of the first amplitude adjustment circuit and the second amplitude adjustment circuit in accordance with a control signal;
A wobble signal detection circuit comprising: a subtraction circuit that outputs a difference between an output signal of the first amplitude adjustment circuit and an output signal of the second amplitude adjustment circuit as the wobble signal. An optical disc device that irradiates a spot light onto an optical recording medium in which a recording area is formed in a spiral or concentric manner on a recording surface, and at least records information,
A wobble signal detection circuit according to claim 1;
An optical disk device comprising: a processing device that performs at least recording using the wobble signal detected by the wobble signal detection circuit.

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