JP2007150744A - Signal multiplexing device, device for separating multiple signal and their method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiplexing device having a simple constitution, minimizing the number of the signal lines of a transmission system, and being capable of transmitting a signal at a high speed, by making the most of the feature of an over-sampling low-amplitude encoding technique and a device for separating a multiple signal. <P>SOLUTION: In the signal multiplexing device, a large number of elements 10a changing an observation signal (such as an output signal from a microphone) into a digital signal by the over-sampling low-amplitude encoding technique are dispersed and arranged and a common signal line 11 connected to these dispersed elements is fitted. In the signal multiplexing device, an element control unit 70a is mounted being fitted at every large number of the elements and outputting a digital output signal to the common signal line 11 at every one period of an over-sampling. The device for separating the multiple signal has an element control unit 120a generating holding signals fitted at every element holding the multiplexed signal at every one period of the over-sampling on the common signal line 11, and a plurality of the elements (such as a loudspeaker) decoding the held digital signals to analog signals in the signal multiplexing device. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for transmitting a large number of observation signals with a small number of transmission lines. For example, a signal multiplexing device that transmits acoustic signals picked up by a large number of microphones with a small number of wires, and a multiplexed signal demultiplexing device that separates the multiplexed signals to reproduce the large number of acoustic signals with a large number of speakers, In addition, the present invention relates to a method capable of faithfully reproducing, for example, a collected sound field in other places using these devices.

When detecting the event in the natural world and transmitting the signal, instead of transmitting the observation signal as an analog signal as it is to improve the noise margin, convert the analog signal to a digital signal once. There is a method of transmitting after (Analog to Digital Conversion, hereinafter referred to as A / D conversion).
For AD conversion, a successive approximation AD converter that keeps an analog signal at a constant value and secures resolution in the amplitude direction, for example, about 8 bits or 16 bits has been often used. When AD conversion is performed by this method, it is premised that the number of bits is increased in order to obtain the accuracy of the amplitude of the signal. In order to transmit the digitized signal, a plurality of signal lines corresponding to at least multiple bits are required. There was a necessary task. In addition, in order to increase the accuracy in the amplitude direction, it is necessary to hold the analog signal at a constant value for a certain period of time. As a result, the conversion takes time, the conversion speed is slow, and the circuit scale is increased. was there.
In particular, when AD converting a large number of signals, for example, converting each of the many microphones into a digital signal by a successive approximation AD converter has a problem that the circuit scale is large and the cost is very high.

  ΣΔ oversampled low amplitude that obtains a high S / N ratio by performing sampling at a frequency sufficiently higher than the Nyquist frequency and increasing the temporal resolution for the successive approximation AD converter having such problems There is a method using an AD converter based on resolution encoding technology. The AD converter based on the ΣΔ oversampled low amplitude resolution encoding technology is capable of digitizing an analog circuit such as an aliasing filter, and the quantization unit and DA conversion unit for converting the analog amount into a digital amount are 1 to several bits. Therefore, cost and power consumption can be reduced.

  FIG. 16 shows an example of a 1-bit AD converter based on the oversampled low amplitude encoding technique, and its operation will be briefly described. The 1-bit AD converter 160 includes a subtractor J, an analog integrator K, and a quantizer L. When the subtractor J subtracts the analog input from the output of the quantizer L and the analog input changes in the increasing direction, the quantizer L outputs a positive pulse. When the analog input changes in the decreasing direction, the quantizer L outputs a negative pulse. When the analog input value does not change, the quantizer L alternately outputs positive and negative pulses. By setting the sampling frequency (pulse interval) to about 2 to 3 MHz, the analog input signal waveform can be AD-converted faithfully.

  FIG. 17 shows a decoding means for decoding a signal digitized by the 1-bit AD converter into an analog signal. Since the 1-bit AD converter generates a 1-bit encoded signal using the algorithm as described above, the decoding unit 170 can be configured with a low-pass filter as shown in FIG. In other words, the analog output signal when the positive polarity pulse is continuously input rises in a staircase pattern, and when the positive and negative pulses are alternately input, the analog output signal maintains the current value, and the negative polarity When a negative pulse is continuously input, the analog output signal decreases toward zero, and when a negative pulse is further input, the analog output signal reaches a negative polarity. In this way, the digital signal of the 1-bit AD converter is decoded into an analog signal. By using such an oversampled low amplitude encoding technique, it is possible to transmit an analog signal with a small number of signal lines (1 to several bits).

FIG. 18 shows a multi-channel encoding apparatus that transmits multi-channel acoustic signals proposed by the inventors at low cost using this oversampled low-amplitude encoding technique. Each of the analog signals from the N microphones (1A to 1N) is A / D converted by the oversampled low amplitude resolution encoding means 180A to 180N. In the packet multiplexing means 16A to which the signal of each microphone after A / D conversion is input, an identification signal for identifying each microphone is attached to the output signal of the A / D converter, and a small set of data, that is, a packet (packet). And then multiplexed and sent to the transmission system 17A. (The description from the packet receiving means 18A to the transmission system 17B is the same as the following description, and will be omitted.)
The packet receiving unit 18B receives the packetized microphone signal and supplies the microphone signal to the decoding units 181A to 181N corresponding to the identification signal in accordance with the identification signal in the packet signal. The decoding units 181A to 181N perform the operations already described with reference to FIG. 14 to decode them into analog signals, which are converted into acoustic signals by the speaker systems 7A to 7N connected to the decoding units 181A to 181N, respectively, and output.

Further, when a plurality of channel signals are conventionally time-division multiplexed, the plurality of channel signals are aggregated in one place, and each channel signal is one in each of a plurality of time slots provided in one cycle of the synchronization signal. The method of sequentially assigning and sending to each of them is common. The multiplexed time division signal is also separated at one place.
As described above, conventionally, since both channel multiplexing and time division multiplexing aggregate the channel signals in one place, the wiring between the multiplexing apparatus and each signal line has been complicated. The same was true for demultiplexing.
JP 2004-191545 A (FIG. 4)

  However, in the conventional technique as described above, for example, the oversampled low amplitude encoding technique is used rather than the case of using the successive approximation type AD converter. However, it cannot be said that the feature using the oversampled low-amplitude coding technique is fully utilized. That is, in multiplexing by packets, it is necessary to identify individual microphones and speaker elements by addresses described in the header of the packet, and there is a transmission speed limit to multiplex signals of many elements. In addition, since individual data becomes large, the number of channels that can be multiplexed is also reduced.

  The present invention has been made in view of such a point, and by taking advantage of the characteristics of the oversampled low-amplitude coding technology, the configuration is simple, the number of signal lines in the transmission system is small, and high-speed signal transmission is possible. It is an object of the present invention to provide a possible multiplexing device and multiple signal demultiplexing device.

A signal multiplexing apparatus according to the present invention multiplexes and outputs a plurality of elements whose observation signals are digital signals by oversampled low amplitude resolution encoding and digital output signals from the plurality of elements to a common signal line in a time division manner. It consists of a control part.
Furthermore, the multiplexed signal demultiplexer according to the present invention includes a control unit that generates a plurality of holding signals that hold time-division multiplexed digital signals output to a common signal line for each oversampling period, and the holding unit. And a plurality of elements for decoding the received signal as an analog signal.

  As described above, according to the signal multiplexing apparatus and the multiplexed signal demultiplexing apparatus of the present invention, the transmission system signal lines are digitized by oversampled low-amplitude codes (1 to several bits common signal line). Therefore, low-speed and high-speed time-division multiplex transmission that does not require an identification signal for each transmission signal can be realized.

Hereinafter, embodiments of the apparatus of the present invention will be described with reference to the drawings, but the description of the operation also serves as an explanation of embodiments of the method of the invention. In the following description, the same components are denoted by the same reference numerals, and the description will not be repeated.
[First Embodiment]
[Example 1]
FIG. 1 shows a first embodiment of a signal multiplexing apparatus according to the present invention. A / D conversion outputs of a plurality of elements 10a to 10n that convert the observation signal S into digital signals by oversampled low amplitude resolution encoding are connected to the common signal line 11, respectively. A sampling clock 12 for activating each of the plurality of elements 10 a to 10 n and gate signals 13 a to 13 n for outputting the A / D conversion result of the observation signal, which is an output of the element, to the common signal line 11 in a time division manner are the control unit 100. Is supplied by

  An example of the element is shown in FIG. FIG. 2 shows one of the elements 10a to 10n using a microphone 30 that detects sound as an observation signal. The element 10a is obtained by integrating a microphone 30a, a 1-bit oversampled A / D converter 22a, and a gate element 23a. The sound wave is converted into an electric signal by the microphone 30a, the electric signal is amplified by the amplifier 21a, and the amplified signal is output at the timing when the sampling clock from the control unit 100 is “1” (meaning logic level 1). A 1-bit A / D converter 22a performs A / D conversion to an oversampling low amplitude resolution digital signal. The gate element 23 a is controlled at the timing when the gate signal from the control unit 100 is “1”, and the A / D converted digital signal is output to the common signal line 11.

  An operation time chart of the control unit 100 is shown in FIG. 3 and its operation will be described. The control unit 100 supplies the final frequency-divided output signal of the n-stage frequency divider circuit 101 that operates at the timing of the fall of the master clock 33 to each of the elements 10 a to 10 n as the sampling clock 12. The first half of the elements 10a to 10n is supplied with a sampling clock 12￣ (the symbol A￣ means the inversion of A) obtained by inverting the final frequency-divided output signal of the frequency dividing circuit 101, and the second half of the device 10a to 10n. The final frequency division output signal of the frequency dividing circuit 101 is supplied as it is. That is, the first half elements 10a to 10 * (* is a code corresponding to half the total number of elements) are sampled while the sampling clock 12 is “0”, and the remaining half elements are sampled during the period “1”. Are sampled. By setting the frequency of the sampling clock 12 to, for example, about 2 MHz, the 1-bit A / D converter 22a operates in an oversampling state.

  The gate signals 13a to 13n for determining the timing for outputting the digital output signal, which is the A / D conversion result of each element 10a to 10n, to the common signal line 11 are the final frequency divided outputs (nth stage) of the frequency dividing circuit 101. Differentiating circuit 102 that generates a pulse signal having a time width corresponding to one cycle of master clock 33 at the falling timing, and an n-stage shift register that shifts the pulse signal output from differentiating circuit 102 at the rising timing of master clock 33 103 and AND gates 104 a to 104 n that take the logical product of the output of each stage of the shift register 103 and the master clock 33.

For example, if the frequency of the sampling clock 12 is 2 MHz and the number of elements is n, the master clock 33 is set to a frequency of n × 2 MHz. The differentiating circuit 102 periodically generates a pulse having a time width corresponding to one cycle of the master clock 33 at the falling timing of the final divided output signal of the frequency dividing circuit 101. The pulse generated by the differentiating circuit 102 is input to the n-stage shift register 103 and converted into a signal that is delayed (shifted) by one cycle of the time width of one cycle of the master clock 33 (1Q, 2Q). , 3Q, ...).
The gate signal of each element is generated by the logical product of the output signal of each stage of the n-stage shift register 103 shifted by one period of the master clock 33 and the master clock 33. The gate signal 13a of the element 10a is generated at the timing of the clock 1 of the master clock 33 by the AND gate 104a. The gate signal 13b of the element 10b is generated at the timing of the clock 2 of the master clock 33 by the AND gate 104b.

Similarly, n gate signals for n elements are generated at different timings. As a result, the sound waves detected by the elements 10 a to 10 n are time-division multiplexed on the common signal line 11.
As described above, according to the signal multiplexing apparatus of the present invention, it is possible to transmit a high-speed signal with a minimum signal line without attaching individual identification signals to a plurality of elements. The time division multiplexed signal on the common signal line 11 does not include a synchronization signal.
[Example 2]
FIG. 4 shows a second embodiment in which an element control section is provided for each element as the control section, and the number of wirings for controlling the elements is reduced. Element control units 40a, 40b, 40c, and 40d are provided for the respective elements 10a, 10b, 10c, and 10d, and sampling clocks 12a to 12d are supplied from the element control units 40a to 40d to the elements 10a to 10d. Yes. The element control units 40a to 40d are sequentially connected in accordance with a formula determined by sequential connection lines 41a to 41c from the previous element control unit. An initial instruction generation unit 42 is connected to the element control unit 40a of the first stage element 10a. A master clock 33 is supplied from the master clock line LMC to the initial instruction generator 42 and the element controllers 40a to 40d. The outputs of the elements 10a to 10d are connected to the common signal line 11 via the element control units 40a to 40d. FIG. 3 shows an example in which there are four elements, but n elements can be connected in the same connection relationship.

  Example 2 is more specifically shown in FIG. 5 (which is divided into FIGS. 5-1 and 5-2 for the convenience of drawing, but is originally one). In FIG. 5, a reset signal line LR for sending a reset signal 50 for initializing the circuit to each element control unit is added to FIG. 4, but the other configuration is exactly the same as FIG. The reset signal 50 is connected to all reset terminals of the T-type flip-flop (Toggle type Flip Flop and hereinafter referred to as TFF) and D-type flip-flop (hereinafter referred to as DFF and the like) used in FIG. This initializes the entire circuit. This signal is “1” (initialization) when the operation is stopped and “0” when the operation is performed. The element controllers 40a to 40d that control the elements 10a to 10d include frequency dividers 51a to 51d, gate signal generators 52a to 52d, and gate elements for the purpose of the element controller itself generating a sampling clock and a gate signal. 53a to 53d are provided respectively. In the description of FIG. 2, an example in which the gate elements 23a to 23n are integrated with each element is shown. However, in FIG. 5, the gate element 23a is incorporated as the gate elements 53a to 53d on the element control unit side. Shown in configuration. There is no change in operation. An initialization instruction generation unit 42 is provided only in the element control unit 40a that controls the first-stage element 10a.

  Each element control unit 40a to 40d supplies sampling clocks 12a to 12d generated by each element to each element 10a to 10d, and outputs a digital signal from each element to the common signal line 11 via the gate elements 53a to 53d. To do. Each element control part is connected by a sequential connection line. The element controllers 40a and 40b are connected by a sequential connection line 41a, the element controllers 40b and 40c are connected by a sequential connection line 41b, and the element controllers 40c and 40d are connected by a sequential connection line 41c. The sequential connection line 41d is not connected to the element control unit 40d in the final stage of this embodiment.

The time chart showing the operation of FIG. 5 is shown in FIG. 6, and the operation will be described. When the frequency of the sampling clock supplied from the element control units 40a to 40d to the elements 10a to 10d is 2 MHz, the frequency of the master clock 33 is four times 8 MHz.
Frequency dividing circuits 51a to 51d constituted by two TFF stages in each element control unit 40a to 40d divide the frequency of the master clock 33 at the falling edge of the clock signal input to the T terminal, and supply it to each element. Sampling clocks 12a to 12d are generated. The phases of the sampling clocks 12a and 12b of the elements 10a and 10b and the sampling clocks 12c and 12d of the elements 10c and 10d are different from each other by 180 °. In other words, the output having the different polarity of the last TFF constituting the frequency dividing circuit having the same configuration is used as the sampling clock. The sampling clocks of the elements 10a and 10b are taken from the QFF of the TFF, and the sampling clocks of the elements 10c and 10d are taken from the Q terminal of the TFF. Therefore, after initialization by the reset signal 50, the elements 10a and 10b are sampled first, and then the elements 10c and 10d are sampled. The elements 10a and 10b and the elements 10b and 10c are activated alternately by a sampling clock which is a signal having a duty of 50%.

The element control unit 40a that controls the first-stage element 10a is provided with an initialization instruction generation unit 42 that is configured by a differentiation circuit that generates a pulse at the rising edge of Q of the last TFF of the frequency dividing circuit 51a. The initialization instruction generator 42 generates an initialization instruction pulse having a width corresponding to one cycle of the master clock 33 at the rising edge of Q of the last TFF of the frequency divider 51a, and outputs a sampling clock (of the last TFF of the frequency divider 51a). It occurs periodically at the fall timing of Q).
The initialization instruction pulse is input to the D terminal of the DFF constituting the gate signal generation unit 42 a and is ANDed to obtain a logical product of the Q output of the DFF ₅₂ a delayed by a half cycle of the master clock 33 and the master clock 33. The gate signal 1 is obtained by the gate G _52a . The gate signal 1 is connected to the control terminal of the gate element 53a that controls the connection of the digital output signal of the element 10a to the common signal line 11.

The Q output of the DFF _52a constituting the gate signal generation unit 52a is a signal obtained by delaying the initialization instruction pulse by a half cycle of the master clock 33, and the pulse from the rising edge of the clock 1 to the rising edge of the clock 2 in FIG. It is. This pulse is supplied to the element control unit 40b through the sequential connection line 41a as an output instruction signal to the next stage.
The output instruction signal supplied by the sequential connection line 41a is input to the D terminal of the DFF _52b constituting the gate signal generation unit 52b of the element control unit 40b. The Q output of the DFF _52b becomes “1” (logic level 1) at the rising edge of the clock 2 of the master clock 33, and changes to “0” at the next rising edge of the clock 3. That is, the output instruction signal from the element control unit 40a is a signal delayed by one clock of the master clock 33. The gate signal 2 is generated by an AND gate G _52b that takes the logical product of the Q output of the DFF _52b delayed by one clock of the master clock 33 and the master clock 33. The gate signal 2 is connected to the control terminal of the gate element 53b of the element 10b.

Similarly, the element control unit 40c generates an output instruction signal that becomes “1” from the rising edge of the clock 3 of the master clock 33 to the rising edge of the clock 4, and becomes “1” at the timing of the clock 3 of the master clock 33. A gate signal 3 is generated.
The element control unit 40d generates an output instruction signal that is “1” from the rising edge of the clock 4 of the master clock 33 to the rising edge of the clock 5, and the gate signal 4 that is “1” at the timing of the clock 4 of the master clock 33. Generate.
Since FIG. 5 shows an example in which there are only four elements, the output instruction signal from the fourth-stage element control unit 30d is open. It is possible to connect a control unit. In that case, the frequency of the master clock 33 may be at least n times the frequency of the sampling clock.

  When the operation of FIG. 5 described above is summarized, the elements 10a and 10b are activated (sampled) while the master clock 33 is “0”, and the elements 10c and 10d are activated during the opposite “1” period. Activated. In this state, the digital output signal of the element 10a is output to the common signal line 11 at the timing of the clocks 1, 5, 9 of the master clock 33, the element 10b is the clocks 2, 6, 10, and the element 10c is the clocks 3, 7, 11. The element 10d is output to the common signal line 11 at the timing of clocks 4, 8, and 12. Since this operation is repeated while the master clock 33 is generated, the digital output signals observed by the elements 10a to 10d can be multiplexed and transmitted through the common signal line 11.

The second embodiment described above has an effect of reducing long wirings for element control by providing an element control unit for each element as compared with the first embodiment shown in FIG. In the first embodiment, since there is one control unit 100 that controls n elements, a large number of wires are required to control each of the elements. According to the second embodiment, for the n elements, there are four systems of the common signal line, the reset signal line LR for initializing, the master clock line LMC, and the sequential connection line 41 for connecting each element control unit. It can be configured with only signal lines (wiring).
Although the description has been made in the form in which the sequential connection line 41d from the last element control unit 40d of Example 2 is not provided, the sequential connection line 41d from the element control unit 40d is connected to the first stage as shown by a broken line in FIG. You may connect to the element control part 40a. In this way, it is also possible to connect the element control units in a ring shape with a sequential connection line. In that case, the initial instruction generation unit 42 can be replaced with a simple switch. When the switch 44 indicated by the broken line in FIG. 4 is turned on for a certain time (may be a short time) to generate a gate signal in the element control unit 40a, each element control unit is sequentially connected via the sequential connection lines 41a to 41d. Performs the operation described above.
[Example 3]
FIG. 7 shows a third embodiment in which the wiring for controlling the elements is further reduced. FIG. 7 is a sequential connection in which each element control unit is connected in an equation by replacing the frequency divider provided in each element control unit shown in the second embodiment with element control units 70a to 70d replaced by eigenvalue counters. The line is lost. Since the other configuration is the same except for the difference, FIG. 7 is omitted, and FIG. 8 showing an example in which FIG. 7 is specifically configured will be described.

FIG. 8 (divided into FIG. 8-1 and FIG. 8-2 for convenience of drawing, but originally one piece) shows an example with four elements as in the second embodiment. The difference from the already described second embodiment is only that the frequency dividing circuits 51a to 51d in the element control units 40a to 40d are replaced with eigenvalue counters 80a to 80d.
The configuration of the eigenvalue counters 80a to 80d is a simple 2-bit binary counter (in this example, there are 4 elements, which is 22 bits), and the decoders 81a to 81d are configured so that each counter generates a carry with its own eigenvalue. Have. FIG. 9 shows the operation time chart. The decoder 81a provided in the eigenvalue counter 80a of the element control unit 40a generates a pulse that is composed of an AND gate and becomes “1” during a period when the count value of the eigenvalue counter is 0, and supplies the pulse to the gate signal generation unit 52a.

The element control unit 40b generates a pulse that is “1” during the period when the count value of the eigenvalue counter is 1, and supplies the pulse to the gate signal generation unit 52b. Similarly, the period of the count value 2 is the timing of the element 10c, and the period of the count value 3 is the timing of the element 10d.
The pulses generated by the eigenvalue counters 80a to 80d are the same as the signals for instructing the timing of gate signal generation to the element control unit at the next stage by the sequential connection lines 41a to 41c shown in the second embodiment.
As described above, by providing the eigenvalue counter in each element control unit, it is possible to eliminate the sequential connection line shown in the second embodiment. As a result, the signals of the n elements can be time-division-multiplexed and transmitted using only the three wires of the common signal line 11, the reset signal line LR, and the master clock line LMC. In this example, the number of elements is four. However, even if the number of elements is increased, the present invention can be implemented only by increasing the count values of the eigenvalue counters 80a to 80d.

In the configuration as described above, the process of digitizing multiple observation signals by oversampled low amplitude resolution encoding and the process of outputting the digitized multiple observation signals to a common signal line in a time division manner Thus, a signal multiplexing method can be realized.
[Second Embodiment]
[Example 1]
FIG. 10 shows a multiple signal demultiplexer according to the present invention. N elements 60a to 60n for decoding a digital signal into an analog signal are connected to a common signal line 11 through which a plurality of signals obtained by converting the observation signal into a digital signal by oversampled low-amplitude resolution encoding is transmitted. Each element is supplied with holding signals 20a to 20n for holding the digital signal multiplexed on the common signal line 11 from the control unit 200 for each oversampling period.

An example of the elements 60a to 60n is shown in FIG. FIG. 11 shows one of the elements 60a to 60n using the speaker 110, for example. The element 60a includes a holding element 111 that holds a digital signal on the common signal line 11 by a holding signal 20a supplied from the control unit 200, a decoding unit 112 that decodes the digital signal held by the holding element 111 into an analog signal, It comprises an amplifier 113 that amplifies the output signal of the decoding means 112 and supplies it to the speaker 110.
Since the decoding unit 112 is the same as that in FIG. 14 described in the background art, the description is omitted. By configuring the element 60a in this way, it is possible to reproduce, for example, a sound wave digitized with a period of an oversampling frequency.

  The operation of the control unit 200 is almost the same as the operation of the first embodiment of the signal multiplexing apparatus described in FIG. Therefore, see FIG. 3 for the time chart. The differentiation circuit 102 in FIG. 3 corresponds to 202, and the AND gate 104a corresponds to 204a. The control unit 200 generates an n-stage divider circuit 201 that operates at the falling timing of the master clock 33, and generates a pulse signal having a time width corresponding to one cycle of the master clock 33 at the falling timing of the final divided output. Differentiating circuit 202, n-stage shift register 203 for shifting the pulse signal output from differentiating circuit 102 at the rising timing of master clock 33, and the logical product of the output of each stage of shift register 203 and master clock 33. And AND gates 204a to 204n.

The differentiation circuit 202 periodically generates a pulse having a time width corresponding to one period of the master clock 33 at the falling timing of the final frequency division output signal of the frequency division circuit 201. The pulse generated by the differentiating circuit 202 is input to the n-stage shift register 203 and converted into a signal that is delayed (shifted) by one cycle of the time width of one cycle of the master clock 33 (1Q, 2Q). , 3Q, ...).
A holding signal of each element is generated by a logical product of the output signal of each stage of the n-stage shift register 203 shifted by one period of the master clock 33 and the master clock 33. The holding signal of the element 60a is generated at the timing of the clock 1 of the master clock 33 by the AND gate 204a. The holding element 111 is a latch circuit composed of a DFF or the like, and holds, for example, a signal on the common signal line 11 that is read when the holding signal is “1” and changes to “0”. The gate signal of the element 10b is generated at the timing of the clock 2 of the master clock 33 by the AND gate 204b.

  Similarly, the digital signals output to the common signal line 11 are held at timings corresponding to the n holding signals for the n elements. Therefore, if the same master clock frequency and initial operation as those of the signal multiplexing apparatus that has been digitized and multiplexed on the common signal line 11 by over-sampling low-amplitude resolution encoding are started at the same time, the multiplexed signal can be obtained by the above-described configuration. Separation is possible. The initial operation can be easily started by using the same reset signal as the reset signal on the signal multiplexer side also on the demultiplexer side.

  In the above example, the timing at which the microphone-side signal is output on the common signal line 11 coincides with the timing at which the demultiplexer-side holding circuit holds (latches) the signal on the common signal line 11. In general, however, the falling timing of the holding signal is earlier than the data on the common signal line 11 becomes indefinite, so that the holding signal can be reliably held. If you are concerned about the operation due to the delay around this area, you can generate a hold signal using a signal with a frequency higher than that of the master clock. It is.

The specific circuit shown for explaining the present invention is only an example, and it goes without saying that the eigenvalue counter and the like can be modified in various ways depending on the design method.
[Example 2]
Example 2 in which the control unit is an element control unit provided for each element and the number of wirings is reduced is divided into FIG. 12 (FIGS. 12-1 and 12-2 are divided for convenience of drawing. Is). Element control units 120a, 120b, 120c, and 120d are provided for the respective elements 60a, 60b, 60c, and 60d, and the elements 60a to 60d are held by the holding elements 111a to 111d provided in the respective element control units. A signal is being supplied. In Example 2, it is set as the structure which incorporated 111a-111d in each element control part. The operation is almost the same as the operation of FIG. 5 described in the second embodiment of the signal multiplexing apparatus.

Therefore, the explanation of the operation is omitted by clarifying the corresponding reference numerals. 5A corresponds to the initialization instruction generator 122 in FIG. 12, the frequency divider 51 corresponds to the frequency divider 121, and the gate signal generator 52 corresponds to the hold signal generator 123.
FIG. 13 shows an operation time chart of the demultiplexer of FIG. The holding signal 20 a in the element control unit 120 a is generated at the timing of the clock 1 of the master clock 33. The holding signal 20b generated by the element control unit 120b is generated at the timing of the clock 2 of the master clock 33. Similarly, the hold signal 20c of the element 60c is generated at the timing of the clock 3 and the hold signal of the element 60d is generated at the timing of the clock 4, and the process is repeated thereafter.

In the example of FIG. 12, since the holding element 111 is formed of a DFF, the digital signal on the common signal line 11 at the moment when the holding signal falls is operated. Now, assuming that the signal multiplexer also assigns the gate signal 13a corresponding to the hold signal 20a to the element 10a composed of the microphone at a specific position, the sound wave captured at the position of the microphone is reproduced by the speaker of the element 60a. Can do.
For example, FIG. 14 shows an example in which the third embodiment of the signal multiplexing apparatus is applied. FIG. 14 shows an example in which the signal multiplexing apparatus according to the present invention is incorporated in a curtain 140 attached to a window or the like of a room. Many elements 10 a to 10 n made of microphones are dispersedly arranged on the entire surface of the curtain 140 hung on the curtain rail 141, and these elements are connected by a common signal line 11. Other control lines 142 indicated by broken lines are wired along the common signal line 11. The other control lines 142 include, for example, a power supply line for supplying power to each element, a reset signal for initialization, and a master clock.

  The signal multiplexing device side is configured like the curtain 140, and the multiplexed signal separation device side is not shown, but is the same curtain shape in which the elements in FIG. 14 are replaced with speakers. In addition, the element 60a is placed at a position corresponding to the same position on the curtain of the speaker (element 60a) for reproducing the sound wave collected at the position of the element 10a on the signal multiplexer side. Then, if the curtain-shaped multiplex signal demultiplexer is hung on the window of another room and both curtains are connected by a common signal line, the sound field of the room where the signal multiplexer is placed is changed to the other room. It is possible to communicate faithfully.

A common point between the signal multiplexing apparatus and the multiplexed signal demultiplexing apparatus described with reference to FIG. 14 is that many elements are distributed, and the common signal line 11 and other control lines 142 are arranged along the arrangement of these elements. The time division multiplexed signal on the common signal line does not include a synchronization signal. The common signal line 11 and the other control lines 142 may be arranged not only in one dimension but also in almost two dimensions as shown in FIG. 14, or as shown in FIG. As shown, the common signal line 11 and the other control lines 142 may be connected in a ring by connecting the start and end. In this case, in the embodiment shown in FIGS. 5 and 12, the sequential connection line from the terminal element control unit is connected to the gate signal generation unit of the start element control unit instead of the signal from the initialization instruction generation unit 42. do it. In this case, it is necessary to set the frequency of the master clock 33 to the number of adjustment elements equal to the oversampling frequency.
[Example 3]
The multiple signal demultiplexer can also eliminate the sequential connection line shown in the second embodiment. A third embodiment in which the sequential connection lines are eliminated is shown in FIG. 19 (which is divided into FIGS. 19-1 and 19-2 for convenience of drawing, but is originally one). Eigenvalue counters 80a to 80d are provided in each element control unit of the second embodiment (FIG. 12) of the multiplex signal demultiplexing apparatus as in the case of the third embodiment (FIG. 8) of the signal multiplexing apparatus. Is. The reference numerals are the same, and the description of the operation is omitted. As described above, also in the multiplex signal demultiplexer, by replacing the frequency dividing circuit in each element control unit shown in the second embodiment with an eigenvalue counter, a sequential connection line is not necessary.

As a result, the signals of the n elements can be demultiplexed by only three wirings of the common signal line 11, the reset signal line LR, and the master clock line LMC.
In the configuration as described above, the digital signal on the common signal line on which the signal digitized by oversampled low amplitude resolution encoding is time-division multiplexed and transmitted is retained in every oversampling cycle. A multiple signal separation method for separating signals on the common signal line can be realized.
The signal multiplexing device and the multiplexed signal demultiplexing device according to the present invention have been described above using the example of the element including the microphone and the speaker. However, the present invention is not limited to this. Other sensors may be used as shown in FIG.

FIG. 15A shows an element using a temperature sensor instead of the microphone. By disposing a large number of temperature sensors 150 as shown in FIG. 14, it is possible to finely grasp the temperature distribution of a room or a relatively large object. Since the room temperature does not change as fast as the sound, there is no need to operate with oversampling. However, it is possible to take advantage of the feature of the present invention that a large number of information can be transmitted with a small number of signal lines.
FIG. 15B shows an element using an acceleration sensor 151 instead of the microphone. Many triaxial acceleration sensors are used for robots and the like. When a large number of such a plurality of pieces of information are transmitted, it can be handled by increasing the number of common signal lines. By simply increasing the number of common signal lines, the present invention can be applied to control of a robot or the like, for example.

The use of other sensors is also conceivable. For example, the present invention can be used when a river (PH) sensor is used to measure a river environment. In that case, since the master clock may be wired over several kilometers, it is necessary to devise such as transmitting the master clock with an optical fiber cable with little delay and loss. However, even in such applications, the technical idea of the present invention can be utilized as it is.
As described above, according to the signal multiplexing apparatus and the multiplexed signal demultiplexing apparatus of the present invention, the signal line of the transmission system is only a signal line (1 to several bits common signal line) with few oversampled low amplitude encoded digital signals. It is possible to realize low-speed and high-speed time division multiplex transmission that can be formed and does not require an identification signal for each transmission signal.

In the above-described embodiment, the example of 1-bit A / D conversion and 1-bit decoder has been described. However, the AD converter and the decoder based on the ΣΔ oversampled low-amplitude resolution encoding technique are increased to about 3 bits. It is well known that it can be done. When amplitude accuracy is required, a case of 2 bits or 3 bits is also assumed. In that case, the present invention can be similarly realized if the 1-bit A / D converter and the decoding means described above are simply multi-bited and a common signal line is provided for each bit.
In addition, Embodiments 1 to 3 of the signal multiplexing device of the present invention and Embodiments 1 to 3 of the multiplexed signal demultiplexing device can be combined in an independent relationship with each other. The features of the invention, such as a simple configuration, a minimum number of signal lines in the transmission system, and high speed can be obtained.

The figure which shows the function structural example of Example 1 of the signal multiplexing apparatus by this invention. The figure which shows an example (microphone) of the element in FIG. The figure which shows the operation | movement time chart of the control part 100 in FIG. The figure which shows the function structural example of Example 2 of the signal multiplexing apparatus by this invention. The figure which shows the specific structural example of Example 2 of the signal multiplexing apparatus by this invention. The figure which shows the specific structural example of Example 2 of the signal multiplexing apparatus by this invention. The figure which shows the operation | movement time chart of FIGS. 5-1 and 5-2. The figure which shows the function structural example of Example 3 of the signal multiplexing apparatus by this invention. The figure which shows the specific structural example of Example 3 of the signal multiplexing apparatus by this invention. The figure which shows the specific structural example of Example 3 of the signal multiplexing apparatus by this invention. The figure which shows the operation | movement time chart of FIGS. 8-1 and 8-2. The figure which shows the function structural example of Example 1 of the multiplex signal separation apparatus by this invention. The figure which shows an example (speaker) of the element in FIG. The figure which shows the function structural example of Example 2 of the multiple signal separator by this invention. The figure which shows the function structural example of Example 2 of the multiple signal separator by this invention. The figure which shows the operation | movement time chart of FIG. The figure which shows the example of application of the signal multiplexing apparatus or multiple signal demultiplexing apparatus of this invention. The figure which shows the example of another element. The figure which shows the example of the 1 bit AD converter by the conventional oversample low amplitude encoding technique. The figure which shows the conventional oversample 1 bit decoding means. The figure which shows the conventional multi-channel encoding apparatus. The figure which shows the specific structural example of Example 3 of the multiplex signal separation apparatus by this invention. The figure which shows the specific structural example of Example 3 of the multiplex signal separation apparatus by this invention.

Claims (8)

A plurality of elements that convert the observation signal into a digital signal by oversampled low amplitude resolution encoding;
A common signal line for transmitting digital observation signals of the plurality of elements,
A control unit for outputting the digital observation signals of the plurality of elements to the common signal line in a time-sharing manner;
A signal multiplexing device comprising: The signal multiplexing device according to claim 1, wherein
The control unit is configured as an element control unit provided for each element, and each element control unit receives the digital signal from the plurality of elements in response to an output instruction signal from a sequential connection line connected to the preceding stage. In addition to outputting to the communication line, an output instruction signal is sequentially sent to the connection line to the next stage element.
A signal multiplexing apparatus characterized in that the first-stage element control section generates an output instruction signal for each oversampling cycle. The signal multiplexing device according to claim 1, wherein
The control unit is configured as an element control unit provided for each element.
A signal multiplexing apparatus that generates a time indicated by a unique identification number for each element and outputs the digital signal to the common signal line at that time. A common signal line for transmitting the time-division multiplexed observation signal digital signal;
A control unit for generating a holding signal for holding the digital signal on the common signal line for each period of oversampling;
A plurality of elements for decoding the held signal as an analog signal;
A multiple signal demultiplexer comprising: The multiple signal demultiplexer according to claim 5,
The control unit is configured as an element control unit provided for each element, and each element control unit holds a signal on the common signal line in response to a holding instruction signal from a sequential connection line connected to the previous stage. And
The device controller of the first stage generates a holding instruction signal for each oversampling cycle. The multiple signal demultiplexer according to claim 5,
The control unit is configured as an element control unit provided for each element, and each element control unit generates a time indicated by a unique identification number for each element, and at that time, a signal on the common signal line is generated. A multiple signal demultiplexer characterized by being held. Digitizing multiple observation signals by oversampled low amplitude resolution encoding;
A process of outputting the plurality of digitized observation signals to a common signal line in a time division manner,
A signal multiplexing method for multiplexing signals according to the above.   Multiplexing that separates signals on a common signal line by a process of holding a signal on a common signal line, which is transmitted by time-division multiplexing of a signal digitized by oversampled low-amplitude resolution encoding, for each period of oversampling Signal separation method.

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