JPS62200847A - Serial transmission system - Google Patents

Abstract

PURPOSE:To decrease the time in serial transmission by converting parallel data comprising plural bits into a serial signal comprising one time length code and sending the result at the sending side and converting the time length code sent from the sending side into the parallel data comprising plural bits at the reception side. CONSTITUTION:A transmission circuit 1 encodes a parallel data in, e.g., 2-bit and converts it into a serial data having a time length corresponding to the 2-bit data and sends the result to a reception circuit 2 via a transmission line 3. Plural sample timings are given to the reception circuit 2, the 2-bit data are sent in the lump such as '00', '01', '10', '11' at one leading and the 2-bit parallel data are sent by one serial data transmission. Thus, the data transmission time is reduced and the data are processed quickly.

Description

[Detailed Description of the Invention] [Summary] The present invention converts parallel data (parallel code) consisting of multiple bits into a serial signal consisting of one time length code on the transmitting side and transmits the converted signal. By converting the time length code sent from the transmitting side into parallel data (parallel code) consisting of multiple bits, time in serial transmission is reduced.

[Industrial application field]

The present invention relates to a serial transmission method suitable for serial transmission of data between, for example, a small computer and a workstation (printer, display, etc.).

[Conventional technology]

In the conventional serial transmission method, as shown in Figure 1O, the signal level sent through the transmission line is
“1” or “1” depending on the length of time that the state of “1” continues.
In other words, in the illustrated example, if the sampling width is 5T, when the signal level "1" state is 3T, which is shorter than 5T, it is "0", and when the signal level is 3T, which is longer than 5T, it is 0".
When , it is determined as "1".

[Problem that the invention seeks to solve]

In the conventional serial transmission method described above, "0" or "
As shown in Figure 10, it takes 12 times the sampling width to transmit 1 bit information of 1", so there is a problem that data transmission takes time and data processing cannot be done quickly. Ta.

[Means for solving problems]

In order to solve the above conventional problems, the present invention decodes 2-bit parallel data on the transmitting side, converts it into one serial data having a time length corresponding to the 2-bit data, and transmits the data. On the receiving side, the serial data is decoded into 2-bit data based on the time length of the serial data.

[For production]

FIG. 1 is a principle diagram of the serial transmission system according to the present invention, in which (1) is a transmitting circuit, (2) is a receiving circuit, (
3) is a transmission line connecting the above-mentioned transmitting circuit (11) and receiving circuit (2); (IA) is an encoder provided on the transmitting side and converts the parallel signal into a time length code; (2A)
is a decoder provided on the receiving side and converts the time length code into a parallel signal. In FIG. 1, a transmitting circuit (11, for example, decodes 2-bit parallel data, converts it into one serial data having a time length as shown in FIG. 2 corresponding to the 2-bit data, and transmits it. Line (3
) to the receiving circuit (2).

In the receiving circuit (2), by providing multiple sample timings, "
00”, “01”, “10”, 11” etc. 2
Bits are transmitted all at once, and 2-bit parallel data can be transmitted by transmitting serial data once.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail.

Figure 3 is a transmission system diagram on the transmitting side.
) is the transmission timing generation circuit, (5) is the control circuit, (6
) is a data bus, and (7) is a driver. In the above transmission system, the control circuit (5) sends transmission data to the transmission circuit +11 via the data bus (6), and
Drives the transmission timing generation circuit (4). The transmission timing generation circuit (4) generates transmission timing signals STO, STI to ST4°SFT shown in FIG. 5, as described later.
CLK is generated and sent to the transmitting circuit (1). The transmitting circuit (1) decodes parallel data and converts it into serial data using the above-mentioned transmitting timing signal from the transmitting timing generating circuit (4). The transmitting circuit (
The serial data from 1) is matched in level between the transmitting circuit side and the transmission line side by the driver (7), and is sent to the receiving side via the transmission line (3).

FIG. 4 is a specific circuit configuration diagram of the transmitting circuit (1). Shifter 1 (101) in FIG. 0 is a 9-bit parallel in-parallel out shifter, and Set C
The data of D o ” D 7 is sent by LK,
Further, it is shifted in the direction of the arrow shown in the figure by SFT CLK. (102) is a 2-bit decoder, FFI (
103) is a JK flip-flop whose output is inverted and held at the rising or falling edge of the clock input depending on the state of the input to J, Gz (104) to Gs (10B)
is a gate.

When transmitting data, from the control circuit (5) to the transmission circuit (
Set CLK to shifter 1 (101) that constitutes 11.
is sent out, and along with this, transmission data Do=D7 via the data bus (6) is set in the shifter 1 (101). Next, the transmission timing generation circuit (4) is driven by a signal from the control circuit (5). The transmission timing generation circuit (4) generates transmission timing signals STO, STI to ST4, and SFT CLK shown in FIG.
), Gate G+ (104) ~ Gate G, (107)
, FFI (103). In addition, the above SF
T CLK is generated at a timing synchronized with STO, and the above SFT from the transmission timing generation circuit (4)
CLK is used to synchronize the transmitting circuit +11.

In the above configuration, in the transmitting circuit (1), STO is “1”.
”, 5FTCLK becomes “1” at the same timing.
”.At this time, shifter 1 (101) is SF,
Transmission data D previously set by Set CLK from the control circuit (5) by SF1 of T CLK.
Shift o=Dt by l bits. And its output S
Data to be sent first to X and SO (1)o
s I)+ ) is set. At the same time, FFI (103) is supplied to the J input terminal s'
It is set to "l" by r o and transmission begins. The data sent to sx, so is decoded by the decoder (102) to determine the timing to reset the FFI (103). The timing for applying this reset is "sx" as shown in FIG.

If SO” is “00”, it is 3T, if “Ol” is 8T, “
10" corresponds to a time length of 13T, and "11" corresponds to a time length of 18T.

In other words, the above values of sx, so are decoded by the decoder (102), and when "sx, so" is "00", the output DECO of the decoder (lO2) becomes 1", and the FFI (103) is reset. STI is selected by the gate G+ (104) as a timing, and is supplied to the input terminal of the FFI (103) via the gate 0s (108), and reset is applied at the timing of 1srt. 01”, the decode output DEC1 becomes “l” and FFI (
103) as the reset timing of gate G2 (
105), Sr1 is selected. Similarly,”
When sx, so” are “10” and “11”, the respective decode outputs DEC2 and DEC3 become “1”, and gate G3 (106) and gate G4 (107) are used as reset timing of FFI (103).
), Sr1 and Sr1 are selected.

As described above, the second
Serial data as shown in the figure is obtained, and the obtained serial data is passed through the transmission line (3) via the driver (7).
). Note that the above-mentioned STO is performed four times in a series of sequences, for example, in the case of 8 bits.
It will be repeated if necessary. Also, SFT
SF2 of CLK is generated at the same timing as Sr1, and at the same time notifies the end of a series of timings, it shifts shifter 1 by 1 bit and prepares for the next 2-pit 1-transmission. (Since shifter 1 is shifted by 1 bit by the next SFI, 2 new bits are set in DEC (102).) Next, the receiving circuit (2) will be explained. FIG. 6 is a reception system diagram on the reception side, in which (8) is a reception timing generation circuit and (9) is a receiver. In the above receiving system, data input ζ sent from the transmitting side is received by the receiver (9) via the transmission line (3), and is further input to the receiving circuit (2). The receiving circuit (2) is
Based on the above received data, the reception timing generation circuit (
8), and the reception timing generation circuit (8) generates the reception timing signal RT1 shown in FIG. 8 as described later.
, RT2, and RT3, and sends them to the receiving circuit (2). The receiving circuit (2) processes the serial data input as parallel data output according to the above-mentioned receiving timing signal from the receiving timing generating circuit (8),
The data is sent to a control circuit (5) via a data bus (6), and the control circuit (5) controls and drives a printer or the like.

FIG. 7 is a specific circuit diagram of the receiving circuit (2). FF2 (201) to FF6 (205) in the diagram
is a flip-flop, and FF2 (201) to F
F5 (204) is composed of a D flip-flop that reads the state of data input into the output at the rising or falling edge of the clock, and FF6 (205) is composed of a JK flip-flop. In addition, the above FF2 (2
01) to FF4 (203) operate by synchronizing the data input data input via the receiver (9) with the same clock. Chic 2 (206)
is an 8-bit serial in-parallel out shifter,
Ge (207) to 012 (213) are gates.

During data reception, the data input received by the receiver (9) via the transmission line (3) is transmitted to FF2 (20
1) to FF4 (203), gate G12 (21
The circuit 3) generates a received signal A synchronized with the internal clock. Also, at this time, gate GH2 (2
The above-mentioned reception timing generation circuit (8) is driven by the RTST signal shown in FIG. FF5 (2'04), FF6 where RT2 and RT3 constitute the receiving circuit (2)
(205), the gate G is also supplied to (207).

The above-mentioned R'r' ST signal is generated at the timing when the rising edge of the received signal is captured, and the above-mentioned reception timing signals RTI, RT2, RT3 generated by the reception timing generation circuit (8) are generated based on the reception timing. Then, the sampling timing is created by the above-mentioned reception timing signals RTI, RT2, and RT3. Therefore, when sampling the received data, FF5 (204)
The state of the received data (“l” or “0”) at the sample timing SPO shown in FIG. 2 is sampled by the reception timing signal RTI supplied from the reception timing generation circuit (8), and the generate. That is, the data input terminal of FF5 (204) is supplied with the reception signal A synchronized by the aforementioned FF2 (201) to FF3 (202), and the clock input terminal is supplied with the reception timing signal RTI. The received signal is sampled by the timing signal RTI, and the sampled signal is sent to the output terminal (CL) of XB.
and set (retain) this FF5 (2
04) is generated at the output of G)G, + (
212). In addition, according to the above value of B,
The method of subsequent sampling can then be determined. Also, FF
The RTST signal is input to the J input terminal of 6 (205), and the K
A reception timing signal RT2 is supplied to the input terminal, and a strobe signal STB1 shown in FIG. 8 is set at the output by the RTST signal. This strobe signal 5TBI is supplied to gate G7 (208) and gate G+o (211).

In the above F F 5 (204), if the input A is “l”, the output B will be “0”, and the input A will be O
”, the output loop B becomes “l”.

Now, considering the case where A, which is an input to FF5 (204), is already "0" before the RTI timing, A becomes "O" and B becomes "1" at the RTI timing. At this time, since aB = "1m, the output of gate G11 (212) is "0", and since A is "O", gate Ga (2
The output of 09) is “0”, therefore the output of Ge (210) is 0”, and the input of shifter 2 (206) is “0”.
becomes. RT, which is then supplied to the clock input terminal of shifter 2 (206) via gate G6 (207).
At timing 2, set "0" to D7 of shifter 2 (20'i), and similarly, at timing RT3, shift the previously set "0" from data terminal D7 to D6 and set D7 to "0". As a result, the shifter 2 (206) performs a shift operation based on the clock, and the value of D7 at that time is G? (208) and the gate G+o(
211). Also, if the input A of FF5 (204) has not yet become 0 at the RTI timing, A will be 1 at the R'T'l timing.
, Masu B becomes "0". At this time, gate Go (212
) will depend on the output of gate Goo (211), but gate Gro (211) has an FF
6 (205) supplies the strobe signal STB1 generated at the timing shown in FIG. The strobe signal STB1 is R”rs as shown in FIG.
This signal is "1" from the falling edge of the T signal to the falling edge of the reception timing signal RT2. Considering the time before RT2 is input, the strobe signal STB1 is 1", so the gate Goo( The output of gate Go (211) becomes "L", and the output of gate Go (212) becomes "O". At this time,
Gate Gg (209) is supplied with strobe signal STB 1 via gate c, (208) and the above-mentioned received signal A, and its output is sent to the input terminal of shifter 2 (206) via gate G9 (210). and is set to D7 at the timing of RT2. Furthermore, new input data is set in D7 while shifting data from D7 to D6 at the timing of RT3, but at this time STB 1 = “0
” Therefore, A or +B is input to the shifter 2 by G7 to GH according to the value of D7 set by RT2. That is, when D7 is “0”, the output of GIG is “1”,
Since G7 is "0", the value of B is input by Gll, and when D7 is "1", the output of G10 is "0", and G7 is
”, so the value of A is input by G8.The above shifter 2 (206) has an 8-bit configuration, so it becomes full when there are 4 inputs, but at this time, a flag is sent to the control circuit (5). is sent, (D?, Df, ...Do)
The configuration is such that the parallel data of is taken into the control circuit (5) via the data bus (6). Alternatively, a buffer may be provided between the shifter 2 (206) and the control circuit (5), and the buffer may be configured to send out a seven-level signal to notify that it is full, and to take in data.

In the above-mentioned embodiment, an example was explained in which the transmitting side and the receiving side were each equipped with a transmitting circuit (11) and a receiving circuit (2), but as shown in FIG. 9, the transmitting circuit (1)
It can also be used as a control interface for a small computer workstation by having a configuration that includes both a receiver circuit (2) and a receiver circuit (2).

〔Effect of the invention〕

As explained above, the present invention decodes 2-bit parallel data on the transmitting side, converts it into one serial data having a time length corresponding to the 2-bit data, and transmits it, and the receiving side decodes the above serial data. The structure is configured to decode into 2-bit data based on the time length of , and 2-bit parallel data can be sent by sending serial data once, so the transmission time in serial transmission can be reduced. is obtained.

[Brief explanation of drawings]

1121 is a principle diagram for explaining the present invention, FIG. 2 is a waveform diagram showing data timing in serial transmission of the present invention, FIG. 3 is a transmission system diagram according to the present invention, and FIG. 4 is a transmitting circuit according to the present invention. 5 is a waveform diagram showing the transmission timing according to the present invention, FIG. 6 is a receiving system diagram according to the present invention, FIG. 7 is a circuit diagram of the receiving circuit according to the present invention, and FIG. 8 is a waveform diagram showing the transmission timing according to the present invention. FIG. 9 is a waveform diagram showing reception timing according to the present invention; FIG. 9 is a configuration diagram showing another embodiment according to the present invention;
Figure O is a waveform diagram showing data timing in conventional serial transmission. (1)...Transmission circuit, (2)...Reception circuit, (3)
...Transmission line. ＆ Kakeru Figure $ - Momoro's Tenita Taimi) Figure 2 Figure 2 for the rate date; Figure 6 Figure 6 of Setoreito Tomome 1 and Iword Daimi Sig Figure 1 of Seotsu (Figure 9)

Claims (1)

[Claims] Decodes 2 bits of parallel data during transmission, and
By converting it into one serial data having a time length corresponding to the bit parallel data and transmitting it, and decoding it into 2-bit parallel data based on the time length of the one serial data at the time of reception, one serial data A serial transmission method characterized by being able to send 2-bit parallel data by sending data.