JPS59163937A - Decoding system of digital code - Google Patents

Abstract

PURPOSE:To decode a transmitted digital code by receiving a receiving code of a specific code form, applying an exclusive OR between the said code and a code delayed by 1 bit, and applying exclusive OR between an output code and a code delayed by one bit and NOT operation to the result. CONSTITUTION:A code is applied with the finite sum conversion into a transmission code inserted with one code in 1 bit to each 1 bit of a binary digital information code string having a time slot T0 and a clock frequency f0 to be transmitted at the transmission side and the code is transmitted. The received code is received at a terminal 16 at the receiving side and the finite difference conversion is applied to a T0/2 delay circuit 17 and an exclusive OR circuit 18. NOT operation is applied at a circuit 20 to the converted code string (m) after the exclusive OR is applied to a code delayed by a T0/2 delay circuit 19. The outputted code train (o) waveform-shaped by clocks q, q' frequency-dividing 22 a 2 f0 clock from a terminal 21 by 1/2 and decoded into code strings r, r'. Thus, the code is cooded simply and surely.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a digital code decoding system, and more specifically, in a binary transmission system such as an optical fiber transmission system or an optical data link, it is possible to decode a digital code based on a special conversion rule. This relates to a method for decoding a transmission code encoded in 1 to the original information code.

[Prior art]

In binary transmission systems such as optical fiber transmission systems and optical data links, the transmitting side inserts a 1-bit 61" code on the time axis for each bit of the input binary digital information code string to be transmitted. A code format is used in which a transmission code with a frequency θ which is twice the input clock frequency is obtained, a summation conversion is performed on this transmission code, and the reverse code conversion operation is performed on the receiving side.Hereinafter, This code format is DMI
(Differential Mode Invers
ion) code.

FIG. 1 shows an example of a DMI code conversion circuit, where 1 is an information code input terminal, 2 is a "'l" code insertion circuit, 3 is an exclusive OR circuit, and 4 is a T. /2 delay circuit, 5 is an output terminal. The principle of this operation will be explained below with reference to the time chart of FIG.

Time slot T from input terminal 1. , clock frequency 1
A binary digital information code string having ゜ (FIG. 2 a) is input, and a "1" code is inserted by the ``''1# code insertion circuit 2. This code string ~' (FIG. 2 b) is , given by the following equation.

When n = 2n -1, SrL' = I,
(i) When n == 27z, S,'=i
(2) For this code string SrL', the output code string (second Figure C) is obtained. At this time, the output signal
is given by X,': XrL/, -1■Sn' (3). Here, "■" is an exclusive OR. The system composed of these circuits 3 and 4 is a summation conversion circuit.

In the DMI code obtained using this code string or a similar code rule, the clock frequency of the code converted code string is 2fo
The delay time for 1 bit is %/2.

FIG. 3 shows a basic block diagram of a conventional decoding circuit for a corrupted DMI code. In Figure 3, 6 is DMI
Sign input terminal, 7 is T. /2 delay circuit, 8 is exclusive OR circuit, 9 is 2fo clock input terminal, 1o is 1//2
Frequency dividing circuit, 11 and 12 are D type flip-flops, 1
3 is a clock phase detection circuit, 14 is a monitor signal selection switch, and 15 is an output terminal.

FIG. 4 is a time chart for explaining the operation of FIG. 3, and the principle of operation of FIG. 3 will be explained based on this.

DMI received code string XrL from input terminal 6! (Fig. 4d
) is buried by 1V2 in the delay circuit 17 (Fig. 4e),
Exclusive OR circuit 8: performs exclusive OR and performs differential conversion. That is, XrL'■XrL'-,: S, /
From (4), exclusive OR circuit 8
The output signal sequence (Fig. 4 f) corresponds to the signal before the summation transformation in Fig. 1, and the original information code IU and the inserted '1'' code are arranged alternately. The clock signal 2foC from the clock input terminal 9 extracted in Figure 4g) is 1z
The frequency is divided by the frequency divider 10, and 1.02 sets of clock output waveforms (FIG. 4 and i) having mutually opposite phases are obtained. Using the clock h, the D-type flip-flop 11 reproduces the original information code string (FIG. 4j) from the signal after differential conversion (FIG. 4f). At this time, the time chart in FIG. 4 shows the assumption that the D type flip-flop 11 operates at the rising edge of the 3rd turn signal.

By the way, the phase of the output clock signal of the output of the 1/2 frequency divider 10 is inverted depending on the initial value. Then h in Figure 4
tsJ and k are exchanged, and the original information code string E is output from the flip-flop 12. Therefore, as shown in FIG. 3, it is necessary to detect the Q outputs of flip-flops 11 and 12 with the clock phase detection circuit 13, and to switch the switch 14 so that the information code string is always guided to the output terminal 15. .

In this way, in the conventional DMI code decoding circuit, the clock 4. Since there is phase uncertainty in this method, it has the disadvantage of requiring large-scale synchronization circuits such as a phase detection circuit and a signal switching circuit.

[Purpose of the invention]

An object of the present invention is to provide a decoding circuit that can easily and reliably obtain the original information code without requiring a large-scale synchronization circuit.

[Summary of the Invention] The present invention performs exclusive OR conversion between a received DMI code and a code delayed by 1 bit from the received DMI code, and further converts the output code and a code obtained by delaying the output code by 1 bit. This method is characterized in that the binary digital code string inputted on the transmitting side is obtained by performing exclusive OR of and then negating the result.

[Embodiments of the invention]

FIG. 5 is an embodiment of the present invention, and is a block diagram of a DMI code decoding circuit. In FIG. 5, 16 is a DMI code input terminal, and 17 is T. /2 delay circuit, 18 is an exclusive OR circuit, and 19 is T. 2 is a delay circuit, 2 is an exclusive OR NOT circuit, 21 is a 2FO clock input terminal, n is a 1z2 frequency divider circuit, 2 is a D type flip-flop, 5 is an information code output terminal, and 5 is f. This is a clock output terminal. Figure 6 shows
3 is a time chart for explaining the operation of this circuit.

DMI code string XrL'(8
6), first the delay circuit 17 and the exclusive OR circuit 18
Then, the code string shown in FIG. 6 is obtained. In this code string, the original information code string Eyu and '11)l code are arranged alternately. Next, convert this code string to T. The signal is shifted by 1 bit in the /2 delay circuit 19 (FIG. 6n), and the exclusive OR is performed in the circuit section, followed by its negation.

Then, 1 = I = IT, (51).Here, "-" represents negation.Therefore, the output of the circuit section contains the original information code as shown in Fig. 60. is 2
The bits will be lined up one by one.

Ideally, the output code string 0 of the circuit section is the original information code string before DMI code conversion. However, in reality, jitter increases due to delays in electronic circuits and slight phase shifts in logic circuits, causing waveform distortion. Furthermore, a clock output signal that is in phase with the output information code is required to operate the circuit connected to this circuit. Therefore, in order to waveform shape this code string (FIG. 6 0), f. clock is required. In FIG. 5, the 21o clock signal (61qp) from the clock input terminal 21 is applied to the 174 frequency divider circuit f. The frequency is divided into At this time, clocks of both positive and negative phases are generated as shown in q and q of FIG. 6, but in this decoding circuit, the clock f. outputs the information code string r (or r') in FIG. 6 to the output terminal at a phase of q (or q'). That is, the original information code string can be decoded regardless of the clock phase.

Therefore, the circuit shown in FIG. 5 does not require a circuit for detecting the phase of the clock and accurately outputting the information code string, making it possible to significantly reduce the number of circuit components in the decoding circuit.

〔Effect of the invention〕

As explained above, according to the present invention, when decoding a DMI code, it is possible to ignore the phase uncertainty when dividing the 2M clock signal into fo.
The MI decoding circuit can be easily configured without a complicated circuit for detecting the clock phase and outputting the correct information code string, and also reliably prevents signal loss until the correct information code string is output. There are advantages that can be achieved.

[Brief Description of the Drawings] Figure 1 is a diagram showing an example of a DMI code conversion circuit, Figure 2 is a timing diagram for explaining the operating principle of Figure 1, and Figure 3 is a conventional DMI code decoding circuit. Basic block diagram of 4th
3 is a timing diagram for explaining the operation of FIG. 3, and FIG. 5 is a basic block diagram of an embodiment of the decoding circuit according to the present invention.
FIG. 6 is a timing diagram for explaining the operation of FIG. 5. 16...DMI code input terminal, 17...To/2
Delay circuit, 18... Exclusive OR circuit, 19...
・T0/2 delay circuit, addition...exclusive OR NOT circuit, 4...2fo clock input terminal, n...1
/2 frequency divider circuit, D type flip-flop,
Sae...information code output terminal, 6...fo clock signal output terminal. Fig. 1 27-=+ Co bar, ×2×3X4〆s X6 X7 ×g ×f
×t. Figure 3 Figure 5 Cause January Figure 4

Claims (1)

[Claims] (1) On the transmitting side, a transmission code with a clock frequency twice that of the input clock frequency is created by inserting one bit of 1'' code into each bit of the input binary digital information code string to be transmitted. In a code conversion method in which summation conversion is performed on this transmission code, and the reverse code conversion operation is performed on the receiving side, on the receiving side, the exclusive logic of the received code and a code delayed by 1 bit of this received code is calculated. Japanese Natori,
A digital code characterized in that the output code and a code obtained by delaying the output code by 1 bit are subjected to exclusive OR and then negated to obtain a binary digital information code string input on the transmitting side. Decoding method.