JP2007140490A - Semiconductor device, and display device and electronic equipment each having the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption by reducing the amplitude of a data line when controlling lighting/extinction of a light-emitting element. <P>SOLUTION: A semiconductor device includes; a first transistor to which a first scan signal is supplied through a first scan line; a second transistor to which a second scan signal is supplied through a second scan line; a third transistor which is turned on or off depending on a first signal supplied from a current supply line through the first transistor and a second signal supplied from a data line through the second transistor; a pixel electrode; and the light-emitting element which emits light by a driving current flowing between the pixel electrode and a counter electrode. The first signal cuts electrical connection between the current supply line and the pixel electrode through the third transistor, and the second signal makes the current supply line and the pixel electrode electrically connected through the third transistor. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device. The present invention particularly relates to a pixel structure in an active matrix display including a light-emitting element and manufactured using a semiconductor device. In addition, the present invention relates to a display device including a semiconductor device and an electronic device including the display device.

  Note that the semiconductor device here refers to all devices that can function by utilizing semiconductor characteristics.

  In recent years, the demand for thin displays has rapidly expanded mainly for TVs, PC monitors, mobile terminals, and the like, and further development is being promoted. Thin displays include liquid crystal display devices (LCDs) and display devices equipped with light emitting elements. In particular, active matrix displays using light emitting elements are combined with the advantages of existing LCDs such as thinness, light weight, and high image quality. Therefore, it is expected as a next-generation display because it has features such as a high response speed and a wide visual field characteristic.

In an active matrix display using a light-emitting element, the most basic pixel structure is the structure shown in FIG. 24A (see, for example, FIGS. 19, 20A, and 20B of Patent Document 1). ). In FIG. 24A, a pixel includes a driving transistor 2402 that controls supply of current to the light-emitting element 2404, and a switch that takes the potential of the data line 2406 into a gate (hereinafter also referred to as nodeG) of the driving transistor 2402 through a scanning line 2405. A storage capacitor 2403 that holds the potential of the transistor 2401 and the nodeG is included.
JP 2004-4910 A

  In FIG. 24A, an active matrix display having a light-emitting element 2404 is driven by supplying an analog value to the gate of the driving transistor 2402 and continuously changing the analog value to express analog. It is divided into driving and digital driving for supplying a digital value to the gate of the driving transistor 2402. In digital driving, there is a digital time gray scale method in which one frame period is divided into a plurality of subframes, and a light emission period is controlled to express a gray scale. Digital driving has advantages such as being more resistant to variations in transistors than analog driving.

  FIG. 24B shows a specific example of the potential relationship and operation timing when driving the above-described pixel of FIG. 24A, and the operation will be described. At this time, the driving method of the light emitting element 2404 is digital driving. As shown in FIG. 24B, in the pixel structure shown in FIG. 24A, when the scanning line 2405 becomes a potential for turning on the driving transistor 2402 (here, a High potential), the potential of the data line 2406 is taken into nodeG.

  In FIG. 24A, since the switch transistor 2401 is an N-channel transistor and the driving transistor 2402 is a P-channel transistor, when the potential of the scan line 2405 becomes High, the switch transistor 2401 is turned on and the potential of the data line 2406 is Is taken into nodeG and the low potential of the data line 2406 is taken in, so that the light emitting element 2404 emits light, and when the high potential of the data line 2406 is taken into nodeG, each potential is set so that the light emitting element 2404 is turned off.

  A specific example of each potential will be described. In FIG. 24A, the potential of the counter electrode of the light-emitting element 2404 is GND (hereinafter, 0 V), the potential of the current supply line 2407 is 7 V, and the data line 2406 is high. The potential is 7 V, the Low potential is 0 V, the High potential of the scanning line 2405 is 10 V, and the Low potential is 0 V.

  A change in potential of each wiring is described with reference to FIG. In the period where the scanning line 2405 is 10 V, the switch transistor 2401 is turned on, and the potential of the data line 2406 is taken into the nodeG. If a potential of 0V is taken into nodeG, Vgs (gate-source voltage) is applied to the driving transistor 2402, and the driving transistor 2402 operates sufficiently in the linear region. At this time, a voltage of about 7 V is applied to the light emitting element 2404, and a current flows depending on the resistance of the light emitting element 2404 to emit light. In addition, when a potential of 7 V is taken into nodeG, the driving transistor 2402 is turned off with Vgs of 0 V, and the light emitting element 2404 is turned off. The potential of nodeG is held by the storage capacitor 2403 until the potential of the scanning line 2405 becomes High again.

  In the example described with reference to FIG. 24A, the High potential and Low potential of the data line 2406 are directly set to the nodeG potential. In general, the High potential of the data line 2406 is set equal to or higher than the potential of the current supply line 2407. Therefore, when the voltage applied to the light emitting element 2404, that is, the potential of the current supply line 2407 is increased, the voltage of the data line 2406 needs to be increased.

  By the way, in the digital drive, the scanning line 2405 outputs a selection pulse in order of each row by the scanning line driving circuit, and the data line 2406 outputs a data signal to all the columns simultaneously by the data line driving circuit in accordance with the selection pulse of each row. Is done.

The power consumption of the driving circuit of the display device that is digitally driven is predominantly the power consumption of the buffer portion of the data line driving circuit that charges and discharges the data line 2406. When the frequency is F, the capacity is C, and the voltage is V, the power consumption P is generally obtained by the equation (1).
P = FCV ² (F: frequency C: capacity V: voltage) (1)

  Therefore, it can be seen from equation (1) that setting the voltage of the data line 2406 small is effective for power saving.

  In view of the above problems, the pixel configuration of the present invention relates to control of the light emitting state / light-off state of a light emitting element, and proposes a pixel configuration and a driving method capable of reducing the voltage of a data line and reducing power consumption.

  According to one aspect of the semiconductor device of the present invention, a first transistor in which a first scanning signal is applied to a gate through a first scanning line, and a second scanning signal to the gate through a second scanning line. The second transistor to be applied, the third transistor to be driven and controlled in accordance with the first signal and the second signal applied to the gate, the pixel electrode, the pixel electrode, and the counter electrode flowing between A first signal supplied from the current supply line via the first transistor is electrically connected to the pixel electrode from the current supply line via the third transistor. The second signal supplied from the data line through the second transistor is a signal for electrically connecting the current supply line and the pixel electrode by the third transistor. .

  Still another semiconductor device of the present invention includes a first transistor in which a first scanning signal is applied to a gate through a first scanning line, and a second scanning signal through a second scanning line. A second transistor applied to the gate, a third transistor driven and controlled according to the first signal and the second signal applied to the gate, a pixel electrode, a pixel electrode, and a counter electrode A first signal supplied from the power supply line via the first transistor is an electric current between the current supply line via the third transistor and the pixel electrode. The second signal supplied from the data line via the second transistor is a signal for electrically connecting the current supply line and the pixel electrode by the third transistor. And

  The potential of the power supply line and the potential of the current supply line may be different.

  The first transistor and the second transistor may be N-channel transistors, and the third transistor may be a P-channel transistor.

  Still another semiconductor device of the present invention includes a first transistor in which a first scanning signal is applied to a gate through a first scanning line, and a second scanning signal through a second scanning line. The second transistor applied to the gate, the third transistor driven and controlled according to the potential of the current supply line, and the drive controlled according to the first signal and the second signal applied to the gate. A fourth transistor, a pixel electrode, and a light-emitting element that emits light by a driving current flowing between the pixel electrode and the counter electrode, from the first scan line through the first transistor and the third transistor. The first signal supplied is a signal for disconnecting the electrical connection between the current supply line and the pixel electrode via the fourth transistor, and the second signal supplied from the data line via the second transistor. The signal of the current supply line A structure is a signal for electrically connecting the pixel electrode by a fourth transistor.

  The first transistor, the second transistor, and the third transistor may be N-channel transistors, and the fourth transistor may be a P-channel transistor.

  Still another semiconductor device of the present invention includes a first transistor in which a first scanning signal is applied to a gate through a first scanning line, and a second scanning signal through a second scanning line. The second transistor applied to the gate, the third transistor driven and controlled according to the potential of the current supply line, the fourth transistor driven and controlled by the first scanning signal, and the gate applied A fifth transistor driven and controlled in accordance with the first signal and the second signal, a pixel electrode, and a light emitting element that emits light by a driving current flowing between the pixel electrode and the counter electrode. The first signal supplied from one scanning line via the first transistor and the fourth transistor is a signal for disconnecting the electrical connection between the current supply line and the pixel electrode via the fifth transistor. Second from the data line The second signal supplied through the transistor has a structure which is a signal to electrically connect the current supply line and the pixel electrode by a fifth transistor.

  The first transistor, the second transistor, the third transistor, and the fourth transistor may be N-channel transistors, and the fifth transistor may be a P-channel transistor.

  Further, the amplitude of the first scanning signal may be larger than the amplitude of the second scanning signal.

  According to another aspect of the method for driving a semiconductor device of the present invention, a first transistor in which a first scanning signal is applied to a gate through a first scanning line, and a second scanning signal is applied to a second scanning line. Through the second transistor applied to the gate via the third transistor, the third transistor driven and controlled in accordance with the potential applied to the gate, the pixel electrode, and the drive current flowing between the pixel electrode and the counter electrode. The first transistor is turned on by the first scanning signal, and the gate of the third transistor is electrically connected between the current supply line and the pixel electrode via the third transistor. The first signal for disconnecting the first transistor is input from the current supply line via the first transistor, the first transistor is turned off by the first scanning signal, and the second scanning signal is output. By the second There is a second period in which the transistor is turned off, and a third period in which the second scan signal is input to the second transistor. In the third period, the potential of the data line is the potential of the second scan signal. When smaller, the second signal for electrically connecting the current supply line and the pixel electrode by the third transistor is input to the gate of the third transistor from the data line via the second transistor. The configuration is as follows.

  The first signal may be input via a first transistor from a wiring having a potential different from that of the current supply line.

  The first transistor and the second transistor may be N-channel transistors, and the third transistor may be a P-channel transistor.

  According to still another method of driving a semiconductor device of the present invention, a first transistor in which a first scanning signal is applied to a gate through a first scanning line and a second scanning signal in a second scanning are used. A second transistor applied to the gate via the line, a third transistor controlled by the potential of the current supply line, a fourth transistor controlled by the signal applied to the gate, And a light emitting element that emits light by a drive current flowing between the pixel electrode and the counter electrode. The first transistor is turned on by the first scanning signal, and the gate of the fourth transistor includes The first signal for disconnecting the electrical connection between the current supply line and the pixel electrode via the four transistors is input from the first scanning line via the first transistor and the third transistor. 1 period A second period in which the first transistor is turned off by the first scanning signal and the second transistor is turned off by the second scanning signal, and the second scanning signal is input to the second transistor A third period, and in the third period, when the potential of the data line is lower than the potential of the second scanning signal, a current supply line and a pixel electrode are connected to the fourth transistor at the gate of the fourth transistor. The second signal to be electrically connected by the transistor is input from the data line through the first transistor and the second transistor.

  The first transistor, the second transistor, and the third transistor may be N-channel transistors, and the fourth transistor may be a P-channel transistor.

  According to still another method of driving a semiconductor device of the present invention, a first transistor in which a first scanning signal is applied to a gate through a first scanning line and a second scanning signal in a second scanning are used. A second transistor applied to the gate via the line, a third transistor controlled by the potential of the current supply line, a fourth transistor controlled by the first scanning signal, and applied to the gate Including a fifth transistor that is driven and controlled in response to a signal to be emitted, a pixel electrode, and a light-emitting element that emits light by a drive current flowing between the pixel electrode and the counter electrode. The first transistor and the fourth transistor are turned on, and the first signal for disconnecting the electrical connection between the current supply line and the pixel electrode through the fifth transistor is supplied to the gate of the fifth transistor. 1 A first period input from the scan line through the first transistor and the fourth transistor, the first transistor is turned off by the first scan signal, and the second transistor is turned on by the second scan signal There is a second period in which the transistor is turned off, and a third period in which the second scanning signal is input to the second transistor. In the third period, the potential of the data line is smaller than the potential of the second scanning signal. At this time, a second signal for electrically connecting the current supply line and the pixel electrode by the fourth transistor is input to the gate of the fourth transistor from the data line through the first transistor. The configuration.

  The first transistor, the second transistor, the third transistor, and the fourth transistor may be N-channel transistors, and the fifth transistor may be a P-channel transistor.

  Further, the amplitude of the first scanning signal may be larger than the amplitude of the second scanning signal.

  By using the semiconductor device and the driving method of the present invention, a potential for turning on the driving transistor applied to the gate of the driving transistor is supplied from the data line, and a potential for turning off the driving transistor is supplied to another current supply line or the like. It can be supplied from wiring. Therefore, the semiconductor device and the driving method of the present invention can set the voltage of the data line to be low, and can greatly reduce the power consumption.

  Hereinafter, embodiments and examples of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in the drawings described below, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
A first embodiment of the semiconductor device of the present invention will be described. A specific pixel configuration is shown in FIG. 1 and will be described in detail. Although only one pixel is shown here, a plurality of pixels are actually arranged in a matrix in the row direction and the column direction in the pixel portion of the semiconductor device.

  In the pixel structure of the present invention, the first transistor 101 (also referred to as a reset transistor) that takes in the potential of the current supply line 109 to the node G during a period when the first scanning line 106 is selected by the first scanning signal, A second transistor 102 (also referred to as a selection transistor) that controls whether the node G and the data line 108 are turned on by the potential of the data line 108 and the potential of the second scanning line 107 during a period in which the scanning line 107 is selected; A third transistor 103 (also referred to as a drive transistor) that controls current supply from the current supply line 109 to the light-emitting element 105 with a potential of nodeG and a storage capacitor 104 that holds the potential of nodeG are included. Note that in this embodiment, for the sake of description, N-channel transistors are used for the first transistor 101 and the second transistor 102, and P-channel transistors are used for the third transistor 103. The light-emitting element 105 will be described on the assumption that a current flows from the current supply line 109 to the counter electrode 110 and emits light. However, when the configuration of the light emitting element is changed or when the polarity of the transistor is changed, the connection of terminals of each transistor and the signal to each wiring may be changed as appropriate.

  Note that one of two electrodes of the storage capacitor 104 is connected to the gate of the third transistor 103 and the other is connected to the current supply line 109. The storage capacitor 104 is provided to more reliably maintain the voltage (gate voltage) between the gate and the source of the third transistor 103, but the node G holds the potential of nodeG with a parasitic capacitor such as the third transistor 103. If possible, a storage capacitor is not necessarily provided. In addition, one electrode of the storage capacitor 104 is not necessarily connected to the current supply line 109 as long as the potential of the gate of the third transistor 103 can be held.

Note that in this specification, a transistor is described as an example in which a thin film transistor (TFT) is used. As the semiconductor used for the channel formation region, amorphous silicon or crystalline silicon is used. Further, as a semiconductor used for the channel formation region, a compound semiconductor, more preferably an oxide semiconductor may be used. Examples of the oxide semiconductor include zinc oxide (ZnO), titanium oxide (TiO ₂ ), magnesium zinc oxide (Mg _x Zn _1-x O), cadmium zinc oxide (Cd _x Zn _1-x O), and cadmium oxide (CdO). ) Or an In—Ga—Zn—O-based amorphous oxide semiconductor (a-IGZO) or the like may be used.

In the present specification, the connection means an electrical connection unless otherwise specified. On the contrary, the disconnection means a state in which they are electrically separated by a switch such as a transistor.

  One of the source and the drain of the first transistor 101 is connected to the current supply line 109. The other of the source and the drain of the first transistor 101 is connected to the gate of the third transistor 103. The gate of the first transistor 101 is connected to the first scanning line 106. One of the source and the drain of the second transistor 102 is connected to the data line 108. The other of the source and the drain of the second transistor 102 is connected to the gate of the third transistor 103. The gate of the second transistor 102 is connected to the second scanning line 107. One of the source and the drain of the third transistor 103 is connected to the current supply line 109. The other of the source and the drain of the third transistor 103 is connected to a pixel electrode (not shown). One electrode of the light emitting element 105 is connected to the pixel electrode, and the other electrode is connected to the counter electrode 110. One electrode of the storage capacitor 104 is connected to the gate of the third transistor 103, and the other electrode is connected to the current supply line 109.

Note that in this specification, the light-emitting element can have a structure sandwiched between a pixel electrode and a counter electrode.

In this embodiment mode, one electrode of the light-emitting element is connected to the pixel electrode, and the other electrode of the light-emitting element is connected to the counter electrode. However, the pixel electrode also serves as one electrode of the light-emitting element. The other electrode may also be used. In that case, the pixel electrode functions as an anode of the light emitting element, and the counter electrode functions as a cathode of the light emitting element.

  Note that a potential Vss lower than that of the current supply line 109 is set to the counter electrode 110 of the light emitting element 105. Note that Vss is a potential that satisfies Vss <Vdd with reference to the potential Vdd set in the current supply line 109 during the light emission period of the pixel. For example, Vss = GND (ground potential) may be used.

  Next, the operation method of the pixel configuration in FIG. 1 is described with reference to FIGS. 2A, 2B, 3A, 3B, 4A, and 4B. explain.

  First, FIG. 2A shows a timing chart of the first scanning line 106, the second scanning line 107, the data line 108, and the node G for the pixel configuration of FIG. 1 of the present invention. In the pixel configuration of the present invention, there are a reset period, a blank period, and a sustain period (a period in which the state is maintained by the storage capacitor until the next data signal is input after being turned on or off by the data signal). .

  In the pixel configuration of the present invention, a potential for turning off the driving transistor is input in advance to the gate of the driving transistor in the pixel, that is, the storage capacitor. This period in which a signal for turning off the driving transistor is previously input to the gate of the driving transistor in the pixel is referred to as a reset period in this specification.

  In the pixel configuration of the present invention, a signal for controlling on / off of the driving transistor is controlled by the first scanning line and the second scanning line. Therefore, in the pixel configuration of the present invention, if the first scanning line and the second scanning line simultaneously turn on the first transistor and the second transistor, current is supplied between the current supply line and the data line. It is not preferable. Therefore, in the pixel configuration of the present invention, a period in which neither the first transistor nor the second transistor is turned on is provided in order to prevent a current supply line from energizing the data line by providing a blank period. In this embodiment, a period in which neither the first transistor nor the second transistor is turned on by the control of the first scan line and the second scan line is referred to as a blank period. Of course, this blank period is not necessarily provided when another switch or the like is provided in order to prevent the current supply line from energizing the data line in this pixel configuration.

  2A, 2 </ b> B, 3, and 4, a description will be given of specific examples of changes and timings of potentials of respective portions in the reset period, the blank period, and the sustain period, and on and off of each transistor. When the voltage applied to the light emitting element is 8 V, the potential of the current supply line 109 is 8 V, the potential of the counter electrode 110 is 0 V, the High potential of the first scanning line 106 is 10 V, the Low potential is 0 V, and the second scan. The high potential of the line 107 is 3V, the low potential is 0V, the high potential of the data line 108 is 3V, and the low potential is 0V. The threshold values of the first transistor 101 and the second transistor 102 are 1 V, and the third transistor 103 operates in a sufficiently linear region.

First, in the reset period, the potential of the first scanning line 106 becomes High (10 V), the first transistor 101 is turned on, and the node G becomes the potential 8 V of the current supply line 109, and Vgs (gate and gate) of the third transistor 103. The voltage between the sources) becomes 0 V, and the third transistor 103 is turned off (FIG. 3A).

Next, a blank period is provided to prevent the first transistor 101 and the second transistor 102 from being turned on at the same time and energizing between the current supply line 109 and the data line 108. In addition, it is necessary to determine the potential of the data signal before the second scanning line 107 is set to High (3 V). The potential of the data line 108 is set to Low (0 V) when the light emitting element is turned on, and is set to High (3 V) when turned off (FIG. 3B).

In the sustain period, when the second scanning line 107 is set to High (3 V), if the potential of the data line 108 is High (3 V), the second transistor 102 is turned off because Vgs (voltage between the gate and the source) is 0 V. , NodeG maintains 8V (FIG. 4B). Further, when the second scanning line 107 is set to High (3 V), if the potential of the data line 108 is Low (0 V), Vgs of the second transistor 102 is turned on to 3 V, and nodeG is the same as the potential of the data line 108. The voltage becomes 0 V (FIG. 4A). As a result, the potential of nodeG is determined to be High (8 V) or Low (0 V), and is held by the holding capacitor 104 for a certain period.

  As described above, the pixel configuration and the driving method of the semiconductor device of the present invention relate to the control of the light emitting state / light-off state of the light emitting element according to the data signal, and the third transistor for driving the potential of the data line in the light emitting state. The gate potential of the third transistor for driving is set to the gate potential of the current supply line in the unlit state. Therefore, the voltage of the data line can be set low, and the power consumption can be greatly reduced.

This embodiment can be freely combined with any of the other embodiments and examples.
(Embodiment 2)

  In this embodiment mode, a structure of the present invention which is different from the pixel structure shown in FIG. 1 is described. FIG. 5 shows a specific configuration and will be described. Although only one pixel is shown here, a plurality of pixels are actually arranged in a matrix in the row direction and the column direction in the pixel portion of the semiconductor device.

In the first embodiment, the gate of the driving transistor when the light emitting element is turned off has the same potential as the current supply line. In this embodiment, a power supply line that can supply a potential different from that of the current supply line is provided, and the drive transistor can be turned off more reliably. As a result, when the potential is held for a certain period by the holding capacitor, a margin can be taken against fluctuation factors such as a leakage current when the transistor is off.

  As shown in FIG. 5, the pixel structure of this embodiment mode includes a first transistor 101 (also referred to as a reset transistor) that takes in the potential of the power supply line 551 by the first scanning line 106 and data by the second scanning line 107. A second transistor 102 (also referred to as a selection transistor) that takes in the potential of the line 108 to the node G, and a third transistor 103 (also referred to as a drive transistor) that controls current supply from the current supply line 109 to the light-emitting element 105 by the potential of the node G. In addition, a storage capacitor 104 that holds the potential of nodeG is included. Note that in this embodiment, for the sake of description, N-channel transistors are used for the first transistor 101 and the second transistor 102, and P-channel transistors are used for the third transistor 103. The light-emitting element 105 will be described on the assumption that a current flows from the current supply line 109 to the counter electrode 110 and emits light. However, when the configuration of the light emitting element is changed or when the polarity of the transistor is changed, the connection of terminals and signals may be changed as appropriate. The storage capacitor is also as described in the first embodiment.

  One of the source and the drain of the first transistor 101 is connected to the power supply line 551. The other of the source and the drain of the first transistor 101 is connected to the gate of the third transistor 103. The gate of the first transistor 101 is connected to the first scanning line 106. One of the source and the drain of the second transistor 102 is connected to the data line 108. The other of the source and the drain of the second transistor 102 is connected to the gate of the third transistor 103. The gate of the second transistor 102 is connected to the second scanning line 107. One of the source and the drain of the third transistor 103 is connected to the current supply line 109. The other of the source and the drain of the third transistor 103 is connected to a pixel electrode (not shown). One electrode of the light emitting element 105 is connected to the pixel electrode, and the other electrode is connected to the counter electrode 110. One electrode of the storage capacitor 104 is connected to the gate of the third transistor 103, and the other electrode is connected to the power supply line 551.

Note that although one electrode of the light-emitting element is connected to the pixel electrode and the other electrode of the light-emitting element is connected to the counter electrode in this embodiment mode, the structure in which the pixel electrode serves as one electrode of the light-emitting element is used. The structure which serves also as the other electrode of a light emitting element may be sufficient.

  FIG. 6 shows an example of a Vgs (voltage between gate and source) -Ids (current between drain and source) curves of a transistor. 6A shows the characteristics of the N-channel transistor, and FIG. 6B shows the characteristics of the P-channel transistor. In an ideal transistor, as indicated by a curve 601 in FIG. 6A and a curve 603 in FIG. 6B, Ids is sufficiently small when Vgs is 0 V, and the transistor functions can be achieved. However, as can be seen from the curve 602 in FIG. 6A and the curve 604 in FIG. 6B, the characteristics of the transistor shift, and current may flow even when Vgs is 0 V. And led to problems such as increased power consumption. In particular, in a light-emitting element with high light emission efficiency, light emission is visually recognized even with a small current, and a display defect tends to occur.

  In this embodiment mode, a power supply line 551 is provided. The potential Vdd2 of the power supply line 551 is set to a potential satisfying Vdd1 <Vdd2 as compared with the potential Vdd1 of the current supply line 109. For example, the potential of the current supply line 109 is 8V and the potential of the power supply line 551 is 10V. Accordingly, the gate of the driving transistor 103 when the light is turned off becomes 10 V, and the driving transistor 103 is surely at a potential to be turned off.

Note that in the pixel configuration in FIG. 5 in this embodiment mode, the driving method, timing, and the like are the same as those in FIGS. 2 to 4 shown in Embodiment Mode 1 and the description thereof. In addition, although the power supply line 551 is arranged in parallel with the data line 108, of course, it may be arranged perpendicular to the data line 108, and the arrangement of the power supply line 551 is not limited.

According to this embodiment, by setting the potentials of the current supply line and the power supply line separately, a signal for reliably turning off the drive transistor can be input to the gate of the drive transistor and applied to the gate of the drive transistor. A potential for turning on the driving transistor can be supplied from the data line, and a potential for turning off the driving transistor can be supplied from another wiring such as a current supply line. Therefore, the voltage of the data line can be set low, and the power consumption can be greatly reduced.

This embodiment can be freely combined with any of the other embodiments and examples.
(Embodiment 3)

  In this embodiment mode, a structure of the present invention which is different from the pixel structure shown in FIGS. 1 and 5 will be described. FIG. 7 shows a specific configuration and will be described. Although only one pixel is shown here, a plurality of pixels are actually arranged in a matrix in the row direction and the column direction in the pixel portion of the semiconductor device.

The pixel of this embodiment mode is characterized in that the first scan line 706 has three stages of potentials: a high potential (High potential), an intermediate potential (Middle potential), and a low potential (Low potential). Then, during the period in which the first scan line 706 is selected, the potential of the first scan line 706 is set to a high potential (High potential), the third transistor 711 and the first transistor 701 are turned on, and the node G has the first potential. A potential subtracted by the absolute value of the threshold value of the third transistor 711 from the high potential (High potential) of the scan line 706 is taken in. Then, the first scan line 706 becomes an intermediate potential (Middle potential), and the third transistor 711 is turned off. In addition, the pixel structure of this embodiment mode is based on the potential of the second transistor 702 controlled by the potential of the data line 708 and the potential of the second scan line 707, and the potential of the first scan line 706 having an intermediate potential (Middle potential). The first transistor 701 to be controlled, the fourth transistor 703 (also referred to as a driving transistor) that controls current supply from the current supply line 709 to the light emitting element 705 by the potential of the node G, and the first scanning line 706 The third transistor 711 and the storage capacitor 704 that holds the potential of the nodeG. During the period when the second scan line 707 is selected, conduction between the node G and the data line is controlled by the second transistor 702 and the first transistor 701.

Note that in this embodiment, for description, N-channel transistors are used for the first transistor 701 and the second transistor 702, and P-channel transistors are used for the third transistor 711 and the fourth transistor 703. Use. The light-emitting element 705 will be described on the assumption that a current flows from the current supply line 709 toward the counter electrode 710 and emits light. However, when the configuration of the light emitting element is changed or when the polarity of the transistor is changed, the connection of terminals and signals may be changed as appropriate.

Note that one of the two electrodes of the storage capacitor 704 is connected to the gate of the fourth transistor 703 and the other is connected to the current supply line 709. Although the storage capacitor 704 is provided to more reliably maintain the voltage (gate voltage) between the gate and the source of the fourth transistor, the storage capacitor 704 can hold the potential of the node G with a parasitic capacitor such as the fourth transistor 703. In this case, it is not always necessary to provide a storage capacitor. In addition, one electrode of the storage capacitor 704 is not necessarily connected to the current supply line 709 as long as the potential of the gate of the fourth transistor 703 can be held.

  One of the source and the drain of the first transistor 701 is connected to the first scan line 706 through the third transistor 711. The other of the source and the drain of the first transistor 701 is connected to the gate of the fourth transistor 703. The gate of the first transistor 701 is connected to the first scanning line 706. One of the source and the drain of the second transistor 702 is connected to the data line 708. The other of the source and the drain of the second transistor 702 is connected to one of the source and the drain of the first transistor 701. The gate of the second transistor 702 is connected to the second scanning line 707. One of the source and the drain of the third transistor 711 is connected to the first scan line 706. The other of the source and the drain of the third transistor 711 is connected to one of the source and the drain of the first transistor 701. The gate of the third transistor 711 is connected to the current supply line. One of the source and the drain of the fourth transistor 703 is connected to the current supply line 709. The other of the source and the drain of the fourth transistor 703 is connected to a pixel electrode (not shown). One electrode of the light emitting element 705 is connected to the pixel electrode, and the other electrode is connected to the counter electrode 710. One electrode of the storage capacitor 704 is connected to the gate of the fourth transistor 703, and the other electrode is connected to the current supply line 709.

Note that in this specification, the light-emitting element can have a structure sandwiched between a pixel electrode and a counter electrode.

In this embodiment mode, one electrode of the light-emitting element is connected to the pixel electrode, and the other electrode of the light-emitting element is connected to the counter electrode. However, the pixel electrode also serves as one electrode of the light-emitting element. The other electrode may also be used. In that case, the pixel electrode functions as an anode of the light emitting element, and the counter electrode functions as a cathode of the light emitting element.

  Note that the counter electrode 710 of the light emitting element 705 is set to a potential Vss lower than that of the current supply line 709. Note that Vss is a potential that satisfies Vss <Vdd with reference to the potential Vdd set in the current supply line 709 during the light emission period of the pixel. For example, Vss = GND (ground potential) may be used.

  Next, an operation method of the pixel configuration in FIG. 7 will be described with reference to FIGS.

  First, FIG. 8A shows a timing chart of the first scan line 706, the second scan line 707, the data line 708, and the nodeG for the pixel configuration in FIG. 7 of the present invention. In the pixel configuration of the present invention, there are a reset period, a blank period, and a sustain period (a period in which the state is maintained by the storage capacitor until the next data signal is input after being turned on or off by the data signal). .

  In the pixel configuration of the present invention, a potential for turning off the driving transistor is input in advance to the gate of the driving transistor in the pixel, that is, the storage capacitor. This period in which a signal for turning off the driving transistor is previously input to the gate of the driving transistor in the pixel is referred to as a reset period in this specification.

In the pixel configuration of the present invention, a signal for controlling on / off of the driving transistor is controlled by the first scanning line and the second scanning line. Therefore, in the pixel configuration of the present invention, when the first scan line and the second scan line simultaneously turn on the first transistor and the second transistor, the first scan line and the data line are energized. This is not preferable. Therefore, in the pixel configuration of the present invention, in order to prevent the energization between the first scan line and the data line by providing a blank period, a period in which both the first transistor and the second transistor are not turned on is provided. . In this embodiment, a period in which neither the first transistor nor the second transistor is turned on in the first scan line and the second scan line is referred to as a blank period. Of course, this blank period is not necessarily provided when a separate switch or the like is provided in order to prevent energization between the first scanning line and the data line in this pixel configuration.

  8B, 9, and 10, a change in potential of each portion in the reset period, blank period, and sustain period, timing, and on / off of each transistor will be described with specific examples. When the voltage applied to the light emitting element is 8 V, the potential of the current supply line 709 is 8 V, the potential of the counter electrode 710 is 0 V, the High of the first scanning line 706 is 10 V, the Middle potential is 3 V, the Low potential is 0 V, The high potential of the second scanning line 707 is 3V, the low potential is 0V, the high potential of the data line 708 is 3V, and the low potential is 0V. The absolute value of the threshold value of the first transistor 701, the second transistor 702, and the third transistor 711 is 1 V, and the fourth transistor 703 operates in a sufficiently linear region.

First, as shown in FIG. 9A, the potential of the first scan line 706 becomes High (10 V) in the reset period, the first transistor 701 and the third transistor 711 are turned on, and the node G is subjected to the first scan. The value is 9 V, which is obtained by subtracting the threshold value of the first transistor 701 from the potential 10 V of the line 706, and the fourth transistor 703 is turned off.

Next, as illustrated in FIG. 9B, a blank period is provided to prevent the second transistor 702 and the third transistor 711 from being turned on at the same time and supplying current between the first scan line 706 and the data line 708. . By setting the potential of the first scan line 706 to an intermediate potential (3 V) that is lower than the potential of the current supply line 709, the third transistor 711 is turned off and the first scan line 706 and the data line 708 are energized. Can be prevented. In addition, the potential of the data signal needs to be determined before the second scanning line 707 is set to High (3 V). The potential of the data line 708 is set to Low (0 V) when the light emitting element is turned on and is set to High (3 V) when the light emitting element is turned off.

Then, as shown in FIG. 10, when the sustain period is reached and the second scanning line 707 is set to High (3 V), the first scanning line 706 is also at the intermediate potential (3 V), and the potential of the data line 708 is High ( 3V), Vgs of the second transistor 702 is turned off at 0V, the first transistor 701 is also turned off, and nodeG is maintained at 9V (FIGS. 10C and 10D). In addition, when the second scanning line 707 is set to High (3 V), if the potential of the data line 708 is Low (0 V), Vgs of the second transistor 702 becomes 3 V and the first transistor 701 is turned on. nodeG becomes 0 V which is the same as the potential of the data line 708 (FIGS. 10A and 10B). As a result, the potential of nodeG is determined as High (9 V) or Low (0 V) and is held by the holding capacitor 704 for a certain period.

  As described above, by using the pixel configuration and the driving method of the semiconductor device of the present invention, the potential of the fourth transistor is set to the data in the light emitting state with respect to the control of the light emitting state and the off state of the light emitting element in accordance with the data signal. In the light-off state, the gate potential of the fourth transistor can be set to the potential of the current supply line. Therefore, the voltage of the data line can be set low, and the power consumption can be greatly reduced.

  This embodiment can be freely combined with any of the other embodiments and examples.

(Embodiment 4)

  In this embodiment mode, a structure of the present invention, which is different from the pixel structures shown in FIGS. 1, 5, and 7, will be described. FIG. 11 shows a specific configuration and will be described. Although only one pixel is shown here, a plurality of pixels are actually arranged in a matrix in the row direction and the column direction in the pixel portion of the semiconductor device.

In the pixel of this embodiment, the first transistor 1101 is turned on while the first scan line 1106 is selected, and a high potential is captured from the first scan line 1106 to the node G through the fourth transistor 1112. Accordingly, the fifth transistor 1103 is turned off. The high potential of nodeG is higher than the potential of the current supply line 1109 and is set to a value obtained by subtracting the absolute value of the threshold value of the fourth transistor 1112 from the first scan line 1106. In addition, the pixel structure in this embodiment mode emits light from the current supply line 1109 by the potentials of the second transistor 1102, the first transistor 1101, and nodeG controlled by the potential of the data line 1108 and the potential of the second scanning line 1107. A fifth transistor 1103 (also referred to as a driving transistor) that controls current supply to the element 1105, a third transistor 1111 that is controlled by the potential of the source terminal or the drain terminal, and the potential of the first scanning line 1106 are controlled. A fourth transistor 1112 and a storage capacitor 1104 that holds the potential of nodeG are included. Then, conduction between the node G and the data line is controlled by the second transistor 1102 during a period in which the second scan line 1107 is selected. Note that in this embodiment, N-channel transistors are used as the first transistor 1101, the second transistor 1102, the third transistor 1111, and the fourth transistor 1112, and the fifth transistor 1103 is used for description. Uses a P-channel transistor. The light-emitting element 1105 will be described on the assumption that a current flows from the current supply line 1109 to the counter electrode 1110 to emit light. However, when the configuration of the light emitting element is changed or when the polarity of the transistor is changed, the connection of terminals and signals may be changed as appropriate.

Note that one of two electrodes included in the storage capacitor 1104 is connected to the gate of the fifth transistor 1103 and the other is connected to the current supply line 1109. The storage capacitor 1104 is provided to more reliably maintain the voltage (gate voltage) between the gate and the source of the fifth transistor 1103, but the node G holds the potential of the node G with a parasitic capacitor such as the fifth transistor 1103. If possible, a storage capacitor is not necessarily provided. In addition, if the potential of the gate of the fifth transistor 1103 can be held, one electrode of the storage capacitor 1104 is not necessarily connected to the current supply line 1109.

  One of the source and the drain of the first transistor 1101 is connected to the first scan line 1106 through the fourth transistor 1112. The other of the source and the drain of the first transistor 1101 is connected to the gate of the fifth transistor 1103. The gate of the first transistor 1101 is connected to the first scan line 1106. One of the source and the drain of the second transistor 1102 is connected to the data line 1108. The other of the source and the drain of the second transistor 1102 is connected to the gate of the fifth transistor 1103. The gate of the second transistor 1102 is connected to the second scan line 1107. One of the source and the drain of the third transistor 1111 is connected to the current supply line 1109. The other of the source and the drain of the third transistor 1111 is connected to one of the source and the drain of the first transistor 1101. The gate of the third transistor 1111 is connected to the current supply line 1109. One of the source and the drain of the fourth transistor 1112 is connected to the first scan line 1106. The other of the source and the drain of the fourth transistor 1112 is connected to one of the source and the drain of the first transistor 1101. The gate of the fourth transistor 1112 is connected to the first scan line 1106. One of the source and the drain of the fifth transistor 1103 is connected to the current supply line 1109. The other of the source and the drain of the fifth transistor 1103 is connected to a pixel electrode (not shown). One electrode of the light emitting element 1105 is connected to the pixel electrode, and the other electrode is connected to the counter electrode 1110. One electrode of the storage capacitor 1104 is connected to the gate of the fifth transistor 1103, and the other electrode is connected to the current supply line 1109.

Note that although one electrode of the light-emitting element is connected to the pixel electrode and the other electrode of the light-emitting element is connected to the counter electrode in this embodiment mode, the structure in which the pixel electrode serves as one electrode of the light-emitting element is used. The structure which serves also as the other electrode of a light emitting element may be sufficient.

  Note that the counter electrode 1110 of the light emitting element 1105 is set to a potential Vss lower than that of the current supply line 1109. Note that Vss is a potential that satisfies Vss <Vdd with reference to the potential Vdd set in the current supply line 1109 during the light emission period of the pixel. For example, Vss = GND (ground potential) may be used.

  Next, an operation method of the pixel configuration in FIG. 11 will be described with reference to FIGS.

First, FIG. 12A shows a timing chart of the first scan line 1106, the second scan line 1107, the data line 1108, and the nodeG for the pixel structure of FIG. 11 of the present invention. In the pixel configuration of the present invention, there are a reset period, a blank period, and a sustain period (a period in which the state is maintained by the storage capacitor until the next data signal is input after being turned on or off by the data signal). .

  In the pixel configuration of the present invention, a potential for turning off the driving transistor is input in advance to the gate of the driving transistor in the pixel, that is, the storage capacitor. This period in which a signal for turning off the driving transistor is previously input to the gate of the driving transistor in the pixel is referred to as a reset period in this specification.

  In the pixel configuration of the present invention, a signal for controlling on / off of the driving transistor is controlled by the first scanning line and the second scanning line. Therefore, in the pixel configuration of the present invention, when the first scanning line and the second scanning line simultaneously turn on the first transistor and the second transistor, the current supply line and the first scanning line 1106 and the data line It is not preferable because current is applied between the two. Therefore, in the pixel configuration of the present invention, a period in which both the first transistor and the second transistor are not turned on is provided in order to provide a blank period to prevent energization of the data line. In this embodiment, a period in which neither the first transistor nor the second transistor is turned on in the first scan line and the second scan line is referred to as a blank period. Of course, this blank period is not necessarily provided when a separate switch or the like is provided in order to prevent energization of the data line in this pixel configuration.

  FIGS. 12B, 13 and 14 will be described with reference to specific examples of potential change, timing, and on / off of each transistor in the reset period, blank period, and sustain period. When the voltage applied to the light emitting element is 8 V, the potential of the current supply line 1109 is 8 V, the potential of the counter electrode 1110 is 0 V, the High potential of the first scanning line 1106 is 10 V, the Low potential is 0 V, and the second scan. The High potential of the line 1107 is 3 V, the Low potential is 0 V, the High potential of the data line 1108 is 3 V, and the Low potential is 0 V. The absolute value of the threshold value of the first transistor 1101, the second transistor 1102, the third transistor 1111, and the fourth transistor 1112 is 1 V, and the fifth transistor 1103 operates in a sufficiently linear region. Shall.

First, as shown in FIG. 13A, the potential of the first scan line 1106 becomes High (10 V) in the reset period, the first transistor 1101 is turned on, and the third transistor 1111 and the fourth transistor 1112 are turned on. nodeG becomes High (9V). Here, the third transistor 1111 takes in a current from the current supply line 1109, and the fourth transistor 1112 takes in a current from the first scanning line 1106, but the current supply capability is determined from the viewpoint of the wiring resistance. It is advantageous to capture from 1109. The reason for taking in from both the current supply line and the first scanning line is that the High potential period to the node G can be shortened and a potential higher than that of the current supply line can be obtained. Thus, the fifth transistor can be turned off more reliably when the light is turned off.

Next, as shown in FIG. 13B, a blank period is provided, the first transistor 1101 and the second transistor 1102 are turned on simultaneously, and the first scanning line 1106, the current supply line 1109, and the data line 1108 are energized. To prevent. In addition, the potential of the data signal needs to be determined before the second scanning line 1107 is set to High (3 V). The potential of the data line 1108 is set to Low (0 V) when the light emitting element is turned on and is set to High (3 V) when the light emitting element is turned off.

Then, as shown in FIG. 14, when the second scanning line 1107 is set to High (3 V) when the second scanning line 1107 is set to High (3 V), Vgs of the second transistor 1102 is turned off at 0 V when the potential of the data line 1108 is High (3 V). , NodeG maintains High (9 V) (FIG. 14B). Further, when the second scanning line 1107 is set to High (3 V), if the potential of the data line 1108 is Low (0 V), Vgs of the second transistor 1102 is 3 V and is turned on, and nodeG is the same as the potential of the data line 1108. The voltage becomes 0 V (FIG. 14A). As a result, the potential of the nodeG is determined as High (9 V) or Low (0 V) and is held by the holding capacitor 1104 for a certain period.

  As described above, by using the pixel configuration and the driving method of the semiconductor device of the present invention, regarding the control of the light emitting state / light-off state of the light emitting element according to the data signal, the potential of the data line is used for driving in the light emitting state. The gate potential of the fifth transistor is set, and in the light-off state, the potential of the current supply line can be written to the gate of the fifth transistor for driving. Therefore, the voltage of the data line can be set low, and the power consumption can be greatly reduced.

  This embodiment can be freely combined with any of the other embodiments and examples.

  A cross-sectional structure of a light-emitting device including the semiconductor device of the present invention will be described with reference to the drawings. Here, a cross-sectional structure of the light-emitting device including the second transistor for selection, the third transistor for driving, and the light-emitting element in FIG. 1 will be described in order with reference to FIG.

  As the substrate 1201 having an insulating surface, a glass substrate, a quartz substrate, a stainless steel substrate, or the like can be used. In addition, a substrate made of a plastic such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN) or a flexible synthetic resin such as acrylic can be used as long as it can withstand the processing temperature in the manufacturing process.

  First, a base film is formed over the substrate 1201. As the base film, an insulating film such as silicon oxide, silicon nitride, or silicon nitride oxide can be used. Next, an amorphous semiconductor film is formed over the base film. The thickness of the amorphous semiconductor film is 25 to 100 nm. As the amorphous semiconductor, not only silicon but also silicon germanium can be used. Subsequently, the amorphous semiconductor film is crystallized as necessary to form a crystalline semiconductor film 1202. As a method for crystallization, a heating furnace, laser irradiation, irradiation of light emitted from a lamp, or a combination thereof can be used. For example, a crystalline semiconductor film is formed by adding a metal element to an amorphous semiconductor film and performing heat treatment using a heating furnace. Thus, the addition of a metal element is preferable because crystallization can be performed at a low temperature.

  Note that a thin film transistor (TFT) formed using a crystalline semiconductor has a higher field-effect mobility and a higher ON current than a TFT formed using an amorphous semiconductor, and thus is more suitable as a transistor used in a semiconductor device.

  Next, the crystalline semiconductor film 1202 is patterned into a predetermined shape. Next, an insulating film functioning as a gate insulating film is formed. The insulating film is formed with a thickness of 10 to 150 nm so as to cover the semiconductor film. For example, a silicon oxynitride film, a silicon oxide film, or the like can be used, and a single layer structure or a stacked structure may be used.

  Next, a conductive film functioning as a gate electrode is formed through the gate insulating film. Although the gate electrode may be a single layer or a stacked layer, it is formed by stacking conductive films here. The conductive films 1203A and 1203B are formed using an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing these elements as main components. In this embodiment, a tantalum nitride film with a thickness of 10 to 50 nm is formed as the conductive film 1203A, and a tungsten film with a thickness of 200 to 400 nm is formed as the conductive film 1203B.

  Next, an impurity element is added using the gate electrode as a mask to form an impurity region. At this time, a low concentration impurity region may be formed in addition to the high concentration impurity region. The low concentration impurity region is called an LDD (Lightly Doped Drain) region.

  Next, insulating films 1204 and 1205 functioning as interlayer insulating films are formed. The insulating film 1204 is preferably an insulating film containing nitrogen. Here, the insulating film 1204 is formed using a 100 nm silicon nitride film by a plasma CVD method. The insulating film 1205 is preferably formed using an organic material or an inorganic material. As the organic material, polyimide, acrylic, polyamide, polyimide amide, benzocyclobutene, or siloxane can be used. Siloxane has a skeletal structure with a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Examples of the inorganic material include oxygen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y) (x and y are natural numbers), and the like. Alternatively, an insulating film containing nitrogen can be used. Note that a film made of an organic material has good flatness, but moisture and oxygen are absorbed by the organic material. In order to prevent this, an insulating film containing an inorganic material is preferably formed over the insulating film made of an organic material.

  Next, after a contact hole is formed in the interlayer insulating film 1206, a conductive film 1207 functioning as a source wiring and a drain wiring of the transistor is formed. As the conductive film 1207, a film formed of an element of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), or silicon (Si) or an alloy film using these elements can be used. In this embodiment, a laminated film of a titanium film, a titanium nitride film, a titanium-aluminum alloy film, and a titanium film is formed.

  Next, an insulating film 1208 is formed so as to cover the conductive film. The material shown for the interlayer insulating film 1206 can be used for the insulating film 1208. Next, a pixel electrode 1209 (also referred to as a first electrode) is formed in the opening provided in the insulating film 1208. In order to improve the step coverage of the pixel electrode 1209 in the opening, the end surface of the opening may be rounded so as to have a plurality of radii of curvature.

  As a material of the pixel electrode 1209, it is preferable to use a conductive material such as a metal, an alloy, an electrically conductive compound, or a mixture thereof having a high work function (work function of 4.0 eV or more). Specific examples of the conductive material include indium oxide containing tungsten oxide (IWO), indium zinc oxide containing tungsten oxide (IWZO), indium oxide containing titanium oxide (ITO), and indium tin oxide containing titanium oxide. A thing (ITTiO) etc. can be used. Needless to say, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide added with silicon oxide (ITSO), or the like can also be used.

  The composition proportion of the conductive material is as follows. The composition ratio of indium oxide containing tungsten oxide may be 1.0 wt% tungsten oxide and 99.0 wt% indium oxide. The composition ratio of indium zinc oxide containing tungsten oxide may be 1.0 wt% tungsten oxide, 0.5 wt% zinc oxide, and 98.5 wt% indium oxide. The indium oxide containing titanium oxide may be 1.0 wt% to 5.0 wt% titanium oxide and 99.0 wt% to 95.0 wt% indium oxide. The composition ratio of indium tin oxide (ITO) may be 10.0 wt% tin oxide and 90.0 wt% indium oxide. The composition ratio of indium zinc oxide (IZO) may be 10.7 wt% zinc oxide and 89.3 wt% indium oxide. The composition ratio of indium tin oxide containing titanium oxide may be 5.0 wt% titanium oxide, 10.0 wt% tin oxide, and 85.0 wt% indium oxide. The above composition ratio is an example, and the ratio of the composition ratio may be set as appropriate.

  Next, an electroluminescent layer 1210 is formed by an evaporation method or an inkjet method. The electroluminescent layer 1210 includes an organic material or an inorganic material, and includes an electron injection layer (EIL), an electron transport layer (ETL), a light emitting layer (EML), a hole transport layer (HTL), and a hole injection layer (HIL). ) And the like. Note that the boundaries between the layers are not necessarily clear, and there are cases where the materials constituting the layers are partially mixed and the interface is unclear.

  Note that the electroluminescent layer is preferably formed using a plurality of layers having different functions such as a hole injecting and transporting layer, a light emitting layer, and an electron injecting and transporting layer.

  Note that the hole injecting and transporting layer is preferably formed using a composite material including a hole transporting organic compound material and an inorganic compound material that exhibits an electron accepting property with respect to the organic compound material. By adopting such a configuration, many hole carriers are generated in an organic compound that has essentially no intrinsic carrier, and extremely excellent hole injecting and transporting properties can be obtained. Due to this effect, the drive voltage can be made lower than in the prior art. In addition, since the hole injecting and transporting layer can be thickened without causing an increase in driving voltage, a short circuit of the light emitting element due to dust or the like can be suppressed.

  Examples of hole transporting organic compound materials include copper phthalocyanine (abbreviation: CuPc), vanadyl phthalocyanine (abbreviation: VOPc), 4,4 ′, 4 ″ -tris (N, N-diphenylamino) triphenyl. Amine (abbreviation: TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenylamino] triphenylamine (abbreviation: MTDATA), 1,3,5-tris [N , N-di (m-tolyl) amino] benzene (abbreviation: m-MTDAB), N, N′-diphenyl-N, N′-bis (3-methylphenyl) -1,1′-biphenyl-4,4 '-Diamine (abbreviation: TPD), 4,4'-bis [N- (1-naphthyl) -N-phenylamino] biphenyl (abbreviation: NPB), 4,4'-bis {N- [4-di ( m-tri ) Amino] phenyl-N-phenylamino} biphenyl (abbreviation: DNTPD), 4,4 ′, 4 ″ -tris (N-carbazolyl) triphenylamine (abbreviation: TCTA), and the like. Never happen.

  Note that examples of the inorganic compound material exhibiting electron acceptability include titanium oxide, zirconium oxide, vanadium oxide, molybdenum oxide, tungsten oxide, rhenium oxide, ruthenium oxide, and zinc oxide. Vanadium oxide, molybdenum oxide, tungsten oxide, and rhenium oxide are particularly preferable because they can be vacuum-deposited and are easy to handle.

Note that the electron injecting and transporting layer is formed using an electron transporting organic compound material. Specifically, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [h] -quinolinato) beryllium (Abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) (4-phenylphenolato) aluminum (abbreviation: BAlq), bis [2- (2′-hydroxyphenyl) benzoxazolate] zinc (abbreviation) : Zn (BOX) ₂ ), bis [2- (2′-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) ₂ ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), 2- ( 4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole Abbreviation: PBD), 1,3-bis [5- (4-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 2,2 ′, 2 ″-(1,3,5-benzenetriyl) -tris (1-phenyl-1H-benzimidazole) (abbreviation: TPBI), 3- (4-biphenylyl) -4-phenyl-5- (4- tert-butylphenyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-biphenylyl) -4- (4-ethylphenyl) -5- (4-tert-butylphenyl) -1,2 , 4-triazole (abbreviation: p-EtTAZ) and the like, but is not limited thereto.

Note that the light-emitting layer includes 9,10-di (2-naphthyl) anthracene (abbreviation: DNA), 9,10-di (2-naphthyl) -2-tert-butylanthracene (abbreviation: t-BuDNA), 4 , 4′-bis (2,2-diphenylvinyl) biphenyl (abbreviation: DPVBi), coumarin 30, coumarin 6, coumarin 545, coumarin 545T, perylene, rubrene, periflanthene, 2,5,8,11-tetra (tert-) Butyl) perylene (abbreviation: TBP), 9,10-diphenylanthracene (abbreviation: DPA), 5,12-diphenyltetracene, 4- (dicyanomethylene) -2-methyl- [p- (dimethylamino) styryl] -4H -Pyran (abbreviation: DCM1), 4- (dicyanomethylene) -2-methyl-6- [2- (julolidin-9-yl) e And tenenyl] -4H-pyran (abbreviation: DCM2), 4- (dicyanomethylene) -2,6-bis [p- (dimethylamino) styryl] -4H-pyran (abbreviation: BisDCM), and the like. In addition, bis [2- (4 ′, 6′-difluorophenyl) pyridinato-N, C ^{2 ′} ] iridium (picolinate) (abbreviation: FIrpic), bis {2- [3 ′, 5′-bis (trifluoromethyl) ) Phenyl] pyridinato-N, C ^{2 ′} } iridium (picolinate) (abbreviation: Ir (CF ₃ ppy) ₂ (pic)), tris (2-phenylpyridinato-N, C ^{2 ′} ) iridium (abbreviation: Ir (Ppy) ₃ ), bis (2-phenylpyridinato-N, C ^{2 ′} ) iridium (acetylacetonate) (abbreviation: Ir (ppy) ₂ (acac)), bis [2- (2′-thienyl) pyridinato -N, C ^{3 ']} iridium (acetylacetonate) _{(abbreviation: Ir (thp) 2 (acac} )), bis (2-phenylquinolinato--N, C ^2') iridium (Asechirua Tonato) _{(abbreviation: Ir (pq) 2 (acac} )), bis [2- (2'-benzothienyl) pyridinato -N, C ^{3 ']} iridium (acetylacetonate) (abbreviation: Ir _(btp) 2 (acac A compound capable of emitting phosphorescence such as)) can also be used.

  In addition to the singlet excited light emitting material, a triplet excited material containing a metal complex or the like may be used for the light emitting layer. For example, among red light emitting pixels, green light emitting pixels, and blue light emitting pixels, a red light emitting pixel having a relatively short luminance half time is formed of a triplet excitation light emitting material, and the other A singlet excited luminescent material is used. The triplet excited luminescent material has a feature that the light emission efficiency is good, so that less power is required to obtain the same luminance. That is, when applied to a red pixel, the amount of current flowing through the light emitting element can be reduced, so that reliability can be improved. As a reduction in power consumption, a red light-emitting pixel and a green light-emitting pixel may be formed using a triplet excitation light-emitting material, and a blue light-emitting pixel may be formed using a singlet excitation light-emitting material. By forming a green light-emitting element having high human visibility with a triplet excited light-emitting material, power consumption can be further reduced.

  The light emitting layer may be configured to perform color display by forming light emitting layers having different emission wavelength bands for each pixel. Typically, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) is formed. In this case as well, it is possible to improve color purity and prevent mirror reflection (reflection) of the pixel portion by providing a filter that transmits light in the emission wavelength band on the light emission side of the pixel. Can do. By providing the filter, it is possible to omit a circularly polarizing plate that has been conventionally required, and it is possible to eliminate the loss of light emitted from the light emitting layer. Furthermore, a change in color tone that occurs when the pixel portion (display screen) is viewed obliquely can be reduced.

  In addition, examples of the polymer electroluminescent material that can be used for forming the light emitting layer include polyparaphenylene vinylene, polyparaphenylene, polythiophene, and polyfluorene.

  In any case, the layer structure of the electroluminescent layer can be changed, and instead of having a specific hole or electron injecting and transporting layer or a light emitting layer, it has an electrode layer exclusively for this purpose, or a light emitting layer. The deformation in which the material is dispersed is acceptable as long as the object as the light emitting element can be achieved.

  Further, a color filter (colored layer) may be formed on the sealing substrate. The color filter (colored layer) can be formed by an evaporation method or a droplet discharge method. When the color filter (colored layer) is used, high-definition display can be performed. This is because the color filter (colored layer) can correct a broad peak to be sharp in the emission spectrum of each RGB.

  Further, full color display can be performed by forming a material exhibiting monochromatic light emission and combining a color filter and a color conversion layer. The color filter (coloring layer) and the color conversion layer may be formed over the second substrate (sealing substrate) and attached to the substrate 1201, for example.

  Then, a counter electrode 1211 (also referred to as a second electrode) is formed by a sputtering method or an evaporation method. One of the pixel electrode 1209 and the counter electrode 1211 serves as an anode and the other serves as a cathode.

As the cathode material, it is preferable to use a metal, an alloy, an electrically conductive compound, a mixture thereof, or the like having a low work function (work function of 3.8 eV or less). Specific examples of the cathode material include elements belonging to Group 1 or Group 2 of the periodic table of elements, that is, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, and alloys containing these (Mg : Ag, Al: Li) and compounds (LiF, CsF, CaF ₂ ), as well as transition metals including rare earth metals. However, since the cathode needs to have translucency, these metals or an alloy containing these metals are formed very thinly, and are formed by lamination with a metal (including an alloy) such as ITO.

After that, a protective film made of a silicon nitride film or a DLC (Diamond Like Carbon) film may be provided so as to cover the counter electrode 1211. The light emitting device of the present invention is completed through the above steps.

  This embodiment can be freely combined with the above embodiment modes and embodiments. That is, a potential for turning on the driving transistor applied to the gate of the driving transistor can be supplied from the data line, and a potential for turning off the driving transistor can be supplied from another wiring such as a current supply line. Therefore, the voltage of the data line can be set low, and the power consumption can be greatly reduced.

  In this embodiment, an example of an active matrix display using the pixel structure of the present invention will be described with reference to FIG.

  The active matrix display includes a substrate 501 on which transistors and wirings are formed, an FPC 508 that connects the wiring portion to the outside, a light emitting element, and a counter substrate 502 that seals the light emitting element.

  The substrate 501 is connected to a display unit 506 including a plurality of pixels arranged in a matrix, a data line driving circuit 503, a scanning line driving circuit A 504, a scanning line driving circuit B 505, and an FPC 508 for inputting various power supplies and signals. Part 507.

  The data line driver circuit 503 includes circuits such as a shift register, a latch, a level shifter, and a buffer, and outputs data to the data lines in each column. Each of the scan line driver circuit A 504 and the scan line driver circuit B 505 includes circuits such as a shift register, a level shifter, and a buffer. The scan line driver circuit A 504 is a second scan line in each row, and the scan line driver circuit B 505 is A selection pulse is sequentially output to the first scanning line of each row.

  The light emission of the light emitting element is controlled in accordance with the data signal written to each pixel at the timing when the selection pulse is output by the scanning line driving circuit.

  In addition to the above drive circuit, circuits such as a central processing unit and a controller may be integrally formed on the substrate 501. Then, the number of external circuits (ICs) to be connected is reduced, and the weight and thickness can be further increased, which is particularly effective for a portable terminal or the like.

  Note that in this specification, as shown in FIG. 16, a panel in which an FPC is attached and an EL element is used as a light-emitting element is referred to as an EL module in this specification.

  This embodiment can be freely combined with the above embodiment modes and embodiments. That is, a potential for turning on the driving transistor applied to the gate of the driving transistor can be supplied from the data line, and a potential for turning off the driving transistor can be supplied from another wiring such as a current supply line. Therefore, the voltage of the data line can be set low, and the power consumption can be greatly reduced.

  In this embodiment, an example will be described in which the potential of the current supply line is corrected to suppress the influence of the change in the current value of the light emitting element due to the change in the environmental temperature and the change with time.

  The light-emitting element has a property that its resistance value (internal resistance value) changes depending on the ambient temperature. Specifically, when the room temperature is a normal temperature, the resistance value decreases when the temperature is higher than normal, and the resistance value increases when the temperature is lower than normal. Therefore, when the temperature increases, the current value increases and becomes higher than the desired luminance. When the same voltage is applied when the temperature decreases, the current value decreases and the luminance becomes lower than the desired luminance. Further, the light emitting element has a property that its current value decreases with time. Specifically, when the light emission time and the light extinction time are accumulated, the resistance value increases with the deterioration of the light emitting element. For this reason, when the same voltage is applied when the light emission time and the light extinction time are accumulated, the current value decreases and the luminance becomes lower than desired luminance.

  Due to the properties of the light-emitting element described above, when the environmental temperature changes or changes with time occur, the luminance varies. In this embodiment, the correction by using the potential of the current supply line of the present invention can suppress the influence of the change in the current value of the light emitting element due to the change in environmental temperature and the change with time.

  FIG. 17 shows a circuit configuration. The semiconductor device shown in FIG. 1 is arranged in the pixel, and the description similar to that in FIG. 1 is omitted. In FIG. 17, a third transistor for driving 1403 and a light emitting element 1404 are connected between a current supply line 1401 and a counter electrode 1402. Then, a current flows from the current supply line 1401 to the counter electrode 1402. The light emitting element 1404 emits light according to the magnitude of current flowing therethrough.

  In the case of such a pixel structure, if the potentials of the current supply line 1401 and the counter electrode 1402 are fixed, the characteristics deteriorate if current continues to flow through the light emitting element 1404. The characteristics of the light emitting element 1404 vary depending on the temperature.

  Specifically, when a current continues to flow through the light emitting element 1404, the voltage-current characteristic shifts. That is, the resistance value of the light emitting element 1404 increases, and the flowing current value decreases even when the same voltage is applied. Moreover, even if the same magnitude | size electric current flows, luminous efficiency will fall and a brightness | luminance will fall. As the temperature characteristics, when the temperature decreases, the voltage-current characteristics of the light-emitting element 1404 shift, and the resistance value of the light-emitting element 1404 increases.

  Therefore, the influence of deterioration and fluctuation as described above is corrected using a monitoring circuit. In this embodiment, by adjusting the potential of the current supply line 1401, deterioration of the light emitting element 1404 and fluctuation due to temperature are corrected.

  Therefore, the configuration of the monitor circuit will be described. A monitor current source 1408 and a monitor light emitting element 1409 are connected between the first monitor power line 1406 and the second monitor power line 1407. An input terminal of a sampling circuit 1410 for outputting the potential of the monitor light emitting element 1409 is connected to a contact point between the monitor light emitting element 1409 and the monitor current source 1408. A current supply line 1401 is connected to the output terminal of the sampling circuit 1410. Therefore, the potential of the current supply line 1401 is controlled by the output of the sampling circuit 1410.

  Next, the operation of the monitor circuit will be described. First, when the light emitting element 1404 emits light with the brightest number of gradations, the monitoring current source 1408 passes a current having a magnitude desired to flow through the light emitting element 1404. The current value at this time is Imax.

  Then, a voltage having a magnitude necessary for flowing a current having a magnitude Imax is added to the voltage across the monitor light emitting element 1409. Even if the voltage-current characteristic of the monitor light emitting element 1409 changes due to deterioration, temperature, or the like, the voltage across the monitor light emitting element 1409 also changes accordingly and becomes an optimum magnitude. Therefore, the influence of fluctuations (deterioration, temperature change, etc.) of the monitor light emitting element 1409 can be corrected.

  The voltage applied to the monitor light emitting element 1409 is input to the input terminal of the sampling circuit 1410. Therefore, the output terminal of the sampling circuit 1410, that is, the potential of the current supply line 1401 is corrected by the monitor circuit, and the light emitting element 1404 is corrected for deterioration and fluctuation due to temperature.

  Note that the sampling circuit 1410 may be anything as long as it outputs a voltage corresponding to the input current. For example, the voltage follower circuit is a kind of amplifier circuit, but is not limited thereto. A circuit may be configured by combining any one or more of an operational amplifier, a bipolar transistor, and a MOS transistor.

  Note that the monitor light emitting element 1409 is preferably formed on the same substrate by the same manufacturing method as the pixel light emitting element 1404. This is because the correction is shifted if the characteristics are different between the monitor and the pixel.

  Note that the light-emitting element 1404 arranged in the pixel has a period in which current is not frequently supplied. Therefore, if the monitor light-emitting element 1409 is continuously supplied with current, the monitor light-emitting element 1409 has a longer period. Deterioration greatly progresses. For this reason, the potential output from the sampling circuit 1410 is a potential as if the correction has been tightly applied. Therefore, the degree of deterioration of the monitor light emitting element 1049 may be controlled to match the actual degree of deterioration of the light emitting element 1404 arranged in the pixel. For example, on average, if the lighting rate of the entire screen is 30%, a current may be supplied to the monitor light emitting element 1409 only during a period corresponding to a luminance of 30%. At that time, a period in which no current flows in the monitor light emitting element 1409 occurs. However, it is necessary to keep the voltage supplied from the output terminal of the sampling circuit 1410 unchanged. In order to realize this, a capacitor element is provided at the input terminal of the sampling circuit 1410, and the potential when a current is supplied to the monitor light emitting element 1409 may be held there.

  Note that if the monitor circuit is operated in accordance with the brightest number of gradations, a potential that has been heavily corrected is output, but this causes burn-in in pixels (the degree of deterioration for each pixel). Since the luminance unevenness due to fluctuations becomes inconspicuous, it is desirable to operate the monitor circuit in accordance with the brightest number of gradations.

  In this embodiment, it is more preferable that the third transistor for driving 1403 is operated in a linear region. By operating in the linear region, the third transistor for driving 1403 generally operates as a switch. Therefore, it is possible to make it difficult for the third transistor 1403 for driving to be affected by the deterioration of the driving characteristics and the change in characteristics due to the temperature. When operating only in the linear region, it is often digitally controlled whether or not current flows through the light emitting element 1404. In that case, in order to increase the number of gradations, it is preferable to combine a time gradation method, an area gradation method, or the like.

  This embodiment can be freely combined with the above embodiment modes and embodiments.

  As an electronic device including the semiconductor device of the present invention, a television receiver, a video camera, a digital camera, a goggle type display, a navigation system, a sound reproduction device (car audio component, etc.), a computer, a game device, a portable information terminal (mobile computer) A mobile phone, a portable game machine, an electronic book, etc.) and an image playback apparatus (specifically, a digital versatile disc (DVD)) provided with a recording medium, and a display capable of displaying the image. Device). Specific examples of these electronic devices are shown in FIGS. 18, 19, 20A to 20B, 21A to 21B, 22, 23A to 23 (). E).

  FIG. 18 shows an EL module in which a display panel 5001 and a circuit board 5011 are combined. A circuit board 5011 is provided with a control circuit 5012, a signal dividing circuit 5013, and the like, and is electrically connected to the display panel 5001 through a connection wiring 5014.

  The display panel 5001 includes a pixel portion 5002 provided with a plurality of pixels, a scanning line driver circuit 5003, and a signal line driver circuit 5004 for supplying a video signal to the selected pixel. Note that in the case of manufacturing an EL module, a semiconductor device which forms a pixel in the pixel portion 5002 may be manufactured using the above embodiment. In addition, a control driver circuit portion such as the scan line driver circuit 5003 or the signal line driver circuit 5004 can be manufactured using the TFT formed in the above embodiment. As described above, the EL module television shown in FIG. 18 can be completed.

  FIG. 19 is a block diagram illustrating a main configuration of an EL television receiver. A tuner 5101 receives a video signal and an audio signal. The video signal includes a video signal amplifying circuit 5102, a video signal processing circuit 5103 that converts a signal output from the video signal into a color signal corresponding to each color of red, green, and blue, and the video signal as input specifications of the driver IC. Processing is performed by a control circuit 5012 for conversion. The control circuit 5012 outputs a signal to each of the scanning line side and the signal line side. In the case of digital driving, a signal dividing circuit 5013 may be provided on the signal line side so that an input digital signal is divided into m pieces and supplied.

  Of the signals received by the tuner 5101, the audio signal is sent to the audio signal amplifier circuit 5105, and the output is supplied to the speaker 5107 through the audio signal processing circuit 5106. The control circuit 5108 receives control information on the receiving station (reception frequency) and volume from the input unit 5109 and sends a signal to the tuner 5101 and the audio signal processing circuit 5106.

  As shown in FIG. 20A, a television receiver can be completed by incorporating an EL module into a housing 5201. A display screen 5202 is formed by the EL module. In addition, a speaker 5203, an operation switch 5204, and the like are provided as appropriate.

  FIG. 20B illustrates a television receiver that can carry only a display wirelessly. A housing and a signal receiver are incorporated in the housing 5212, and the display portion 5213 and the speaker portion 5217 are driven by the battery. The battery can be repeatedly charged by a charger 5210. The charger 5210 can transmit and receive a video signal, and can transmit the video signal to a signal receiver of the display. The housing 5212 is controlled by operation keys 5216. The device illustrated in FIG. 20B can also be referred to as a video / audio two-way communication device because a signal can be sent from the housing 5212 to the charger 5210 by operating the operation key 5216. In addition, by operating the operation key 5216, a signal is transmitted from the housing 5212 to the charger 5210, and further, a signal that can be transmitted by the charger 5210 is received by another electronic device, thereby controlling communication of the other electronic device. It can be said to be a general-purpose remote control device. The present invention can be applied to the display portion 5213.

  The transistor which is applied to the gate electrode of the driving transistor in the pixel of the display portion by using the semiconductor device of the present invention in the television receiver shown in FIGS. 18, 19, 20A to 20B. The potential for controlling on / off of the data line and the potential of the amplitude of the data line can be set separately. Accordingly, the amplitude of the data line can be set to a low amplitude, a semiconductor device with greatly reduced power consumption can be provided, and a product with greatly reduced power consumption can be provided to the customer. .

  Of course, the present invention is not limited to a television receiver, and is applied to various uses as a display medium of a particularly large area such as a monitor of a personal computer, an information display board in a railway station or airport, an advertisement display board in a street, etc. can do.

  FIG. 21A shows a module in which a display panel 5301 and a printed wiring board 5302 are combined. The display panel 5301 includes a pixel portion 5303 provided with a plurality of pixels, a first scan line driver circuit 5304, a second scan line driver circuit 5305, and a signal line driver circuit that supplies a video signal to the selected pixel. 5306 is provided.

  The printed wiring board 5302 is provided with a controller 5307, a central processing unit 5308 (CPU), a memory 5309, a power supply circuit 5310, an audio processing circuit 5311, a transmission / reception circuit 5312, and the like. The printed wiring board 5302 and the display panel 5301 are connected by a flexible wiring board 5313 (FPC). The flexible wiring substrate 5313 may be provided with a capacitor, a buffer circuit, or the like so as to prevent noise from being applied to a power supply voltage or a signal or a rise in signal from being slow. Further, the controller 5307, the audio processing circuit 5311, the memory 5309, the central processing unit 5308, the power supply circuit 5310, and the like can be mounted on the display panel 5301 using a COG (Chip On Glass) method. The scale of the printed wiring board 5302 can be reduced by the COG method.

  Various control signals are input / output through an interface unit 5314 (I / F) provided on the printed wiring board 5302. An antenna port 5315 for transmitting and receiving signals to and from the antenna is provided on the printed wiring board 5302.

  FIG. 21B shows a block diagram of the module shown in FIG. This module includes a VRAM 5316, a DRAM 5317, a flash memory 5318, and the like as the memory 5309. The VRAM 5316 stores image data to be displayed on the panel, the DRAM 5317 stores image data or audio data, and the flash memory 5318 stores various programs.

  The power supply circuit 5310 supplies power for operating the display panel 5301, the controller 5307, the central processing unit 5308, the sound processing circuit 5311, the memory 5309, and the transmission / reception circuit 5312. Depending on the specifications of the panel, the power supply circuit 5310 may be provided with a current source.

  The central processing unit 5308 includes a control signal generation circuit 5320, a decoder 5321, a register 5322, an arithmetic circuit 5323, a RAM 5324, an interface 5319 for the central processing unit 5308, and the like. Various signals input to the central processing unit 5308 via the interface 5319 are temporarily held in the register 5322 and then input to the arithmetic circuit 5323, the decoder 5321, and the like. The arithmetic circuit 5323 performs an operation based on the input signal and designates a place to send various commands. On the other hand, the signal input to the decoder 5321 is decoded and input to the control signal generation circuit 5320. The control signal generation circuit 5320 generates a signal including various instructions based on the input signal, and a location designated by the arithmetic circuit 5323, specifically, a memory 5309, a transmission / reception circuit 5312, an audio processing circuit 5311, a controller 5307, and the like. Send to.

  The memory 5309, the transmission / reception circuit 5312, the sound processing circuit 5311, and the controller 5307 operate according to the received commands. The operation will be briefly described below.

  A signal input from the input unit 5325 is sent to the central processing unit 5308 mounted on the printed wiring board 5302 via the interface unit 5314. The control signal generation circuit 5320 converts the image data stored in the VRAM 5316 into a predetermined format according to a signal sent from the input unit 5325 such as a pointing device or a keyboard, and sends the image data to the controller 5307.

  The controller 5307 performs data processing on a signal including image data sent from the central processing unit 5308 in accordance with the specifications of the panel, and supplies the processed signal to the display panel 5301. Further, the controller 5307, based on the power supply voltage input from the power supply circuit 5310 and various signals input from the central processing unit 5308, Hsync signal, Vsync signal, clock signal CLK, AC voltage (AC Cont), switching signal L / R is generated and supplied to the display panel 5301.

  In the transmission / reception circuit 5312, signals transmitted / received as radio waves in the antenna 5328 are processed. Specifically, high-frequency signals such as an isolator, a band-pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun. Includes circuitry. A signal including audio information among signals transmitted and received in the transmission / reception circuit 5312 is sent to the audio processing circuit 5311 in accordance with a command from the central processing unit 5308.

  A signal including audio information sent in accordance with a command from the central processing unit 5308 is demodulated into an audio signal in the audio processing circuit 5311 and sent to the speaker 5327. An audio signal sent from the microphone 5326 is modulated by the audio processing circuit 5311 and sent to the transmission / reception circuit 5312 in accordance with a command from the central processing unit 5308.

  The controller 5307, the central processing unit 5308, the power supply circuit 5310, the sound processing circuit 5311, and the memory 5309 can be mounted as a package of this embodiment. This embodiment can be applied to any circuit other than a high-frequency circuit such as an isolator, a band pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun.

  FIG. 22 illustrates one mode of a mobile phone including the module illustrated in FIGS. 21 (A) to 21 (B). The display panel 5301 is incorporated in a housing 5330 so as to be detachable. The shape and size of the housing 5330 can be changed as appropriate in accordance with the size of the display panel 5301. The housing 5330 to which the display panel 5301 is fixed is fitted to the printed board 5331 and assembled as a module.

  The display panel 5301 is connected to the printed board 5331 through the flexible wiring board 5313. A signal processing circuit 5335 including a speaker 5332, a microphone 5333, a transmission / reception circuit 5334, a central processing unit, a controller, and the like is formed over the printed board 5331. Such a module is combined with the input means 5336, the battery 5337, and the antenna 5340 and stored in the housing 5339. The pixel portion of the display panel 5301 is arranged so that it can be seen from an opening window formed in the housing 5339.

  The mobile phone according to the present embodiment can be transformed into various modes according to the function and application. For example, a configuration may be adopted in which a plurality of display panels are provided, or the housing is divided into a plurality of parts as appropriate and can be opened and closed by a hinge.

  In the mobile phone shown in FIG. 22, the display panel 5301 is formed by arranging semiconductor devices similar to those described in Embodiment Mode 1 in a matrix. In the semiconductor device, the potential for controlling on and off of the transistor applied to the gate electrode of the driving transistor in the pixel and the potential of the amplitude of the data line can be set separately. Therefore, it is possible to set the amplitude of a signal input to the data line to be small, and it is possible to provide a semiconductor device with significantly reduced power consumption. Since the display panel 5301 including the semiconductor device has similar characteristics, this mobile phone achieves a significant reduction in power consumption. With such a feature, it is possible to provide customers with products with significantly reduced power consumption.

  FIG. 23A illustrates a television device, which includes a housing 6001, a support base 6002, a display portion 6003, and the like. In this television device, the display portion 6003 is formed by arranging semiconductor devices similar to those described in Embodiment Mode 1 in a matrix. In the semiconductor device, the potential for controlling on and off of the transistor applied to the gate electrode of the driving transistor in the pixel and the potential of the amplitude of the data line can be set separately. Therefore, it is possible to set the amplitude of a signal input to the data line to be small, and it is possible to provide a semiconductor device with significantly reduced power consumption. Since the display portion 6003 including the semiconductor device has similar characteristics, the power consumption of the television device is greatly reduced. With such a feature, it is possible to provide customers with products with significantly reduced power consumption.

  FIG. 23B illustrates a computer, which includes a main body 6101, a housing 6102, a display portion 6103, a keyboard 6104, an external connection port 6105, a pointing mouse 6106, and the like. In this computer, the display portion 6103 is formed by arranging semiconductor devices similar to those described in Embodiment Mode 1 in a matrix. In the semiconductor device, the potential for controlling on and off of the transistor applied to the gate electrode of the driving transistor in the pixel and the potential of the amplitude of the data line can be set separately. Therefore, it is possible to set the amplitude of a signal input to the data line to be small, and it is possible to provide a semiconductor device with significantly reduced power consumption. Since the display portion 6103 which includes the semiconductor device has similar characteristics, this computer can achieve significant reduction in power consumption. With such a feature, it is possible to provide customers with products with significantly reduced power consumption.

  FIG. 23C illustrates a portable computer, which includes a main body 6201, a display portion 6202, a switch 6203, operation keys 6204, an infrared port 6205, and the like. In this portable computer, the display portion 6202 is formed by arranging semiconductor devices similar to those described in Embodiment Mode 1 in a matrix. In the semiconductor device, the potential for controlling on and off of the transistor applied to the gate electrode of the driving transistor in the pixel and the potential of the amplitude of the data line can be set separately. Therefore, it is possible to set the amplitude of a signal input to the data line to be small, and it is possible to provide a semiconductor device with significantly reduced power consumption. Since the display portion 6202 which includes the semiconductor device has similar characteristics, this portable computer can achieve significant reduction in power consumption. With such a feature, it is possible to provide customers with products with significantly reduced power consumption.

  FIG. 23D illustrates a portable game machine, which includes a housing 6301, a display portion 6302, speaker portions 6303, operation keys 6304, a recording medium insertion portion 6305, and the like. In this portable game machine, the display portion 6302 is formed by arranging semiconductor devices similar to those described in Embodiment Mode 1 in a matrix. In the semiconductor device, the potential for controlling on and off of the transistor applied to the gate electrode of the driving transistor in the pixel and the potential of the amplitude of the data line can be set separately. Therefore, it is possible to set the amplitude of a signal input to the data line to be small, and it is possible to provide a semiconductor device with significantly reduced power consumption. Since the display portion 6302 which includes the semiconductor device has similar characteristics, this portable game machine can achieve significant reduction in power consumption. With such a feature, it is possible to provide customers with products with significantly reduced power consumption.

  FIG. 23E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 6401, a housing 6402, a display portion A6403, a display portion B6404, and a recording medium (such as a DVD). A reading unit 6405, operation keys 6406, a speaker unit 6407, and the like are included. The display portion A 6403 mainly displays image information, and the display portion B 6404 mainly displays character information. In this image reproduction device, the display portion A 6403 and the display portion B 6404 are configured by arranging semiconductor devices similar to those described in Embodiment 1 in a matrix. In the semiconductor device, the potential for controlling on and off of the transistor applied to the gate electrode of the driving transistor in the pixel and the potential of the amplitude of the data line can be set separately. Therefore, it is possible to set the amplitude of a signal input to the data line to be small, and it is possible to provide a semiconductor device with significantly reduced power consumption. Since the display portion A 6403 and the display portion B 6404 which are formed using the semiconductor device have similar characteristics, the power consumption of the image reproduction device is significantly reduced. With such a feature, it is possible to provide customers with products with significantly reduced power consumption.

  Display devices used in these electronic devices can use not only a glass substrate but also a heat-resistant plastic substrate depending on the size, strength, or purpose of use. As a result, the weight can be further reduced.

  It should be noted that the examples shown in the present embodiment are only examples and are not limited to these applications.

  This embodiment can be implemented by being freely combined with any description of the above embodiment modes and embodiments.

1 is a circuit diagram according to a first embodiment of the present invention. The timing chart figure of Embodiment 1 of this invention. 1 is a diagram of Embodiment 1 of the present invention. FIG. 1 is a diagram of Embodiment 1 of the present invention. FIG. Circuit diagram of Embodiment 2 of the present invention The figure for demonstrating Embodiment 2 of this invention. The circuit diagram of Embodiment 3 of this invention. The timing chart figure of Embodiment 3 of this invention. One form figure of Embodiment 3 of this invention. One form figure of Embodiment 3 of this invention. The circuit diagram of Embodiment 4 of this invention. Timing chart of Embodiment 4 of the present invention One form figure of Embodiment 4 of this invention. One form figure of Embodiment 4 of this invention. Sectional drawing of Example 1 of this invention. The perspective view of Example 2 of this invention. The circuit diagram of Example 3 of the present invention. FIG. 4 is a diagram of an electronic apparatus according to a fourth embodiment of the present invention. FIG. 4 is a diagram of an electronic apparatus according to a fourth embodiment of the present invention. FIG. 4 is a diagram of an electronic apparatus according to a fourth embodiment of the present invention. FIG. 4 is a diagram of an electronic apparatus according to a fourth embodiment of the present invention. FIG. 4 is a diagram of an electronic apparatus according to a fourth embodiment of the present invention. FIG. 4 is a diagram of an electronic apparatus according to a fourth embodiment of the present invention. The figure which shows the prior art example of this invention.

Explanation of symbols

101 Transistor 102 Transistor 103 Transistor 104 Holding Capacitor 105 Light Emitting Element 106 Scan Line 107 Scan Line 108 Data Line 109 Current Supply Line 110 Counter Electrode 501 Substrate 502 Counter Substrate 503 Data Line Driver Circuit 504 Scan Line Driver Circuit A
505 Scan line driving circuit B
506 Display unit 507 FPC connection unit 508 FPC
551 Power supply line 601 N-channel transistor characteristic curve 602 N-channel transistor characteristic curve 603 P-channel transistor characteristic curve 604 P-channel transistor characteristic curve 701 Transistor 702 Transistor 703 Transistor 704 Storage capacitor 705 Light emission Element 706 Scan line 707 Scan line 708 Data line 709 Current supply line 710 Counter electrode 711 Transistor 1101 Transistor 1102 Transistor 1103 Transistor 1104 Storage capacitor 1105 Light emitting element 1106 Scan line 1107 Scan line 1108 Data line 1109 Current supply line 1110 Counter electrode 1111 Transistor 1112 Transistor 1201 Substrate 1202 Crystalline semiconductor film 1203A Conductive film 1203B Conductive film 1204 Insulating film 120 Insulating film 1206 Interlayer insulating film 1207 Conductive film 1208 Insulating film 1209 Pixel electrode 1210 Electroluminescent layer 1211 Counter electrode 1401 Current supply line 1402 Counter electrode 1403 Transistor 1404 Light emitting element 1406 First monitor power supply line 1407 Second monitor power supply line 1408 Monitor Current source 1409 Monitor light emitting element 1410 Sampling circuit 2401 Switch transistor 2402 Drive transistor 2403 Storage capacitor 2404 Light emitting element 2405 Scan line 2406 Data line 2407 Current supply line 5001 Display panel 5002 Pixel portion 5003 Scan line drive circuit 5004 Signal line drive circuit 5011 Circuit board 5012 Control circuit 5013 Signal division circuit 5014 Connection wiring 5101 Tuner 5102 Video signal amplification circuit 5103 Video signal processing circuit 105 Audio signal amplifier circuit 5106 Audio signal processing circuit 5107 Speaker 5108 Control circuit 5109 Input unit 5201 Case 5202 Display screen 5203 Speaker 5204 Operation switch 5210 Battery charger 5212 Case 5213 Display unit 5216 Operation key 5217 Speaker unit 5301 Display panel 5302 Print wiring Substrate 5303 Pixel unit 5304 Scanning line drive circuit 5305 Scanning line drive circuit 5306 Signal line drive circuit 5307 Controller 5308 Central processing unit 5309 Memory 5310 Power supply circuit 5311 Audio processing circuit 5312 Transmission / reception circuit 5313 Flexible wiring board 5314 Interface unit 5315 Antenna port 5316 VRAM
5317 DRAM
5318 Flash memory 5319 Interface 5320 Control signal generation circuit 5321 Decoder 5322 Register 5323 Arithmetic circuit 5324 RAM
5325 Input means 5326 Microphone 5327 Speaker 5328 Antenna 5330 Housing 5331 Printed circuit board 5332 Speaker 5333 Microphone 5334 Transmission / reception circuit 5335 Signal processing circuit 5336 Input means 5337 Battery 5339 Case 5340 Antenna 6001 Case 6002 Support stand 6003 Display portion 6101 Main body 6102 Case 6103 Display unit 6104 Keyboard 6105 External connection port 6106 Pointing mouse 6201 Main body 6202 Display unit 6203 Switch 6204 Operation key 6205 Infrared port 6301 Case 6302 Display unit 6303 Speaker unit 6304 Operation key 6305 Recording medium insertion unit 6401 Main unit 6402 Case 6403 Display unit A
6404 Display portion B
6405 Recording medium (DVD etc.) reading unit 6406 Operation key 6407 Speaker unit

Claims (22)

A first transistor in which a first scan signal is applied to the gate via a first scan line; a second transistor in which a second scan signal is applied to the gate via a second scan line; A third transistor driven and controlled in accordance with the first signal and the second signal applied to the gate, a pixel electrode, and a light emitting element that emits light by a driving current flowing between the pixel electrode and the counter electrode; Including,
The first signal supplied from the current supply line via the first transistor is a signal for disconnecting an electrical connection between the current supply line and the pixel electrode via the third transistor;
The second signal supplied from the data line through the second transistor is a signal for electrically connecting the current supply line and the pixel electrode by the third transistor. Semiconductor device. A first transistor in which a first scan signal is applied to the gate via a first scan line; a second transistor in which a second scan signal is applied to the gate via a second scan line; A third transistor driven and controlled in accordance with the first signal and the second signal applied to the gate, a pixel electrode, and a light emitting element that emits light by a driving current flowing between the pixel electrode and the counter electrode; Including,
The first signal supplied from the power supply line via the first transistor is a signal for disconnecting the electrical connection between the current supply line via the third transistor and the pixel electrode,
The second signal supplied from the data line through the second transistor is a signal for electrically connecting the current supply line and the pixel electrode by the third transistor. Semiconductor device.   3. The semiconductor device according to claim 2, wherein a potential of the power supply line is different from a potential of the current supply line.   4. The semiconductor device according to claim 1, wherein a storage capacitor is provided between the gate of the third transistor and the current supply line.   5. The semiconductor device according to claim 1, wherein the first transistor and the second transistor are N-channel transistors, and the third transistor is a P-channel transistor. A first transistor in which a first scan signal is applied to the gate via a first scan line; a second transistor in which a second scan signal is applied to the gate via a second scan line; A third transistor driven and controlled according to the potential of the current supply line; a fourth transistor driven and controlled according to the first and second signals applied to the gate; the pixel electrode; A light emitting element that emits light by a driving current flowing between the pixel electrode and the counter electrode,
The first signal supplied from the first scan line via the first transistor and the third transistor is an electric current between the current supply line via the fourth transistor and the pixel electrode. Is a signal to disconnect
The second signal supplied from the data line through the second transistor is a signal for electrically connecting the current supply line and the pixel electrode by the fourth transistor. Semiconductor device.   7. The semiconductor device according to claim 6, wherein a storage capacitor is provided between a gate of the fourth transistor and the current supply line.   8. The semiconductor according to claim 6, wherein the first transistor, the second transistor, and the third transistor are N-channel transistors, and the fourth transistor is a P-channel transistor. apparatus. A first transistor in which a first scan signal is applied to the gate via a first scan line; a second transistor in which a second scan signal is applied to the gate via a second scan line; A third transistor driven and controlled in accordance with the potential of the current supply line; a fourth transistor driven and controlled by the first scanning signal; and a first signal and a second signal applied to the gate. A fifth transistor that is driven and controlled in response, a pixel electrode, and a light emitting element that emits light by a driving current flowing between the pixel electrode and the counter electrode,
The first signal supplied from the first scan line via the first transistor and the fourth transistor is an electric current between the current supply line via the fifth transistor and the pixel electrode. Is a signal to disconnect
The second signal supplied from the data line through the second transistor is a signal for electrically connecting the current supply line and the pixel electrode by the fifth transistor. Semiconductor device.   10. The semiconductor device according to claim 9, wherein a storage capacitor is provided between the gate of the fifth transistor and the current supply line.   11. The transistor according to claim 9, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are N-channel transistors, and the fifth transistor is a P-channel transistor. There is a semiconductor device.   12. The semiconductor device according to claim 1, wherein an amplitude of the first scanning signal is larger than an amplitude of the second scanning signal.   A display device comprising the semiconductor device according to claim 1 in each pixel.   An electronic apparatus comprising the display device according to claim 13. A first transistor in which a first scan signal is applied to the gate via a first scan line; a second transistor in which a second scan signal is applied to the gate via a second scan line; A third transistor that is driven and controlled in accordance with a potential applied to the gate, a pixel electrode, and a light emitting element that emits light by a driving current flowing between the pixel electrode and the counter electrode,
The first transistor is turned on by the first scanning signal, and the electrical connection between the current supply line and the pixel electrode via the third transistor is disconnected at the gate of the third transistor. A first period in which the first signal is input from the current supply line through the first transistor;
A second period in which the first transistor is turned off by the first scanning signal and the second transistor is turned off by the second scanning signal;
A third period in which the second scanning signal is input to the second transistor;
In the third period, when the potential of the data line is lower than the potential of the second scanning signal, the third transistor has the current supply line and the pixel electrode connected to the gate of the third transistor. A method for driving a semiconductor device, wherein a second signal for electrical connection is input from the data line through the second transistor.   16. The method for driving a semiconductor device according to claim 15, wherein the first signal is input through the first transistor from a wiring having a potential different from that of the current supply line.   17. The method for driving a semiconductor device according to claim 15 or 16, wherein the first transistor and the second transistor are N-channel transistors, and the third transistor is a P-channel transistor. A first transistor in which a first scan signal is applied to the gate via a first scan line; a second transistor in which a second scan signal is applied to the gate via a second scan line; A third transistor that is driven and controlled by the potential of the current supply line, a fourth transistor that is driven and controlled according to a signal applied to the gate, a pixel electrode, and a current flowing between the pixel electrode and the counter electrode A light emitting element that emits light by a drive current,
The first transistor is turned on by the first scanning signal, and the electric connection between the current supply line and the pixel electrode via the fourth transistor is disconnected at the gate of the fourth transistor. A first period in which the first signal is input from the first scan line via the first transistor and the third transistor;
A second period in which the first transistor is turned off by the first scanning signal and the second transistor is turned off by the second scanning signal;
A third period in which the second scanning signal is input to the second transistor;
In the third period, when the potential of the data line is lower than the potential of the second scanning signal, the fourth transistor has the current supply line and the pixel electrode connected to the gate of the fourth transistor. A method for driving a semiconductor device, wherein a second signal for electrical connection is input from the data line through the first transistor and the second transistor.   19. The semiconductor device according to claim 18, wherein the first transistor, the second transistor, and the third transistor are N-channel transistors, and the fourth transistor is a P-channel transistor. Driving method. A first transistor in which a first scan signal is applied to the gate via a first scan line; a second transistor in which a second scan signal is applied to the gate via a second scan line; A third transistor driven and controlled by the potential of the current supply line; a fourth transistor driven and controlled by the first scanning signal; and a fifth transistor driven and controlled by a signal applied to the gate. And a pixel electrode, and a light emitting element that emits light by a driving current flowing between the pixel electrode and the counter electrode,
The first transistor and the fourth transistor are turned on by the first scanning signal, and the gate of the fifth transistor has an electrical connection between the current supply line via the fifth transistor and the pixel electrode. A first period in which a first signal for disconnecting a general connection is input from the first scan line via the first transistor and the fourth transistor;
A second period in which the first transistor is turned off by the first scanning signal and the second transistor is turned off by the second scanning signal;
A third period in which the second scanning signal is input to the second transistor;
In the third period, when the potential of the data line is lower than the potential of the second scanning signal, the fourth transistor has the current supply line and the pixel electrode connected to the gate of the fourth transistor. A method for driving a semiconductor device, wherein a second signal for electrical connection is input from the data line through the first transistor.   21. The first transistor, the second transistor, the third transistor, and the fourth transistor are N-channel transistors, and the fifth transistor is a P-channel transistor. A method for driving a semiconductor device.   22. The method for driving a semiconductor device according to claim 15, wherein an amplitude of the first scanning signal is larger than an amplitude of the second scanning signal.

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